TP11368N - Texas Instruments High-Performance Analog

TP11368

Octal Adaptive Differential PCM Processor

Literature Number: SNAS568

TP11368

Octal Adaptive Differential PCM Processor

General Description

The TP11368 is an octal (8) channel Adaptive Differential

Pulse Code Modulation (ADPCM) transcoder, fully compat-

ible to ITU G.726 recommendation in 40 kbps, 32 kbps,

24 kbps, 16 kbps and ANSI 32 kbps modes. The TP11368

ADPCM processor can operate on up to 16 independent

channels in an 8 kHz frame. Each channel is individually

configured, supporting both full and half duplex operation.All

input/output transfers occur on an interrupt basis using se-

rial, double buffered data registers. Together with National’s

TP3054/57 COMBO®or TP3070/71 COMBO II devices, the

TP11368 forms complete ADPCM channels with Codec/

filtering.

Features

nCCITT G.726 compatible at 40, 32, 24, 16 kbps

nANSI T1.301 compatible at 32 kbps

n16-channel half-duplex (encode or decode) or 8-channel

full-duplex operation in 8 kHz frame

nEach channel individually configurable

nSelectable µ-law or A-law PCM coding

nAsynchronous 16 MHz master clock operation

nTTL and CMOS compatible inputs and outputs

n28-pin PLCC or 24-pin DIP packages

nPower consumption of typ. 6 mW at +5V per full-duplex

channel

nOn-Chip Power-On-Reset

n−40˚C to +85˚C operating temperature range

nSingle 5V supply

Block Diagram

TRI-STATE®and COMBO®are registered trademarks of National Semiconductor Corporation.

DS012902-1

FIGURE 1. Block Diagram

March 1997

TP11368 Octal Adaptive Differential PCM Processor

Connection Diagrams

Pin Descriptions

TSI

Transmit PCM serial data input. TSI is an 8-bit PCM data

stream and is shifted into an 8-bit serial-to-parallel register

on the falling edges of PSCK while CE and TRB are high.

The last 8 bits of TSI are latched and transferred to the core

for processing at the falling edge of CE.

TSO

Transmit ADPCM TRI-STATE®serial data output. TSO is a

data bit stream of 4- to 5-bit length, and is shifted out with the

rising edge of ASCK when CE is high following the process-

ing of a transmit channel. TSO is in TRI-STATE mode while

CE is low or while RSO output is active.

RSI

ReceiveADPCM serial data input. RSI is a data bit stream of

4- to 5-bit length, and is shifted in with the falling edges of

ASCK while CE is high and TRB is low. The last 4 or 5 bits of

RSI are latched and transferred to the core for processing at

the falling edge of CE.

RSO

Receive PCM TRI-STATE serial data output. RSO is an 8-bit

PCM data stream and is shifted out with the rising edges of

PSCK when CE is high following the processing of a receive

channel. RSO is in TRI-STATE mode while CE is low or while

TSO output is active.

PSCK

PCM serial clock input. PSCK is used to shift PCM data into

TSI or out of RSO while CE is active (high). The transfer de-

pends on the logic state of TRB.

ASCK

ADPCM serial clock input. ASCK is used to shift ADPCM

data into RSI or out of TSO while CE is active (high). The

transfer depends on the logic state of TRB.

CLK

Master clock input. CLK may be asynchronous to PSCK or

ASCK.

Chip enable input. When CE is high, it enables data transfer.

The falling edge of CE latches and transfers the serial data

TSI or RSI to the core for processing and strobes the control

signals QSEL0, QSEL1, PCM1, EN and INIT. CE should

change state only when PSCK and ASCK are high. CE,

when low, sets the TSO and RSO outputs into TRI-STATE

mode.

TRB

Transmitter or receiver select. A logic low at TRB selects the

receiver of the channel processed. A logic high enables the

transmitter of the channel processed. TRB determines which

input register is enabled and which output register and out-

put is enabled. TRB should be stable while CE is high.

Channel enable input. EN is strobed in with the falling edge

of CE.Alogic high at the falling edge of CE indicates that the

channel is active, and the ADPCM will process the data just

clocked in.

INIT

Channel initialization input. INIT is read at the falling edge of

CE.Alogic high at the falling edge of CE causes theADPCM

processor to initialize the channel currently processing.

PCM1

PCM coding law select. A logic low at PCM1 selects 8-bit

µ-law, while a logic high selects 8-bit A-law with even bit in-

version.

Plastic Chip Carrier

DS012902-2

Top View

Order Number TP11368V

See NS Package Number V28A

Plastic Dual-In-Line

DS012902-3

Top View

Order Number TP11368N

See NS Package Number N24A

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Pin Descriptions (Continued)

QSEL0, QSEL1

ADPCM bit rate select inputs. The QSEL0 and QSE1 signals

are strobed in with the falling edge of CE. The QSEL0 and

QSEL1 select the conversion bit rate of the PCM data just

clocked in at the TSI input or the bit rate of the ADPCM data

just clocked in at the RSI input. See

Table 1

RSTB

Chip reset input.Alow to high transition at RSTB initiates the

reset sequence which initializes the channel variables for all

16 channels. A logic low applied to this pin sets the

transcoder into a low power dissipation mode. RSTB should

be pulled high for normal operation.

TST0, TST1, TST2

Test inputs for factory testing purposes. TST0–2 should be

tied low for normal operation.

CC1

CC2

Positive power supply input pins. V

=5V ±5%. A 0.1 µF

bypass capacitor should be connected between V

CC1

and

GND1, and V

CC2

and GND2.

GND1, GND2

Ground input pins.

Not connected.

Functional Description

Adaptive Differential Pulse Code Modulation (ADPCM) is a

transcoding algorithm for voice and voice band data trans-

mission. The use ofADPCM reduces the channel bandwidth

requirements from the standard 64 kbps PCM signal by a

factor of two or more. It is used for converting a 64 kbps

A-law or µ-law PCM channel to and from a 40, 32, 24 or

16 kbps channel. The 8-bit PCM signal is reduced to 2–5 bits

ADPCM signal depending on the selected bit rate in the en-

coder.

The TP11368 meets the ITU (CCITT) G.726 recommenda-

tion for 40, 32, 24, and 16 kbps ADPCM, as well as ANSI

T1.301 for 32 kbps. Each channel can be operated with an

independently selectable bit rate determined by QSEL1 and

QSEL0 (see

Table 1

TABLE 1. Bit Rate Selection

QSEL1 QSEL0 ADPCM Bit Rate

0 0 32 kbps

0 1 24 kbps

1 0 16 kbps

1 1 40 kbps

The ADPCM encoder converts the 64 kbps A-law or µ-law

PCM input signal to a uniform PCM signal which is sub-

tracted from an estimated signal obtained from an adaptive

predictor. A 31-, 15-, 7-, or 4-level non-uniform quantizer is

used to assign five, four, three or two binary digits, respec-

tively, to the value of the difference signal for transmission.

The ADPCM decoder reconstructs the original PCM signal

by adding the received quantized signal to the signal estima-

tion calculated by the predictor. A synchronous coding ad-

justment unit prevents cumulative distortion occurring on

synchronous tandem codings (ADPCM-PCM-ADPCM) un-

der certain conditions.

The adaptive predictor consists of two independent predictor

structures. One structure uses a second order recursive filter

which models the poles, and the other uses a sixth order

non-recursive filter which models the zeros in the input sig-

nal. This dual structure enables effective handling of both

speech and voice band data signals.

ADPCM PROCESSING

ADPCM to PCM Decoding Operation

When a logic “0” of TRB is latched in with the falling edge of

CE, theADPCM processor is set to the decoding mode. Data

applied at the RSI input is sampled with the falling edge of

ASCK into a 5-bit ADPCM serial register. Within the next

cycle of CE, the decoder converts the ADPCM input data to

an 8-bit companded PCM data after 123 master clocks

(CLK). The 8-bit parallel PCM data is loaded into a

parallel-to-serial shift register and shifted out at the RSO out-

put with the rising edges of PSCK.

PCM to ADPCM Encoding Operation

A logic “1” of TRB at the falling edge of CE sets the ADPCM

processor to the encoding mode. Data applied at the TSI in-

put is sampled in an internal 8-bit PCM register with the fall-

ing edge of PSCK. During the next cycle of CE, the encoder

converts the companded 8-bit PCM data into a 5-, 4-, 3- or

2-bit ADPCM data, which will be shifted out during the third

cycle of CE at the TSO output with the rising edges ofASCK.

The TP11368 requires one master clock signal CLK. The

master clock signal CLK is not required to be synchronous to

the serial I/O clocks ASCK or PSCK. The serial interface

uses the serial clocks ASCK and PSCK and chip enable CE

for receiving and transmitting data. The data is internally

synchronized to the master clock CLK. There is a lower limit

of the clock frequency for CLK resulting from the number of

clock cycles required for processing the data.

Table 2

shows

the required clock cycles per channel depending on the se-

lected mode.

TABLE 2. Processing Cycles

Mode of Operation CLK Cycles Needed

Decoder 123

Encoder 123

Initialized Channel 45

Disabled Channel 4

The sampling period (usually 125 µs for 8 kHz frame) divided

by the number of CLK cycles gives the required minimum

CLK period. A slightly higher CLK frequency is used in order

to allow for jitter and inaccuracies in the CLK rate. As an ex-

ample, for an eight channel ADPCM codec, CLK frequency

is 16 MHz as shown in the following calculations:

CLK

=125 µs/(16 *123) =63.5 ns

CLKmin

=1/t

CLK

=15.75 MHz

CLKnom

=16.0 MHz

The period of CE must be equal to or greater than the re-

quired number of CLK cycles times the period of CLK. CE

must be low for more than 4 CLK cycles.

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Functional Description (Continued)

The TP11368 is capable of processing 16 independent chan-

nels (half duplex) or 8 full-duplex PCM channels within 125

µs (8 kHz).

The logic state of TRB at the falling edge of CE determines

which input register is active during that CE period and which

output register will be active in the following third CE period.

The input data is processed (PCM data encoded or ADPCM

data decoded) during the second cycle and shifted out in the

third cycle of CE while CE is high.

SERIAL I/O

Input data is transferred into the TP11368 on the falling edge

of the clock signal, while output data is transmitted on the ris-

ing edge of the clock signal. PCM data is transferred syn-

chronously using PSCK, while ADPCM data is transferred

synchronously using ASCK. The clock signals ASCK and

PSCK should be high while CE changes. All serial data is

transferred with MSB first.

Figure 2

and

Figure 3

show the

serial input and output structures, respectively.

PCM Serial Input Register

The serial PCM data to be encoded is shifted into the 8-bit

PCM input register with the falling edges of PSCK while CE

and TRB are high. The falling edge of CE latches the state of

the input register and transfers the last 8 bits data prior to the

CE transition to the core for processing. The 8-bit PCM input

ADPCM Serial Input Register

The ADPCM serial input register is a 5-bit shift register to

store the 5-bit data in the 40 kbpsADPCM mode. Serial input

data is latched in with the falling edges of ASCK while CE is

high and TRB is low. A minimum number of five low going

ASCK pulses must be available within the CE pulse when

operating in the 40 kbps mode. For the 32, 24 and 16 kbps

modes, a minimum of four low going ASCK pulses must be

available while CE is high. The falling edge of CE latches the

last 5 bits data in the 40 kbps mode or the last 4 bits data in

the 32, 24, and 16 kbps modes prior to the CE transistion.

See

Table 3

for the position of the ADPCM data in the 5-bit

input register when 5ASCK low going pulses occur while CE

is high and TRB is low. Note that bit 1 in

Table 3

is the LSB.

ADPCM Output Register

The internal encoded parallelADPCM data is loaded into the

5-bit ADPCM output register with the falling edge of CE sig-

nal. The first MSB data is shifted out after the rising edge of

CE, subsequent ADPCM serial data is shifted out with the

rising edge of ASCK.

Table 4

shows the transfer order of the

ADPCM output data. If more than 4 ASCK clocks are avail-

able while CE is high in the 32, 24, and 16 kbps modes, the

ADPCM output data will recirculate starting with the MSB. In

the case of the 40 kbps mode, theADPCM output pattern will

recirculate, starting with the MSB, with the fifth rising edge of

ASCK while CE is high.

PCM Output Register

The decoded 8-bit parallel PCM data is loaded into an 8-bit

parallel-to-serial output shift register with the falling edge of

CE. The MSB data is shifted out with the leading edge of CE,

and subsequent data are shifted out with the rising edges of

PSCK while CE is high. The 8-bit PCM data at the RSO out-

put will recirculate with the MSB first after the seventh rising

edge of PSCK while CE is high.

Figure 4

shows the full duplex timing diagram for the 40 kbps

mode. For the 32, 24 and 16 kbps modes only fourASCK low

pulses are needed while CE is high (see

Figure 5

TRB is alternate high and low in the full duplex mode at each

falling edge of CE for a transmit (encoder) operation followed

DS012902-4

FIGURE 2. Serial Input Structure

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Functional Description (Continued)

by a receive (decoder) operation. For the encoding opera-

tion, the PCM data is stored in the 8-bit shift register at the

falling edge of CE while TRB is high. The TP11368 pro-

cesses the data within 123 CLK periods during the following

cycle of CE. The encoded ADPCM data is loaded into the

5-bit parallel-to-serial output register with the falling edge of

CE. The MSB data is shifted out first with the leading edge of

CE, and subsequent data is shifted out with the rising edge

of ASCK. For the decoding operation, the ADPCM data is

latched and transferred to the core at the falling edge of CE

while TRB is low. The data is processed within 123 CLK pe-

riods and the decoded 8-bit PCM data is shifted out with the

MSB first.

PSCK and ASCK are the clocks for the PCM and ADPCM

data streams, respectively. They must be high during the

transition of CE. Note that PSCK and ASCK are shown as

gated clocks as an option to conserve power. PSCK and

ASCK need only be valid while CE is high.

DS012902-5

FIGURE 3. Serial Output Structure

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Functional Description (Continued)

DS012902-6

FIGURE 4. Full Duplex Timing Diagram (40 kbps ADPCM mode)

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Functional Description (Continued)

Table 3

shows the position of theADPCM data in the 5-bit in-

put register when five ASCK low going pulses are available

while CE is high. Only the last four bits of the ADPCM input

transferred to the core for processing in the 32, 24 and 16

kbps modes. In the 40 kbps mode, the last five bits prior to

DS012902-7

FIGURE 5. Full Duplex Timing Diagram (32 kbps ADPCM mode)

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Functional Description (Continued)

the falling edge of CE are latched in. In

Table 3

, the last input

bit prior to to the CE falling edge is the LSB of the ADPCM

data word.

Note that the serial input data is referenced to the falling

edge of CE while the serial output data is referenced to the

rising edge of CE.

Table 4

shows the transfer order of the ADPCM output data.

In the case where there are more ASCK clocks than the AD-

PCM data, the ADPCM output will recirculate.

For example, if the 32 kbps mode is selected, and eight low

pulses of ASCK exist within the CE high pulse, the following

ADPCM encoded data D3-D2-D1-D0-D3-D2-D1-D0 will ap-

pear at the TSO output (

Table 5

TABLE 3. Transfer Order of ADPCM Input Data (RSI). The Last Bit Prior[to] the Falling Edge of CE is the LSB of the

ADPCM Data

QSEL1 QSEL0 Mode Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 0 32 kbps x D3 D2 D1 D0

0 1 24 kbps x D2 D1 D0 x

1 0 16 kbps x D1 D0 x x

1 1 40 kbps D4 D3 D2 D1 D0

(MSB) (LSB)

Note 1: x=Don’t Care state

TABLE 4. Transfer Order of ADPCM Output Data (TSO) with 4 ASCK Rising Edgesile CE is High (the First Bit is the

MSB Data Bit following the Rising Edge of CE)

QSEL1 QSEL0 Mode Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 0 32 kbps D3 D2 D1 D0 D3

0 1 24 kbps D2 D1 D0 x D2

1 0 16 kbps D1 D0 x x D1

1 1 40 kbps D4 D3 D2 D1 D0

(MSB) (LSB)

Note 2: x=unknown (but defined) state

TABLE 5. Transfer Order of ADPCM Output Data (TSO)th 7 Rising Edges (7 Low Pulses) while CE is High

QSEL1 QSEL0 Mode Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 0 32 kbps D3 D2 D1 D0 D3 D2 D1 D0

0 1 24 kbps D2 D1 D0 x D2 D1 D0 x

1 0 16 kbps D1 D0 x x D1 D0 x x

1 1 40 kbps D4 D3 D2 D1 D0 D4 D3 D2

Note 3: x=unknown (but defined) state

SINGLE-CHANNEL INITIALIZATION AND

ALL-CHANNEL RESET

The TP11368 ADPCM processor can be initialized on a

per-channel basis via the use of INIT or on an all-channel ba-

sis via the use of RSTB. In both cases, the internal ADPCM

variables are initialized to the default values as suggested by

the ITU G.726 recommendation.

An individual channel can be initialized to the desired con-

figuration by setting the corresponding data variables PCM1,

EN, QSEL(0,1) and by asserting the INIT pin high. The con-

figuration data and INIT signal are strobed at the falling edge

of CE. For an initialization cycle, the period of CE must be 45

master clock (CLK) cycles. The transcoder is then ready to

process the next channel.

The active low RSTB signal is used for a “warm” reset as

well as for facilitating device testing. The initialization of the

internal memory takes 726 CLK cycles after the RSTB goes

inactive (logic “1”). The first transition of CE is allowed six

CLK cycles after RSTB goes inactive. It is recommended

that CE be kept low during the initialization phase.The rec-

ommended values for ASCK and PSCK during initialization

are logic “1”, and that for TSI and RSI logic “0”.Any data (TSI

and RSI) applied during the initialization phase will be lost,

however, they won’t affect the proper initialization process.

The minimum low time of RSTB is 2 CLK cycles.

The chip resumes operation on the first negative edge of CE

after the completion of the initialization.

POWER-ON-RESET

The on-chip Power-On-Reset macro is activated when exter-

nal power is first applied to the device. It has the same func-

tion as the external RSTB pin which initializes all channels to

the default values defined in the ITU Recommendation

G.726. At power up, the outputs TSO and RSO are in

TRI-STATE mode. This “cold” reset process is asynchronous

and takes approximately 2000 CLK cycles for the initializa-

tion.

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Functional Description (Continued)

CHANNEL NOP

Each channel can be independently disabled. When EN is at

logic low on the falling edge of CE, the ADPCM transcoder

processing for that channel is disabled. The processor re-

quires 4 CLK cycles for CE to maintain all channel variables.

The data output ports are also placed in known states. After

this the processor waits for the next interrupt. TSO outputs

the following data after a channel NOP:

TABLE 6. TSO at Channel NOP

QSEL1 QSEL0 Mode TSO

0 0 32 kbps 0000

0 1 24 kbps 0000

1 0 16 kbps 0000

1 1 40 kbps 00000

The data pattern at TSO in

Table 6

are shown with four

ASCK clocks within the CE high pulse for the 32- , 24-,

16-kbps modes and five ASCK clocks within the CE high

pulse for the 40 kbps mode. In the case where ASCK pulses

are more than four or five, the given pattern recirculates with

the MSB first.

In the idle state, RSO outputs the following data (bit repre-

sentation with the sign-bit on the left followed by the MSB,

the sign-bit is the first bit after the rising edge of CE):

TABLE 7. RSO at Channel NOP

PCM1 Mode RSO

0 8-Bit µ-Law 11111111

1 8-Bit A-Law 11010101

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Absolute Maximum Ratings (Note *NO

TGT: FNXref NS0466*)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

to GND 7V

Voltage at Any Digital

Inputs or Outputs GND − 0.3V to V

+ 0.3V

Storage Temperature Range −45˚C to +125˚C

Lead Temperature

(Soldering, 10 sec) 300˚C

Latch-up Immunity on any Pin ±75 mA

(28-pin PLCC) 79˚C/W

(24-pin DIP) 49˚C/W

DC Electrical Characteristics

Unless otherwise noted, limits printed in bold characters are guaranteed forV

=5.0V ±5%, GND1 =GND2 =0V, T

−40˚C to +85˚C by correlation with 100%electrical testing at T

=25˚C. All other limits are assured by correlation with other

production tests and/or product design and characterization. Typical values are specified at V

=+5V, T

=25˚C.

Symbol Parameter Conditions Min Typ Max Units

CC0

Supply Current CLK =16.0 MHz, RSTB =Low 1.8 mA

(Power Down Mode)

CC1

Supply Current CLK =16.0 MHz, RSTB =High 10 12 mA

(Power Up Mode)

Power Dissipation 50 mW

Input Low Voltage For ASCK, PSCK, CE, TRB, 0.8 V

Input High Voltage CLK, RSTB 2.4 V

Input Low Voltage For PCM1, RSI, TSI, QSEL0, 0.7 V

Input High Voltage QSEL1, INIT, EN 2.0 V

Output Low Voltage I

=4mA 0.4 V

Output High Voltage I

=−4 mA 2.4 V

=−0.4 mA; V

=4.75V V

− 0.8 V

Input Low Current GND <V

, All Signal Inputs −10 µA

Input High Current V

, All Signal Inputs 10 µA

Test Inputs TST0, TST1, TST2 (Note 4) 150 µA

Output Current in High GND <V

, TSO and RS0 −10 10 µA

Impedance State

Input Capacitance 10 pF

Output Capacitance 10 pF

Capacitive Load 100 pF

Note 4: Test inputs have internal pull-down resistor.

Timing Specifications

Unless otherwise noted, limits printed in bold characters are guaranteed for V

=5.0V ±5%, GND1 =GND2 =0V, T

−40˚C to +85˚C by correlation with 100%electrical testing at T

=25˚C. All other limits are assured by correlation with other

production tests and/or product design and characterization. Typical values are specified at V

=+5V, T

=25˚C.

Symbol Parameter Conditions Min Typ Max Units

CLK

CLK Frequency (Note 5) Assuming 50%Duty Cycle 15.8 16 18 MHz

CLK

CLK Duty-Cycle 40%50%60%CLK

Period

Rise Time (CLK, CE, 10 ns

ASCK, PSCK)

Fall Time (CLK, CE, 10 ns

ASCK, PSCK)

CEP

CE Period Encode or Decode 123 CLK

Initialization 45 Cycles

Disable 9

CEL

CE Pulse Width, Low 4CLK

Cycles

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Timing Specifications (Continued)

Unless otherwise noted, limits printed in bold characters are guaranteed for V

=5.0V ±5%, GND1 =GND2 =0V, T

−40˚C to +85˚C by correlation with 100%electrical testing at T

=25˚C. All other limits are assured by correlation with other

production tests and/or product design and characterization. Typical values are specified at V

=+5V, T

=25˚C.

Symbol Parameter Conditions Min Typ Max Units

HDCEL

Hold Time, CE low after 15 ns

PSCK/ASCK High

SUCEH

Setup Time, CE High Before 15 ns

PSCK/ASCK Low

TRBH

TRB Hold Time From CE Low 20 ns

TRBS

TRB Setup Time From ASCK Low and PSCK Low 20 ns

TSI, RSI Setup Time From ASCK Low and PSCK Low 20 ns

TSI, RSI Hold Time From ASCK Low and PSCK Low 20 ns

PSCK/ASCK

PSCK/ASCK High and 55 ns

Low Times

TSO, RSO Turn On Time From CE High 40 ns

TSO, RSO Propagation From ASCK High or PSCK High 40 ns

Delay Time

OFF

TSO, RSO Turn Off Time From CE Low 20 ns

(Valid Data to TRI-STATE)

Setup Time for Control From CE Low

Signals (INIT, EN, 20 ns

PCM1, QSEL1, QSEL0)

Hold Time for Control From CE Low

Signals (INIT, EN, 20 ns

PCM1, QSEL1, QSEL0)

RSTL

RSTB Pulse Width Low 2 CLK

Cycles

RSTH

RSTB High to the First 6 CLK

CE High-Low Transition Cycles

Note 5: Values for 8 full-duplex (decoding and encoding) or 16 half-duplex (decoding or encoding) channels operation in a 125 µs period.

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Timing Specifications (Continued)

DS012902-8

FIGURE 6. ADPCM Timing

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Applications Information

DS012902-9

FIGURE 7. Typical Application of ADPCM Transcoders in an E1 Trunk

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Applications Information (Continued)

DS012902-10

FIGURE 8. Timing Diagram of 4 TP11368 (Encoding) in an E1 Trunk Pair Gain System

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Applications Information (Continued)

DS012902-11

FIGURE 9. Timing Diagram of ADPCM Decoding Processor

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Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead (0.600" Wide) Molded Dual-In-Line Package

Order Number TP11368N

NS Package Number N24A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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28-Lead Molded Plastic Leaded Chip Carrier

Order Number TP11368V

NS Package Number V28A

TP11368 Octal Adaptive Differential PCM Processor

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