FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND VREF AD5317R VLOGIC 2.5V REFERENCE INPUT REGISTER DAC REGISTER STRING DAC A SCLK VOUTA BUFFER INTERFACE LOGIC Low drift 2.5 V reference: 2 ppm/C typical Tiny package: 3 mm x 3 mm, 16-lead LFCSP Total unadjusted error (TUE): 0.1% of FSR maximum Offset error: 1.5 mV maximum Gain error: 0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch: 0.5 nV-sec Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply -40C to +105C temperature range SYNC SDIN SDO INPUT REGISTER DAC REGISTER STRING DAC B VOUTB BUFFER DAC REGISTER INPUT REGISTER STRING DAC C VOUTC BUFFER DAC REGISTER INPUT REGISTER STRING DAC D VOUTD BUFFER POWER-ON RESET GAIN x1/x2 RSTSEL GAIN LDAC RESET POWERDOWN LOGIC 10800-001 Data Sheet Quad, 10-Bit nanoDAC(R) with 2 ppm/C Reference, SPI Interface AD5317R Figure 1. APPLICATIONS Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5317R, a member of the nanoDAC(R) family, is a low power, quad, 10-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm x 3 mm LFCSP and a TSSOP package. Table 1. Related Devices The AD5317R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 A at 3 V while in power-down mode. 1. The AD5317R employs a versatile SPI interface that operates at clock rates up to 50 MHz and contains a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Rev. B Interface SPI IC 2 1 Reference Internal External Internal External 12-Bit AD5684R AD5684 AD5694R AD5694 10-Bit AD53171 AD5316R AD5316 The AD5317 and AD5317R are not pin-to-pin or software compatible. PRODUCT HIGHLIGHTS 2. 3. Precision DC Performance. Total unadjusted error: 0.1% of FSR maximum Offset error: 1.5 mV maximum Gain error: 0.1% of FSR maximum Low Drift 2.5 V On-Chip Reference. 2 ppm/C typical temperature coefficient 5 ppm/C maximum temperature coefficient Two Package Options. 3 mm x 3 mm, 16-lead LFCSP 16-lead TSSOP Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5317R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands .................................................. 21 Applications ....................................................................................... 1 Daisy-Chain Operation ............................................................. 21 Functional Block Diagram .............................................................. 1 Readback Operation .................................................................. 22 General Description ......................................................................... 1 Power-Down Operation ............................................................ 22 Product Highlights ........................................................................... 1 Load DAC (Hardware LDAC Pin) ........................................... 23 Revision History ............................................................................... 2 LDAC Mask Register ................................................................. 23 Specifications..................................................................................... 3 Hardware Reset (RESET) .......................................................... 24 AC Characteristics........................................................................ 5 Reset Select Pin (RSTSEL) ........................................................ 24 Timing Characteristics ................................................................ 6 Internal Reference Setup ........................................................... 25 Daisy-Chain and Readback Timing Characteristics ............... 7 Solder Heat Reflow..................................................................... 25 Absolute Maximum Ratings............................................................ 9 Long-Term Temperature Drift ................................................. 25 ESD Caution .................................................................................. 9 Thermal Hysteresis .................................................................... 25 Pin Configurations and Function Descriptions ......................... 10 Applications Information .............................................................. 26 Typical Performance Characteristics ........................................... 11 Microprocessor Interfacing ....................................................... 26 Terminology .................................................................................... 17 AD5317R to ADSP-BF531 Interface........................................ 26 Theory of Operation ...................................................................... 19 AD5317R to SPORT Interface .................................................. 26 Digital-to-Analog Converter .................................................... 19 Layout Guidelines....................................................................... 26 Transfer Function ....................................................................... 19 Galvanically Isolated Interface ................................................. 27 DAC Architecture ....................................................................... 19 Outline Dimensions ....................................................................... 28 Serial Interface ............................................................................ 20 Ordering Guide .......................................................................... 28 Standalone Operation ................................................................ 21 REVISION HISTORY 5/2017--Rev. A to Rev. B Changes to Table 2 Summary.......................................................... 3 Changes to Table 3 ............................................................................ 5 Changes to Table 4 and Figure 2 ..................................................... 6 Changes to Table 5 and Figure 4 ..................................................... 7 Changes to Figure 5 .......................................................................... 8 Changes to Table 6 ............................................................................ 9 Changes to VLOGIC Pin Description and RESET Pin Description, Table 7 .............................................................................................. 10 Changes to Figure 16 to Figure 19 ................................................ 12 Changes to Figure 20 to Figure 24 ................................................ 13 Changes to Figure 30 ...................................................................... 14 Changes to Figure 37 ...................................................................... 15 Changes to Figure 38 ...................................................................... 16 Changes to Table 8 .......................................................................... 20 Changes to Readback Operation Section .................................... 22 Changes to Hardware Reset (RESET) Section ............................ 24 Added Long-Term Temperature Drift Section and Figure 49; Renumbered Sequentially.............................................................. 25 Changes to Ordering Guide .......................................................... 28 2/2014--Rev. 0 to Rev. A Change to Table 2 ..............................................................................3 Change to Table 7 ........................................................................... 10 Deleted Figure 10, Renumbered Sequentially ............................ 11 Deleted Long-Term Temperature Drift Section and Figure 50 ...................................................................................... 1025 7/2012--Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD5317R SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V VLOGIC 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 k; CL = 200 pF. Table 2. Parameter STATIC PERFORMANCE 1 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Total Unadjusted Error Min Short-Circuit Current 4 Load Impedance at Rails 5 Power-Up Time REFERENCE OUTPUT Output Voltage 6 Reference TC 7, 8 Output Impedance2 Output Voltage Noise2 Output Voltage Noise Density2 Load Regulation, Sourcing2 Load Regulation, Sinking2 Output Current Load Capability2 Line Regulation2 Thermal Hysteresis2 0.12 0.5 0.5 1.5 1.5 0.1 0.1 0.1 0.2 0.4 +0.1 +0.01 0.02 0.01 1 1 0.15 2 3 2 0 0 Capacitive Load Stability Resistive Load 3 Load Regulation Max 10 Offset Error Drift2 Gain Temperature Coefficient2 DC Power Supply Rejection Ratio2 DC Crosstalk2 OUTPUT CHARACTERISTICS 2 Output Voltage Range Typ VREF 2 x VREF Unit Bits LSB LSB mV mV % of FSR % of FSR % of FSR % of FSR V/C ppm mV/V V V/mA V 80 V V nF nF k V/mA 80 V/mA 40 25 2.5 mA s 2 10 1 2.4975 2 0.04 12 240 20 40 5 100 125 25 2.5025 5 V ppm/C V p-p nV/Hz V/mA V/mA mA V/V ppm ppm Rev. B | Page 3 of 28 Test Conditions/Comments Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register External reference; gain = 2; TSSOP Internal reference; gain = 1; TSSOP Of FSR/C DAC code = midscale; VDD = 5 V 10% Due to single channel, full-scale output change Due to load current change Due to power-down (per channel) Gain = 1 Gain = 2, see Figure 28 RL = RL = 1 k 5 V 10%, DAC code = midscale; -30 mA IOUT +30 mA 3 V 10%, DAC code = midscale; -20 mA IOUT +20 mA See Figure 28 Coming out of power-down mode; VDD = 5 V At ambient See the Terminology section 0.1 Hz to 10 Hz At ambient; f = 10 kHz, CL = 10 nF At ambient At ambient VDD 3 V At ambient First cycle Additional cycles AD5317R Parameter LOGIC INPUTS2 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance LOGIC OUTPUTS (SDO)2 Output Low Voltage, VOL Output High Voltage, VOH Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD IDD Normal Mode 9 All Power-Down Modes 10 Data Sheet Min Typ Max Unit Test Conditions/Comments 2 0.3 x VLOGIC A V V pF Per pin 0.4 V V pF ISINK = 200 A ISOURCE = 200 A 5.5 3 5.5 5.5 V A V V 0.7 1.3 4 6 mA mA A A 0.7 x VLOGIC 2 VLOGIC - 0.4 4 1.62 2.7 VREF + 1.5 0.59 1.1 1 Gain = 1 Gain = 2 VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V Internal reference off Internal reference on, at full scale -40C to +85C -40C to +105C DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 4 to 1020. 2 Guaranteed by design and characterization; not production tested. 3 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110C. 4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 x 1 mA = 25 mV (see Figure 28). 6 Initial accuracy presolder reflow is 750 V; output voltage includes the effects of preconditioning drift. See the Terminology section. 7 Reference is trimmed and tested at two temperatures and is characterized from -40C to +105C. 8 Reference temperature coefficient calculated as per the box method. See the Terminology section for more information. 9 Interface inactive. All DACs active. DAC outputs unloaded. 10 All DACs powered down. 1 Rev. B | Page 4 of 28 Data Sheet AD5317R AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; RL = 2 k to GND; CL = 200 pF to GND; 1.62 V VLOGIC 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Total Harmonic Distortion 4 Output Noise Spectral Density Output Noise Min Typ 5 0.8 0.5 0.13 0.1 0.2 0.3 -80 300 6 Max 7 Unit s V/s nV-sec nV-sec nV-sec nV-sec nV-sec dB nV/Hz V p-p Guaranteed by design and characterization, not production tested. See the Terminology section. Temperature range is -40C to +105C, typical @ 25C. 4 Digitally generated sine wave @ 1 kHz. 1 2 3 Rev. B | Page 5 of 28 Test Conditions/Comments 3 1/4 to 3/4 scale settling to 1 LSB 1 LSB change around major carry At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz DAC code = midscale, 10 kHz, gain = 2, internal reference enabled 0.1 Hz to 10 Hz AD5317R Data Sheet TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.62 V VLOGIC 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1 SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates) SYNC Falling Edge to SCLK Fall Ignore LDAC Pulse Width Low SYNC Rising Edge to LDAC Rising Edge SYNC Rising Edge to LDAC Falling Edge LDAC Falling Edge to SYNC Rising Edge Minimum Pulse Width Low Pulse Activation Time Power-Up Time 2 1.62 V VLOGIC < 2.7 V Min Max 20 10 10 15 5 5 10 20 870 16 15 20 30 840 30 30 4.5 Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 2.7 V VLOGIC 5.5 V Min Max 20 10 10 10 5 5 10 20 830 10 15 20 30 800 30 30 4.5 Guaranteed by design and characterization; not production tested. Time to exit power-down to normal mode of AD5686R/AD5685R/AD5684R operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded. 1 2 E t10 t1 SCLK t8 t3 t2 t7 t14 t4 SYNC t9 t6 t5 SDIN DB23 DB0 t11 t13 LDAC1 t12 LDAC2 VOUT t15 t16 10800-002 RESET 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. B | Page 6 of 28 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s Data Sheet AD5317R DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS 17B All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V VLOGIC 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 5. Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Parameter 1 SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time SDO Data Valid from SCLK Rising Edge SYNC Rising Edge to SCLK Falling Edge SYNC Rising Edge to SDO Disable 16F E A A E A A E A A E A A E A A 1 Min 66 33 33 33 5 5 15 60 1.62 V VLOGIC < 2.7 V Max Min 40 20 20 20 5 5 10 30 2.7 V VLOGIC 5.5 V Max 45 Unit ns ns ns ns ns ns ns ns ns ns ns 30 15 60 10 60 Guaranteed by design and characterization; not production tested. Circuit and Timing Diagrams 42B 200A VOH (MIN) CL 20pF 200A 10800-003 TO OUTPUT PIN IOL IOH Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications t1 SCLK 24 48 t7 t2 t8 t3 t4 t10 SYNC SDIN t6 DB23 DB0 INPUT WORD FOR DAC N DB23 DB0 t9 INPUT WORD FOR DAC N + 1 DB23 SDO UNDEFINED DB0 INPUT WORD FOR DAC N Figure 4. Daisy-Chain Timing Diagram Rev. B | Page 7 of 28 10800-004 t5 AD5317R Data Sheet t1 SCLK 24 1 t8 t4 t3 24 1 t7 t2 t8 t10 SYNC t6 t5 DB23 DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB0 NOP CONDITION t9 DB23 SDO t11 DB0 HI-Z SELECTED REGISTER DATA CLOCKED OUT Figure 5. Readback Timing Diagram Rev. B | Page 8 of 28 10800-005 SDIN Data Sheet AD5317R ABSOLUTE MAXIMUM RATINGS 1B TA = 25C, unless otherwise noted. Table 6. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Parameter VDD to GND VLOGIC to GND VOUT to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead TSSOP, JA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, JA Thermal Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free (J-STD-020) Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VLOGIC + 0.3 V -40C to +105C -65C to +150C 125C 112.6C/W ESD CAUTION 18B 70C/W 260C Rev. B | Page 9 of 28 AD5317R Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 2B 13 RESET 14 RSTSEL 15 VREF 16 VOUTB AD5317R VOUTA 1 11 SYNC VDD 3 10 SCLK RESET VOUTA 3 14 SDIN SYNC 12 SCLK VOUTC 6 11 VLOGIC 7 10 GAIN SDO 8 9 LDAC VDD 5 TOP VIEW (Not to Scale) VOUTD 10800-006 NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. Figure 6. 16-Lead LFCSP Pin Configuration AD5317R 13 GND 4 GAIN 8 LDAC 7 SDO 6 VOUTD 5 RSTSEL 15 VOUTB 9 VLOGIC VOUTC 4 16 2 VREF 1 TOP VIEW (Not to Scale) 10800-007 12 SDIN GND 2 Figure 7. 16-Lead TSSOP Pin Configuration Table 7. Pin Function Descriptions LFCSP 1 2 3 Pin No. TSSOP 3 4 5 Mnemonic VOUTA GND VDD 4 5 6 6 7 8 VOUTC VOUTD SDO 7 9 8 10 GAIN 9 10 11 12 VLOGIC SCLK 11 13 12 14 13 15 LDAC E E A SYNC Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Power Supply Input. This part can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Serial Data Output. Can be used to daisy-chain a number of AD5317R devices together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to be simultaneously updated. This pin can also be tied permanently low. Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to VREF. When this pin is tied to VLOGIC, all four DAC outputs have a span of 0 V to 2 x VREF. Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 24 clocks. Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. If the pin is not used, tie it permanently to VLOGIC. If the pin is forced low at power-up, the POR circuit does not initialize correctly until the pin is released. Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VLOGIC powers up all four DACs to midscale. Reference Voltage. The AD5317R has a common reference pin. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference output. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Exposed Pad. The exposed pad must be tied to GND. A E A E A A A SDIN RESET E A E A E A E A 14 16 RSTSEL 15 1 VREF 16 17 2 N/A VOUTB EPAD A Rev. B | Page 10 of 28 A E A A A Data Sheet AD5317R TYPICAL PERFORMANCE CHARACTERISTICS 3B 2.5020 VDD = 5V DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 2.5015 2.5010 VDD = 5V TA = 25C VREF (V) 2.5005 2.5000 1 2.4995 2.4990 -20 0 20 40 60 80 100 120 TEMPERATURE (C) CH1 2V 10800-112 2.4980 -40 10800-212 2.4985 M1.0s Figure 11. Internal Reference Noise, 0.1 Hz to 10 Hz Figure 8. Internal Reference Voltage vs. Temperature (Grade B) 2.5000 90 VDD = 5V TA = 25C VDD = 5V 80 2.4999 70 VREF (V) NUMBER OF UNITS 2.4998 60 50 40 30 2.4997 2.4996 2.4995 20 2.4994 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE DRIFT (ppm/C) 2.4993 -0.005 10800-250 0 -0.001 0.001 0.003 0.005 ILOAD (A) Figure 12. Internal Reference Voltage vs. Load Current Figure 9. Reference Output Temperature Drift Histogram 1600 -0.003 10800-113 10 2.5002 VDD = 5V TA = 25C TA = 25C D1 1400 2.5000 1200 VREF (V) 800 600 D3 2.4996 2.4994 400 2.4992 200 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 10. Internal Reference Noise Spectral Density vs. Frequency 2.4990 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Figure 13. Internal Reference Voltage vs. Supply Voltage Rev. B | Page 11 of 28 10800-117 0 10 D2 10800-111 NSD (nV/ Hz) 2.4998 1000 AD5317R Data Sheet 0.15 0.5 0.12 0.3 0.09 ERROR (LSB) INL (LSB) 0.06 0.1 -0.1 0.03 INL 0 DNL -0.03 -0.06 -0.3 -0.09 VDD = 5V TA = 25C -0.12 156 312 468 625 781 938 CODE -0.15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 10800-125 0 10800-118 -0.5 5.0 VREF (V) Figure 14. INL Figure 17. INL Error and DNL Error vs. VREF 0.5 0.15 0.12 0.3 0.09 ERROR (LSB) DNL (LSB) 0.06 0.1 -0.1 0.03 INL 0 DNL -0.03 -0.5 -0.12 TA = 25C INTERNAL REFERENCE = 2.5V -0.15 2.7 3.2 3.7 4.2 156 312 468 625 781 938 CODE 0.10 0.12 0.08 0.09 0.06 0.06 0.04 ERROR (% of FSR) 0.15 0 INL DNL -0.03 -0.06 0.02 0 FULL-SCALE ERROR GAIN ERROR -0.02 -0.04 -0.09 -0.06 -0.12 -0.08 VDD = 5V INTERNAL REFERENCE = 2.5V -0.10 -40 -20 0 20 40 VDD = 5V INTERNAL REFERENCE = 2.5V -0.15 -40 10 5.2 Figure 18. INL Error and DNL Error vs. Supply Voltage 60 110 TEMPERATURE (C) 10800-124 ERROR (LSB) Figure 15. DNL 0.03 4.7 SUPPLY VOLTAGE (V) Figure 16. INL Error and DNL Error vs. Temperature 60 80 100 120 TEMPERATURE (C) Figure 19. Gain Error and Full-Scale Error vs. Temperature Rev. B | Page 12 of 28 10800-127 0 10800-119 -0.09 10800-126 -0.06 -0.3 Data Sheet AD5317R 0.10 1.2 0.8 0.6 ZERO-CODE ERROR 0.2 OFFSET ERROR -20 0 20 40 60 80 100 120 TEMPERATURE (C) 0.06 0.05 0.04 0.03 0.02 0.01 0 -40 10800-128 0 -40 0.07 0.08 0.08 TOTAL UNADJUSTED ERROR (% of FSR) 0.10 ERROR (% of FSR) 0.06 0.04 0.02 GAIN ERROR 0 FULL-SCALE ERROR -0.04 4.7 5.2 10800-129 -0.06 SUPPLY VOLTAGE (V) 40 60 80 100 120 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 TA = 25C INTERNAL REFERENCE = 2.5V -0.10 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) Figure 24. TUE vs. Supply Voltage, Gain = 1 Figure 21. Gain Error and Full-Scale Error vs. Supply Voltage 0 TOTAL UNADJUSTED ERROR (% of FSR) 1.5 1.0 0.5 ZERO-CODE ERROR 0 OFFSET ERROR -0.5 -1.0 TA = 25C INTERNAL REFERENCE = 2.5V -1.5 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) 10800-130 ERROR (mV) 20 Figure 23. TUE vs. Temperature 0.10 -0.08 TA = 25C INTERNAL REFERENCE = 2.5V -0.10 2.7 4.2 3.7 3.2 0 TEMPERATURE (C) Figure 20. Zero-Code Error and Offset Error vs. Temperature -0.02 -20 10800-132 0.4 0.08 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 VDD = 5V -0.09 T = 25C A INTERNAL REFERENCE = 2.5V -0.10 0 156 312 468 Figure 22. Zero-Code Error and Offset Error vs. Supply Voltage 624 CODE Figure 25. TUE vs. Code Rev. B | Page 13 of 28 780 936 1023 10800-133 ERROR (mV) 1.0 VDD = 5V 0.09 INTERNAL REFERENCE = 2.5V 10800-131 TOTAL UNADJUSTED ERROR (% of FSR) VDD = 5V 1.4 INTERNAL REFERENCE = 2.5V AD5317R Data Sheet 7 VDD = 5V 6 TA = 25C GAIN = 2 INTERNAL 5 REFERENCE = 2.5V VDD = 5V TA = 25C EXTERNAL REFERENCE = 2.5V 25 20 0xFFFF VOUT (V) HITS 4 15 10 0xC000 3 0x8000 2 0x4000 1 0x0000 0 5 540 560 580 600 620 640 IDD (mA) -2 -0.06 10800-135 0 -0.04 -0.02 0 0.04 0.06 LOAD CURRENT (A) Figure 29. Source and Sink Capability at 5 V Figure 26. IDD Histogram with External Reference, 5 V 5 VDD = 5V 30 T = 25C A INTERNAL REFERENCE = 2.5V 25 VDD = 3V TA = 25C GAIN = 1 EXTERNAL REFERENCE = 2.5V 4 3 0xFFFF VOUT (V) 20 15 10 0xC000 2 0x8000 1 0x4000 0x0000 0 5 -1 1000 1020 1040 1060 1080 1100 1120 1140 IDD FULL SCALE (mA) -2 -60 10800-136 0 -40 -20 0 20 40 60 IOUT (mA) Figure 27. IDD Histogram with Internal Reference, VREF = 2.5 V, Gain = 2 10800-139 HITS 0.02 10800-138 -1 Figure 30. Source and Sink Capability at 3 V 1.0 1.4 0.8 1.2 0.6 0.4 CURRENT (mA) SINKING 5V 0 -0.2 SOURCING 5V -0.4 1.0 ZERO CODE 0.8 0.6 EXTERNAL REFERENCE, FULL-SCALE 0.4 -0.6 -1.0 0 5 10 15 20 25 LOAD CURRENT (mA) 30 0 -40 10 60 TEMPERATURE (C) Figure 31. Supply Current vs. Temperature Figure 28. Headroom/Footroom vs. Load Current Rev. B | Page 14 of 28 110 10800-140 0.2 SOURCING 2.7V -0.8 10800-200 VOUT (V) SINKING 2.7V 0.2 FULL-SCALE Data Sheet AD5317R 4.0 3.5 2.5008 DAC A DAC B DAC C DAC D 3.0 2.5003 VOUT (V) VOUT (V) 2.5 2.0 2.4998 2.4993 CHANNEL B TA = 25C VDD = 5.25V INTERNAL REFERENCE = 2.5V CODE = 7FFF TO 8000 ENERGY = 0.227206nV-sec 2.4988 2 0 4 6 VDD = 5V 0.5 TA = 25C INTERNAL REFERENCE = 2.5V 1/4 TO 3/4 SCALE 0 10 20 40 80 160 10800-141 1.0 320 TIME (s) 12 Figure 35. Digital-to-Analog Glitch Impulse 0.06 0.003 6 CH A CH B CH C CH D VDD CH B CH C CH D 5 4 0.03 3 0.02 2 0.01 1 0 0 VDD (V) 0.04 VOUT AC-COUPLED (V) 0.002 0.001 0 -0.001 -1 15 10 TIME (s) -0.002 0 5 10 15 20 10800-145 5 10800-142 TA = 25C INTERNAL REFERENCE = 2.5V -0.01 -10 -5 0 25 TIME (s) Figure 33. Power-On Reset to 0 V Figure 36. Analog Crosstalk, Channel A 3 CH A CH B CH C CH D SYNC T GAIN = 2 2 VOUT (V) GAIN = 1 1 0 -5 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 0 5 TIME (s) 10 Figure 34. Exiting Power-Down to Midscale VDD = 5V TA = 25C EXTERNAL REFERENCE = 2.5V CH1 2V M1.0s A CH1 802mV Figure 37. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Rev. B | Page 15 of 28 10800-146 1 10800-143 VOUT (V) 10 TIME (s) Figure 32. Settling Time, 5 V 0.05 8 10800-144 1.5 AD5317R Data Sheet 20 T VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 0 -20 THD (dBV) -40 1 -60 -80 -100 -120 -140 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V A CH1 802mV 0 FREQUENCY (Hz) Figure 40. Total Harmonic Distortion @ 1 kHz Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference 4.0 1600 VDD = 5V TA = 25C 1400 INTERNAL REFERENCE = 2.5V 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 10800-149 M1.0s -180 10800-147 CH1 2V -160 FULL-SCALE MIDSCALE ZERO-SCALE 3.9 3.8 0nF 0.1nF 10nF 0.22nF 4.7nF VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 1200 VOUT (V) 800 600 3.6 3.5 3.4 3.3 400 3.2 200 100 1k 10k FREQUENCY (Hz) 100k 1M 3.0 1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 TIME (ms) Figure 41. Settling Time vs. Capacitive Load Figure 39. Noise Spectral Density Rev. B | Page 16 of 28 1.630 10800-150 0 10 3.1 10800-148 NSD (nV/ Hz) 3.7 1000 Data Sheet AD5317R TERMINOLOGY 4B Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 14. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 15. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5317R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 20. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed in percent of full-scale range (% of FSR). A plot of full-scale error vs. temperature can be seen in Figure 19. Gain Error Gain error is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Offset Error Drift Offset error drift is a measurement of the change in offset error with a change in temperature. It is expressed in V/C. Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/C. Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5317R with Code 4 loaded to the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) DC PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in mV/V. VREF is held at 2.5 V, and VDD is varied by 10%. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and is measured from the rising edge of SYNC. E A A Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 35). Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/Hz. A plot of noise spectral density is shown in Figure 39. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in V. DC crosstalk due to load current change is a measurement of the impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in V/mA. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. Rev. B | Page 17 of 28 AD5317R Data Sheet Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC in response to a digital code change and subsequent analog output change of another DAC. It is measured by loading one channel with a full-scale code change (all 0s to all 1s and vice versa) using the write to and update commands while monitoring the output of another channel that is at midscale. The energy of the glitch is expressed in nV-sec. Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Voltage Reference TC Voltage reference TC is a measurement of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/C, as follows: VREFmax - VREFmin 6 TC = x 10 VREFnom x TempRange where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 2.5 V. TempRange is the specified temperature range of -40C to +105C. Rev. B | Page 18 of 28 Data Sheet AD5317R THEORY OF OPERATION 5B DIGITAL-TO-ANALOG CONVERTER The resistor string structure is shown in Figure 43. It is a string of resistors, each of Value R. The code loaded to the DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because the DAC is a string of resistors, it is guaranteed monotonic. 19B The AD5317R is a quad, 10-bit, serial input, voltage output DAC with an internal reference. The part operates from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5317R in a 24-bit word format via a 3-wire serial interface. The AD5317R incorporates a power-on reset circuit to ensure that the DAC output powers up to a known output state. The device also has a software power-down mode that reduces the typical current consumption to typically 4 A. VREF R TRANSFER FUNCTION 20B The internal reference is on by default. Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by R R TO OUTPUT AMPLIFIER D VOUT = VREF x Gain N 2 DAC ARCHITECTURE 21B The DAC architecture consists of a string DAC followed by an output amplifier. Figure 42 shows a block diagram of the DAC architecture. VREF 2.5V REF R R 10800-053 where: D is the decimal equivalent of the binary code that is loaded to the DAC register as follows: 0 to 1023 for the 10-bit device. N is the DAC resolution (10-bits). Gain is the gain of the output amplifier and is set to 1 by default. The gain can be set to x1 or x2 using the gain select pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. When this pin is tied to VDD, all four DAC outputs have a span of 0 V to 2 x VREF. Figure 43. Resistor String Structure Output Amplifiers 43B The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The actual range depends on the value of VREF, the GAIN pin, offset error, and gain error. The GAIN pin selects the gain of the output. * * REF (+) DAC REGISTER RESISTOR STRING REF (-) GND VOUTX GAIN (GAIN = 1 OR 2) 10800-052 INPUT REGISTER If this pin is tied to GND, all four outputs have a gain of 1, and the output range is 0 V to VREF. If this pin is tied to VDD, all four outputs have a gain of 2, and the output range is 0 V to 2 x VREF. The output amplifiers are capable of driving a load of 1 k in parallel with 2 nF to GND. The slew rate is 0.8 V/s with a 1/4 to 3/4 scale settling time of 5 s. Figure 42. Single DAC Channel Architecture Block Diagram Rev. B | Page 19 of 28 AD5317R Data Sheet Table 8. Command Bit Definitions SERIAL INTERFACE 2B The AD5317R has a 3-wire serial interface (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPITM, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The AD5317R contain an SDO pin to allow the user to daisy-chain multiple devices together (see the Daisy-Chain Operation section) or for readback. Command C2 C1 0 0 0 0 E A A C3 0 0 Input Shift Register 4B The input shift register of the AD5317R is 24 bits wide. Data is loaded MSB first (DB23) and the first four bits are the command bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address bits, DAC A, DAC B, DAC C, DAC D (see Table 9), and finally the data-word. The data-word comprises the 10-bit input code, followed by six don't care bits (see Figure 44). These data bits are transferred to the input register on the 24 falling edges of SCLK and are updated on the rising edge of SYNC. 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 1 1 ... 1 1 1 0 0 0 ... 1 1 1 0 0 1 ... 1 0 1 0 1 0 ... 1 Description No operation Write to Input Register n (dependent on LDAC) Update DAC Register n with contents of Input Register n Write to and update DAC Channel n Power down/power up DAC Hardware LDAC mask register Software reset (power-on reset) Internal reference setup register Set up DCEN register (daisy-chain enable) Set up readback register (readback enable) Reserved Reserved No operation, daisy-chain mode E E A A Address Bits DAC C DAC B 0 0 0 1 1 0 0 0 0 1 1 1 DAC D 0 0 0 1 0 1 A Commands can be executed on individual DAC channels, combined DAC channels, or on all DAC channels, depending on the address bits selected (see Table 9). 1 DAC A 1 0 0 0 1 1 C2 Selected DAC Channel 1 DAC A DAC B DAC C DAC D DAC A and DAC B All DACs 17F Any combination of DAC channels can be selected using the address bits. DB23 (MSB) C3 DB0 (LSB) C1 C0 DAC DAC DAC DAC D9 D C B A D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 10800-054 DATA BITS COMMAND BITS A A Table 9. Address Bits and Selected DACs E A C0 0 1 ADDRESS BITS Figure 44. AD5317R Input Shift Register Contents Rev. B | Page 20 of 28 Data Sheet AD5317R STANDALONE OPERATION 23B AD5317R 68HC11* The write sequence begins by bringing the SYNC line low. Data from the SDIN line is clocked into the 24-bit input shift register on the falling edge of SCLK. After the last of the 24 data bits is clocked in, SYNC should be brought high. The programmed function is then executed, that is, an LDAC-dependent change in DAC register contents and/or a change in the mode of operation. If SYNC is taken high before the 24th clock, invalid data may be loaded to the DAC. SYNC must be brought high for a minimum of 20 ns (single channel, see t8 in Figure 2) before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. SYNC should be idled at the rails between write sequences for even lower power operation of the part. The SYNC line is kept low for 24 falling edges of SCLK, and the DAC is updated on the rising edge of SYNC. E A A SDIN MOSI E SCK SCLK PC7 SYNC PC6 LDAC A A E A A SDO MISO E A A E SDIN A A AD5317R E A A SCLK E A A SYNC LDAC E A A SDO E A A After the data is transferred into the input register of the addressed DAC, all DAC registers and outputs can be updated by taking LDAC low while the SYNC line is high. E A SDIN E A A AD5317R A WRITE AND UPDATE COMMANDS SCLK 24B Write to Input Register n (Dependent on LDAC) E 45B SYNC A A Command 0001 allows the user to write to each DAC's dedicated input register individually. When LDAC is low, the input register is transparent (if not controlled by the LDAC mask register). LDAC SDO E A 10800-057 A E A A *ADDITIONAL PINS OMITTED FOR CLARITY. Update DAC Register n with Contents of Input Register n Figure 45. Daisy-Chaining the AD5317R 46B Command 0010 loads the DAC registers/outputs with the contents of the input registers selected and updates the DAC outputs directly. E Write to and Update DAC Channel n (Independent of LDAC) E A Command 0011 allows the user to write to the DAC registers and update the DAC outputs directly. DAISY-CHAIN OPERATION 25B For systems that contain several DACs, the SDO pin can be used to daisy-chain several devices together. This function is enabled through a software executable daisy-chain enable (DCEN) command. Command 1000 is reserved for this DCEN function (see Table 8). The daisy-chain mode is enabled by setting Bit DB0 in the DCEN register. The default setting is standalone mode, where DB0 = 0. Table 10 shows how the state of the bit corresponds to the mode of operation of the device. Table 10. Daisy-Chain Enable (DCEN) Register DB0 0 1 Description Standalone mode (default) DCEN mode A A 47B A The SCLK pin is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO line to the SDIN input on the next DAC in the chain, a daisy-chain interface is constructed. Each DAC in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 x N, where N is the total number of devices that are updated. If SYNC is taken high at a clock that is not a multiple of 24, invalid data may be loaded to the DAC. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. A continuous SCLK source can be used only if SYNC can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. E A A E A E A E A Rev. B | Page 21 of 28 A A A AD5317R Data Sheet READBACK OPERATION Table 11. Modes of Operation Readback mode is invoked through a software executable readback command. If the SDO output is disabled via the daisychain mode disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is disabled again. Command 1001 is reserved for the readback function. This command, in association with selecting one of the address bits, DAC A to DAC D, selects the register to read. Note that only one DAC register can be selected during readback. The remaining three address bits must be set to Logic 0. The remaining data bits in the write sequence are don't care bits. If more than one or no bits are selected, DAC Channel A is read back by default. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. Operating Mode Normal Operation Power-Down Modes 1 k to GND 100 k to GND Three-State 26B 2. PDx0 0 0 1 1 1 0 1 Any or all DACs (DAC A to DAC D) can be powered down to the selected mode by setting the corresponding bits. See Table 12 for the contents of the input shift register during the power-down/power-up operation. When both Bit PDx1 and Bit PDx0 (where x is the channel selected) in the input shift register are set to 0, the part works normally with its normal power consumption of 1.1 mA at 5 V. However, for the three power-down modes, the supply current falls to 4 A at 5 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different power-down options (see Table 11). The output is connected internally to GND through either a 1 k or a 100 k resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 46. For example, to read back the DAC register for Channel A, the following sequence should be implemented: 1. PDx1 0 Write 0x900000 to the AD5317R input register. This configures the part for read mode with the DAC register of Channel A selected. Note that all data bits, DB15 to DB0, are don't care bits. Follow this with a second write, a NOP condition, 0x000000 (0xF00000 in daisy-chain mode). During this write, the data from the register is clocked out on the SDO line. DB23 to DB20 contain undefined data, and the last 16 bits contain the DB19 to DB4 DAC register contents. AMPLIFIER DAC VOUTX POWER-DOWN OPERATION 27B POWER-DOWN CIRCUITRY RESISTOR NETWORK 10800-058 The AD5317R provides three separate power-down modes. Command 0100 is designated for the power-down function (see Table 8). These power-down modes are software programmable by setting eight bits, Bit DB7 to Bit DB0, in the input shift register. There are two bits associated with each DAC channel. Table 11 shows how the state of the two bits corresponds to the mode of operation of the device. Figure 46. Output Stage During Power-Down The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the DAC registers are unaffected when in power-down. The DAC registers can be updated while the device is in power-down mode. The time required to exit power-down is typically 4.5 s for VDD = 5 V. Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation 1 18F DB23 0 DB22 1 DB21 0 DB20 0 Command bits (C3 to C0) 1 DB19 to DB16 X Address bits (don't care) DB15 to DB8 X DB7 PDD1 DB6 PDD0 Power-Down Select DAC D X = don't care. Rev. B | Page 22 of 28 DB5 PDC1 DB4 PDC0 Power-Down Select DAC C DB3 PDB1 DB2 PDB0 Power-Down Select DAC B DB1 PDA1 DB0 (LSB) PDA0 Power-Down Select DAC A Data Sheet AD5317R LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER E 28B E A A A A The AD5317R DAC has double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC register are controlled by the LDAC pin. Command 0101 is reserved for the software LDAC function. Address bits are ignored. Writing to the DAC using Command 0101 loads the 4-bit LDAC register (DB3 to DB0). The default for each channel is 0; that is, the LDAC pin works normally. Setting the bits to 1 forces this DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC pin. This flexibility is useful in applications where the user wishes to select which channels respond to the LDAC pin. E E A A E E A A A A A A OUTPUT AMPLIFIER E VREF VOUTX E A A 10-BIT DAC A A E A A The LDAC mask register gives the user extra flexibility and control over the hardware LDAC pin (see Table 13). Setting the LDAC bits (DB3 to DB0) to 0 for a DAC channel means that this channel's update is controlled by the hardware LDAC pin. DAC REGISTER LDAC E A A E A A E A A INPUT REGISTER E A A Table 13. LDAC Overwrite Definition E A INTERFACE LOGIC 10800-059 A SCLK SYNC SDIN SDO Load LDAC Register E A A LDAC Bits (DB3 to DB0) 0 1 E Figure 47. Simplified Diagram of Input Loading Circuitry for a Single DAC Instantaneous DAC Updating (LDAC Held Low) E 48B A A LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the rising edge of SYNC and the output begins to change (see Table 14). E A A A A LDAC Pin LDAC Operation E A A 1 or 0 X1 E A A Determined by the LDAC pin. DAC channels are updated and override the LDAC pin. DAC channels see LDAC as 1. E A A E A A E A E A A A 1 X = don't care. Deferred DAC Updating (LDAC Is Pulsed Low) E 49B A A LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by taking LDAC low after SYNC has been taken high. The update now occurs on the falling edge of LDAC. E A A E A E A A A E A A Table 14. Write Commands and LDAC Pin Truth Table 1 E A A 19F Hardware LDAC Pin State VLOGIC GND 2 VLOGIC A Command 0001 Description Write to Input Register n (dependent on LDAC) 0010 Update DAC Register n with contents of Input Register n E A A 20F 0011 Write to and update DAC Channel n A E Input Register Contents Data update Data update No change GND No change VLOGIC GND Data update Data update DAC Register Contents No change (no update) Data update Updated with input register contents Updated with input register contents Data update Data update A high to low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When LDAC is permanently tied low, the LDAC mask bits are ignored. 1 Rev. B | Page 23 of 28 AD5317R Data Sheet HARDWARE RESET (RESET) RESET SELECT PIN (RSTSEL) E 30B A A 31B RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the RESET select pin. It is necessary to keep RESET low for a minimum of 30 ns to complete the operation (see Figure 2). When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value while the RESET pin is low. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0110 is designated for this software reset function (see Table 8). Any events on LDAC during a power-on reset are ignored. If the RESET pin is pulled low at power-up, the device does not initialize correctly until the pin is released. E A A E A A E A A E A A The AD5317R contains a power-on reset circuit that controls the output voltage during power-up. By connecting the RSTSEL pin low, the output powers up to zero scale. Note that this is outside the linear region of the DAC. By connecting the RSTSEL pin high, VOUT powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. E A A E A A A E A Rev. B | Page 24 of 28 Data Sheet AD5317R INTERNAL REFERENCE SETUP LONG-TERM TEMPERATURE DRIFT By default, the internal reference is on at power-up. To reduce the supply current, the on-chip reference can be turned off. Command 0111 is reserved for setting up the internal reference. To turn off the internal reference, set the software programmable bit, DB0, in the input shift register using Command 0111, as shown in Table 16. Table 15 shows how the state of the DB0 bit corresponds to the mode of operation. Figure 49 shows the change in the VREF (ppm) value after 1000 hours at 25C ambient temperature. Table 15. Internal Reference Setup Register Internal Reference Setup Register (Bit DB0) 0 1 Action Reference on (default) Reference off 140 INTERNAL REFERENCE DRIFT (PPM) 32B SOLDER HEAT REFLOW 120 100 80 60 40 20 0 As with all IC reference voltage circuits, the reference value experiences a shift induced by the soldering process. Analog Devices, Inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. The output voltage specification in Table 2 includes the effect of this reliability test. Figure 48 shows the effect of solder heat reflow (SHR) as measured through the reliability test (precondition). 60 POSTSOLDER HEAT REFLOW 50 PRESOLDER HEAT REFLOW 0 100 200 300 400 500 600 700 800 900 1000 ELAPSED TIME (Hours) Figure 49. Reference Drift Through to 1000 Hours THERMAL HYSTERESIS Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. Thermal hysteresis data is shown in Figure 50. It is measured by sweeping the temperature from ambient to -40C, then to +105C, and then back to ambient. The VREF delta is then measured between the two ambient measurements (shown in blue in Figure 50). The same temperature sweep and measurements were immediately repeated, and the results are shown in red in Figure 50. 40 HITS -20 10800-249 3B 9 30 8 20 FIRST TEMPERATURE SWEEP SUBSEQUENT TEMPERATURE SWEEPS 7 6 2.498 2.499 2.500 2.501 2.502 VREF (V) HITS 0 10800-060 10 5 4 3 Figure 48. SHR Reference Voltage Shift 2 0 -200 -150 -100 -50 DISTORTION (ppm) 0 50 10800-062 1 Figure 50. Thermal Hysteresis Table 16. 24-Bit Input Shift Register Contents for Internal Reference Setup Command 1 DB23 (MSB) 0 1 DB22 DB21 1 1 Command bits (C3 to C0) DB20 1 DB19 to DB16 X Address bits (don't care) X = don't care. Rev. B | Page 25 of 28 DB15 to DB1 X Don't care DB0 (LSB) 1 or 0 Reference setup register AD5317R Data Sheet APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING LAYOUT GUIDELINES Microprocessor interfacing to the AD5317R is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 3- or 4-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The device requires a 24-bit data-word with data valid on the rising edge of SYNC. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5317R is mounted should be designed so that the AD5317R lies on the analog plane. AD5317R TO ADSP-BF531 INTERFACE The SPI interface of the AD5317R is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 51 shows the AD5317R connected to the Analog Devices, Inc., Blackfin(R) DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5317R. AD5317R In systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. ADSP-BF531 PF9 PF8 SYNC SCLK SDIN LDAC RESET 10800-164 SPISELx SCK MOSI The AD5317R should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply, located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Figure 51. ADSP-BF531 Interface AD5317R TO SPORT INTERFACE The Analog Devices ADSP-BF527 has one SPORT serial port. Figure 52 shows how one SPORT interface can be used to control the AD5317R. AD5317R The AD5317R LFCSP model has an exposed pad beneath the device. Connect this pad to the GND supply for the part. For optimum performance, use special considerations to design the motherboard and to mount the package. For enhanced thermal, electrical, and board level performance, solder the exposed pad on the bottom of the package to the corresponding thermal land pad on the PCB. Design thermal vias into the PCB land pad area to further improve heat dissipation. The GND plane on the device can be increased (as shown in Figure 53) to provide a natural heat sinking effect. AD5317R ADSP-BF527 LDAC RESET GND PLANE Figure 52. SPORT Interface BOARD Figure 53. Pad Connection to Board Rev. B | Page 26 of 28 10800-166 GPIO0 GPIO1 SYNC SCLK SDIN 10800-165 SPORT_TFS SPORT_TSCK SPORT_DTO Data Sheet AD5317R CONTROLLER In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. iCoupler(R) products from Analog Devices provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5317R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 54 shows a 4-channel isolated interface to the AD5317R using an ADuM1400. For further information, visit http://www.analog.com/icouplers . SERIAL CLOCK IN SERIAL DATA OUT SYNC OUT LOAD DAC OUT 1 ADuM14001 VIA VIB VIC VID ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE ADDITIONAL PINS OMITTED FOR CLARITY. Figure 54. Isolated Interface Rev. B | Page 27 of 28 VOA VOB VOC VOD TO SCLK TO SDIN TO SYNC TO LDAC 10800-167 GALVANICALLY ISOLATED INTERFACE AD5317R Data Sheet 3.10 3.00 SQ 2.90 PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 4 5 8 0.50 0.40 0.30 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 56. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5317RBCPZ-RL7 AD5317RBRUZ AD5317RBRUZ-RL7 EVAL-AD5317RDBZ 1 Resolution 10 Bits 10 Bits 10 Bits Temperature Range -40C to +105C -40C to +105C -40C to +105C Accuracy (Typ) 0.12 LSB INL 0.12 LSB INL 0.12 LSB INL Reference Tempco (ppm/C) 5 (max) 5 (max) 5 (max) Z = RoHS Compliant Part. (c)2012-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10800-0-5/17(B) Rev. B | Page 28 of 28 Package Description 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP Evaluation Board Package Option CP-16-22 RU-16 RU-16 Branding DG6