100331SC - Fairchild Semiconductor

Februa ry 199 0

Revised August 2000

100331 Low Power Triple D-Type Flip-Flop

100331

Low Power Triple D-Type Flip-Flop

General Description

The 100331 contains th ree D-type, ed ge-trigger ed master/

slave flip-flops with true and complement outputs, a Com-

mon Cloc k (CPC), a nd Master S et (MS) and M aster Reset

(MR) inputs. Each flip-flop has individual Clock (CPn),

Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters

a master when both CPn and CPC are LOW a nd transfe rs

to a slave when CPn or CPC (or both) go HIGH. The Master

Set, Master Reset and individual CDn and SDn inputs over-

ride the Clock inputs. All inputs have 50 kΩ pull-down

resistors.

Features

■35% power reduction of the 100131

■2000V ESD protection

■Pin/function compatible with 100131

■Voltage compensated operating range = −4.2V to −5.7V

■Available to industrial grade temperature range

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the o rdering c ode.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP/SOIC

28-Pin PL CC

Order Number Package Number Package Description

100331SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

100331PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100331QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100331QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

Pin Names Description

CP0–CP2Individual Clock Inputs

CPCCommon Clock Input

D0–D2Data Inputs

CD0–CD2Individual Direct Clear Inputs

SDnIndividual Direct Set Inputs

MR Master Reset Input

MS Master Set Input

Q0-Q2Data Outputs

Q0–Q2Complementary Data Outputs

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100331

Truth Tables

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Don’t Care

U = Undefined

t = Time before CP Positive Tr a nsiti o n

t + 1 = Time after CP Positive Transition



= LOW-to-H I GH Transition

Logic Diagram

Synchronous Operation (Each Flip-Flop)

Inputs Outputs

DnCPnCPCMS MR Qn(t + 1)

SDnCDn



LLLL



LLLH



LLL



LLH

XLLLLQ

n(t)

XHXLLQ

n(t)

XXHLLQ

n(t)

Asy n chrono us Operation (Each Flip-Flop)

Inputs Outputs

DnCPnCPCMS MR Qn(t + 1)

SDnCDn

XXXHLH

XXXLHL

XXXHHU

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100331

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “A bsolute Maximum Ratings” are those value s beyond whic h

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (N ote 3)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are cho-

sen to guarante e operation under “worst case” conditions.

Storage Temperature (TSTG)−65°C to +150°C

Maximum Junction Temperature (TJ)+150°C

Pin Potential to Ground Pin (VEE)−7.0V to +0.5V

Input Voltage (DC) VEE to +0.5V

Output Current

(DC Output HIGH) −50 mA

ESD (Note 2) ≤ 2000V

Case Temperature (TC)

Commercial 0°C to +85°C

Industrial −40°C to +85°C

Supply Voltage (VEE)−5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1025 −955 −870 mV VIN = VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with

VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V

VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.5 µAV

IN = VIL (Min)

IIH Input HIGH Current 240 µAV

IN = VIH (Max)

IEE Power Supply Current −122 −65 mA Inputs OPEN

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100331

Commercial Version (Continued)

DIP AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

SOIC and PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

fMAX Toggle Frequency 375 375 375 MHz Figures 2, 3

tPLH Propagati on Delay 0.75 2.00 0.75 2.00 0.75 2.00 ns

tPHL CPC to Output Figures 1, 3

tPLH Propagati on Delay 0.75 2.00 0.75 2.00 0.75 2.00 ns

tPHL CPn to Output

tPLH Propagati on Delay 0.70 1.70 0.70 1.70 0.70 1.80 CPn, CPC = L

Figures 1, 4

tPHL CDn, SDn to Output ns

tPLH 0.70 2.00 0.70 2.00 0.70 2.00 CPn, CPC = H

tPHL

tPLH Propagati on Delay 1.10 2.60 1.10 2.60 1.10 2.60 CPn, CPC = L

tPHL MS, MR to Output ns

tPLH 1.10 2.80 1.10 2.80 1.10 2.80 CPn, CPC = H

tPHL

tTLH Transition Time 0.35 1.30 0.35 1.30 0.35 1.30 ns Figures 1, 3, 4

tTHL 20% to 80%, 80% to 20%

tSSetup Time Figure 5

Dn0.40 0.40 0.40 ns

CDn, SDn (Release Time) 1.30 1.30 1.30 Figure 4

MS, MR (Release Time) 2.30 2.30 2.30

tHHold Time Dn0.5 0.5 0.7 ns Figure 5

tPW(H) Pulse Width HIGH

CPn, CPC, CDn, 2.00 2.00 2.00 ns Figures 3, 4

SDn, MR, MS

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

fMAX Toggle Frequency 400 400 400 MHz Figures 2, 3

tPLH Propagation Delay 0.75 1.80 0.75 1.80 0.75 1.80 ns

tPHL CPC to Output Figures 1, 3

tPLH Propagation Delay 0.75 1.80 0.75 1.80 0.75 1.80 ns

tPHL CPn to Output

tPLH Propagation Delay 0.70 1.50 0.70 1.50 0.70 1.60 CPn, CPC =L

Figures 1, 4

tPHL CDn, SDn to Output ns

tPLH 0.80 1.80 0.70 1.80 0.70 1.80 CPn, CPC = H

tPHL

tPLH Propagation Delay 1.10 2.40 1.10 2.40 1.10 2.40 CPn, CPC = L

tPHL MS, MR to Output ns

tPLH 1.10 2.60 1.10 2.60 1.10 2.60 CPn, CPC = H

tPHL

tTLH Tr ansition Time 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 3, 4

tTHL 20% to 80%, 80% to 20%

tSSetup Time Figure 5

Dn0.30 0.30 0.30

CDn, SDn (Release Time) 1.20 1.20 1.20 ns Figure 4

MS, MR (Release Time) 2.20 2.20 2.20

tHHold Time Dn0.5 0.5 0.7 ns Figure 5

tPW(H) Pulse Width HIGH

CPn, CPC, CDn, 2.00 2.00 2.00 ns Figures 3, 4

SDn, MR, MS

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100331

Commercial Version (Continu ed)

Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged dev ice. Th e specif ications apply to any ou tputs s witchin g in the same dire ction either HI GH-to-L OW (tOSHL), or LOW- to-HIGH (tOSLH) , or in op posite

directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by de s ign.

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.75 1.40 0.75 1.40 0.80 1.50 ns Figures 1, 3 PLCC Only

tPHL CPC to Output

tPLH Propagation Delay 0.70 1.40 0.75 1.40 0.80 1.50 ns

tPHL CPn to Output

tPLH Propagation Delay 0.70 1.50 0.70 1.50 0.80 1.60 CPn, CPC =L

Figures 1, 4

tPHL CDn, SDn to Output ns PLCC Only

tPLH 0.80 1.70 0.80 1.70 0.80 1.80 CPn, CPC = H

tPHL PLCC Only

tPLH Propagation Delay 1.10 2.00 1.10 2.00 1.20 2.10 CPn, CPC = L

tPHL MS, MR to Output ns PLCC Only

tPLH 1.20 2.10 1.20 2.10 1.30 2.20 CPn, CPC = H

tPHL PLCC Only

tOSHL Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 100 100 100 ps (Note 4)

Common Clock to Output Path

tOSHL Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 235 235 235 ps (Note 4)

CPn to Output Path

tOSLH Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 120 120 120 ps (Note 4)

Common Clock to Output Path

tOSLH Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 275 275 275 ps (Note 4)

CPn to Output Path

tOST Maximum Skew Opposite Edge ps PLCC Only

Output-to-Output Variation 125 125 125 (Note 4)

Common Clock to Output Path

tOST Maximum Skew Opposite Edge ps PLCC Only

Output-to-Output Variation 265 265 265 (Note 4)

CPn to Output Path

tPS Maximum Skew PLCC Only

Pin (Signal) Transition Variation 90 90 90 ps (Note 4)

Common Clock to Output Path

tPS Maximum Skew PLCC Only

Pin (Signal) Transition Variation 90 90 90 ps (Note 4)

CPn to Output Path

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100331

Industrial Version

PLCC DC Electrical Characteristics (Note 5)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C

Note 5: The specified limits represe nt the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity and guard bandi ng can be achi ev ed by decre asin g t he all owable syste m op era ti ng r anges. Co ndi ti ons fo r t est ing shown in the ta ble s are cho-

sen to guarant ee opera t ion under “worst case” conditions .

PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Symbol Parameter TC = −40°CT

C = 0°C to +85°CUnits Conditions

MinMaxMinMax

VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1095 −1035 mV VIN = VIH (Min) Loading with

VOLC Output LOW Voltage −1565 −1610 mV or VIL (Max) 50Ω to −2.0V

VIH Input HIGH V olta ge −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW V olta ge −1830 −1480 −1830 1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.5 0.5 µAV

IN = VIL (Min)

IIH Input HIGH Current 300 240 µAV

IN = VIH (Max)

IEE Power Supply Current −122 −60 −122 −65 mA Inputs Open

Symbol Parameter TC = −40°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

fMAX Toggle Frequency 375 400 400 MHz Figures 2, 3

tPLH Propagation Delay 0.75 1.80 0.75 1.80 0.75 1.80 ns

tPHL CPC to Output Figures 1, 3

tPLH Propagation Delay 0.70 1.80 0.75 1.80 0.75 1.80 ns

tPHL CPn to Output

tPLH Propagation Delay 0.60 1.50 0.70 1.50 0.70 1.60 CPn, CPC = L

Figures 1, 4

tPHL CDn, SDn to Output ns

tPLH 0.70 1.80 0.70 1.80 0.70 1.80 CPn, CPC = H

tPHL

tPLH Propagation Delay 1.10 2.40 1.10 2.40 1.10 2.40 CPn, CPC = L

tPHL MS, MR to Output ns

tPLH 1.10 2.60 1.10 2.60 1.10 2.60 CPn, CPC = H

tPHL

tTLH Transition Time 0.20 1.40 0.35 1.10 0.35 1.10 ns Figures 1, 3, 4

tTHL 20% to 80%, 80% to 20%

tSSetup Time Figure 5

Dn1.00 0.30 0.30

CDn,SD

n(Release Time) 1.50 1.20 1.20 ns Figure 4

MS, MR (Release Time) 2.50 2.20 2.20

tHHold Time Dn0.7 0.5 0.7 ns Figure 5

tPW(H) Pulse Width HIGH

CPn, CPC, CDn, 2.00 2 .00 2.00 ns Figures 3, 4

SDn, MR, MS

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100331

Test Circuits

FIGURE 1. AC Test Circuit

Notes:

VCC, VCCA = +2V , VEE = −2.5V

L1 and L2 = Equal length 50Ω impedance lines

RT = 50Ω terminator internal to scope

Decoupli ng 0.1 µF from GND to VCC and VEE

All unused outputs are loaded with 50Ω to GND

CL = Fixture and stray capacitance ≤ 3 pF

FIGURE 2. Toggle Frequency Test Ci rcuit

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100331

Switching Waveforms

FIGURE 3. Propagation Delay (Clock) and Transition Times

FIGURE 4. Propagation Delay (Resets)

FIGURE 5. Data Setup and Hold Time

Note:

tS is the minimum time before the transition of the clock that information must be present at the data input.

tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.

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100331

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100331 Low Power Triple D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.