2EDL05 family Datasheet Please read the Important Notice and Warnings at the end of this document Version 2.9
www.infineon.com/gdHalfBridge 1 of 21 2019-01-24
2EDL05 family
2EDL05x06xx family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
Features
• Infineon thin-film-SOI-technology
• Fully operational to +600 V
• Floating channel designed for bootstrap operation
• Output source/sink current capability +0.36 A/-0.7 A
• Integrated Ultra-fast, low RDS(ON) Bootstrap Diode
• Tolerant to negative transient voltage up to -100 V
(Pulse width is up 300 ns) given by SOI-technology
• 10 ns typ., 60 ns max. propagation delay matching
• dV/dt immune ±50 V
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout for both channels
• 3.3 V, 5 V and 15 V input logic compatible
• RoHS compliant
Product summary
V
OFFSET = 620 V max.
I
O+/-
(typ.)
= 0.36 A/0.7 A
V
OUT
= 10 V - 17.5 V
Delay Matching
= 60 ns max.
t
f
/t
r
(typ.)
= 24 ns/48 ns
Package
DSO-14
DSO-8
Potential applications
• Motor drives, General purpose inverters
• Refrigeration compressors, home appliance
• Half-bridge and full-bridge converters in offline AC-DC power supplies for telecom and lighting
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Description
The 2ED05 is a 600-V half-bridge gate driver family. Its Infineon thin-film-SOI technology provides excellent
ruggedness and noise immunity. The Schmitt trigger logic inputs are compatible with standard CMOS or LSTTL
logic down to 3.3 V. The output drivers features a high pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high
side configuration which operates up to 600 V. Additionally, the offline clamping function provides an inherent
protection of the parasitic turn-on by floating gate conditions when IC is not supplied.
Figure 1 Typical application diagram
LIN
HO
VS
LO
GND
To
Load
HIN
VCC
DC-Bus
- DC-Bus
2EDL05x06yy
To Opamp /
Comparator
VB
VB
VCC
µC
PWM_H
PWM_L
GND
+5V
Refer to lead assignments for
correct pin configuration. This
diagram show electrical
connections only. Please refer to
our application notes and design
tips for proper circuit board
layout.
2EDL05 family Datasheet 2 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
Ordering information
Ordering information
Sales Name Special
function
output
current
Target
transistor
typ. LS UVLO-
thresholds
Bootstrap
diode
Package
Evaluation board
2EDL05I06PF
2EDL05I06PJ
deadtime,
interlock
0.5 A
IGBT 12.5 V / 11.6 V
Yes
DSO-8
DSO-14
EVAL-2EDL05I06PF
2EDL05I06BF
–
DSO-8
2EDL05N06PF
2EDL05N06PJ
deadtime,
interlock
MOSFET 9.1 V / 8.3 V DSO-8
DSO-14
Table of contents
Features ........................................................................................................................................ 1
Product summary ........................................................................................................................... 1
Package ......................................................................................................................................... 1
Potential applications ..................................................................................................................... 1
Product validation .......................................................................................................................... 1
Description .................................................................................................................................... 1
Ordering information ...................................................................................................................... 2
Table of contents ............................................................................................................................ 2
1 Block diagram ........................................................................................................................ 3
2 Lead definitions ..................................................................................................................... 3
3 Functional description ............................................................................................................ 4
3.1 Low Side and High Side Control Pins (LIN, HIN)..................................................................................... 4
3.1.1 Input voltage range ............................................................................................................................ 4
3.1.2 Switching levels .................................................................................................................................. 4
3.1.3 Input filter time .................................................................................................................................. 4
3.2 VDD and GND ........................................................................................................................................... 4
3.3 VB and VS (High Side Supplies) ............................................................................................................... 5
3.4 LO and HO (Low and High Side Outputs) ............................................................................................... 5
3.5 Undervoltage lockout (UVLO) ................................................................................................................. 5
3.6 Bootstrap diode ....................................................................................................................................... 5
3.7 Deadtime and interlock function ............................................................................................................ 6
3.8 Tolerant to negative transient voltage on VS pin (-VS) .......................................................................... 6
4 Electrical parameters ............................................................................................................. 9
4.1 Absolute maximum ratings ..................................................................................................................... 9
4.2 Required operation conditions ............................................................................................................. 10
4.3 Operating Range ................................................................................................................................... 10
4.4 Static logic function table ..................................................................................................................... 11
4.5 Static parameters .................................................................................................................................. 11
4.6 Dynamic parameters ............................................................................................................................. 13
5 Timing diagrams ................................................................................................................... 14
6 Package information ............................................................................................................. 17
7 Qualification information ....................................................................................................... 19
8 Related products ................................................................................................................... 19
Revision history............................................................................................................................. 20
2EDL05 family Datasheet 3 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
1 Block diagram
VDD
LO
GND
UV-
DETECT
DELAY
LIN
VS
HO
VB
BIAS NETWORK - VB
COMPA
RATOR
HV LEVEL-SHIFTER
+ REVERSE-DIODE
LATCH
UV-
DETECT
Gate-
Drive
HIN
GND / PGND
LEVEL-
SHIFTER
Gate-
Drive
SO8, 2EDL05x06yF: 500 mA,
Functional options depending on type:
Interlock, Deadtime, Filter times,
Propagation delay
Boostrap diode
VDD
VDD
VDD
Figure 2 Functional block diagram
2 Lead definitions
Table 1 2EDL05 family lead definitions
Pin no.
Name Function
1
VDD
Low-side and logic supply voltage
2 HIN
Logic input for high-side gate driver output (HO), in phase. Schmitt trigger inputs
with hysteresis and pull down
3 LIN
Logic input for low-side gate driver output (LO), in phase. Schmitt trigger inputs
with hysteresis and pull down
4
GND
Low-side gate drive return
5
LO
Low-side driver output
6
VS
High voltage floating supply return
7
HO
High-side driver output
8
VB
High-side gate drive floating supply
Figure 3 2EDL05 family lead assignments (top view)
VDD
1 14
HIN
2 13
3 12
4 11
LIN
5 10
6 9
7 8
GND
LO
nc
nc
1 8
2 7
3 6
4 5
2EDL (SO8) 2EDL (0.5A, SO14)
nc
VB
HO
VS
nc
nc
nc
VDD VB
HIN HO
VS
LIN
GND LO
2EDL05 family Datasheet 4 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
3 Functional description
3.1 Low Side and High Side Control Pins (LIN, HIN)
3.1.1 Input voltage range
All input pins have the capability to process input voltages up to the supply voltage of the IC. The inputs are
therefore internally clamped to VDD and GND by diodes. An internal pull-down resistor is high ohmic, so that it
can keep the IC in a safe state in case of PCB crack.
3.1.2 Switching levels
The Schmitt trigger input threshold is such to guarantee LSTTL and CMOS compatibility down to 3.3 V controller
outputs. The input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses
according to Figure 4 and Figure 5. Please note, that the switching levels of the input structures remain constant
even though they can accept amplitudes up to the IC supply level.
Figure 4 Input pin structure
3.1.3 Input filter time
Figure 5 Input filter timing diagram
Short pulses are suppressed by means of an input filter. All IC, which have undervoltage lockout (UVLO)
thresholds for MOSFET, have an input filter time of tFILIN = 75 ns typ. and 150 ns max. All IC having UVLO thresholds
for IGBT have filter times of tFILIN = 150 ns min and 200 ns typ.
3.2 VDD and GND
VDD is the low side supply and it provides power to both the input logic and the low side output power stage.
The input logic is referenced to GND ground as well as the under-voltage detection circuit. Output power stage
is also referenced to GND ground.
The undervoltage lockout circuit enables the device to operate at power on when a typical supply voltage higher
than VDDUV+ is present. Please see section 3.5 “Undervoltage lockout” for further information.
VZ=5.25 V
INPUT
NOISE
FILTER
VIH; VIL
ILIN
IHIN
LINx
HINx
Vcc
2EDL-family
LIN HIN
LIN
LO HO
LO
high
low
t
FILIN
t
FILIN
a) b)
2EDL05 family Datasheet 5 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
A filter time of typ. 1.8µs1 helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at
the supply pins will avoid parasitic UVLO events.
3.3 VB and VS (High Side Supplies)
VB to VS is the high side supply voltage. The high side circuit can float with respect to GND following the external
high side power device emitter/source voltage. Due to the low power consumption, the floating driver stage can
be supplied by bootstrap topology connected to VDD. A filter time of typ. 1.8µs1 helps to suppress noise from the
UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO events.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VDDUV+ is present. Please see section 3.5 “Undervoltage lockout” for further information. Details on bootstrap
supply section and transient immunity can be found in application note EiceDRIVER™ 2EDL family: Technical
description.
3.4 LO and HO (Low and High Side Outputs)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive for IGBT
and MOSFET devices. Low side output is state triggered by the respective input, while high side output is edge
triggered by the respective input. In particular, after an undervoltage condition of the VBS supply, a new turn-on
signal (edge) is necessary to activate the high side output. In contrast, the low side outputs switch to the state of
their respective inputs after an undervoltage condition of the VDD supply.
The output current specification IO+ and IO- is defined in a way, which considers the power transistors miller
voltage.This helps to design the gate drive better in terms of the application needs. Nevertheless, the devices are
also characterised for the value of the pulse short circuit value IOpk+ and IOpk–.
3.5 Undervoltage lockout (UVLO)
Two different UVLO options are required for IGBT and MOSFET. The types 2EDL05I06Px and 2EDL05I06BF are
designed to drive IGBT. There are higher levels of undervoltage lockout for the low side UVLO than for the high
side. This supports an improved start up of the IC, when bootstrapping is used. The thresholds for the low side
are typically VDDUV+ = 12.5 V (positive going) and VDDUV– = 11.6 V (negative going). The thresholds for the high side
are typically VBSUV+ = 11.6 V (positive going) and VBSUV– = 10.7 V (negative going).
The types 2EDL05N06Px are designed to drive power MOSFET. A similar distinction for the high side and low side
UVLO threshold as for IGBT is not realised here. The IC shuts down all the gate drivers power outputs, when the
supply voltage is below typ. VDDUV- = 8.3 V (min. / max. = 7.5 V / 9 V). The turn-on threshold is typ. VDDUV+ = 9.1 V (min.
/ max. = 8.3 V / 9.9 V)
3.6 Bootstrap diode
An ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential
resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor
initially.
1 Not subject of production test, verified by characterisation
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
3.7 Deadtime and interlock function
The IC provides a hardware fixed deadtime. The deadtime is different for the two MOSFET types (2EDL05N06Px)
and for the two IGBT types (2EDL05I06Px). The deadtimes are particularly typ. 380 ns for IGBT and typ. 75 ns for
MOSFET. An additional interlock function prevents the two outputs from being activated simultaneously.
The part 2EDL05I06BF does not have the deadtime feature and also not the interlock function. Here, the two
outpus can be activated simultaneously.
3.8 Tolerant to negative transient voltage on VS pin (-VS)
A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power switches transition on and off quickly while carrying a large current. A typical three phase
inverter circuit is shown in Figure 6; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 7 and 8) switches off, while the U phase current is flowing to
an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the
low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC
bus voltage to the negative DC bus voltage.
Figure 6 Three phase inverter
Figure 7 Q1 conducting Figure 8 D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 9 and 10), and Q4
IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,
swings from the positive DC bus voltage to the negative DC bus voltage.
Input
Voltage
DC+ BUS
To
Load
Q1
Q2
Q3
Q4
Q5
Q6
D1
D2
D3
D4
D5
D6
UVW
DC- BUS
V
S1
V
S2
V
S3
Q1
ON
D2
VS1
Q2
OFF
IU
DC+ BUS
DC- BUS
DC+ BUS
Q1
OFF
D1
D2
DC- BUS
V
S1
Q2
OFF
I
U
2EDL05 family Datasheet 7 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
Figure 9 D3 conducting Figure 10 Q4 conducting
However, in a real inverter circuit the VS voltage swing does not stop at the level of the negative DC bus but
instead swings below the level of the negative DC bus. This undershoot voltage is called “negative transient
voltage”.
The circuit shown in Figure 11 depicts one leg of the three phase inverter; Figures 12 and 13 show a simplified
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit
from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch
is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic
elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the
low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures).
This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative
voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS
pin).
Figure 11 Parasitic Elements Figure 12 VS positive Figure 13 VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt
is greater than in normal operation.
Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
indication of the 2EDL05 family’s robustness can be seen in Figure 14, where the 2EDL05 Safe Operating Area is
shown at VBS=15 V based on repetitive negative VS spikes. A negative transient voltage falling in the grey area
DC+ BUS
Q3
OFF
D3
D4
DC- BUS
V
S2
Q4
OFF
I
V
DC+ BUS
Q3
OFF
D3
DC- BUS
V
S2
Q4
ON
I
V
DC+ BUS
D1
D2
DC- BUS
V
S1
Q1
Q2
L
C1
L
E1
L
C2
L
E2
DC+ BUS
DC- BUS
Q1
ON
D2
Q2
OFF
VS1
VLC1
+
-
VLE1
+
-
IU
DC+ BUS
Q1
OFF
D1
DC- BUS
Q2
OFF
V
S1
V
LC2
-
+
V
LE2
-
+
I
U
V
D2
-
+
2EDL05 family Datasheet 8 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent
damage to the IC do not appear if negative VS transients fall inside the SOA.
Figure 14 Negative transient voltage SOA on VS pin for 2EDL05 family @ VBS=15 V
Even though the 2EDL05 family has been shown to be able to handle these large negative transient voltage
conditions, it is highly recommended that the circuit designer always limit the negative transient voltage on VS
pin as much as possible by careful PCB layout and component use.
2EDL05 family Datasheet 9 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
4 Electrical parameters
4.1 Absolute maximum ratings
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C).
Table 2 Absolute maximum ratings
Parameter
Symbol Min. Max. Unit
High side offset voltage
1
VS
V
DD-
V
BS-6 600 V
High side offset voltage (
tp<300ns)1 VDD -VBS –
100
–
High side offset voltage
1
V
B
V
DD
– 6
620
High side offset voltage (
tp<300ns)1 VDD – 100 –
High side floating supply voltage (
VB vs. VS) (internally
clamped)
VBS -1 20
High side output voltage (V
HO
vs. V
S
)
V
HO
-0.5
V
B
+ 0.5
Low side supply voltage (internally clamped)
VDD -1 20
Low side output voltage (
VLO
vs.
VGND
)
VLO
-0.5
VGND
+ 0.5
Input voltage LIN,HIN
V
IN
-0.5
V
DD
+ 0.5
Power dissi
pation (to package)2 DSO8
DSO14
P
D
–
–
0.6
0.85
W
Thermal resistanc
e DSO8
(junction to ambient, see section
6) DSO14
Rth(j-a)
–
–
195
139
K/W
Junction temperature
3 TJ – 150 °C
Storage temperature
TS
- 40
150
offset voltage slew rate
4
dV
S
/dt
–
50 V/ns
1 In case VDD > VB there is an additional power dissipation in the internal bootstrap diode between pins VDD and VB in case of activated
bootstrap diode. Insensitivity of bridge output to negative transient voltage up to –100V is not subject to production test – verified by
design / characterization.
2 Consistent power dissipation of all outputs. All parameters are inside operating range.
3 Qualification stress tests cover a max. junction temperature of 150°C for 1000 h.
4 Not subject of production test, verified by characterisation.
2EDL05 family Datasheet 10 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
4.2 Required operation conditions
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C).
Table 3 Required Operation Conditions
Parameter Symbol Min. Max. Unit
High side offset voltage1 VB
7
620
V
Low side supply voltage (internally clamped)
VDD 10 20
4.3 Operating Range
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C)
Table 4
Operating range
Parameter
Symbol
Min.
Max.
Unit
High side floating supply
offset voltage VS VDD - VBS
-1
500
V
High side floating supply offset voltage (
VB vs. VDD, statically) VBDD -1.0 500
High side floating supply voltage (
VB vs. VS)1
IGBT-Types
VBS 13 17.5
MOSFET-Types
10 17.5
High side output voltage (
VHO vs. VS) VHO 0 VBS
Low side output voltage (
VLO
vs.
VGND
)
VLO 0 VDD
Low side supply
voltage
IGBT-Types
V
DD
13 17.5
MOSFET-Types 10 17.5
Logic input voltages LIN,HIN
2
VIN 0 17.5
Pulse width for ON or OFF
3
IGBT-Types
t
IN 0.8 – µs
MOSFET-Types 0.3 –
Ambient temperature
Ta -40 105 °C
Thermal coefficient
DSO8
(junction to top, see section 6) DSO14
Ψ
th(j-top)
–
–
8.0
6.0
K/W
1 Logic operational for VB (VB vs. VGND) > 7.0 V.
2 All input pins (HIN, LIN) are internally clamped (see abs. maximum ratings).
3 The input pulse may not be transmitted properly in case of input pulse width at LIN and HIN below 0.8µs (IGBT types) or 0.3 µs
(MOSFET) respectively.
2EDL05 family Datasheet 11 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
4.4 Static logic function table
VDD
VBS
LO
HO
<
V
DDUV– X 0 0
15V
<V
BSUV–
LIN
0
15V
15V
0
0
15V
15V
0
0
15V 15V LIN HIN
all voltages with reference to GND
4.5 Static parameters
VDD = VBS = 15V unless otherwise specified. (Ta=25°C).
Table 5
Static parameters
Parameter
Symbol
Values
Unit Test
condition
Min. Typ. Max.
High level input voltage
VIH 1.7 2.1 2.4 V
Low level input voltage
V
IL
0.7 0.9 1.1
High level output voltage
LO
HO
VOH –
–
VDD -0.45
VB -0.45
VDD -1
VB -1
IO = - 20 mA
Lo
w level output voltage LO
HO
VOL –
–
VGND+0.13
VS+0.13
VGND+0.3
VS +0.3
IO = 20 mA
V
DD supply undervoltage
positive going threshold
IGBT-types
VDDUV+ 11.8 12.5 13.2
MOSFET types
8.3 9.1 9.9
V
BS supply undervoltage
positive going threshold
IGBT-types VBSUV+ 10.9 11.6 12.4
MOSFET types
8.3 9.1 9.9
V
DD supply undervoltage
negative going threshold
IGBT-types
VDDUV– 10.9 11.6 12.4
MOSFET types 7.5 8.3 9
V
BS supply undervoltage
nega
tive going threshold
IGBT-types
VBSUV– 10 10.7 11.7
MOSFET types
7.5 8.3 9
V
DD and VBS supply UVLO
hysteresis
IGBT-types VDDUVH
VBSUVH
0.5 0.9 –
MOSFET types
0.5 0.9 –
High side leakage current betw. VS and
GND
ILVS+ – 1 12.5 µA VS = 600V
High side leakage current betw. VS and
GND
ILVS+ 1 – 10 – TJ = 125 °C,
VS = 600 V
Quiescent current
VBS supply (VB only) IQBS1 – 170 300 HO = low
depending on
current types
Quiescent current
VBS supply (VB only) IQBS2 – 170 300 HO = high
depending on
current types
Quiescent current VDD supply (VDD only)
IQDD1
– 0.3 0.6 mA VLIN = float.
1 Not subject of production test, verified by characterisation
2EDL05 family Datasheet 12 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
Table 5
Static parameters
Parameter
Symbol
Values
Unit Test
condition
Min. Typ. Max.
Quiescent current VDD supply (VDD only)
IQDD2 – 0.28 0.6 VLIN = 3.3 V,
VHIN=0
Quiescent current VDD supply (VDD only)
IQDD3 – 0.28 0.6 VLIN=0 , VHIN=3.3
V
Input bias current
ILIN+ 15 35 60 µA VLIN = 3.3 V
Input bias current
ILIN– – 0 – VLIN = 0
Input bias current
IHIN+ 15 35 60 VHIN = 3.3 V
Input bias current
I
HIN–
– 0 – VHIN = 0
Mean output current for load capacity
charging in range from 3 V (20%) to 6
V
(40%)
IO+ 0.18 0.23 – A CL = 22 nF
Peak output current turn on (single pulse)
IOpk+1 – 0.36 – RL = 0 Ω, tp <10 µs
Mean output current for load capacity
discharging in range
from 12 V (80%) to 9 V
(60%)
IO– 0.39 0.48 – CL = 22 nF
Peak output current turn off (single pulse)
IOpk–1 – 0.70 – RL = 0 Ω, tp <10 µs
Bootstrap diode forward
voltage between
VDD and VB
V
F,BSD – 1.0 1.2 V IF = 0.3 mA
Bootstrap diode forward
current between
VDD and VB
I
F,BSD 30 55 80 mA VDD – VB = 4 V
Bootstrap diode resistance
RBSD 20 36 54 Ω VF1 = 4 V, VF2 = 5 V
1 Not subject of production test, verified by characterisation
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
4.6 Dynamic parameters
VDD = VBS = 15 V, VS = VGND, CL = 180 pF unless otherwise specified. (Ta=25°C).
Table 6
Dynamic parameters
Parameter
Symbol
Values Unit Test
condition
Min.
Typ.
Max.
Turn
-on propagation
delay
IGBT types
t
on
280 420 610 ns
V
LIN/HIN
= 0 or 3.3
V
MOSFET types 210 310 460
Turn
-off propagation
delay
IGBT types
toff 260 400 590
MOSFET types 200 300 440
Turn
-on rise time tr – 48 80 VLIN/HIN = 0 or 3.3
V
CL = 1 nF
Turn
-off fall time tf – 24 40
Input filter time at
LIN/HIN for turn on and
off
IGBT types
tFILIN 120 192 – VLIN/HIN = 0 & 3.3
V
MOSFET types
HIN
LIN
50
100
100
150
170
250
Dead time
(not for 2EDL05I06BF)
IGBT types DT 260 380 540 ns VLIN/HIN = 0 & 3.3
V
MOSFET types 30 75 140
Dead time matching
abs(DT_LH
– DT_HL)
for single IC (not for
2EDL05I06BF)
IGBT types MDT – 10 80 ext. dead time
0ns
MOSFET types 10 50
Matching delay ON, abs(ton_HS
- ton_LS) MTON – 10 60 external dead
time > 500 ns
Matching delay OFF, abs(toff_HS
-toff_LS) MTOFF – 10 60 external dead
time >500 ns
Output pulse width
matching. PW
in-PWout
IGBT types
PM – 20 80 PWin > 1 µs
MOSFET types – 20 70
2EDL05 family Datasheet 14 of 21 Version 2.9
www.infineon.com/gdHalfBridge 2019-01-24
2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
5 Timing diagrams
Figure 15 Timing of short pulse suppression
Figure 16 Timing of of internal deadtime
LIN
HIN
HO
LO
1.65V 1.65V
80%
20% 20%
80%
PW
OUT
t
on
t
off
t
r
t
f
PW
IN
Figure 17 Input to output propagation delay times and switching times definition
HIN/LIN
HIN/LIN
HO/LO
HO/LO
low
t
IN
< t
FILIN
t
IN
t
IN
> t
FILIN
t
FILIN
t
IN
HIN/LIN
HIN/LIN
HO/LO
HO/LO
high
t
FILIN
t
IN
< t
FILIN
t
IN
t
IN
> t
FILIN
t
IN
LIN1,2,3
HIN1,2,3
HO1,2,3
LO1,2,3
12 V
3V
3V
12V
1.65V 1.65V
DT DT
2EDL05 family Datasheet 15 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
Figure 18 Operating areas (IGBT UVLO levels)
Figure 19 Operating areas (MOSFET UVLO levels)
HIN/LIN
HO/LO
PWIN
PWOUT
MTon
PM = PWIN - PWOUT
HIN/LIN PWIN
HO/LO
MToff
PM = PWIN - PWOUT
PWOUT
Figure 20 Output pulse width timing and matching delay timing diagram for positive logic
2EDL05 family Datasheet 17 of 21 Version 2.9
www.infineon.com/gdHalfBridge 2019-01-24
2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
6 Package information
Max. reflow solder temperature: 265°C acc. JEDEC
Max. wave solder temperature: 245°C acc. JEDEC
Figure 22 Package outline PG-DSO-8
Figure 23 PCB reference layout
left: Reference layout
right: detail of footprint
The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is
measured. The junction temperature is
j=
Ψ
th(j-top) ∙
+
top
Table 7
Data of reference layout
Dimensions
Material
Metal (Copper)
76.2
× 114.3 × 1.5 mm³ FR4 (λtherm = 0.3 W/mK) 70µm (λtherm = 388 W/mK)
2EDL05 family Datasheet 18 of 21 Version 2.9
www.infineon.com/gdHalfBridge 2019-01-24
2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
Max. reflow solder temperature: 265°C acc. JEDEC
Max. wave solder temperature: 245°C acc. JEDEC
Figure 24 Package outline PG-DSO-14
Figure 25 PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint
The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is
measured. The junction temperature is
j=
Ψ
th(j-top) ∙
+
top
Table 8
Data of reference layout
Dimensions
Material
Metal (Copper)
76.2
× 114.3 × 1.5 mm³ FR4 (λtherm = 0.3 W/mK) 70µm (λtherm = 388 W/mK)
2EDL05 family Datasheet 19 of 21 Version 2.9
www.infineon.com/gdHalfBridge 2019-01-24
2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
7 Qualification information1
Table 9 Qualification information
Qualification level
Industrial2
Note: This family of ICs has passed JEDEC’s Industrial
qualification. Consumer qualification level is granted by
extension of the higher Industrial level.
Moisture sensitivity level DSO-8/-14
MSL33, 260°C
(per IPC/JEDEC J-STD-020)
ESD
Charged device model
Class C3 (> 1.0 kV)
(per JESD22-C101)
Human body model Class 2
(per JEDEC standard JESD22-A114)
IC latch-up test Class II Level A
(per JESD85)
RoHS compliant
Yes
8 Related products
Table 10
Product
Description
Gate Driver ICs
6EDL04I06
/
6EDL04N06
600 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low R
DS(ON)
bootstrap
diodes with over-current protection (OCP), 240/420 mA source/sink current drive, Fault reporting,
and Enable for MOSFET or IGBT switches.
2EDL23I06 /
2EDL23N06
600 V, Half-bridge thin-film SOI level shift gate driver with integrated high speed, low
RDSON bootstrap diode, with over-current protection (OCP), 2.3/2.8 A source/sink current driver,
and one pin Enable/Fault function for MOSFET or IGBT switches.
Power Switches
IKD04N60R / RF
600 V TRENCHSTOP™ IGBT with integrated diode in PG-TO252-3 package
IKD06N65ET6
650 V TRENCHSTOP™ IGBT with integrated diode in DPAK
IPD65R950CFD
650 V CoolMOS CFD2 with integrated fast body diode in DPAK
IPN50R950CE
500 V CoolMOS CE Superjunction MOSFET in PG-SOT223 package
iMOTION™ Controllers
IRMCK099
iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field Oriented Control
(FOC) for Permanent Magnet Synchronous Motors (PMSM).
IMC101T
High performance Motor Control IC for variable speed drives based on field oriented control (FOC)
of permanent magnet synchronous motors (PMSM).
1 Qualification standards can be found at Infineon’s web site www.infineon.com
2 Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales
representative for further information.
3 Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for
further information.
2EDL05 family Datasheet 20 of 21 Version 2.9
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2EDL05 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode
Revision history
Document version
Date of release
Description of changes
0.85
2013-04-16 Change term VCC in VDD
2.
6 2016-06-01 Update maximum Ta from 95oC to 105oC in Table 3
2.7
2016
-
08
-
18
Updated disclaimer, trademarks. Upated parameter V
HO
2.8
2018
-
11
-
19
Updated ESD HBM information
2.9
2019-01-24 Updated Chapter 3.8 Tolerant to negative transient voltage on VS pin
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2019 Infineon Technologies AG.
All Rights Reserved.
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document?
Email: erratum@infineon.com
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2019-01-24
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