ANALOG LC7M0S DEVICES High Speed 4- and 8-Channel 8-Bit ADCs AD7824/AD7828 1.1 Scope. This specification covers the detail requirements of 4- and 8-channel high speed 8-bit A/D converters. The AD7824 provides 4 multiplexed analog inputs, while the AD7828 provides 8. A haif-flash conversion technique gives a conversion rate of 2.5s per channel and the parts have a built-in track/hold function capable of digitizing full-scale signals of up to 10kHz on all channels. 1.2 Part Number. The complete part numbers per Table 1 of this specification are as follows: Device Part Number! -1 AD7824TQ/883B and AD7828T(X)883B -2 AD7824UQ/883B and AD7828U(X)883B NOTE See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: Q-24 for AD7824 (X) Package Description Q Q-28 28-Pin Cerdip E E-28A 28-Contact LCC 1.3 Absolute Maximum Ratings. (T= + 25C unless otherwise noted) Vpp .- ee ee ce ee es OV, +7V Digital Input Voltage to GND (RD, CS, AO, AL & A2) 2... ee eee ~0.3V, Vpp Digital Output Voltage to GND (DBO, DB7, RDY & INT) ........-.20006- ~0.3V, Vpp VreF (+)tOGND 2.2.0. ee ee ee eee es Veer (-), Vpp Vrer(~)TOGND . 2... ee ee OV, Vrer (+) Analog Input (Any Channel) 2... 1... ee tt te tee ~0.3V, Vpp Operating Temperature Range 2... ees 55C to +125C Storage Temperature Range... 1. 1. et ees 65C to + 150C Lead Temperature (Soldering 10sec) 2... 2. ee ee ee ee ee + 300C Power Dissipation Upto +78 2. ee ee ee 450m W Derates above +75C by 2... ee ee 6m WC 1.5 Thermal Characteristics. Thermal Resistance 6j = 35C/W for Q-24, Q-28 and E-28A 8yq = 120C/W for Q-24, Q-28 and E-28A REV. A ANALOG-TO-DIGITAL CONVERTERS 6-147 RS ANALOG-TO-DIGITAL CONVERTEAD7824/AD7828 SPECIFICATIONS Table 1. Design Sub | Sub | Sub Limit Group] Group| Group Test Symbol] Device | TnieT, 1 2,3 4 Test Condition! Units Resolution RES |-1,2 /8 This is the minimum resolu- | Bits tion for which no missing codes are guaranteed. Total Unadjusted Error TUE |-1 1 1 1 +LSB max -2 172 1 V2 12 Analog Input Voltage Range Vin -1,2 | Vrer(-) Vmin Vrer(+) Vmax Analog Input Leakage Current In -1,2 |3 3 3 (Any Channel) +pA max Analog Input Capacitance -1,2 | 45 OVto +5V pF typ Reference Input Resistance Rm -1,2 [1 1 1 kN min 4 4 4 kN max Digital Input High Level View -1,2 | 2.4 24 | 24 AO, Al & A2,RD,CS Vmin Digital Input Low Level Vin -1,2 | 0.8 08 | 0.8 AO, Al & A2, RD, CS V max Digital Input High Current Im -1,2 | 1.0 1.0 1.0 CS, RD, AO, Al & A2 pA max Digital Input Low Current In ~1,2 | -10 -1.0 | -1.0 CS, RD, AO, Al & A2 pA max Digital Input Capacitance Cr -1,2 | 8.0 CS, RD, AO, Al & A2 pF max Digital Output High Level Von | -1,2 | 40 4.0 | 4.0 DBO-DB7, INT Vmin source = 360pA Digital Output Low Level Vor -1,2 | 0.4 0.4 =| 0.4 DBO-DB7, INT V max Is~x = 1.6mA Digital Output Low Level? Vor -1,2 | 0.4 0.4 0.4 RDY; Isnvx = 2.6mA V max Floating State LeakageCurrent |Ioyur | -1,2 | 3.0 3.0 | 3.0 DBO-DB7 pA max Digital Output Capacitance Cour | -1,2 | 8.0 pF max Slew Rate, Tracking -1,2 | 0.157 V/us max Supply Current from Vpp Ipp -1,2 | 16.0 20.0 | 20.0 CS = RD= 2.4V mA max Power Supply Sensitivity -1,2 | 14 1/4 4 Vpp = 5V +5% + LSB max CS to RD Setup Time tcs -1,2 |0 ns min CS to RD Hold Time tcso | -1,2 | 0 ns min. CS to RDY Delay. Pull-Up Resistor 5k troy -1,2 | 60 40ns max at + 25C ns max Conversion Time, Mode 0 tcrp ~1,2 | 2.8 2.0 2.8 2.0us max at + 25C ps max Data Access Time after RD* tacc: | 1,2 | 120 85ns maxat + 25C ns max RD to INT Delay* tntn | 1,2 | 100 75ns max at + 25C ns max Data Hold Time tou -1,2 | 70 60ns max at + 25C ns max Delay Time Between Conversions | tp -1,2 | 600 500ns min at + 25C ns min Read Pulse Width, Mode 1 trp -1,2 [80 ns min 400 ns max Data Access Time After INT, , Mode 0* taocz | 1,2 | 70 50ns max at + 25C ns max Multiplexer Address Setup Time | tas -1,2 |0 ns min Multiplexer Address Hold Time | tan -1,2 | 40 ns min NOTES 'Vpp = +5V3 Vanr(+) = +5V; Vagp() = GND = 0V unless otherwise specified . Specifications apply for Mode 0. All input contro! signals are specified with t, = t; = 20ns (i0% to 90% of + 5V) and timed from a voltage level of + 1.6V. Total unadjusted error includes offset, full scale and linearity errors. 3RDY in an open drain output. C= SOpF. 5 Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V, Defined as the time required for the date lines to change 0.5V when loaded with the circuits of Figure 2. 6-148 ANALOG-TO-DIGITAL CONVERTERS REV. AAD7824/AD7828 Test Circuits 5V 5V ks aka DBN DBN DEN 3ks2 100pF 100pF 10pF DGND L Sons DGND L Sacro a. High-Z to Vow b. High-Zto Vo, a.Von to High-Z b. Voz to High-Z Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Data Hold Time Test 3.2.1 Functional Block Diagram and Terminal Assignments. Vaee (+) DB7 - FLASH r DBS _ att Tbe AIN) = rT - 284 = = THREE 468IT AIN4 Sauxe STATE _]Mex oac ORIVERS aoe Vase! +) Vecel+) __ DBS AINS 16 FLesr | pez ADC 0B1 (4LsB) . DBO ADDRESS ; TIMING AND CONTROL int we mr { { J AO Al A2e* RDY ts RD *AD7824 - 4-CHANNEL MUX AD7828 - 8-CHANNEL MUX **A2 - AD7B2B ONLY Q Package (Cerdip) E Package (LCC) 24-PIN 0.3" WIDE 28-PIN 0.8" WIDE ne. wen 2 z z z z Qa an Vv a ane [1 | Voo wt [28) ane 4302 1 #28 27 26 ii AINS (2 23 [NC AINS | 2 27] AINS. AIN2 [I 22] a0 ain | 3 28 | Voo AINZ 5 LJ 25 Ao : Al ans [a | aifar a 25] ao AINT 6 2 NC 7 23 A2 ne [5 | [20] 087 AIN2 | 5 2afat AD7828 ogo 8 TOP VIEW 22 O87 veo [ | AD7#24 19 ] 086 ams | 23] Az TorviEw Ap7e28 bei 9 21 DBE (Not to Scale) oer [7] fe] DBs NCL? TOP VIEW 22} 087 DB2 10 20 DBS (Not to Scale) vez [8 | v7} oes DBO] & 21 | DB6 pe 11 19 DB4 ves [9 | 16 | CS be1 20 | 08S RD | 10 15 ] pov oe2/}10 19 | Daa 12 13 1% 18 16 17 18 ES. * eB INT J 14 | Vaeet +) 0e3|11 lia )es 2 i a an > > GND | 12 13 | Vacel 1 RD | 12 17] RDY INT] 13 16 | Vier +) GND {14 [15] Vneet-) REV. A ANALOG-TO-DIGITAL CONVERTERS 6-149 ANALOG-TO-DIGITAL CONVERTERS aAD7824/AD7828 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (81). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). Von = 5 q A1, R3 FOR PROTECTION ONLY | A2 IS A PULL-UP Rl Tl RS tk al al AIN 4 AIN 3 AIN 2 AIN 1 AD7828 NC TOP VIEW (Not to Scale} DBO DB1 DB2 DB3 AD7824/AD7828 Burn-In Philosophy 2| Vop Al RDY Vaer + Ver - Voo = 5V @ Rt $rz e V4 1001 f 47k AIN 4 Voo AIN 3 NC AIN2 at AIN 1 A2 NC DB7 080 =6AD7824 = DBE pei NottoScalal ope DB2 0B4 OB3 cs aa > 22 Ro ROY 4 4 Int Vaee + GND Veer See P R2 R1 Ban = $10n EIEN 8 wt Ci a = . . takammmerorhe Ta hammrranercac al. Vv 5 < | op OV 5Vv CcSRD ov POWER-UP t-1ws= CONVERT START So \ ge After power-up the device performs a conversion on CS /RD going low. AIN 1 and AIN 4 are tied to ground so the device will output the all zeros code, thus putting the output drive N-channels under maximum stress for the period of burn-in. The pull-up resistor on the Al pin will stress this input inverter during burn-in to show up drifts in input logic threshold. Address input A2 is tied to ground causing the initial conversion to occur on channel 2. CS and RD, require OV to maintain all zeros on the 3-state outputs. Apart from the conversion on power-up the device is burned-in the static mode taking a maximum Ipp of 15mA from the 5V supply. 6-150 ANALOG-TO-DIGITAL CONVERTERS REV. AAD7824/AD7828 REV. A 5.0 Timing and Control. The AD7824/AD7828 have two digital inputs for t for timing and control. These are Chip Select (CS) and Read (RD). A READ operation brings CS and RD low which starts a conversion and latches the multiplexer address inputs (see Table 2). There are two modes of operation as outlined by the timing diagrams of Figures 3 and 4. Mode 0 is designed for microprocessors which can be driven into a WAIT state. A READ operation (i.e., CS and RD are taken low) starts a conversion and data is read when conversion is complete. Mode 1 does not require microprocessor WAIT states. A READ operation initiates a conversion and reads the previous conversion results. Table 2. Truth Table for Input Channel Selection AD7824 AD7828 CHANNEL Al__ AO A2 Al AO 0 0 0 0 0 AIN1 0 1 0 0 1 AIN2 1 0 0 1 0 AIN 3 1 1 0 1 1 AIN 4 1 0 0 AIN 5 1 0 1 AIN6 1 1 0 AIN7 I 1 I AIN 8 5.1 Mode 0. Figure 3 shows the timing diagram for Mode 0 operation. This mode can only be used for microprocessors which have a WAIT state facility, whereby a READ instruction cycle can be extended to accommodate slow memory devices. A READ operation brings CS and RD low, which latches the analog multiplexer address inputs and starts a conversion. The data bus (DB7-DBO) remains in the three-state condition until conversion is complete. There are two converter status outputs on the AD7824/AD7828, interrupt (INT) and ready (RDY) which can be used to drive the microprocessor READY/WAIT input. The RDY is an open drain output (no internal pull-up device) which goes low on the falling edge of CS and RD and goes high impedance at the end of conversion, when the 8-bit conversion result appears on the data outputs. If the RDY output status is not required, then the external pull-up resistor can be omitted. The INT input goes low when conversion is complete and returns high on the rising edge of CS or RD. 5.2 Mode 1. Mode 1 operation is designed for applications where the microprocessor is not forced into a WAIT state. A READ operation takes CS and RD low, which latches the multiplexer address inputs and triggers a conversion (see Figure 4). Data from the previous conversion is read from the three-state data outputs (DB7-DBO). This data may be disregarded if not required. The RDY output (open drain output) is low for the duration of the READ operation and goes high impedance on the rising edge of CS or RD. If the RDY output status is not required, then the external pull-up resistor can be omitted. At the end of conversion INT goes low. A second READ operation is required to access the new conversion result. This READ operation latches a new address into the multiplexer inputs and starts another conversion. INT returns high at the end of the second READ operation, when CS and RD returns high. A delay of 2.5s must be allowed between READ operations. ANALOG-TO-DIGITAL CONVERTERS 6-151 ANALOG-TO-DIGITAL CONVERTERS aAD7824/AD7828 ft tess s [ = tess toon} bee tas jo~ i tas L eu ZZKBXZZ// 77 ZLLLL LLL LLL RDY an int ~ pe troy ~~ tam = - ; Figure 3. Mode 0 Timing Diagram Jp >F - tess Je tro of fetes tess teo } je tr oh f sit 77XEEY 7/777 ri ADDRESS VALID VALID ROY > tan tan INT 6-152 ANALOG-TO-DIGITAL CONVERTERS a taces >| DATA _{ / L - > le ton taces | F al }~- ton f OLD NEW DATA DATA Figure 4. Mode 1 Timing Diagram tern REV. A