G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features : Description :
∗ 262,144 words by 16 bits organization.
∗ Fast access time and cycle time.
∗ Dual
CAS
Input.
∗ Low power dissipation.
∗ Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Refresh and Test Mode Capability.
∗ 512 refresh cycles per 8ms.
∗ Available in 40-Pin 400 mil SOJ and 40/44
Pin TSOP(II)
∗ Single 5.0V±10% Power Supply.
∗ All inputs and Outputs are TTL
compatible.
∗ Extended Data-Out(EDO) Page Mode
operation.
The GLT44016 is a 262,144 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT44016 offers Fast
Page mode with Extended Data Output, and
has both BYTE WRITE and WORD WRITE
access cycles via two
CAS
pins. The
GLT44016 has symmetric address and
accepts 512-cycle refresh in 8ms interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 512 x 16 bits within a page, with cycle
times as short as 10ns.
The GLT44016 is best suited for
graphics, and DSP applications requiring
high performance memories.
HIGH PERFORMANCE 25 28 30 35 40 50
Max.
RAS
Access Time, (tRAC)25 ns 28 ns 30 ns 35 ns 40 ns 50 ns
Max. Column Address Access Time, (tCAA)13 ns 13 ns 16 ns 18 ns 20 ns 25 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC)10 ns 10 ns 12 ns 13 ns 15 ns 20 ns
Min. Read/Write Cycle Time, (tRC)45 ns 45 ns 60 ns 65 ns 70 ns 85 ns
Max.
CAS
Access Time (tCAC)8 ns 8 ns 10 ns 11 ns 12 ns 14 ns
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Configuration :
Pin Descriptions:
Name Function
A0 - A8Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
DQ1 - DQ16 Data Inputs / Outputs
VCC +5V Power Supply
VSS Ground
NC No Connection
GLT44016
SOJ Top View TSOP(Type II)
Top View
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Absolute Maximum Ratings* Capacitance*
TA=25°C, VCC=5V±10%, VSS=0V
Operating Temperature, TA (ambient)
.......................................-0°C to +70°C
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to VSS...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
CIN1
CIN2
COUT
Parameter
Address Input
RAS
,
,
UCAS
,
WE
,
OE
Data Input/Output
Max.
5
7
7
Unit
pF
pF
pF
*Note:Operation above Absolute Maximum Ratings can
abversely affect device reliability. *Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
CAS
means
UCAS
and
LCAS
.
l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
512
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
RAS CLOCK
GENERATOR
Data I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS I/O
BUFFER
MEMORY
ARRAY
REFRESH
COUNTER
.
.
X0 - x8
512 × 16
Y0 - Y8
9
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
OE
WE
RAS
UCAS
VCC
VSS
A0
A1
A7
A8
ADDRESS BUFFERS
AND PREDECODERS ROW
DECODERS
LCAS
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
Truth Table: GLT44016
Function RAS CASL
CASH WE OE ADDRESS DQs Notes
Stanby HH→XH→XX X High-Z
Read: Word L L L HLROW/COL Data Out
Read: Lower Byte L L H H LROW/COL Lower Byte,Data-Out
Upper Byte,High-Z
Read: Upper Byte LHLHLROW/COL Lower Byte,High-Z
Upper Byte,Data-Out
Write: Word(Early
Write) L L L L XROW/COL Data-In
Write: Lower Byte
(Early) L L HLXROW/COL Lower Byte,Data-In
Upper Byte,High-Z
Write: Upper Byte
(Early) LHL L XROW/COL Lower Byte,High-Z
Upper Byte,Data-In
Read Write L L L H→L L→HROW/COL Data-Out,Data-In 1,2
EDO-Page-
Mode Read
1st Cycle
2nd Cycle
L
L
H→L
H→L
H→L
H→L
H
H
L
L
ROW/COL
COL
Data-Out
Data-Out
1
1
EDO-Page-
Mode Write
1st Cycle
2nd Cycle
L
L
H→L
H→L
H→L
H→L
L
L
X
X
ROW/COL
COL
Data-In
Data-In
2
2
EDO-Page-
Mode Read-
Write
1st Cycle
2nd Cycle
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L→H
L→H
ROW/COL
COL
Data-Out,Data-In
Data-Out,Data-In
1,2
1,2
Hidden
Refresh Read
Write
L→H→L
L→H→L
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
Data-Out
Data-In
1
2,3
RAS
-Only Refresh LH H X X ROW High-Z
CBR Refresh H→LL L X X High-Z 4
Notes:
1. These READ cycles may also be BYTE READ cycles (either
UCAS
or
active).
2. These WRITE cycles may also be BYTE READ cycles (either
UCAS
or
active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (
UCAS
or
).
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.
Sym. Parameter Test Conditions Access
Time Min. Typ Max. Unit Notes
ILI Input Leakage Current
(any input pin) 0V ≤ VIN ≤ 5.5V
(All other pins not under
test=0V)
-10 +10 µA
ILO Output Leakage Current
(for High-Z State) 0V ≤ Vout ≤ 5.5V
Output is disabled (Hiz) -10 +10 µA
ICC1 Operating Current,
Random READ/WRITE tRC = tRC (min.) tRAC = 25ns
tRAC = 28ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 50ns
270
270
250
210
190
170
mA 1,2
ICC2 Standby Current,(TTL)
RAS
,
UCAS
,
at VIH
other inputs ≥VSS 4mA
ICC3 Refresh Current,
RAS
-Only
RAS
cycling,
UCAS
,
at VIH
tRC = tRC (min.)
tRAC = 25ns
tRAC = 28ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 50ns
270
270
250
210
190
170
mA 2
ICC4 Operating Current,
EDO Page Mode
RAS
at VIL,
UCAS
,
address cycling:tPC=tPC(min.)
tRAC = 25ns
tRAC = 28ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 50ns
270
270
250
210
190
170
mA 1,2
ICC5 Refresh Current,
CAS
Before
RAS
RAS
,
UCAS
,
address cycling:
tRC=tRC (min.)
tRAC = 25ns
tRAC = 28ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 50ns
270
270
250
210
190
170
mA 1
ICC6 Standby Current, (CMOS)
RAS
≥VCC-0.2V,
UCAS
≥VCC-0.2V,
≥VCC-0.2V,
All other inputs VSS
2mA
VIL Input Low Voltage -1 +0.8 V3
VIH Input High Voltage 2.4 VCC+1 V3
VOL Output Low Voltage IOL = 4.2mA 0.4 V
VOH Output High Voltage IOH = -5.0mA 2.4 V
Notes:
1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open.
2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in
random Read/Write and EDO Fast Page Mode.
3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC
parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 6 -
AC Characteristics
TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V
An initial pause of 100 µs and 8
CAS
-before-
RAS
or
RAS
-only refresh cycles are required after power-up.
25 28 30 35 40 50
Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Read or Write Cycle Time tRC 45 45 60 65 70 85 ns
Read Modify Write Cycle Time tRWC 67 67 79 86 91 106 ns
RAS Precharge Time tRP 15 15 25 25 25 30 ns
RAS Pulse Width tRAS 25 100k 28 100k 30 100k 35 100k 40 100k 50 100k ns
Access Time from RAS tRAC 25 28 30 35 40 50 ns 1,2,3
Access Time from CAS tCAC 8 8 10 11 12 14 ns 1,5,10
Access Time from Column Address tAA 13 13 16 18 20 25 ns 1,5,6
CAS to Output Low-Z tCLZ 0 0 0 0 0 0 ns
CAS to Output High-Z tCEZ 050537383838ns
RAS Hold Time tRSH 777888ns
RAS Hold Time Referenced to OE tROH 447888ns
CAS Hold Time tCSH 25 25 25 30 35 42 ns
CAS Pulse Width tCAS 4 4 4.5 568ns
RAS to CAS Delay Time tRCD 10 17 10 17 10 20 11 24 12 28 13 36 ns
RAS to Column Address Delay Time tRAD 8 12 8 12 8 14 9 17 10 20 11 25 ns 7
CAS to RAS Precharge Time tCRP 555555ns
Row Address Set-Up Time tASR 000000ns
Row Address Hold Time tRAH 446789ns
Column Address Set-Up Time tASC 000000ns
Column Address Hold Time tCAH 445667ns
Column Address to RAS Lead Time tRAL 13 13 16 18 20 25 ns
Column Address Hold Time Referenced to RAS tAR 19 19 25 30 34 35 ns
Read Command Set-Up Time tRCS 000000ns
Read Command Hold Time Referenced to CAS tRCH 000000ns 4
Read Command Hold Time Referenced to RAS tRRH 000000ns 4
Write Command Set-Up Time tWCS 000000ns 8,9
Write Command Hold Time tWCH 445666ns
Write Command Pulse Width tWP 445666ns
Write Command to RAS Lead Time tRWL 777888ns
Write Command to CAS Lead Time tCWL 556777ns
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
AC Characteristics
25 28 30 35 40 50
Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Data Set-Up Time tDS 0 0 0 0 0 0 0 0 ns
Data Hold Time tDH 447888ns
Data Hold Time Referenced to RAS tDHR 19 19 27 32 36 37 ns
RAS to WE E Delay Time tRWD 36 36 43 49 54 64 ns
CAS to WE Delay Time tCWD 19 19 21 23 24 26 ns
Column Address to WE Delay Time tAWD 24 24 27 30 32 37 ns
RAS to CAS Precharge Time tRPC 000000ns
Access Time from CAS Precharge tCPA 15 15 18 20 22 27 ns
EDO Page Mode Cycle Time tPC 10 10 12 13 15 20 ns
EDO Page Mode Read-Modify-Write Cycle Time tPRWC 35 35 39 43 45 50 ns
CAS Precharge Time (EDO Page Mode) tCP 3 3 4.5 568ns
RAS Pulse Width (EDO Page Mode Only) tRASP 25 100k 28 100k 30 100K 35 100k 40 100k 50 100k ns
Access Time from OE tOEA 8 8 10 11 12 14 ns
OE to Data Delay Time tOED 557888ns
OE to Output High-Z tOEZ 373737383808ns
OE Command Hold Time tOEH 556677ns
Data Output Hold after CAS low tDOH 445555ns
RAS to Output High-Z tREZ 373737383838ns
WE to Output High-Z tWEZ 3 10 3 10 3 10 3 10 3 10 3 12 ns
OE to CAS Hold Time tOCH 888888ns
CAS Hold Time to OE tCHO 888888ns
OE Precharge Time tOEP 888888ns
CAS Set-Up Time for CAS -before-RAS Cycle tCSR 5 5 10 10 10 10 ns
CAS Hold Time for CAS -before-RAS Cycle tCHR 6 6 7 8 8 10 ns
Transition Time tT1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 2 50 ns
Refresh Period tREF 888888ms
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 8 -
Notes:
1. Measure with a load equivalent to one TTL inputs and 50 pF.
2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA
dominant.
3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRCD (max.), access time will be
controlled by tCAC.
4. Either tRRH or tRCH must be satisfied for a Read Cycle.
5. Access time is determined by the longest of tCAA, tCAC and tCPA.
6. Assumes that tRAD ≥ tRAD (max.).
7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.)
is specified as a reference point only. If tRAD is greater than the specified tRAD (max.)
limit, the access time is controlled by tCAA and tCAC.
8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
9. tWCS (min.) must be satisfied in an Early Write Cycle.
10. tDS and tDH are referenced to the latter occurrence of
of
WE
.
tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 1.5 ns.
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 9 -
Read Cycle
ROW
ADDRESS COLUMN
ADDRESS
DATA-OUT
t
RC
tRAS tRP
tCRP
tCSH
tRCD tRSH
tCAS
tCRP
tASR tRAH
tRAD tASC tCAHtRAL
tRCH
tRRH
tAR
tRCS
tAA
tOEA
tCEZ
tOEZ
tCAC
tCLZ
tRAC
Don't Care
VIH-
VIL-
RAS
VIH-
VIL-
CAS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VOH-
VOL-
DQ
Early Write Cycle NOTE : DOUT = Open
tRP
t
RC
tCRP
tCSH
tCRP tRCD tRSH
tCAS
tASR
tRAH
tRAD
tASC tCAH tRAL
tCWL
tRWL
tWCR
tWCH
tWP
tWCS
tAR
tDS tDH
tDHR
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
VIH-
VIL-
RAS
VIH-
VIL-
CAS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VIH-
VIL-
DQ
Don't Care
tRAS
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 10 -
Late Write Cycle ( OE Controlled Write) NOTE : DOUT = Open
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
OED
t
OEH
t
DH
COLUMN
ADDRESS
Read - Modify - Write Cycle
t
RP
t
RC
t
CRP
t
CRP
t
RCD
t
RSH
VALID
DATA-OUT
COLUMN
ADDRESS
ROW
ADDR.
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Don't Care
t
RAS
VALID
DATA-IN
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
CSH
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
RAC
t
DH
t
DS
t
OED
t
OEZ
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
Fast Page Read Cycle
t
RASP tRP
tCRP tRCD tCAS
VIH-
VIL-
RAS
VIH-
VIL-
CAS
tCAS
tCAS
tCP tCP
tPC tPC
tRSH
tASR
tRAD
tRAH
tASC tCAH
tCSH
tASC tASC
tCAH tCAH
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQ VIH-
VIL-
ROW
ADDR. COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
Don't Care
tRCS tRCH tRCS tRCS tRCH tRRH
tOEA
tCAC
tOEA
tCAC
tCLZ
tRAC tAA
tOEZ
tOFF
tAA tCLZ tOEZ tOEZtOFF
tOFF
tCLZ
tAA
VALID
DATA-UOT VALID
DATA-UOT VALID
DATA-UOT
Fast Page Write Cycle NOTE : DOUT = Open
t
RASP
t
RP
tCRP tRCD tCAS
VIH-
VIL-
RAS
VIH-
VIL-
CAS
tCAS
tCAS
tCP tCP
tPC tPC
tRSH
tASR
tRAD
tRAH
tASC tCAH
tCSH
tASC tASC
tCAH tCAH
tWCS
tWP
tWCH tWCS tWCStWCH tWCH
tWP tWP
tDS tDS tDStDH tDS tDS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQ VIH-
VIL-
ROW
ADDR. COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
tCWL tCWL tCWL tRWL
tRHCP
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
Fast Page Mode Late Write Cycle
t
RASP
t
RP
tCRP tRCD tCAS
VIH-
VIL-
RAS
VIH-
VIL-
CAS
tCAS
tCAS
tCP tCP
tPC
tRSH
tASC tASC
tCAH tCAH
tDS tDS
tDH tDS tDH
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQ VIH-
VIL-
ROW
ADDR. COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
VALID
DATA-IN
Don't Care
tCSH
tRHCP
tCRP
VALID
DATA-IN VALID
DATA-IN
tASR tRAH
tRAD
tASC
tCAH tRAL
tRCS
tWP tWP tWP
tCWL tCWL tCWL
tRCS tRCS tRWL
tOEH tOEH tOEH
tOED tOED tDH tOED
Hi-Z Hi-Z Hi-Z
Fast Page Read - Modify - Write Cycle
t
RASP
t
RP
VIH-
VIL-
RAS
VIH-
VIL-
CAS
Don't Care
tCSH
tRCD tCAS tCP tCAS
tRSH tCRP
tRAD
tRAH
tASR tASC
tCAH
tASC tCAH tRAL
tPRWC
tRCS
tWP
tCWL
tWP
tCWL
tRWL
tCWD
tAWD
tRWD
tOEA
tCWD
tAWD
tCPWD
tOEA
tOEH
tRAC
tAA
tCAC
tOEZ
tOED
tDS
tDH
tAA
tCAC
tOEZ
tOED
tDS
tDH
tCLZ tCLZ
VALID
DATA-OUT VALID
DATA-IN VALID
DATA-OUT VALID
DATA-IN
ROW
ADDR. COL.
ADDR. COL.
ADDR.
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VI/OH-
VI/OL-
DQ
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 13 -
CAS Before RAS Refresh Cycle
VIH-
VIL-
RAS
tRAS tRAStRP tRP
t
RC
t
RC
tCSR tCSRtCHR tCHRtRPC tRPC tCRP
VIH-
VIL-
CAS
RAS -Only Refresh Cycle
V
IH-
V
IL-
RAS
tRAS tRAS
tRP tRP
t
RC
t
RC
tRPC tCRP
V
IH-
V
IL-
CAS
tCRP
tASR tASRtRAH tRAH
ROW ROW
Address
V
IH-
V
IL-
Hidden Refresh Cycle ( Read )
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
RAC
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
CAC
t
RCS
t
ASC
t
CAH
t
ASR
t
CAH
t
RAD
t
RAL
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
t
RC
t
WHR
t
AA
t
OEA
t
CLZ
t
OFF
t
OEZ
DATA-OUT
OPEN
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 14 -
Hidden Refresh Cycle ( Write ) NOTE : DOUT =Open
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
DH
t
WP
t
WCH
t
WCS
t
ASC
t
CAH
t
ASC
t
CAH
t
RAD
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
DATA-IN
t
RC
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 15 -
CAS - Before RAS Refresh Counter Test Cycle
t
CAS
t
CPT
VIH-
VIL-
RAS
VIH-
VIL-
CAS
t
RP
t
RAS
t
CSR
t
CHR
t
RSH
t
RAL
t
ASC
t
AA
t
CAC
t
RCS
t
RRH
t
RCH
t
WRP
t
WRH
t
WRH
t
WRP
t
OEA
t
CEZ
t
OEZ
t
CLZ
t
RWL
t
CWL
t
WCH
t
WCS
t
WP
t
DS
t
DH
t
RCS
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
DH
t
DS
t
OED
t
OEZ
t
CLZ
t
CAC
t
AA
t
OEA
OPEN
COLUMN
ADDRESS
VALID DATA-OUT
VALID DATA-IN
Don't Care
VALID
DATA-IN
VALID
DATA-OUT
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VOH-
VOL-
DQ
VIH-
VIL-
WE
VIH-
VIL-
OE
VIH-
VIL-
DQ
VIH-
VIL-
WE
VIH-
VIL-
OE
VI/OH-
VI/OL-
DQ
Read Cycle
Write Cycle
Read-Modify-Write
t
CAH
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 16 -
Ordering Information
Part Number
SPEED
POWER
FEATURE
PACKAGE
GLT44016-25J4 25ns Normal EDO 40L 400mil SOJ
GLT44016-28J4 28ns Normal EDO 40L 400mil SOJ
GLT44016-30J4 30ns Normal EDO 40L 400mil SOJ
GLT44016-35J4 35ns Normal EDO 40L 400mil SOJ
GLT44016-40J4 40ns Normal EDO 40L 400mil SOJ
GLT44016-50J4 50ns Normal EDO 40L 400mil SOJ
GLT44016-25TC 25ns Normal EDO 44L 400mil TSOP
GLT44016-28TC 28ns Normal EDO 44L 400mil TSOP
GLT44016-30TC 30ns Normal EDO 44L 400mil TSOP
GLT44016-35TC 35ns Normal EDO 44L 400mil TSOP
GLT44016-40TC 40ns Normal EDO 44L 400mil TSOP
GLT44016-50TC 50ns Normal EDO 44L 400mil TSOP
Parts Numbers (Top Mark) Definition :
GLT 4 40 16 - 40 J4
Note : CÙCDROM , HÙHDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
VOLTAGE
Blank : 5V
L : 3.3V
M : Mix Voltage
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
25 : 25ns
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
G-LINK GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 17 -
Package Information
40/44 Lead Thin Small Outline Package SOJ
40/44 Lead Thin Small Outline Package TSOP(Type II)