General Description
The MAX11301 integrates a PIXI™, 12-bit, multichannel,
analog-to-digital converter (ADC) and a 12-bit, multichan-
nel, buffered digital-to-analog converter (DAC) in a single
integrated circuit. This device offers 20 mixed-signal high-
voltage, bipolar ports, which are configurable as an ADC
analog input, a DAC analog output, a general purpose
input (GPI), a general-purpose output (GPO), or an analog
switch terminal. One internal and two external temperature
sensors track junction and environmental temperature.
Adjacent pairs of ports are configurable as a logic-level
translator for open-drain devices or an analog switch.
PIXI ports provide highly flexible hardware configuration
for 12-bit mixed-signal applications. The MAX11301 is best
suited for applications that demand a mixture of analog and
digital functions. Each port is individually configurable with
up to four selectable voltage ranges within -10V to +10V.
The MAX11301 allows for the averaging of 2, 4, 8, 16, 32,
64, or 128 ADC samples from each ADC-configured port
to improve noise performance. A DAC-configured output
port can drive up to 25mA. The GPIO ports can be pro-
grammed to user-defined logic levels, and a GPI coupled
with a GPO forms a logic-level translator.
Internal and external temperature measurements monitor
programmable conditions of minimum and maximum tem-
perature limits, using the interrupt to notify the host if one
or more conditions occur. The temperature measurement
results are made available through the serial interface.
The MAX11301 features an internal, low-noise 2.5V volt-
age reference and provides the option to use external
voltage references with separate inputs for the DAC and
ADC. The MAX11301 uses a 400kHz I2C-compatible
serial interface, operating from a 5V analog supply and a
1.8V to 5.0V digital supply. The PIXI port supply voltages
operate from a wide -12.0V to +12.0V.
The MAX11301 is available in a 40-pin TQFN, 6mm x 6mm
package or a 48-pin TQFP, 9mm x 9mm package specified
over the -40°C to +105°C temperature range.
Applications
●Base-Station RF Power Device Bias Controllers
●System Supervision and Control
●Power-Supply Monitoring
●Industrial Control and Automation
●Control for Optical Components
Benets and Features
●20 Configurable Mixed-Signal Ports Maximize Design
Flexibility Across Platforms
• Up to 20 12-Bit ADC Inputs
▫Single-Ended, Differential, or Pseudo-Differential
▫Range Options: 0 to 2.5V, ±5V, 0 to +10V, -10V
to 0V
▫Programmable Sample Averaging Per ADC Port
▫Unique Voltage Reference for Each ADC PIXI
Port
• Up to 20 12-Bit DAC Outputs
▫Range Options: ±5V, 0 to +10V, -10V to 0V
▫25mA Current Drive Capability with Overcurrent
Protection
• Up to 20 General-Purpose Digital I/Os
▫0 to +5V GPI Input Range
▫0 to +2.5V GPI Programmable Threshold Range
▫0 to +10V GPO Programmable Output Range
▫Logic-Level Shifting Between Any Two Pins
• 60Ω Analog Switch Between Adjacent PIXI Ports
• Internal/External Temperature Sensors, ±1˚C
Accuracy
●Adapts to Specific Application Requirements and
Allows for Easy Reconfiguration as System Needs
Change
●Configurability of Functions Enables Optimized PCB
Layout
●Reduces BOM Cost with Fewer Components in
Small Footprint
• 36mm2 40-Pin TQFN
• 49mm2 48-Pin TQFP
Ordering Information appears at end of data sheet.
PIXI is a trademark of Maxim Integrated Products, Inc..
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX11301.related.
19-7579; Rev 0; 3/15
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
EVALUATION KIT AVAILABLE
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
www.maximintegrated.com Maxim Integrated
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DAC
SEQUENCER
INT
CNVT
D0N
INTERNAL
REFERENCE
ADC
2.5V
2.5V
SERIAL
INTERFACE
AND
DIGITAL
CORE
ADC
SEQUENCER
20
20
20
20
20
DAC
GPI
GPO
AD1
AD0
SCL
SDA
EXT AND INT
TEMP SENSORS
TEMPERATURE
MONITORS D0P
D1N
D1P
DGND AGND AVSSIO
DVDD DAC_REF ADC_INT_REF ADC_EXT_REF AVDD AVDDIO
MAX11301
REFERENCE
MUX
(0≤x≤18)
PORT[x+1]
PORT[x]
AGND1
PIXI PORT
MANAGER
CLOCK
GENERATOR
Functional Diagram
DVDD to DGND .......................................................-0.3V to +6V
AVDD to AGND .......................................................-0.3V to +6V
AVDDIO to AVSSIO ...............................................-0.3V to +25V
AVDDIO to AGND ..................................................-0.3V to +17V
AVSSIO to AGND ..................................................-14V to +0.3V
AGND to AGND1 .................................................. -0.3V to +0.3V
AGND to DGND ...................................................-0.3V to +0.3V
AGND1 to DGND .................................................-0.3V to +0.3V
(PORT0 to PORT19) to AGND ............max of (VAVSSIO - 0.3V)
or -14V to min of (VAVDDIO + 0.3V) or +17V
(PORT0 to PORT19) to AGND (GPI and Bidirectional Level
Translator Modes) .........
-0.3V to min of (VAVDD + 0.3V) or +6V
CNVT to DGND ............-0.3V to min of (VDVDD + 0.3V) or +6V
INT to DGND ...........................................................-0.3V to +6V
(SDA, SCL) to DGND ..............................................-0.3V to +6V
(AD0, AD1) to DGND ....-0.3V to min of (VDVDD + 0.3V) or +6V
DAC and ADC Reference Pins to AGND (DAC_REF,
ADC_INT_REF, ADC_EXT_REF) ................... -0.3V to min of
(VAVDD +0.3V) or +4V
Temperature Sensor Pins
(D0N, D0P, D1N, D1P) to AGND......................... -0.3V to min of
(VAVDD + 0.3V) or +6V
Current into Any PORT Pin ..............................................100mA
Current into Any Other Pin Except Supplies
and Ground .....................................................................50mA
Continuous Power Dissipation (TA = +70°C) (Multilayer board)
TQFN (derate 37mW/°C above +70°C) ...................2963mW
TQFP (derate 36.2mW/°C above +70°C) ...............2898.6mW
Operating Temperature Range ..........................-40ºC to +105°C
Storage Temperature Range .............................-65ºC to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) ....................................... +260°C
TQFN
Junction-to-Case Thermal Resistance (θJC) .................1°C/W
Junction-to-Ambient Thermal Resistance (θJA)...........27°C/W
TQFP
Junction-to-Case Thermal Resistance (θJC) .................2°C/W
Junction-to-Ambient Thermal Resistance (θJA)........27.6°C/W
ADC Electrical Specications
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40
°
C to +105
°
C, unless otherwise noted. Typical values
are at TA = +25
°
C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 3)
Resolution 12 Bits
Integral Nonlinearity INL ±2.5 LSB
Differential Nonlinearity DNL No missing codes over temperature ±1 LSB
Offset Error ±0.5 ±8 LSB
Offset Error Drift ±0.002 LSB/ºC
Gain Error ±11 LSB
Gain Error Drift ±0.01 LSB/ºC
Channel-to-Channel Offset
Matching 1 LSB
Channel-to-Channel Gain
Matching 2 LSB
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
Electrical Characteristics
ADC Electrical Specications
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40
°
C to +105
°
C, unless otherwise noted. Typical values
are at TA = +25
°
C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (SINGLE-ENDED INPUTS)
Signal-to-Noise Plus Distortion SINAD fS = 400ksps, fIN = 10kHz 70 dB
Signal to Noise SNR fS = 400ksps, fIN = 10kHz 71 dB
Total Harmonic Distortion THD fS = 400ksps, fIN = 10kHz -75 dB
Spurious-Free Dynamic Range SFDR fS = 400ksps, fIN = 10kHz 75 dB
Crosstalk -85 dB
DYNAMIC PERFORMANCE (DIFFERENTIAL INPUTS)
Signal-to-Noise Plus Distortion SINAD fS = 400ksps, fIN = 10kHz 71 dB
Signal to Noise SNR fS = 400ksps, fIN = 10kHz 72 dB
Total Harmonic Distortion THD fS = 400ksps, fIN = 10kHz -82 dB
Spurious-Free Dynamic Range SFDR fS = 400ksps, fIN = 10kHz 82 dB
Crosstalk -85 dB
CONVERSION RATE
Throughput (Note 4)
ADCCONV[1:0] = 00 200
ksps
ADCCONV[1:0] = 01 250
ADCCONV[1:0] = 10 333
ADCCONV[1:0] = 11 400
Acquisition Time tACQ
ADCCONV[1:0] = 00 3.5
μs
ADCCONV[1:0] = 01 2.5
ADCCONV[1:0] = 10 1.5
ADCCONV[1:0] = 11 1.0
ANALOG INPUT (All Ports)
Absolute Input Voltage (Note 5) VPORT
Range 1 0 10
V
Range 2 -5 +5
Range 3 -10 0
Range 4 0 2.5
Input Resistance Range 1, 2, 3 70 100 130 kΩ
Range 4 50 75 100 kΩ
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Electrical Characteristics (continued)
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
(VAVDD = 5.0V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V (Internal),
fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA
= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC INTERNAL REFERENCE
Reference Output Voltage Internal references at TA = +25°C 2.494 2.5 2.506 V
REF Output Tempco (Note 6) TC-VREF ±10 ±25 ppm/°C
Capacitor Bypass at ADC_INT_
REF 4.7 10 µF
DAC INTERNAL REFERENCE
Reference Output Voltage Internal references at TA = +25°C 2.494 2.5 2.506 V
REF Output Tempco (Note 6) TC-VREF ±10 ±25 ppm/°C
Capacitor Bypass at DAC_REF 4.7 10 µF
ADC EXTERNAL REFERENCE
Reference Input Range 2 2.75 V
DAC EXTERNAL REFERENCE
Reference Input Range 1.25 2.5 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GPIO EXCEPT IN BIDIRECTIONAL LEVEL TRANSLATION MODE
Programmable Input Logic
Threshold VITH 0.3
V
DACREF V
Input High Voltage VIH VITH +
0.3 V
Input Low Voltage VIL VITH - 0.3 V
Hysteresis ±30 mV
Programmable Output Logic Level VOLVL 04 x
V
DACREF
V
Propagation Delay from GPI Input
to GPO Output in Unidirectional
Level Translating Mode
Midscale threshold-5V logic swing 2 µs
BIDIRECTIONAL LEVEL TRANSLATION PATH AND ANALOG SWITCH
Input High Voltage VIH 1 V
Input Low Voltage VIL 0.2 V
On-Resistance From VAVSSIO + 2.50V to VAVDDIO
- 2.50V 60 Ω
Propagation Delay
10kΩ pullup resistors to rail in each side.
Midvoltage to midvoltage when driving
side goes from high to low
1 µs
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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REF Electrical Specications
GPIO Electrical Specications
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG SWITCH
Turn-On Delay (Note 7) 400 ns
Turn-Off Delay (Note 7) 400 ns
On-Time Duration (Note 7) 1 µs
Off-Time Duration (Note 7) 1 µs
On-Resistance From VAVSSIO + 2.50V to
VAVDDIO - 2.50V 60 Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution N 12 Bits
Output Range (Note 5) VPORT
Range 1 0 +10
VRange 2 -5 +5
Range 3 -10 0
Integral Linearity Error INL From code 100 to code 3996
±0.5
±1.5 LSB
Differential Linearity Error DNL
±0.5
±1 LSB
Offset Voltage At code 100 ±20 LSB
Offset Voltage Tempco 15 ppm/°C
Gain Error From code 100 to code 3996 -0.6 +0.6 % of
FS
Gain Error Tempco From code 100 to code 3996 4ppm of
FS/°C
Power-Supply Rejection
Ratio PSRR 0.4 mV/V
DYNAMIC CHARACTERISTICS
Output Voltage Slew Rate SR 1.6 V/µs
Output Settling Time To ±1 LSB, from 0 to full scale, output load
capacitance of 250pF (Note 8) 40 µs
Settling Time After Current-
Limit Condition 6 µs
Noise f = 0.1Hz to 300kHz 3.8 mVP-P
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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GPIO Electrical Specications (continued)
DAC Electrical Specications
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
(VAVDD = 5.0V, VDVDD = 1.62V to 5.50V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TRACK-AND-HOLD
Digital Feedthrough 5 nV·s
Hold Step (Note 6) 1 6 mV
Droop Rate (Note 6) 0.3 15 mV/s
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I2C IO DC SPECIFICATION
Input Logic-High Voltage
(SDA, SCL, AD0, AD1, CNVT)
VDVDD = 2.5V to 5.5V 0.7 x
VDVDD V
VDVDD = 1.62V to 2.5V 0.85 x
VDVDD
Input Logic-Low Voltage
(SDA, SCL, AD0, AD1, CNVT)
VDVDD = 2.5V to 5.5V 0.3 x
VDVDD V
VDVDD = 1.62V to 2.5V 0.15 x
VDVDD
Input Leakage Current
(SDA, SCL, AD0, AD1, CNVT)-10 +10 µA
Input Capacitance
(SDA, SCL, AD0, AD1, CNVT)10 pF
Output Logic-Low Voltage (SDA) ISNK = 3mA 0.4 V
Output Logic-Low Voltage (INT)
ISNK = 5mA, VDVDD = 2.5V to 5.5V 0.4
V
ISNK = 2mA, VDVDD = 1.62V to 2.5V 0.2
I2C TIMING REQUIREMENTS (Fast Mode) (See Figure 1)
Serial Clock Frequency fSCL 0 400 kHz
Bus Free Time Between STOP
and START Condition tBUF 1.3 µs
Hold Time (Repeated) START
Condition tHD;STA After this period, rst clock pulse is
generated 0.6 µs
SCL Pulse-Width Low tLOW 1.3 µs
SCL Pulse-Width High tHIGH 0.6 µs
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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DAC Electrical Specications (continued)
Interface Digital IO Electrical Specications
(VAVDD = 5.0V, VDVDD = 1.62 to 5.50V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
Figure 1. I2C Timing
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Setup Time for Repeated
START Condition tSU;STA 0.6 µs
Data Hold Time tHD;DAT 0 900 ns
Data Setup Time tSU;DAT 100 ns
SDA and SCL Receiving Rise
Time tr(Note 6)
20 x
(VDVDD
/5.5V)
300 ns
SDA and SCL Receiving Fall
Time tf(Note 6)
20 x
(VDVDD
/5.5V)
300 ns
SDA Transmitting Fall Time tof
20 x
(VDVDD
/5.5V)
250 ns
Setup Time for STOP Condition tSU;STO 0.6 µs
Bus Capacitance Allowed CbVDVDD = 2.5V to 5.5V 400 pF
Pulse Width of Suppressed
Spike tSP 50 ns
SDA
SCL
tBUF
tSU;STO
tr
tSP
tHD;STA
tSU;STA
tf
tHIGH
tSU;DAT
tHD;DAT
tr
tLOW
tHD;STA
tf
S
S
SrP
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Interface Digital IO Electrical Specications (continued)
Internal and External Temperature Sensor Specications
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ACCURACY
Accuracy of Internal Sensor
(Notes 6, 9)
0°C ≤ TJ ≤ +80°C ±0.3 ±2.0 °C
-40°C ≤ TJ ≤ +125°C ±0.7 ±5 °C
Accuracy of External Sensor
(Notes 6, 9)
0°C ≤ TRJ ≤ +80°C ±0.3 ±2.0 °C
-40°C ≤ TRJ ≤ +150°C ±1.0 ±5 °C
Temperature Measurement
Resolution 0.125 °C
External Sensor Junction Current High 68 μA
Low 4 μA
External Sensor Junction Current High Series resistance cancellation mode 136 μA
Low Series resistance cancellation mode 8 μA
Remote Junction Current
Conversion Ratio 17
D0N/D1N Voltage Internally generated 0.5 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VAVDD 4.75 5.25 V
VDVDD 1.62 5.50 V
VAVDDIO VAVDD 15.75 V
VAVSSIO -12.0 0 V
VAVDDIO to VAVSSIO VAVDD 24 V
IAVDD
All ports in high impedance 14 18
mA
LPEN = 1 11
All ports in ADC-related modes 17
All ports in DAC-related modes 18
IDVDD Serial interface in idle mode 2 μA
IAVDDIO All ports in mode 0 150 μA
IAVSSIO All ports in mode 0 -400 μA
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Electrical Characteristics
Power-Supply Specications
The values of VAVDDIO and VAVSSIO supply voltages depend on the application circuit and the device conguration.
VAVDDIO needs to be the maximum of those four values:
●If one or more ports are in mode 3, 4, 5, 6, or 10 (DAC-related modes), VAVDDIO must be set, at minimum, to the
value of the largest voltage driven by any of the ports set in those modes. For improved linearity, it is recommended
to set VAVDDIO 2.0V above the largest voltage value.
●If one or more ports are in mode 7, 8, or 9 (ADC-related modes), VAVDDIO must be set, at minimum, to the value of
the largest voltage applied to any of the ports set in those modes.
●If one or more ports are in mode 11 or 12 (Analog switch-related modes), VAVDDIO must be set, at minimum, to
2.0V above the value of the largest voltage applied to any of the ports functioning as analog switch terminals.
●VAVDDIO cannot be set lower than VAVDD.
VAVSSIO needs to be the minimum of those four values:
●If one or more ports are in mode 3, 4, 5, 6, or 10 (DAC-related modes), VAVSSIO must be set, at maximum, to the
value of the lowest voltage driven by any of the ports set in those modes. For improved linearity, it is recommended
to set VAVSSIO 2.0V below the lowest voltage value.
●If one or more ports are in mode 7, 8, or 9 (ADC-related modes), VAVSSIO must be set, at maximum, to the value
of the lowest voltage applied to any of the ports set in those modes.
●If one or more ports are in mode 11 or 12 (Analog Switch-related modes), VAVSSIO must be set, at maximum, to
2.0V below the value of the lowest voltage applied to any of the ports functioning as analog switch terminals.
●VAVSSIO cannot be set higher than VAGND.
For example, the MAX11301 can operate with only one voltage supply of 5V (±5%) connected to AVDD, AVDDIO, and
DVDD, and one ground of 0V connected to AGND, DGND, and AVSSIO. However, the level of performance presented
in the electrical specifications requires the setting of the supplies connected to AVDDIO and AVSSIO as previously
described.
ADC RANGE
-10V TO 0V -5V TO +5V 0V TO +10V 0 TO 2.5V
DAC RANGE
-10V TO 0V VAVDDIO = +5V
VAVSSIO = -12V
VAVDDIO = +5V
VAVSSIO = -12V
VAVDDIO = +10V
VAVSSIO = -12V
VAVDDIO = +5V
VAVSSIO = -12V
-5V TO +5V VAVDDIO = +7V
VAVSSIO = -10V
VAVDDIO = +7V
VAVSSIO = -7V
VAVDDIO = +10V
VAVSSIO = -7V
VAVDDIO = +7V
VAVSSIO = -7V
0V TO +10V VAVDDIO = +12V
VAVSSIO = -10V
VAVDDIO = +12V
VAVSSIO = -5V
VAVDDIO = +12V
VAVSSIO = -2V
VAVDDIO = +12V
VAVSSIO = -2V
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Recommended VDDIO/VSSIO Supply Selection
(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V
(Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PIXI PORTS
Input Capacitance All PIXI ports 20 pF
Input Resistance All PIXI input pins except ADC mode 50 75 100 kΩ
Startup Time Between stable supplies and accessing
registers 100 ms
HIGH-VOLTAGE OUTPUT DRIVER CHARACTERISTICS
Maximum Output Capacitance 250 pF
Output Low Voltage, DAC Mode Sinking 25mA, VAVSSIO = 0V,
VAVDDIO = 10V
VAVSSIO
+ 1.0 V
Output High Voltage, DAC Mode Sourcing 25mA, VAVSSIO = 0V,
VAVDDIO = 10V
VAVDDIO
- 1.5 V
Output Low Voltage, GPO Mode Sinking 2mA, VAVSSIO = 0V,
VAVDDIO = 10V
VAVSSIO
+ 0.4 V
Output High Voltage, GPO Mode Sourcing 2mA, VAVSSIO = 0V,
VAVDDIO = 10V
VAVDDIO
- 0.4 V
Current Limit Short to AVDDIO 75 mA
Short to AVSSIO 75 mA
Note 2: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range are
guaranteed by design and characterization. Typical specifications are at TA = +25°C.
Note 3: DC accuracy specifications are tested for single-ended ADC inputs only.
Note 4: The effective ADC sample rate for port X configured in mode 6, 7, or 8 is:
[ADC sample rate per ADCCONV]/(([number of ports in modes 6,7,8] + [1 if TMPSEL ≠ 000]) x [2# OF SAMPLES for port X])
Note 5: See the Recommended VDDIO/VSSIO Supply Selection table for each range. For ports in modes 6, 7, 8, or 9, the voltage
applied to those ports must be within the limits of their selected input range, whether in single-ended or differential mode.
Note 6: Specification is guaranteed by design and characterization.
Note 7: Switch controlled by GPI-congured port. One switch terminal connected to 0V, the other terminal connected to 5V through
a 5mA current source. Timing is measured at the 2.5V transition point. Turn-on and turn-off delays are measured from the
edge of the control signal to the 2.5V transition point. Turn-on and turn-off durations are measured between control signal
transitions.
Note 8: In DAC-related modes, the rate, at which PIXI ports congured in mode 1, 3, 4, 5, 6, or 10 are refreshed, is as follows:
1/(40µs x [number of ports in modes 1, 3, 4, 5, 6, 10])
Note 9: Typical (TYP) values represent the errors at the extremes of the given temperature range.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
www.maximintegrated.com Maxim Integrated
│
11
Common PIXI Electrical Specications
(TA = +25°C, unless otherwise noted.)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
01000 2000 3000 4000
DNL (LSB)
DIGITAL OUPUT CODE (DECIMAL)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
ADC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTERNAL REFERENCE toc02
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
01000 2000 3000 4000
INL (LSB)
DIGITAL OUPUT CODE (DECIMAL)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
ADC INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
EXTERNAL REFERENCE toc03
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
01000 2000 3000 4000
DNL (LSB)
DIGITAL OUPUT CODE (DECIMAL)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
ADC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
EXTERNAL REFERENCE toc04
6
8
10
12
14
16
18
20
-50 -25 025 50 75 100 125
OFFSET ERROR (LSB)
TEMPERATURE (°C)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE 0V TO 2.5V
ADC OFFSET ERROR
vs. TEMPERATURE toc05
0
1
2
3
4
5
6
7
8
-50 -25 025 50 75 100 125
GAIN ERROR (LSB)
TEMPERATURE (°C)
RANGE 0V TO 10V RANGE -5V TO +5V
RANGE -10V TO 0V RANGE 0V TO 2.5V
ADC GAIN ERROR
vs. TEMPERATURE toc06
8
9
10
11
12
13
14
15
16
17
18
4.7 4.8 4.9 55.1 5.2 5.3
OFFSET ERROR (LSB)
SUPPLY VOLTAGE (V)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
RANGE 0V TO 2.5V
ADC OFFSET ERROR
vs. SUPPLY VOLTAGE toc07
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
01000 2000 3000 4000
INL (LSB)
DIGITAL OUPUT CODE (DECIMAL)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
ADC INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTERNAL REFERENCE toc01
0
1
2
3
4
5
6
7
4.7 4.8 4.9 55.1 5.2 5.3
GAIN ERROR (LSB)
SUPPLY VOLTAGE (V)
RANGE 0V TO 10V RANGE -5V TO +5V
RANGE -10V TO 0V RANGE 0V TO 2.5V
ADC GAIN ERROR
vs. SUPPLY VOLTAGE toc08
0.1
1
10
100
1000
10000
100000
-50 -25 025 50 75 100 125
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
ADC RANGE 0V TO 10V
IAVDD
toc9a
IAVSSIO
IAVDDIO
IAVDDIO
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Maxim Integrated
│
12
www.maximintegrated.com
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
0.1
1
10
100
1000
10000
100000
-50 -25 025 50 75 100 125
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
ADC RANGE -5V TO +5V
IAVDD
toc9b
IAVSSIO
IAVDDIO
IAVDDIO
0.1
1
10
100
1000
10000
100000
-50 -25 025 50 75 100 125
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
ADC RANGE -10V TO 0V
IAVDD
toc9c
IAVSSIO
IAVDDIO
IAVDDIO
14
14.5
15
15.5
16
16.5
17
17.5
18
0 5 10 15 20
IAVDD CURRENT (mA)
NO.OF ADC-CONFIGURED PORTS
IAVDD
vs. ADC CHANNELS
ADC RANGE
0V TO 10V
toc10
ADC RANGE
-5V TO +5V
ADC RANGE
-10V TO 0V
2.494
2.496
2.498
2.500
2.502
2.504
2.506
-50 -25 025 50 75 100 125
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
ADC INTERNAL REFERENCE
vs. TEMPERATURE toc11
-1.5
-1
-0.5
0
0.5
1
1.5
01000 2000 3000 4000
INL (LSB)
DAC CODE (DECIMAL)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
DAC INTEGRAL NONLINEARITY
vs. DIGITAL CODE
INTERNAL REFERENCE toc12
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
01000 2000 3000 4000
DNL (LSB)
DAC CODE (DECIMAL)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTERNAL REFERENCE toc13
-1.5
-1
-0.5
0
0.5
1
1.5
01000 2000 3000 4000
INL (LSB)
DAC CODE (DECIMAL)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
DAC INTEGRAL NONLINEARITY
vs. DIGITAL CODE
EXTERNAL REFERENCE toc14
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
01000 2000 3000 4000
DNL (LSB)
DAC CODE (DECIMAL)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
EXTERNAL REFERENCE toc15
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-50 -25 025 50 75 100 125
OFFSET ERROR (LSB)
TEMPERATURE (°C)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
DAC OFFSET ERROR
vs. TEMPERATURE toc16
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Maxim Integrated
│
13
www.maximintegrated.com
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-50 -25 025 50 75 100 125
GAIN ERROR (LSB)
TEMPERATURE (°C)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
DAC GAIN ERROR
vs. TEMPERATURE toc17
-2
-1
0
1
2
3
4
4.7 4.8 4.9 55.1 5.2 5.3
OFFSET ERROR (LSB)
SUPPLY VOLTAGE (V)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
DAC OFFSET ERROR
vs. SUPPLY VOLTAGE toc18
-1.5
-1.3
-1.1
-0.9
-0.7
-0.5
-0.3
-0.1
4.7 4.8 4.9 55.1 5.2 5.3
GAIN ERROR (LSB)
SUPPLY VOLTAGE (V)
RANGE 0V TO 10V
RANGE -5V TO +5V
RANGE -10V TO 0V
DAC GAIN ERROR
vs. SUPPLY VOLTAGE toc19
0.1
1
10
100
1000
10000
100000
-50 -25 025 50 75 100 125
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
DAC RANGE 0V TO 10V
IAVDD
toc20a
IAVSSIO
IAVDDIO IAVDDIO
0.1
1
10
100
1000
10000
100000
-50 -25 025 50 75 100 125
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
DAC RANGE -5V TO +5V
IAVDD
toc20b
IAVSSIO
IAVDDIO IAVDDIO
0.1
1
10
100
1000
10000
100000
-50 -25 025 50 75 100 125
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
DAC RANGE -10V TO 0V
IAVDD
toc20c
IAVSSIO
IAVDDIO IAVDDIO
13
14
15
16
17
18
19
0 5 10 15 20
IAVDD CURRENT (mA)
NO. OF DAC-CONFIGURED PORTS
IAVDD
vs. DAC CHANNELS
ADC RANGE
0V TO 10V
toc21a
ADC RANGE
-5V TO +5V
ADC RANGE
-10V TO 0V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 5 10 15 20
IAVDDIO CURRENT (mA)
NO. OF DAC-CONFIGURED PORTS
IAVDDIO
vs. DAC CHANNELS
ADC RANGE
0V TO 10V
toc21b
ADC RANGE
-5V TO +5V
ADC RANGE
-10V TO 0V
0
1
2
3
4
5
6
7
0 5 10 15 20
IAVSSIO CURRENT (mA)
NO. OF DAC-CONFIGURED PORTS
IAVSSIO
vs. DAC CHANNELS
ADC RANGE
0V TO 10V
toc21c
ADC RANGE
-5V TO +5V
ADC RANGE
-10V TO 0V
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Maxim Integrated
│
14
www.maximintegrated.com
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
2.494
2.496
2.498
2.500
2.502
2.504
2.506
-50 -25 025 50 75 100 125
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
DAC INTERNAL REFERENCE
vs. TEMPERATURE
toc22
2V/div
toc23
5µs/div
DAC SETTLING TIME
CHANGE FROM
PSV1 TO PSV2
PSV1 = 0X000
PSV2 = 0XFFF
2V/div
toc24a
2.5µs/div
DAC SETTLING TIME
CHANGE FROM MIN TO MAX
NO LOAD
2V/div
toc24b
2.5µs/div
DAC SETTLING TIME
CHANGE FROM MAX TO MIN
NO LOAD
2V/div
toc24c
50µs/div
DAC SETTLING TIME
CHANGE FROM MIN TO MAX
1µF CAP LOAD
2V/div
toc24d
50µs/div
DAC SETTLING TIME
CHANGE FROM MAX TO MIN
1µF CAP LOAD
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-50 -25 025 50 75 100 125
DROOP RATE (mV/s)
TEMPERATURE (°C)
AVDD = 4.75V
AVDD = 5V
AVDD = 5.25V
DAC DROOP RATE
vs. TEMPERATURE
(DAC RANGE 0 TO 10V) toc25a
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
-50 -25 025 50 75 100 125
DROOP RATE (mV/s)
TEMPERATURE (°C)
AVDD = 4.75V
AVDD = 5V
AVDD = 5.25V
DAC DROOP RATE
vs. TEMPERATURE
(DAC RANGE -5V TO +5V) toc25b
VAVDD = 4.75V
VAVDD = 5V
VAVDD = 5.25V
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Maxim Integrated
│
15
www.maximintegrated.com
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-50 -25 025 50 75 100 125
DROOP RATE (mV/s)
TEMPERATURE (°C)
AVDD = 4.75V
AVDD = 5V
AVDD = 5.25V
DAC DROOP RATE
vs. TEMPERATURE
(DAC RANGE -10V TO 0) toc25c
VAVDD = 4.75V
VAVDD = 5V
VAVDD = 5.25V
0.000
0.100
0.200
0.300
0.400
0.500
0.600
0.700
0.800
0.900
1.000
-50 -25 025 50 75 100 125
VOLTAGE (V)
TEMPERATURE (°C)
DAC V
OH
AND V
OL
vs. TEMPERATURE
(ILOAD = 25mA)
toc26
VOH
VOL
60.0
60.2
60.4
60.6
60.8
61.0
61.2
61.4
61.6
61.8
62.0
-50 -25 025 50 75 100 125
CURRENT (mA)
TEMPERATURE (°C)
DAC DRIVE CURRENT LIMIT
vs. TEMPERATURE
DAC = 0V, SHORTED TO VDDIO
toc27
60.0
60.2
60.4
60.6
60.8
61.0
61.2
61.4
61.6
61.8
62.0
-50 -25 025 50 75 100 125
CURRENT (mA)
TEMPERATURE (°C)
vs. TEMPERATURE
DAC = 10V, SHORTED TO VSSIO
toc28
CS
5V/div
toc29
10µs/div
MAJOR-CODE TRANSITION GLITCH
DAC CODE FROM 0x7FF TO 0x800
DAC VOUT
AC-
COUPLED
1mV/div
20µV/div
toc30
1s/div
DAC OUTPUT NOISE
INTERNAL REFERENCE
(0.1Hz TO 10Hz)
20µV/div
toc31
1s/div
DAC OUTPUT NOISE
EXTERNAL REFERENCE
(0.1Hz TO 10Hz)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
4.7 4.8 4.9 55.1 5.2 5.3
OFFSET (mV)
SUPPLY VOLTAGE (V)
Vth = 0.9V
Vth = 1.65V
Vth = 2.5V
GPI OFFSET
vs. SUPPLY VOLTAGE toc32
VTH = 0.9V
VTH = 1.65V
VTH = 2.5V
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Maxim Integrated
│
16
www.maximintegrated.com
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
0
1
2
3
4
5
6
-50 -25 025 50 75 100 125
OFFSET (mV)
TEMPERATURE (°C)
Vth = 0.9V
Vth = 1.65V
Vth = 2.5V
GPI OFFSET
vs. TEMPERATURE toc33
VTH = 0.9V
VTH = 1.65V
VTH = 2.5V
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
-50 -25 025 50 75 100 125
TEMPERATURE ERROR (°C)
TEMPERATURE (°C)
INTERNAL TEMPERATURE
SENSOR ERROR
vs. TEMPERATURE
toc35
20
22
24
26
28
30
32
34
36
38
40
-50 -25 025 50 75 100 125
HYSTERESIS (±mV)
TEMPERATURE (°C)
VTH = 0.9V
VTH = 1.65V
VTH = 2.5V
GPI HYSTERESIS
vs. TEMPERATURE toc34
VTH = 0.9V
VTH = 1.65V
VTH = 2.5V
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-50 -25 025 50 75 100 125
TEMPERATURE ERROR (°C)
TEMPERATURE (°C)
EXTERNAL TEMPERATURE
SENSOR ERROR
vs. TEMPERATURE
toc36
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Maxim Integrated
│
17
www.maximintegrated.com
Typical Operating Characteristics (continued)
TQFN
6mm x 6mm
MAX11301
TOP VIEW
DVDD
SCL
AD0
AD1
INT
DGND
PORT8
PORT6
PORT5
PORT9
PORT10
PORT11
PORT4
AVDDIO
PORT13
PORT14
PORT15
PORT2
PORT1
PORT0
AGND
SDA
PORT7
PORT16 AVDD
PORT17
PORT18
PORT19
D0N
D0P
DAC_REF
+
AVDDIO
D1P
AGND1
D1N
CNVT
ADC_INT_REF
ADC_EXT_REF PORT3
PORT12 20
19
18
17
16
15
14
13
12
11
21
109876
54321
22
23
2425
26
2728
2930
31
32
33
34
35
36
37
38
39
40
EP
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
www.maximintegrated.com Maxim Integrated
│
18
Pin Congurations
PORT11
PORT10
AVSSIO
PORT9
PORT8
PORT7
PORT6
AVSSIO
PORT5
PORT4
AVDDIO
PORT3
PORT19
DGND
DVDD
SDA
SCL
AD0
AD1
INT
CNVT
ADC_INT_REF
ADC_EXT_REF
DAC_REF
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
AGND
AGND
PORT1
D1P
D1N
AVSSIO
TQFP
7mm x 7mm
81mm2, total area
including pins
D0P
D0N
AVDD
AVDD
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
AVSSIO
PORT18
PORT17
PORT16
AVSSIO
PORT15
PORT14
PORT13
AVDDIO
AGND
PORT12
MAX11301
PORT2
PORT0
AVSSIO
EP
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
www.maximintegrated.com Maxim Integrated
│
19
Pin Congurations (continued)
PIN NAME FUNCTION
TQFN TQFP
1 2 DGND Digital Ground
2 3 DVDD Positive Digital Supply
3 4 SDA Serial Interface Input and Output
4 5 SCL Serial Interface Clock Input
5 6 AD0 Slave Address Bit 0
6 7 AD1 Slave Address Bit 1
7 8 INT Interrupt Open-Drain Output. Active low.
8 9 CNVT ADC Trigger Control Input. Active low.
9 10 ADC_INT_REF ADC Internal Voltage Reference Output. Connect a bypass capacitor at this pin
(4.7µF to 10µF).
10 11 ADC_EXT_REF ADC External Voltage Reference Input. Connect a bypass capacitor at this pin
(4.7µF to 10µF).
11 12 DAC_REF DAC External/Internal Voltage Reference Input. Connect a bypass capacitor at this
pin (4.7µF to 10µF).
12 13 D0P 1st External Temperature Sensor Positive Input
13 14 D0N 1st External Temperature Sensor Negative Input
14 15, 16 AVDD Positive Analog Supply. For TQFP, connect both pins to AVDD.
15 17, 18 AGND Analog Ground. For TQFP, connect both pins to AGND.
16 19 PORT0 Congurable Mixed-Signal Port 0
17 20 PORT1 Congurable Mixed-Signal Port 1
18 21 PORT2 Congurable Mixed-Signal Port 2
19 22 D1P 2nd External Temperature Sensor Positive Input
20 23 D1N 2nd External Temperature Sensor Negative Input
21 25 PORT3 Congurable Mixed-Signal Port 3
22, 33 26, 39 AVDDIO Analog Positive Supply For Mixed-Signal Ports. Connect both pins to AVDDIO.
23 27 PORT4 Congurable Mixed-Signal Port 4
24 28 PORT5 Congurable Mixed-Signal Port 5
25 30 PORT6 Congurable Mixed-Signal Port 6
26 31 PORT7 Congurable Mixed-Signal Port 7
27 32 PORT8 Congurable Mixed-Signal Port 8
28 33 PORT9 Congurable Mixed-Signal Port 9
29 35 PORT10 Congurable Mixed-Signal Port 10
30 36 PORT11 Congurable Mixed-Signal Port 11
31 37 PORT12 Congurable Mixed-Signal Port 12
32 38 AGND1 Analog Ground
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
www.maximintegrated.com Maxim Integrated
│
20
Pin Description
PIN NAME FUNCTION
TQFN TQFP
34 40 PORT13 Congurable Mixed-Signal Port 13
35 42 PORT14 Congurable Mixed-Signal Port 14
36 43 PORT15 Congurable Mixed-Signal Port 15
37 45 PORT16 Congurable Mixed-Signal Port 16
38 46 PORT17 Congurable Mixed-Signal Port 17
39 47 PORT18 Congurable Mixed-Signal Port 18
40 1 PORT19 Congurable Mixed-Signal Port 19
—
24, 29,
34, 41,
44, 48
AVSSIO Analog Negative Supply for Mixed-Signal Ports. For TQFP, connect all pins to AVSSIO.
— — EP Exposed Pad. For TQFN, connect EP to AVSSIO. For TQFP, connect EP to AGND.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Pin Description (continued)
PA Biasing—PIXI Solution
PIXITM
MAX11301
DAC
0 TO 10V
MAX44285
FB2
VOUT2_DET
PTMA210152
STAGE 2
PTMA210152
STAGE 1
RF IN
TDD_CLK2
IOUT2_DET
VG2
VIN_DET
DAC
0 TO 10V
DAC
0 TO 10V
ADC
0 TO 10V
ADC
0 TO 2.5V
MAX17503
DC/DC
MAX14850 USBMAXQ622
VOUT2
(15V TO 28V)
VIN
(36V)
VIN
(36V)
RS
DAC
0 TO 10V
MAX44285
FB1
VOUT1_DET
TDD_CLK1
IOUT1_DET
VG1
DAC
0 TO 10V
ADC
0 TO 10V
ADC
0 TO 2.5V
MAX17503
DC/DC
VOUT1
(15V TO 28V) RS
ISO_I2C I2C
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Typical Application Circuit
Detailed Description
Functional Overview
The MAX11301 has 20 configurable mixed-signal I/O
ports. Each port is independently configured as a DAC
output, an ADC, a GPI input, a GPO, or an analog
switch terminal. User-controllable parameters are avail-
able for each of those configurations. The device offers
one internal and two external temperature sensors. The
serial interface operates as a Fast Mode I2C-compatible
interface.
The DAC is used to drive out a voltage defined by the
DAC data register of the DAC-configured ports. The DAC
uses either an internal or external voltage reference. The
selection of the voltage reference is set for all the ports
and cannot be configured on a port-by-port basis.
The ADC converts voltages applied to the ADC-configured
ports. The ADC can operate in single-ended mode or in
differential mode, by which any two ports can form a dif-
ferential pair. The port configured as the negative input of
the ADC can be used by more than one differential ADC
input pairs. The ADC uses either an internal or external
voltage reference. In some configurations, the ADC uses
the DAC voltage reference. The ADC voltage reference
selection can be configured on a port-by-port basis.
Interrupts provide the host with the occurrence of user-
selected events through the configuration of an interrupt
mask register.
ADC Operations
The ADC is a 12-bit, low-power, successive approxima-
tion analog-to-digital converter, capable of sampling a
single input at up to 400ksps. The ADC’s conversion rate
can be programmed to 400ksps, 333ksps, 250ksps, or
200ksps. The default conversion rate setting is 200ksps.
Each ADC-configured port can be programmed for one of
five input voltage ranges: 0 to +10V, -5V to +5V, -10V to
0V, and 0 to +2.5V. The ADC uses the internal ADC 2.5V
voltage reference, the external ADC voltage reference, or,
in some cases, the DAC voltage reference. The voltage
reference can be selected on a port-by-port basis.
ADC Control
The ADC can be triggered using an external signal CNVT
or from a control bit. CNVT is active-low and must remain
low for a minimal duration of 0.5 µs to trigger a conver-
sion. Four configurations are available:
• Idle mode (default setting).
• Single sweep mode. The ADC sweeps sequentially the
ADC-configured ports, from the lowest index port to
the highest index port, once CNVT is asserted.
• Single conversion mode. The ADC performs a single
conversion at the current port in the series of ADC-
configured ports when CNVT is asserted.
• Continuous sweep mode. The ADC continuously
sweeps the ADC-configured ports. The CNVT port has
no effect in this mode.
ADC Averaging Function
ADC-configured ports can be configured to average
blocks of 2, 4, 8, 16, 32, 64, or 128 conversion results.
The corresponding ADC data register is updated only
when the averaging is completed, thus decreasing the
throughput proportionally. If the number of samples to
average is modified for a given port, the content of the
ADC data register for that port is cleared before starting
to average the new block of samples.
ADC Mode Change
When users change the ADC active mode (continuous
sweep, single sweep, or single conversion), the ADC data
registers are reset. However, ADC data registers retain
content when the ADC is changed to idle mode.
ADC Congurations
The ADC can operate in single-ended, differential, or
pseudo-differential mode. In single-ended mode, the PIXI
port is the positive input to the ADC while the negative
input is grounded internally (Figure 2). In differential mode
(Figure 3), any pair of PIXI ports can be configured as
inputs to the differential ADC. In pseudo-differential mode
(Figure 4), one PIXI port produces the voltage applied
to the negative input of the ADC while another PIXI port
forms the positive input.
The ADC data format is straight binary in single-ended
mode, and two’s complement in differential and pseudo-
differential modes.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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DAC Operations
The MAX11301 uses a 12-bit DAC, which operates at the
rate of 40µs per port. Since up to 20 ports can be config-
ured in DAC-related modes, the minimum refresh rate per
port is 1.25kHz.
No external component is required to set the offset and
gain of the DAC drivers. The PIXI port driver features a
wide output voltage range of ±10V and high current capa-
bility with dedicated power supplies (AVDDIO, AVSSIO).
The DAC uses either the internal or external voltage refer-
ence. Unlike the ADC, the DAC voltage reference cannot
be configured on a port-by-port basis. DAC mode configu-
ration is illustrated in Figure 5.
DAC operations can be monitored by the ADC. In such a
mode, the ADC samples the DAC-configured port to allow
the host to monitor that the voltage at the port is within
expectations given the accuracy of the ADC and DAC.
This ADC monitoring mode is shown in Figure 6.
By default, the DAC updates the DAC-configured ports
sequentially. However, users can configure the DAC so
that its sequence can jump to update the port that just
received new data to convert. After having updated this
port, the DAC continues its default sequence from that
port. In that mode, users should allow a minimum of 80µs
between DAC data register updates for subsequent jump
operations.
In addition to port-specific DAC data registers, the host
can also use the same data for all DAC-related ports
using one of two preset DAC data registers.
All DAC output drivers are protected by overcurrent limit
circuitry. In case of overcurrent, the MAX11301 generates
an interrupt. Detailed status registers are offered to the
host to determine which ports are current limited.
ADC I
2
CSERIAL
INTERFACE
PORT
12 BITS
UP TO 400ksps
SCALING
BLOCK
REFERENCE
MUX
ADC_INT_REF ADC_EXT_REF
INT
SEQUENCER
CNVT
DIGITAL
CORE
ADC I
2
CSERIAL
INTERFACE
ANY
PORT
12 BITS
UP TO 400ksps
SCALING
BLOCK
REFERENCE
MUX
ANY OTHER
PORT
SCALING
BLOCK
SEQUENCER
ADC_INT_REF ADC_EXT_REF
INT
CNVT
DIGITAL
CORE
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Figure 2. ADC with Single-Ended Input
Figure 3. ADC with Differential Inputs
General-Purpose Input and Output
Each PIXI port can be configured as a GPI or a GPO. The
GPI threshold is adjusted by setting the DAC data register
of that GPI port to the corresponding voltage. If the DAC
data register is set at 0x0FFF, the GPI threshold is the DAC
reference voltage. The amplitude of the input signal must
be contained within 0V to VAVDD. The GPI-configured port
can be set to detect rising edges, falling edges, either rising
or falling edges, or none.
When a port is configured as GPO (Figure 8), the ampli-
tude of its logic-one level is set by its DAC data register. If
the DAC data register is set at 0x0FFF, the GPO logic-one
level is four times the DAC reference voltage. The logic-
zero level is always 0V. The host can set the logic state
of GPO-configured ports through the corresponding GPO
data registers.
Unidirectional and Bidirectional
Level Translator Operations
By combining GPI- and GPO-configured ports, unidirec-
tional level translator paths can be formed. The signaling
at the input of the path can be different from the signaling
at the end (Figure 9). For example, a unidirectional path
ADC I
2
CSERIAL
INTERFACE
ANY
PORT
SCALING
BLOCK
REFERENCE
MUX
ANY OTHER
PORT
SCALING
BLOCK
SEQUENCER
DAC
DAC_REF
INTERNAL OR
EXTERNAL FOR
ALL PORTS
SCALING
BLOCK
SEQUENCER
ADC_INT_REF ADC_EXT_REF
INT
CNVT
DIGITAL
CORE
I
2
C
SERIAL
INTERFACE
DIGITAL
CORE SEQUENCER
SCALING
BLOCK
PORT
40µs to ±1 LSB
DAC_REF
INTERNAL OR
EXTERNAL FOR
ALL PORTS
DAC
0mA → 25mA
CURRENT LIMIT at
50mA
INT
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Figure 4. ADC with Pseudo-Differential Input Set by DAC
Figure 5. DAC Configuration
could convert a signal from 1.8V logic level to 3.3V logic
level.
The unidirectional path configuration allows for the trans-
mission of signals received on a GPI-configured port to
one or more GPO-configured ports.
Pairs of adjacent PIXI ports can also form bidirectional
level translator paths that are targeted to operate with
open-drain drivers (Figure 10). When used as a bidi-
rectional level translator, the pair of PIXI ports must be
accompanied with external pullup resistors to meet proper
logic levels.
Internally or Externally Controlled
Analog Switch Operation
Two adjacent PIXI ports can form a 60Ω analog switch
that is controlled by two different configurations. In one
configuration, the switch is dynamically controlled by any
other GPI-configured PIXI port, as illustrated in Figure
11. The signal applied to that GPI-configured port can be
inverted.
In the other configuration, the switch is programmed to be
permanently “ON” by configuring the corresponding PIXI
port. To turn the switch “OFF”, the host must set that PIXI
port in high-impedance configuration.
Power-Supply Brownout Detection
The MAX11301 features a brownout detection circuit that
monitors AVDDIO and AVDD pins. When AVDDIO goes
below approximately 4.0V, an interrupt is registered, and
the interrupt port is asserted if not masked. When AVDD
goes below approximately 4.0V, the device resets.
I2C Operations
The MAX11301 serial interface is compatible with the I2C
Fast Mode (SCL at 400kHz).
The MAX11301 has a configurable 7-bit slave address.
The first four bits of all MAX11301 slave addresses are
always 0111. Slave address bits A2, A1, and A0 are
shown in Table 1. The AD0 and AD1 inputs are connected
to any of three signals: DGND, DVDD, SDA, or SCL giving
eight possible slave addresses, and allowing up to eight
MAX11301 devices to share the bus.
Basic write and read transactions are structured as shown
in Table 2 and Table 3, respectively. For write transac-
tions, the targeted register content is modified only after
I2C
SERIAL
INTERFACE
DIGITAL
CORE SEQUENCER
SCALING
BLOCK
PORT
ADC
REFERENCE
MUX
SCALING
BLOCK
SEQUENCER
DAC_REF
INTERNAL OR EXTERNAL
FOR ALL PORTS
ADC_INT_REF DAC_REF
DAC
INT
CNVT
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Figure 6. DAC Configuration with ADC Monitoring
Table 1. MAX11301 Slave Addresses
Table 2. Single Register I2C Write Transaction Format
Table 3. Single Register I2C Read Transaction Format
PIN AD1 PIN AD0 SLAVE ADDRESS
A6 A5 A4 A3 A2 A1 A0
DGND DGND 0 1 1 1 0 0 0
DGND SDA 0 1 1 1 0 0 1
DGND SCL 0 1 1 1 0 1 0
DGND DVDD 0 1 1 1 0 1 1
DVDD DGND 0 1 1 1 1 0 0
DVDD SDA 0 1 1 1 1 0 1
DVDD SCL 0 1 1 1 1 1 0
DVDD DVDD 0 1 1 1 1 1 1
B7 B6 B5 B4 B3 B2 B1 B0 N/ACK
START
1st byte 7-Bit Slave Address[6:0] R/WB ACK
2nd byte 0 Address[6:0] ACK
3rd byte Data[15:8] ACK
4th byte Data[7:0] ACK
STOP
B7 B6 B5 B4 B3 B2 B1 B0 N/ACK
START
1st byte 7-Bit Slave Address[6:0] R/WB ACK
2nd byte 0 Address[6:0] ACK
RESTART
1st byte 7-Bit Slave Address[6:0] R/WB ACK
3rd byte Data[15:8] ACK
4th byte Data[7:0] NACK (from host)
STOP
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Table 4. Multiple Register I2C Write Transaction Format
Table 5. Multiple Register I2C Read Transaction Format
B7 B6 B5 B4 B3 B2 B1 B0 N/ACK
START
1st byte 7-Bit Slave Address[6:0] R/WB ACK
2nd byte 0 Address_N[6:0] ACK
3rd byte Data_N[15:8] ACK
4th byte Data_N[7:0] ACK
5th byte Data_N+1[15:8] ACK
6th byte Data_N+1[7:0] ACK
7th byte Data_N+2[15:8] ACK
8th byte Data_N+2[7:0] ACK
9th byte Data_N+3[15:8] ACK
10th byte Data_N+3[7:0] ACK
11th byte ACK
… …
41st byte Data_N+19[15:8] ACK
42nd byte Data_N+19[7:0] ACK
STOP
B7 B6 B5 B4 B3 B2 B1 B0 N/ACK
START
1st byte 7-Bit Slave Address[6:0] R/WB ACK
2nd byte 0 Address_N[6:0] ACK
RESTART
1st byte 7-Bit Slave Address[6:0] R/WB ACK
3rd byte Data_N[15:8] ACK
4th byte Data_N[7:0] ACK
5th byte Data_N+1[7:0] ACK
6th byte Data_N+1[15:8] ACK
7th byte Data_N+1[7:0] ACK
8th byte Data_N+2[15:8] ACK
9th byte Data_N+2[7:0] ACK
10th byte Data_N+3[15:8] ACK
11th byte Data_N+3[7:0] ACK
… …
41st byte Data_N+19[15:8] ACK
42nd byte Data_N+19[7:0] NACK
(from host)
STOP
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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the third byte has been fully received. A burst transaction
would simply be the extension of the single register trans-
action, where the address is automatically incremented
from one data word to the next (Table 4 and Table 5).
Each time a new data sample is read or written, the
register address is incremented by one until it reaches the
last register address. The RESTART shown in Tables 3
and 5 could be replaced by a STOP followed by a START.
If a transaction targets an unused address, nothing is
written within the MAX11301 for write transactions, and
all zeros are read back for read transactions. Similarly, if
a write transaction targets a read-only register, nothing is
written to the device.
DAC
I
2
CSERIAL
INTERFACE
PORT GPI
±30mV
HYSTERESIS
SEQUENCER
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
DIGITAL
CORE
INT
I2C
SERIAL
INTERFACE GPO
SCALING
BLOCK
DAC
DIGITAL
CORE PORT
CURRENT LIMIT at 50mA
SEQUENCER
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
INT
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Figure 7. GPI Mode
Figure 8. GPO Mode
Burst Transaction Address
Incrementing Modes
With a burst transaction, the address of the initial register
is entered once. The data of the targeted register can then
be written or read. If the serial clock keeps running with-
out issuing RESTART, the device increments the address
pointer and writes or reads the next data after the next
two bytes. This scheme goes on until the host produces a
NACK (read transactions) or a STOP (write transactions).
There are two address incrementing modes. In one mode,
the address is simply incremented by one (default mode),
while in the other, the address is incremented contextu-
ally. When writing DAC data registers in a burst fashion
using contextual addressing, the host would write the
address of the first port that is DAC-configured (starting
from the lowest port index). As long as the host does not
issue a STOP and another two bytes are received, the
next DAC-configured port is written. This scheme contin-
ues until the last DAC-configured port is reached. At that
point, any additional serial clock cycle results in looping
back to the first DAC-configured port.
The contextual addressing scheme is only valid for writ-
ing DAC data registers, as described above, and reading
ADC data registers.
GPO
SCALING
BLOCK
ANY OTHER
PORT
GPI
ANY
PORT
SEQUENCER SEQUENCER
I2C
SERIAL
INTERFACE
DIGITAL
CORE
DAC DAC
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
INT
LOGIC
CONTROLLER
CHIP1 WITH VDD1
LOGIC LEVEL
V
DD1
PORT[i] PORT[i+1]
VDD2
LOGIC
CONTROLLER
CHIP2 WITH VDD2
LOGIC LEVEL
MAX11301
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Figure 9. Unidirectional Level Translator Path Mode
Figure 10. Bidirectional Level Translation Application Diagram
Interrupt Operations
The MAX11301 issues interrupts to alert the host of vari-
ous events. All events are recorded by the interrupt reg-
ister. The assertion of an interrupt register bit results in
the assertion of the interrupt port (INT) if that interrupt bit
is not masked.
By default, all interrupts are masked upon
power-up or reset.
The interrupts are listed hereafter.
The ADCFLAG (ADC Flag) interrupt indicates that the
ADC just completed a conversion or set of conversions.
It is asserted either at the end of a conversion when the
ADC is in single-conversion mode or at the end of a
sweep when the ADC is either in single-sweep mode or
continuous-sweep mode. ADCFLAG is cleared when the
interrupt register is read.
The ADCDR (ADC Data Ready) interrupt is asserted
when at least one ADC data register is refreshed. Since
one conversion per ADC-configured port is performed per
sweep, many sweeps may be required before refresh-
ing the data register of a given ADC-configured port that
utilizes the averaging function. (See the ADC Averaging
Function section) To determine which ADC-configured
port received a new data sample, the host must read
the ADC status registers. ADCDR is cleared after the
interrupt register and both ADC status registers are read
subsequently.
The ADCDM (ADC Data Missed) interrupt is asserted when
any ADC data register is not read by the host before new
data is stored in that ADC data register.
ADCDM is cleared
after the interrupt register is read.
The GPIER (GPI Event Received) interrupt indicates that
an event has been received on one of the GPI-configured
ports. Each GPI port can be configured to generate an
interrupt for an event such as detecting a rising edge, a
falling edge, or either edge at the corresponding port. If
the GPI port is configured to detect no edge, it is equiva-
lent to masking the interrupt related to that port. A GPI sta-
tus register allows the host to identify which port detected
the event. GPIER is cleared after the interrupt register
and both GPI status registers are read subsequently.
The GPIEM (GPI Event Missed) interrupt informs the
host that it did not service the GPI interrupt caused by the
occurrence of an event recorded by GPI status registers
before another event was received on the same port. The
host must read the interrupt register and the GPI status
registers whenever a GPI event received interrupt occurs;
otherwise, the GPIEM register is asserted upon receiving
the next event. This interrupt must be used in conjunction
with the GPIER interrupt bit to operate properly. GPIEM
is cleared after the interrupt register and both GPI status
registers are read subsequently.
The DACOI (DAC Overcurrent) interrupt indicates that
a DAC-configured port current exceeded approximately
50mA. This limit is not configurable. A DAC overcurrent
status register allows the host to identify which DAC-
configured port exceeded the 50mA current limit. DACOI
is cleared after the interrupt register is read, and both
DAC overcurrent status registers are read subsequently.
The TMPINT[2:0] (Internal Temperature Monitor) inter-
rupt has three sources of interrupt, each independently
controllable: a new internal temperature data is ready, the
internal temperature value exceeds the maximum limit, or
the internal temperature value is below the minimum limit.
TMPINT is cleared after the interrupt register is read.
The TMPEXT1[2:0] (1st External Temperature Monitor)
interrupt has three sources of interrupt, each indepen-
dently controllable: a new first external temperature data
is ready, the first external temperature value exceeds the
maximum limit, or the first external temperature value is
below the minimum limit. TMPEXT1 is cleared after the
interrupt register is read.
The TMPEXT2[2:0] (2nd External Temperature Monitor)
interrupt has three sources of interrupt, each indepen-
dently controllable: a new second external temperature
data is ready, the second external temperature value
exceeds the maximum limit, or the second external tem-
perature value is below the minimum limit. TMPEXT2 is
cleared after the interrupt register is read.
The VMON (High-Voltage Supply Monitor) Supply Voltage
Failure) interrupt is triggered when AVDDIO supply voltage
falls below 4V, approximately. VMON is cleared after the
interrupt register is read.
GPI ANY OTHER PORT
PIXI PORT[i+1]
PIXI PORT[i]
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Figure 11. PIXI Ports as a Controllable Analog Switch
Temperature Sensors Overview
The MAX11301 integrates one internal and two external
temperature sensors. The external sensors are diode-
connected transistors, typically a low-cost, easily mount-
ed 2N3904 NPN type, that replace conventional thermis-
tors or thermocouples. The external sensors’ accuracy
is typically ±1°C over the -40°C to +150°C temperature
range with no calibration necessary. Use of a transistor
with a different ideality factor produces a proportionate dif-
ference in the absolute measured temperature. Parasitic
series resistance results in a temperature reading error
of about 0.25°C per Ohm of resistance. The MAX11301
features a series resistance cancellation mode (RS_
CANCEL) that eliminates this error for resistances up
to 10Ω. The external sensors can also measure the
die temperature of other ICs, such as microprocessors,
that contain a substrate-connected diode available for
temperature-sensing purposes. Temperature data can be
read from the temperature data registers. The tempera-
ture data format is in two’s complement, with one LSB
representing 0.125°C.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Table 6. Register Table (Read/Write)
Register Description
Register bits that are shown unused do not impact device functionality and read out as “0”.
ADDRESS DESCRIPTION B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
0x00 (R) Device ID DEVID[15:0] 0x1424
0x01 (R) Interrupt VMON TMPEXT2[2:0] TMPEXT1[2:0] TMPINT[2:0] DACOI GPIDM GPIDR ADCDM ADCDR ADCFLAG 0x0000
0x02 (R) ADC data status;
ports 0-15 ADCST[15:0] 0x0000
0x03 (R) ADC data status;
ports 16-19 UNUSED ADCST[19:16] 0x0000
0x04 (R)
Overcurrent
status; ports
0-15
DACOIST[15:0] 0x0000
0x05 (R)
Overcurrent
status; ports
16-19 UNUSED DACOIST[19:16] 0x0000
0x06 (R) GPI status; ports
0-15 GPIST[15:0] 0x0000
0x07 (R) GPI status; ports
16-19 UNUSED GPIST[19:16] 0x0000
0x08 (R) Internal
temperature data UNUSED TMPINTDAT[11:0] 0x0000
0x09 (R) 1st external
temperature data UNUSED TMPEXT1DAT[11:0] 0x0000
0x0A (R) 2nd external
temperature data UNUSED TMPEXT2DAT[11:0] 0x0000
0x0B (R) GPI data; ports
15-0 GPIDAT[15:0] 0x0000
0x0C (R) GPI data; ports
19-16 UNUSED GPIDAT[19:16] 0x0000
0x0D (R/W) GPO data; ports
15-0 GPODAT[15:0] 0x0000
0x0E (R/W) GPO data; ports
19-16 UNUSED GPODAT[19:16] 0x0000
0x10 (R/W) Device control Reset BRST LPEN RS_CANCEL TMPPER TmPCTL[2:0] THSHDN DACREF ADCconv[1:0] DACCtL[1:0] ADCCTL[1:0] 0x0000
0x11 (R/W) Interrupt mask VMON
MSK
TMPEXT2
MSK[2:0]
TMPEXT1
MSK[2:0]
TMPINT
MSK[2:0]
DACOI
MSK
GPID
MMSK
GPIDR
MSK
ADCDM
MSK
ADCDR
MSK
ADCFLAG
MSK 0xFFFF
0x12 (R/W) GPI IRQ mode;
ports 0–7 GPIMD_7[1:0] GPIMD_6[1:0] GPIMD_5[1:0] GPIMD_4[1:0] GPIMD_3[1:0] GPIMD_2[1:0] GPIMD_1[1:0] GPIMD_0[1:0] 0x0000
0x13 (R/W) GPI IRQ mode;
ports 8–15 GPIMD_15[1:0] GPIMD_14[1:0] GPIMD_13[1:0] GPIMD_12[1:0] GPIMD_11[1:0] GPIMD_10[1:0] GPIMD_9[1:0] GPIMD_8[1:0] 0x0000
0x14 (R/W) GPI IRQ mode;
ports 16–19 UNUSED GPIMD_19[1:0] GPIMD_18[1:0] GPIMD_17[1:0] GPIMD_16[1:0] 0x0000
0x16 (R/W) DAC preset
data #1 UNUSED DACPRSTDAT1[11:0] 0x0000
0x17 (R/W) DAC preset
data #2 UNUSED DACPRSTDAT2[11:0] 0x0000
0x18 (R/W)
Temperature
monitor
Conguration UNUSED TMPEXT2MONCFG
[1:0]
TMPEXT1MONCFG
[1:0]
TMPINTMONCFG
[1:0] 0x0000
0x19 (R/W)
Internal
temperature high
threshold UNUSED TMPINTHI[11:0] 0x07FF
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
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Table 6. Register Table (continued)
ADDRESS DESCRIPTION B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
0x1A (R/W)
Internal
temperature low
threshold UNUSED TMPINTLO[11:0] 0x0800
0x1B (R/W)
1st external
temperature high
threshold UNUSED TMPEXT1HI[11:0] 0x07FF
0x1C (R/W)
1st external
temperature low
threshold UNUSED TMPEXT1LO[11:0] 0x0800
0x1D (R/W)
2nd external
temperature high
threshold UNUSED TMPEXT2HI[11:0] 0x07FF
0x1E (R/W)
2nd external
temperature low
threshold UNUSED TMPEXT2LO[11:0] 0x0800
0x20 (R/W) Port 0
conguration FUNCID_0[3:0] FUNCPRM_0[11:0] 0x0000
0x21 (R/W) Port 1
conguration FUNCID_1[3:0] FUNCPRM_1[11:0] 0x0000
0x22 (R/W) Port 2
conguration FUNCID_2[3:0] FUNCPRM_2[11:0] 0x0000
0x23 (R/W) Port 3
conguration FUNCID_3[3:0] FUNCPRM_3[11:0] 0x0000
0x24 (R/W) Port 4
conguration FUNCID_4[3:0] FUNCPRM_4[11:0] 0x0000
0x25 (R/W) Port 5
conguration FUNCID_5[3:0] FUNCPRM_5[11:0] 0x0000
0x26 (R/W) Port 6
conguration FUNCID_6[3:0] FUNCPRM_6[11:0] 0x0000
0x27 (R/W) Port 7
conguration FUNCID_7[3:0] FUNCPRM_7[11:0] 0x0000
0x28 (R/W) Port 8
conguration FUNCID_8[3:0] FUNCPRM_8[11:0] 0x0000
0x29 (R/W) Port 9
conguration FUNCID_9[3:0] FUNCPRM_9[11:0] 0x0000
0x2A (R/W) Port 10
conguration FUNCID_10[3:0] FUNCPRM_10[11:0] 0x0000
0x2B (R/W) Port 11
conguration FUNCID_11[3:0] FUNCPRM_11[11:0] 0x0000
0x2C (R/W) Port 12
conguration FUNCID_12[3:0] FUNCPRM_12[11:0] 0x0000
0x2D (R/W) Port 13
conguration FUNCID_13[3:0] FUNCPRM_13[11:0] 0x0000
0x2E (R/W) Port 14
conguration FUNCID_14[3:0] FUNCPRM_14[11:0] 0x0000
0x2F (R/W) Port 15
conguration FUNCID_15[3:0] FUNCPRM_15[11:0] 0x0000
0x30 (R/W) Port 16
conguration FUNCID_16[3:0] FUNCPRM_16[11:0] 0x0000
0x31 (R/W) Port 17
conguration FUNCID_17[3:0] FUNCPRM_17[11:0] 0x0000
0x32 (R/W) Port 18
conguration FUNCID_18[3:0] FUNCPRM_18[11:0] 0x0000
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
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Table 6. Register Table (continued)
ADDRESS DESCRIPTION B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
0x33 (R/W) Port 19
conguration FUNCID_19[3:0] FUNCPRM_19[11:0] 0x0000
0x40 (R) Port 0 ADC data UNUSED ADCDAT_0[11:0] 0x0000
0x41 (R) Port 1 ADC data UNUSED ADCDAT_1[11:0] 0x0000
0x42 (R) Port 2 ADC data UNUSED ADCDAT_2[11:0] 0x0000
0x43 (R) Port 3 ADC data UNUSED ADCDAT_3[11:0] 0x0000
0x44 (R) Port 4 ADC data UNUSED ADCDAT_4[11:0] 0x0000
0x45 (R) Port 5 ADC data UNUSED ADCDAT_5[11:0] 0x0000
0x46 (R) Port 6 ADC data UNUSED ADCDAT_6[11:0] 0x0000
0x47 (R) Port 7 ADC data UNUSED ADCDAT_7[11:0] 0x0000
0x48 (R) Port 8 ADC data UNUSED ADCDAT_8[11:0] 0x0000
0x49 (R) Port 9 ADC data UNUSED ADCDAT_9[11:0] 0x0000
0x4A (R) Port 10 ADC data UNUSED ADCDAT_10[11:0] 0x0000
0x4B (R) Port 11 ADC data UNUSED ADCDAT_11[11:0] 0x0000
0x4C (R) Port 12 ADC data UNUSED ADCDAT_12[11:0] 0x0000
0x4D (R) Port 13 ADC data UNUSED ADCDAT_13[11:0] 0x0000
0x4E (R) Port 14 ADC data UNUSED ADCDAT_14[11:0] 0x0000
0x4F (R) Port 15 ADC data UNUSED ADCDAT_15[11:0] 0x0000
0x50 (R) Port 16 ADC data UNUSED ADCDAT_16[11:0] 0x0000
0x51 (R) Port 17 ADC data UNUSED ADCDAT_17[11:0] 0x0000
0x52 (R) Port 18 ADC data UNUSED ADCDAT_18[11:0] 0x0000
0x53 (R) Port 19 ADC data UNUSED ADCDAT_19[11:0] 0x0000
0x60 (R/W) Port 0 DAC data UNUSED DACDAT_0[11:0] 0x0000
0x61 (R/W) Port 1 DAC data UNUSED DACDAT_1[11:0] 0x0000
0x62 (R/W) Port 2 DAC data UNUSED DACDAT_2[11:0] 0x0000
0x63 (R/W) Port 3 DAC data UNUSED DACDAT_3[11:0] 0x0000
0x64 (R/W) Port 4 DAC data UNUSED DACDAT_4[11:0] 0x0000
0x65 (R/W) Port 5 DAC data UNUSED DACDAT_5[11:0] 0x0000
0x66 (R/W) Port 6 DAC data UNUSED DACDAT_6[11:0] 0x0000
0x67 (R/W) Port 7 DAC data UNUSED DACDAT_7[11:0] 0x0000
0x68 (R/W) Port 8 DAC data UNUSED DACDAT_8[11:0] 0x0000
0x69 (R/W) Port 9 DAC data UNUSED DACDAT_9[11:0] 0x0000
0x6A (R/W) Port 10 DAC data UNUSED DACDAT_10[11:0] 0x0000
0x6B (R/W) Port 11 DAC data UNUSED DACDAT_11[11:0] 0x0000
0x6C (R/W) Port 12 DAC data UNUSED DACDAT_12[11:0] 0x0000
0x6D (R/W) Port 13 DAC data UNUSED DACDAT_13[11:0] 0x0000
0x6E (R/W) Port 14 DAC data UNUSED DACDAT_14[11:0] 0x0000
0x6F (R/W) Port 15 DAC data UNUSED DACDAT_15[11:0] 0x0000
0x70 (R/W) Port 16 DAC data UNUSED DACDAT_16[11:0] 0x0000
0x71 (R/W) Port 17 DAC data UNUSED DACDAT_17[11:0] 0x0000
0x72 (R/W) Port 18 DAC data UNUSED DACDAT_18[11:0] 0x0000
0x73 (R/W) Port 19 DAC data UNUSED DACDAT_19[11:0] 0x0000
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PIXI, 20-Port Programmable Mixed-Signal I/O with
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Register Detailed Description
Device ID Register (Read)
Interrupt Register (Read)
BIT FIELD NAME DESCRIPTION
15:0 DEVID[15:0] Device ID
0001_0100_0010_0100
BIT FIELD NAME DESCRIPTION
0 ADCFLAG ADC ag interrupt
• Asserted when the ADC completes a conversion (ADC set in single-conversion mode) or when
the ADC completes a sweep (ADC set in single-sweep or continuous-sweep mode).
• No interrupt is generated when the ADC is in idle mode.
• Cleared after the interrupt register is read.
1 ADCDR ADC data ready interrupt
• Asserted when any ADC data register receives a new data sample. If a port is congured to
average 2N samples, it takes 2N sweeps for that port data register to be refreshed and assert
ADCDR.
• Data registers are refreshed either at the end of a conversion (ADC set in single-conversion
mode) or at the end of a sweep (ADC set in single-sweep or continuous-sweep mode).
• Cleared after the interrupt register is read, and after both ADCST[15:0] and ADCST[19:16]
registers are read subsequently.
2 ADCDM ADC data missed interrupt
• Asserted when the host missed reading a port’s ADC data register by the time that port’s ADC
data register is overwritten by new data.
• Cleared after the interrupt register is read.
3 GPIDR GPI event ready interrupt
• Asserted when a new event is captured by GPI-congured ports. The type of event is set by the
corresponding GPI IRQ mode register. The host can then consult GPIST[15:0] and GPIST[19:16]
registers to identify the port that caused the interrupt.
• Cleared after the interrupt register is read, and after both GPIST[15:0] and GPIST[19:16] are read
subsequently.
4 GPIDM GPI event missed interrupt
• Asserted when the host missed reading the GPI status register by the time that register is
overwritten.
• Must be used in conjunction with GPIDR for proper operation.
• Cleared after the interrupt register is read, and after both GPIST[15:0] and GPIST[19:16] are read
subsequently.
5 DACOI DAC driver overcurrent interrupt
• Asserted when the DAC driver current exceeds approximately 50mA. The host can then read
DACOIST[15:0] and DACOIST[19:16] to identify the port that caused the interrupt.
• Cleared after the interrupt register is read, and after both DACOIST[15:0] and DACOIST[19:16]
registers are read subsequently.
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PIXI, 20-Port Programmable Mixed-Signal I/O with
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Interrupt Register (Read) (continued)
ADC Status Registers (Read)
Overcurrent Status Registers (Read)
BIT FIELD NAME DESCRIPTION
8:6 TMPINT[2:0] Internal temperature interrupts
• TMPINT[2]: Asserted when the internal temperature value is larger than the value stored in
TMPINTHI[11:0]. Cleared after the interrupt register is read.
• TMPINT[1]: Asserted when the internal temperature value is lower than the value stored in
TMPINTLO[11:0]. Cleared after the interrupt register is read.
• TMPINT[0]: Asserted when a new temperature value is available. Cleared after the interrupt
register is read.
11:9 TMPEXT1[2:0] 1st external temperature interrupts
• TMPEXT1[2]: Asserted when the 1st external temperature value is larger than the value stored in
TMPEXT1HI[11:0]. Cleared after the interrupt register is read.
• TMPEXT1[1]: Asserted when the 1st external temperature value is lower than the value stored in
TMPEXT1LO[11:0]. Cleared after the interrupt register is read.
• TMPEXT1[0]: Asserted when a new temperature value is available. Cleared after the interrupt
register is read.
14:12 TMPEXT2[2:0] 2nd external temperature interrupts
• TMPEXT2[2]: Asserted when the 2nd external temperature value is larger than the value stored in
TMPEXT2HI[11:0]. Cleared after the interrupt register is read.
• TMPEXT2[1]: Asserted when the 2nd external temperature value is lower than the value stored in
TMPEXT2LO[11:0]. Cleared after the interrupt register is read.
• TMPEXT2[0]: Asserted when a new temperature value is available. Cleared after the interrupt
register is read.
15 VMON High-voltage supply monitor interrupt
• Asserted when the high voltage supply (AVDDIO) falls below approximately 4V.
• Cleared after the interrupt register is read.
BIT FIELD NAME DESCRIPTION
15:0
3:0
DACOIST[15:0]
DACOIST[19:16]
Status of DAC drivers overcurrent for ports 0 to 19
• Once a port driver exceeds approximately 50mA, the host can identify which driver caused the
interrupt by reading DACOIST[15:0] and DACOIST[19:16].
• This register content is not affected by any related interrupt mask. Activity on overcurrent
detection is recorded by these registers regardless of the mask interrupt register setting.
• Cleared after the interrupt register is read, and after both DACOIST[15:0] and DACOIST[19:16]
registers are read, subsequently.
BIT FIELD NAME DESCRIPTION
15:0
3:0
ADCST[15:0]
ADCST[19:16]
Status of ADC data received for ports 0 to 19
• Once new data is written in an ADC data register, the corresponding ADCST bit is asserted. The new
data is written only after the set of samples to average is collected when the averaging function is
enabled.
• This register content is not affected by any related interrupt mask. Activity on ADC-congured ports
is recorded by this register regardless of the mask interrupt register setting.
• Cleared after the interrupt register is read, and after both ADCST[15:0] and ADCST[19:16] registers
are read, subsequently.
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PIXI, 20-Port Programmable Mixed-Signal I/O with
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Internal Temperature Data Register (Read)
1st External Temperature Data Register (Read)
2nd External Temperature Data Register (Read)
GPI Status Registers (Read)
BIT FIELD NAME DESCRIPTION
11:0 TMPINTDAT[11:0] Internal temperature measurement data
• Temperature measurement produced by the internal temperature sensor.
• The data sample is represented in two’s complement, and one LSB represents 0.125°C.
BIT FIELD NAME DESCRIPTION
11:0 TMPEXT1DAT[11:0] 1st external temperature measurement data
• Temperature measurement produced by the rst external temperature sensor.
• The data sample is represented in two’s complement, and one LSB represents 0.125°C.
BIT FIELD NAME DESCRIPTION
11:0 TMPEXT2DAT[11:0] 2nd external temperature measurement data
• Temperature measurement produced by the second external temperature sensor.
• The data sample is represented in two’s complement, and one LSB represents 0.125°C.
BIT FIELD NAME DESCRIPTION
15:0
3:0
GPIST[15:0]
GPIST[19:16]
Status of GPI event detection for ports 0 to 19
• Asserted when an event is detected on a GPI-congured port. The type of event to detect is
set by the corresponding GPI IRQ register.
• Once a GPIDT interrupt is generated, the host can identify which GPI port(s) caused the
interrupt by reading GPIST[15:0] and GPIST[19:16] registers.
• GPIST content is not affected by any related interrupt mask. Activity on GPI-congured ports
is recorded by GPIST regardless of the mask interrupt register setting.
• Cleared after the interrupt register is read, and after both GPIST[15:0] and GPIST[19:16]
registers are read, subsequently.
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Interrupt Mask Register (Read/Write)
BIT FIELD NAME DESCRIPTION
0 ADCFLAGMSK ADC ag interrupt mask
• Masks ADCFLAG interrupt bit when asserted.
• In ADC continuous-sweep mode, INT is asserted for 100nS at the end of each sweep whether
ADCFLAG interrupt is cleared or not.
• 1: Prevents the assertion of ADCFLAG interrupt bit from pulling INT low.
• 0: Allows the assertion of ADCFLAG interrupt bit to pull INT low.
1 ADCDRMSK ADC data ready interrupt mask
• Masks ADCDR interrupt bit when asserted.
• 1: Prevents the assertion of ADCDR interrupt bit from pulling INT low.
• 0: Allows the assertion of ADCDR interrupt bit to pull INT low.
2 ADCDMMSK ADC data missed interrupt mask
• Masks ADCDM interrupt bit when asserted.
• 1: Prevents the assertion of ADCDM interrupt bit from pulling INT low.
• 0: Allows the assertion of ADCDM interrupt bit to pull INT low.
3 GPIDRMSK GPI event ready interrupt
• Masks GPIDR interrupt bit when asserted.
• Supersedes the settings in the GPI IRQ Mode registers.
• 1: Prevents the assertion of GPIDR interrupt bit from pulling INT low.
• 0: Allows the assertion of GPIDR interrupt bit to pull INT low.
4 GPIDMMSK GPI event missed interrupt mask
• Masks GPIDM interrupt bit when asserted.
• Can be deasserted only if GPIDRMSK is deasserted.
• 1: Prevents the assertion of GPIDM interrupt bit from pulling INT low.
• 0: Allows the assertion of GPIDM interrupt bit to pull INT low.
5 DACOIMSK DAC driver overcurrent interrupt mask
• Masks DACOI interrupt bit when asserted.
• 1: Prevents the assertion of DACOI interrupt bit from pulling INT low.
• 0: Allows the assertion of DACOI interrupt bit to pull INT low.
8:6 TMPINTMSK[2:0] Internal temperature interrupt mask
• Masks TMPINT[2:0] interrupt bits when asserted on a bit-by-bit basis.
• 1: Prevents the assertion of TMPINT[i] interrupt bit from pulling INT low (0≤i≤2).
• 0: Allows the assertion of TMPINT[i] interrupt bit to pull INT low (0≤i≤2).
11:9 TMPEXT1MSK[2:0] 1st external temperature interrupt mask
• Masks TMPEXT1[2:0] interrupt bits when asserted on a bit-by-bit basis.
• 1: Prevents the assertion of TMPEXT1[i] interrupt bit from pulling INT low (0≤i≤2).
• 0: Allows the assertion of TMPEXT1[i] interrupt bit to pull INT low (0≤i≤2).
14:12 TMPEXT2MSK[2:0] 2nd external temperature interrupt mask
• Masks TMPEXT2[2:0] interrupt bits when asserted on a bit-by-bit basis.
• 1: Prevents the assertion of TMPEXT2[i] interrupt bit from pulling INT low (0≤i≤2).
• 0: Allows the assertion of TMPEXT2[i] interrupt bit to pull INT low (0≤i≤2).
15 VMONMSK High-voltage supply monitor mask
• Masks VMON interrupt bit when asserted.
• 1: Prevents the assertion of VMON interrupt bit from pulling INT low.
• 0: Allows the assertion of VMON interrupt bit to pull INT low.
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PIXI, 20-Port Programmable Mixed-Signal I/O with
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GPI IRQ Mode Registers (Read/Write)
Device Control Register (Read/Write)
BIT FIELD NAME DESCRIPTION
1:0
3:2
5:4
7:6
9:8
11:10
13:12
GPIMD_0[1:0]
GPIMD_1[1:0]
GPIMD_2[1:0]
GPIMD_3[1:0]
GPIMD_4[1:0]
GPIMD_5[1:0]
GPIMD_6[1:0]
GPI interrupt request mode for ports 0 to 19
• Each input port is controlled by GPIMD, a 2-bit code.
• For a given port i (0≤i≤19):
• GPIMD_i[1:0] = 00: GPIST[i] is never asserted
• GPIMD_i[1:0] = 01: GPIST[i] is asserted upon detection of a positive edge
• GPIMD_i[1:0] = 10: GPIST[i] is asserted upon detection of a negative edge
• GPIMD_i[1:0] = 11: GPIST[i] is asserted upon detection of a positive or a negative edge
15:14 GPIMD_7[1:0]
1:0 GPIMD_8[1:0]
3:2 GPIMD_9[1:0]
5:4 GPIMD_10[1:0]
7:6 GPIMD_11[1:0]
9:8 GPIMD_12[1:0]
11:10 GPIMD_13[1:0]
13:12 GPIMD_14[1:0]
15:14 GPIMD_15[1:0]
1:0 GPIMD_16[1:0]
3:2 GPIMD_17[1:0]
5:4 GPIMD_18[1:0]
7:6 GPIMD_19[1:0]
BIT FIELD NAME DESCRIPTION
1:0 ADCCTL[1:0] ADC conversion mode selection
• 00: Idle mode – The ADC does not perform any conversion.
• 01: Single sweep – The ADC performs one conversion for each of the ADC-congured ports
sequentially. The assertion of CNVT triggers the single sweep. The sweep starts with the ADC-
congured port of lowest index and stops with the ADC-congured port of highest index.
• 10: Single conversion – The ADC performs one conversion for the current port. It starts with
the lowest index port that is ADC-congured, and it progresses to higher index ports as CNVT
is asserted.
• 11: Continuous sweep – This mode is not controlled by CNVT. The ADC continuously sweeps
the ADC-congured ports.
3:2 DACCTL[1:0] DAC mode selection
• 00: Sequential update mode for DAC-congured ports.
• 01: Immediate update mode for DAC-congured ports. The DAC-congured port that received
new data is the next port to be updated. After updating that port, the DAC- congured port
update sequence continues from that port onward. A minimum of 80µs must be observed
before requesting another immediate update.
• 10: All DAC-congured ports use the same data stored in DACPRSTDAT1[11:0].
• 11: All DAC-congured ports use the same data stored in DACPRSTDAT2[11:0].
5:4 ADCCONV[1:0] ADC conversion rate selection
• 00: ADC conversion rate of 200ksps (default)
• 01: ADC conversion rate of 250ksps
• 10: ADC conversion rate of 333ksps
• 11: ADC conversion rate of 400ksps
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PIXI, 20-Port Programmable Mixed-Signal I/O with
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Device Control Register (Read/Write) (continued)
GPI Data Registers (Read)
BIT FIELD NAME DESCRIPTION
6 DACREF DAC voltage reference selection
• 0: External reference voltage
• 1: Internal reference voltage
7 THSHDN Thermal shutdown enable
• 0: Thermal shutdown function disabled.
• 1: Thermal shutdown function enabled. If the internal temperature monitor is enabled, and
if the internal temperature is measured to be larger than 145°C, the device is reset, thus
bringing all channels to high-impedance mode and setting all registers to their default value.
10:8 TMPCTL[2:0] Temperature monitor selection
• TMPCTL[0]: Internal temperature monitor (0: disabled; 1: enabled)
• TMPCTL[1]: 1st external temperature monitor (0: disabled; 1: enabled)
• TMPCTL[2]: 2nd external temperature monitor (0: disabled; 1: enabled)
11 TMPPER Temperature conversion time control
• 0: Default conversion time setting. Selected for junction capacitance lter < 100pF.
• 1: Extended conversion time setting. Selected for junction capacitance lter from 100pF to
390pF
12 RS_CANCEL Temperature sensor series resistor cancellation mode
• 0: Temperature sensor series resistance cancellation disabled.
• 1: Temperature sensor series resistance cancellation enabled.
13 LPEN Power mode selection
• 0: Default power mode for normal operations
• 1: Lower power mode. The analog ports are in high-impedance mode. The device can be
brought out of the lower power mode by deasserting this bit. The device would then undergo
the regular power-on sequence.
14 BRST Serial interface burst-mode selection
• 0: Default address incrementing mode. The address is automatically incremented by “1” in
burst mode.
• 1: Contextual address incrementing mode. In burst mode, the address automatically points
to the next ADC- or DAC-congured port data register. Specically, when reading ADC data
(writing DAC data), the serial interface reads (writes to) only the data registers of those ports
that are ADC-congured (DAC-congured). This mode applies to ADC data read and DAC
data write, not DAC data read.
15 RESET Soft reset control
• Self-clearing soft reset register, equivalent to power-on reset.
BIT FIELD NAME DESCRIPTION
15:0
3:0
GPIDAT[15:0]
GPIDAT[19:16]
Data received on GPI ports 0 to 19
• The data received on GPI-congured ports can be read by the host.
• For a given port i (0≤i≤19)
• GPIDAT[i] = 0: A logic zero level is received at GPI port i
• GPIDAT[i] = 1: A logic one level is received at GPI port i
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GPO Data Registers (Read/Write)
DAC Preset Data Registers (Read/Write)
Temperature Monitor Conguration Register (Read/Write)
Internal Temperature Monitor High Threshold Register (Read/Write)
BIT FIELD NAME DESCRIPTION
15:0
3:0
GPODAT[15:0]
GPODAT[19:16]
Data transmitted through GPO ports 0 to 19
• Data written by the host to be transmitted through the GPO-congured ports
• For a given port i (0≤i≤19):
• GPIDAT[i] = 0: A logic zero level is transmitted through GPO port i
• GPIDAT[i] = 1: A logic one level is transmitted through GPO port i
BIT FIELD NAME DESCRIPTION
1:0 TMPINTMONCFG[1:0] Number of samples averaged for calculating the internal temperature
• 00: 4 samples
• 01: 8 samples
• 10: 16 samples
• 11: 32 samples
3:2 TMPEXT1MONCFG[1:0] Number of samples averaged for calculating the 1st external temperature
• 00: 4 samples
• 01: 8 samples
• 10: 16 samples
• 11: 32 samples
5:4 TMPEXT2MONCFG[1:0] Number of samples averaged for calculating the 2nd external temperature
• 00: 4 samples
• 01: 8 samples
• 10: 16 samples
• 11: 32 samples
BIT FIELD NAME DESCRIPTION
11:0 TMPINTHI[11:0] Internal temperature monitor high threshold
• Maximum temperature value beyond which TMPINT[2] is asserted.
• This value is represented in two’s complement; one LSB represents 0.125°C.
BIT FIELD NAME DESCRIPTION
11:0
11:0
DACPRSTDAT1[11:0]
DACPRSTDAT2[11:0]
DAC preset data register 1 and 2
• DAC data used by all ports congured in a DAC-related mode (1, 3, 4, 5, 6, and 10)
• Writing to these registers does not alter the contents of the DAC data registers
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Internal Temperature Monitor Low Threshold Register (Read/Write)
1st External Temperature Monitor High Threshold Register (Read/Write)
1st External Temperature Monitor Low Threshold Register (Read/Write)
2nd External Temperature Monitor High Threshold Register (Read/Write)
2nd External Temperature Monitor Low Threshold Register (Read/Write)
BIT FIELD NAME DESCRIPTION
11:0 TMPINTLO[11:0] Internal temperature monitor low threshold
• Minimum temperature value below which TMPINT[1] is asserted.
• This value is represented in two’s complement; one LSB represents 0.125°C.
BIT FIELD NAME DESCRIPTION
11:0 TMPEXT1HI[11:0] 1st external temperature monitor high threshold
• Maximum temperature value beyond which TMPEXT1[2] is asserted.
• This value is represented in two’s complement; one LSB represents 0.125°C.
BIT FIELD NAME DESCRIPTION
11:0 TMPEXT1LO[11:0] 1st external temperature monitor low threshold
• Minimum temperature value below which TMPEXT1[1] is asserted.
• This value is represented in two’s complement; one LSB represents 0.125°C.
BIT FIELD NAME DESCRIPTION
11:0 TMPEXT2HI[11:0] 2nd external temperature monitor high threshold
• Maximum temperature value beyond which TMPEXT2[2] is asserted.
• This value is represented in two’s complement; one LSB represents 0.125°C.
BIT FIELD NAME DESCRIPTION
11:0 TMPEXT2LO[11:0] 2nd external temperature monitor low threshold
• Minimum temperature value below which TMPEXT2[1] is asserted.
• This value is represented in two’s complement; one LSB represents 0.125°C.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Port Conguration Registers (Read/Write)
BIT FIELD NAME DESCRIPTION
11:0 FUNCPRM_0[11:0]
FUNCPRM_1[11:0]
FUNCPRM_2[11:0]
FUNCPRM_3[11:0]
FUNCPRM_4[11:0]
FUNCPRM_5[11:0]
FUNCPRM_6[11:0]
FUNCPRM_7[11:0]
FUNCPRM_8[11:0]
FUNCPRM_9[11:0]
FUNCPRM_10[11:0]
FUNCPRM_11[11:0]
FUNCPRM_12[11:0]
FUNCPRM_13[11:0]
FUNCPRM_14[11:0]
FUNCPRM_15[11:0]
FUNCPRM_16[11:0]
FUNCPRM_17[11:0]
FUNCPRM_18[11:0]
FUNCPRM_19[11:0]
FUNCPRM_i[4:0]: ASSOCIATED PORT
• Denes the port to use in conjunction with a port congured in mode 4, 8, or 11.
FUNCPRM_i[7:5]: # OF SAMPLES (for ADC-related functional modes only)
• Denes the number of samples to be captured and averaged before loading the result in the
port’s ADC data register. The coding of the number of samples is 2# OF SAMPLES. The number of
samples to average can be 1, 2, 4, 8, 16, 32, 64, or 128.
FUNCPRM_i[10:8]: RANGE
• Determines the input voltage range of ports congured in input modes, or the output voltage
range of ports congured in output modes.
• In ADC- or DAC-related modes, RANGE cannot be set to 000.
VOLTAGE RANGE CODES ADC VOLTAGE RANGE (V) DAC VOLTAGE RANGE (V)
000 No Range Selected No Range Selected
001 0 to +10 0 to +10
010 -5 to +5 -5 to +5
0 11 -10 to 0 -10 to 0
100 0 to +2.5 -5 to +5
101 Reserved Reserved
11 0 0 to +2.5 0 to +10
111 Reserved Reserved
FUNCPRM_i[11]: AVR (for ADC-related functional modes only)
• ADC voltage reference selection
• 0: ADC internal voltage reference
• 1: ADC external voltage reference (all modes except mode 6) or DAC voltage reference
determined by DACREF (mode 6 only)
FUNCPRM_i[11]: INV (for GPI-controlled functional modes only)
• Asserted to invert the data received by the GPI-congured port.
• 0: Data received from GPI-congured port is not inverted
• 1: Data received from GPI-congured port is inverted
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Port Configuration Registers (Read/Write) (continued)
BIT FIELD NAME DESCRIPTION
15:12 FUNCID_0[3:0]
FUNCID_1[3:0]
FUNCID_2[3:0]
FUNCID_3[3:0]
FUNCID_4[3:0]
FUNCID_5[3:0]
FUNCID_6[3:0]
FUNCID_7[3:0]
FUNCID_8[3:0]
FUNCID_9[3:0]
FUNCID_10[3:0]
FUNCID_11[3:0]
FUNCID_12[3:0]
FUNCID_13[3:0]
FUNCID_14[3:0]
FUNCID_15[3:0]
FUNCID_16[3:0]
FUNCID_17[3:0]
FUNCID_18[3:0]
FUNCID_19[3:0]
Functional mode for port i (0≤i≤19)
• When switching from one mode to another, it is recommended to rst switch to the high-
impedance mode. The duration for which the device may need to stay in the transitional high-
impedance mode depends on the application and hardware conguration.
• 0000: Mode 0 - High impedance
• The port is congured in high-impedance mode.
• 0001: Mode 1 - Digital input with programmable threshold, GPI (Figure 7)
• The port is congured as a GPI whose threshold is set through the DAC data register.
The DAC data register for that port needs to be set to the value corresponding to the
intended input threshold voltage. Any input voltage above that programmed threshold is
reported as a logic one. The input voltage must be between 0V and 5V.
• To avoid false interrupts, the port’s GPIERMSK register bit must be asserted. The DAC
data register can then be set for the desired threshold voltage. It may take up to 1ms for
the threshold voltage to be effective. The port’s GPIMD register bit is set next. At that
point,
GPIERMSK can be deasserted for the port to start detecting events. The data resulting
from the comparison between the threshold voltage and the voltage at the port can be
read from the corresponding GPIDAT register bit.
• 0010: Mode 2 - Bidirectional level translator terminal (Figure 10)
• Any pair of adjacent ports can form a bidirectional level translator path. Only the lower
index port of the pair needs to be congured to enable this mode. The other port (index
+ 1) must be set in high-impedance mode.
• Port 19 cannot be set in mode 2.
• The activity on this port is observable through its GPI path. The GPI-related registers are
congured as described for mode 1.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Port Configuration Registers (Read/Write) (continued)
BIT FIELD NAME DESCRIPTION
• 0011: Mode 3 - Register-driven digital output with DAC-controlled level, GPO (Figure 8)
• The port is congured as a GPO driven by the corresponding GPODAT register bit.
The logic one level is set by the DAC data register of that port.
• The port’s DAC data register needs to be set rst. It may require up to 1ms for the
port to be ready to produce the desired logic one level. At that point, the port can
be set in mode 3. The logic level at the port is then controlled by the corresponding
GPODAT
register bit.
• 0100: Mode 4 - Unidirectional path output with DAC-controlled level, GPO (Figure 9)
• The port is congured as a GPO forming the output of a unidirectional level
translator path. The input port of that path is specied by the functional parameter,
ASSOCIATED PORT, and that port must be separately congured in GPI mode. The
port’s DAC data register denes the logic one level. The data received by the GPI-
congured port is transmitted by this port congured in mode 4.
• The data from the associated GPI-congured port can be inverted by asserting the
functional parameter INV.
• Multiple ports congured in mode 4 can refer to the same GPI-congured port
through the functional parameter, ASSOCIATED PORT. Therefore, one GPI-
congured port can transmit its data to multiple ports congured in mode 4.
• To avoid false interrupts and unexpected activity at the port congured in mode 4,
the GPI port must be congured before this port is congured in mode 4.
• Functional parameters to be set: INV, ASSOCIATED PORT
• 0101: Mode 5 - Analog output for DAC (Figure 5)
The port’s DAC data register must be set for the desired voltage at the port. It may
take up to 1ms for the port to reect the data written in the DAC data register.
• Functional parameters to be set: RANGE (codes 001, 010, and 011 apply to this
mode).
• 0110: Mode 6 - Analog output for DAC with ADC monitoring (Figure 6)
• In addition to the functionality of mode 5, the port is sampled by the ADC. The result
of
the ADC conversion is stored in the port’s ADC data register. The host can access
that
register to monitor the voltage at the port.
• When the ADC input voltage range is set from 0V to 2.5V, (RANGE = 100 or 110), the
DAC data register value must be limited to the range of values corresponding to 0V
to
2.5V at the port. Internally, the DAC data register value is clipped, so that the PIXI
port voltage is contained within a range from 0V to 5V to prevent device damage.
• Functional parameters to be set: AVR, RANGE
• 0111: Mode 7 - Positive analog input to single-ended ADC (Figure 2)
• The port is congured as a single-ended ADC input.
• Functional parameters to be set: AVR, RANGE, # OF SAMPLES
• 1000: Mode 8 - Positive analog input to differential ADC (Figure 3)
• The port is congured as a differential ADC positive input.
• Functional parameters to be set: AVR, RANGE, # OF SAMPLES, ASSOCIATED PORT
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Port Configuration Registers (Read/Write) (continued)
BIT FIELD NAME DESCRIPTION
• 1001: Mode 9 - Negative analog input to differential ADC
• The port is congured as a differential ADC negative input.
• The number of samples to average is dened by the associated positive port. The
functional parameters AVR and RANGE must be identical to those used by the
corresponding positive port.
• A port congured in mode 9 can be associated to more than one port congured in
mode 8.
• Functional parameters to be set: AVR, RANGE
• 1010: Mode 10 - Analog output for DAC and negative analog input to differential ADC
(Figure 4)
• While this port drives the voltage corresponding to its DAC data register, it also
operates as the negative input for the ADC.
• The number of samples to average is dened by the associated positive port. The
functional parameters AVR and RANGE must be identical to those used by the
corresponding positive port.
• A port congured in mode 10 can be associated to more than one port congured in
mode 8.
• When the ADC input voltage range is set from 0V to 2.5V (RANGE = 100 or 110), the
DAC data register value must be limited to the range of values corresponding to 0V
to
2.5V at the port. Internally, the DAC data register value is clipped, so that the PIXI
port voltage is contained within a range from 0V to 5V to prevent device damage.
• Functional parameters to be set: AVR, RANGE
• 1011: Mode 11 - Terminal to GPI-controlled analog switch (Figure 11)
• In this mode, two adjacent ports can be connected together through an analog
switch controlled by a GPI-congured port (designated by the functional parameter
ASSOCIATED PORT). This function involves three ports. The switch controlling port
needs to be separately congured in GPI mode. Only the port with the lower index
needs to be congured in mode 11. The port with the higher index can be congured
in any other mode, except mode 2. If the port of higher index operates in an ADC-
related mode (mode 6, 7, 8, or 9), the signals applied to the port in mode 11 must
comply with the input voltage range for which the port of higher index is congured.
• Port 19 cannot be congured in mode 11, as there is no switch between ports 0 and
19.
• Functional parameters to be set: INV, ASSOCIATED PORT
• 1100: Mode 12 - Terminal to register-controlled analog switch
• This mode is identical to Mode 11, except that the switch remains closed as long as this
port is congured in mode 12.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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*Port must be configured separately to a compatible mode.
Table 7. Port Functional Modes
FUNCID[3:0] FUNCPRM[11:0]
MODE DESCRIPTION 15 14 13 12 11 10 9 8 7 6 54 3 2 1 0
0High impedance 0 0 0 0
1
Digital input with
programmable
threshold, GPI
0 0 0 1
2Bidirectional level
translator terminal 0 0 1 0
3
Register-driven digital
output with DAC-
controlled level, GPO
0 0 1 1
4
Unidirectional path
output with DAC-
controlled level, GPO
0 1 0 0 INV ASSOCIATED PORT*
5Analog output for DAC 0 1 0 1 RANGE
6Analog output for DAC
with ADC monitoring 0 1 1 0 AV R RANGE
7Positive analog input to
single-ended ADC 0 1 1 1 AV R RANGE # OF SAMPLES
8Positive analog input to
differential ADC 1 0 0 0 AV R RANGE # OF SAMPLES ASSOCIATED PORT*
9
Negative analog input
to differential ADC 1 0 0 1 AV R RANGE
10
Analog output for DAC
and negative analog
input to differential ADC
(pseudo-differential
mode)
1 0 1 0 AV R RANGE
11
Terminal to GPI-
controlled analog
switch
1 0 1 1 INV ASSOCIATED PORT*
12
Terminal to register-
controlled analog
switch
1 1 0 0
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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ADC Data Registers (Read)
DAC Data Registers
BIT FIELD NAME DESCRIPTION
11:0 ADCDAT_0[11:0]
ADCDAT_1[11:0]
ADCDAT_2[11:0]
ADCDAT_3[11:0]
ADCDAT_4[11:0]
ADCDAT_5[11:0]
ADCDAT_6[11:0]
ADCDAT_7[11:0]
ADCDAT_8[11:0]
ADCDAT_9[11:0]
ADCDAT_10[11:0]
ADCDAT_11[11:0]
ADCDAT_12[11:0]
ADCDAT_13[11:0]
ADCDAT_14[11:0]
ADCDAT_15[11:0]
ADCDAT_16[11:0]
ADCDAT_17[11:0]
ADCDAT_18[11:0]
ADCDAT_19[11:0]
ADC data for port i (0≤i≤19)
• 12-bit data produced by the ADC when converting the analog input signal on port i.
• The conversion result is represented in straight binary for ports congured in single-
ended mode (modes 6, 7), and in two’s complement for ports congured as an ADC
positive input (mode 8) in differential or pseudo-differential mode (mode 9). The ADC
data register of the port congured as an ADC negative input in differential (mode 9) or
pseudo-differential mode (mode 10) contains 0x0000.
BIT FIELD NAME DESCRIPTION
11:0 DACDAT_0[11:0]
DACDAT_1[11:0]
DACDAT_2[11:0]
DACDAT_3[11:0]
DACDAT_4[11:0]
DACDAT_5[11:0]
DACDAT_6[11:0]
DACDAT_7[11:0]
DACDAT_8[11:0]
DACDAT_9[11:0]
DACDAT_10[11:0]
DACDAT_11[11:0]
DACDAT_12[11:0]
DACDAT_13[11:0]
DACDAT_14[11:0]
DACDAT_15[11:0]
DACDAT_16[11:0]
DACDAT_17[11:0]
DACDAT_18[11:0]
DACDAT_19[11:0]
DAC data for port i (0≤i≤19)
• 12-bit DAC data for port i.
• The data is represented in straight binary.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Is mode 1,3,4,5,6,or 10 used?
Configure DACREF,
DACCTL
Wait 200μs
Enter DACDAT[i] for
ports in mode
1,3,4,5,6, or 10*
Are all ports in
mode 3,4,5,6, or 10
configured?
Configure FUNCID[i],
FUNCPRM[i] for ports
in mode 1
Wait 200μs times the
number of ports in
mode 1
Configure FUNCID[i],
FUNCPRM[i] for
selected port
Wait 1ms
Select first port in
mode 3,4,5,6, or 10
Select next port in
mode 3,4,5,6, or 10
Is mode 7,8, or 9 used?
Select first port in
mode 9
Configure FUNCID[i],
FUNCPRM[i] for
selected port
Wait 100μs
Select first port in
mode 7 or 8
Configure FUNCID[i],
FUNCPRM[i] for
selected port
Wait 100μs
Are all ports in mode
9 configured?
Select next port in
mode 9
Are all ports in mode
7 or 8 configured?
Select next port in
mode 7 or 8
Is mode 2,11, or 12 used?
Configure FUNCID[i],
FUNCPRM[i] for ports
in mode 2,11, or 12
Configure Interrupt
Masks (...MSK)
Are Temperature sensors used?
Configure TMPPER,
RSCANCEL,
TMP...MONCFG
Configure ADCCTL
Configure TMPCTL
Configure BRST,
THSHDN,ADCCONV
Y Y
Y
Y
Y
Y
Y
NN
N
N
N
N
N
Start of configuration
Configure GPODAT[i]
for ports in mode 3
End of
configuration
Configure GPIMD[i] for
ports in mode 1
Is DACCTL = 2 or 3?
YN
Enter DACPRSTDAT1
or DACPRSTDAT2
Configure TMP...HI
and TMP...LO
Figure 12. Flow Chart for Initial Configuration of PIXI Ports
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Conguration Software (GUI)
To simplify use of the MAX11301, Maxim has created a GUI for customers to easily configure the device for unique
application needs with a simple drag and drop. The software generates register addresses and corresponding register
values. Figure 13 shows an example of this software with a few function connections.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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Figure 13. Example of GUI to Develop Configuration File
The following table shows the output file of the GUI software.
Generated ondd/mm/yyyy
hr:min
SUPPLY VOLTAGE
VDDIO 12.5
VSSIO -2.5
AVDD 5
DVDD 3.3
ADC_EXT_REF 2.5
DAC_REF 2.5
NAME ADDRESS VALUE DESCRIPTION
gpo_data_15_to_0 0x0D 0x0000 GPO data for PIXI ports 15 to 0
gpo_data_19_to_16 0x0E 0x0000 GPO data for PIXI ports 19 to 16
device_control 0x10 0x00c0 Device main control register
interrupt_mask 0x11 0xffff Interrupt mask register
gpi_irqmode_7_to_0 0x12 0x0000 GPI port 0 to 7 mode register
gpi_irqmode_15_to_8 0x13 0x0000 GPI port 8 to 15 mode register
gpi_irqmode_19_to_16 0x14 0x0000 GPI port 16 to 19 mode register
dac_preset_data_1 0x16 0x0000 DAC preset data #1
dac_preset_data_2 0x17 0x0000 DAC preset data #2
tmp_mon_cfg 0x18 0x0000 Temperature monitor conguration
tmp_mon_int_hi_thresh 0x19 0x07ff Internal temperature monitor high threshold
tmp_mon_int_lo_thresh 0x1A 0x0800 Internal temperature monitor low threshold
tmp_mon_ext1_hi_thresh 0x1B 0x07ff 1st external temperature monitor high threshold
tmp_mon_ext1_lo_thresh 0x1C 0x0800 1st external temperature monitor low threshold
tmp_mon_ext2_hi_thresh 0x1D 0x07ff 2nd external temperature monitor high threshold
tmp_mon_ext2_lo_thresh 0x1E 0x0800 2nd external temperature monitor low threshold
port_cfg_00 0x20 0x7100 Conguration register for PIXI port 0
port_cfg_01 0x21 0x5100 Conguration register for PIXI port 1
port_cfg_02 0x22 0x8103 Conguration register for PIXI port 2
port_cfg_03 0x23 0x9100 Conguration register for PIXI port 3
port_cfg_04 0x24 0x5100 Conguration register for PIXI port 4
port_cfg_05 0x25 0x0000 Conguration register for PIXI port 5
port_cfg_06 0x26 0x6100 Conguration register for PIXI port 6
port_cfg_07 0x27 0x0000 Conguration register for PIXI port 7
port_cfg_08 0x28 0x1000 Conguration register for PIXI port 8
port_cfg_09 0x29 0x3000 Conguration register for PIXI port 9
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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The following table shows the output file of the GUI software.
port_cfg_10 0x2A 0x0000 Conguration register for PIXI port 10
port_cfg_11 0x2B 0xc000 Conguration register for PIXI port 11
port_cfg_12 0x2C 0x0000 Conguration register for PIXI port 12
port_cfg_13 0x2D 0x1000 Conguration register for PIXI port 13
port_cfg_14 0x2E 0x400d Conguration register for PIXI port 14
port_cfg_15 0x2F 0x2000 Conguration register for PIXI port 15
port_cfg_16 0x30 0x0000 Conguration register for PIXI port 16
port_cfg_17 0x31 0x1000 Conguration register for PIXI port 17
port_cfg_18 0x32 0xb011 Conguration register for PIXI port 18
port_cfg_19 0x33 0x0000 Conguration register for PIXI port 19
dac_data_port_00 0x60 0x0000 DAC data register for PIXI port 0
dac_data_port_01 0x61 0x0000 DAC data register for PIXI port 1
dac_data_port_02 0x62 0x0000 DAC data register for PIXI port 2
dac_data_port_03 0x63 0x0000 DAC data register for PIXI port 3
dac_data_port_04 0x64 0x0000 DAC data register for PIXI port 4
dac_data_port_05 0x65 0x0000 DAC data register for PIXI port 5
dac_data_port_06 0x66 0x0000 DAC data register for PIXI port 6
dac_data_port_07 0x67 0x0000 DAC data register for PIXI port 7
dac_data_port_08 0x68 0x0666 DAC data register for PIXI port 8
dac_data_port_09 0x69 0x0666 DAC data register for PIXI port 9
dac_data_port_10 0x6A 0x0000 DAC data register for PIXI port 10
dac_data_port_11 0x6B 0x0000 DAC data register for PIXI port 11
dac_data_port_12 0x6C 0x0000 DAC data register for PIXI port 12
dac_data_port_13 0x6D 0x0666 DAC data register for PIXI port 13
dac_data_port_14 0x6E 0x0666 DAC data register for PIXI port 14
dac_data_port_15 0x6F 0x0000 DAC data register for PIXI port 15
dac_data_port_16 0x70 0x0000 DAC data register for PIXI port 16
dac_data_port_17 0x71 0x0666 DAC data register for PIXI port 17
dac_data_port_18 0x72 0x0000 DAC data register for PIXI port 18
dac_data_port_19 0x73 0x0000 DAC data register for PIXI port 19
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
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+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
PART TEMP RANGE PIN-PACKAGE
MAX11301GCM+ -40°C to +105°C 48 TQFP-EP*
MAX11301GCM+T -40°C to +105°C 48 TQFP-EP*
MAX11301GTL+ -40°C to +105°C 40 TQFN-EP*
MAX11301GTL+T -40°C to +105°C 40 TQFN-EP* PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
48 TQFP-EP C48E+8 21-0065 90-0138
40 TQFN-EP T4066+3 21-0141 90-0054
Layout, Grounding, Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the MAX11301 package. Noise in AVDD,
AGND, AVDDIO, AVSSIO, ADC_REF_INT, ADC_EXT_
INT, and DAC_REF affects the device performance.
Bypass AVDD, DVDD, AVDDIO, and AVSSIO to ground
with 0.1µF and 10µF bypass capacitors. Bypass ADC_
INT_REF and DAC_REF to ground with capacitors whose
values are shown in the REF Electrical Specifications
table. Bypass ADC_EXT_REF to ground with a 4.7µF
capacitor. Place the bypass capacitors as close as pos-
sible to the respective pins and minimize capacitor lead
and trace lengths for best supply-noise rejection. For
optimum heat dissipation, connect the exposed pad (EP)
to a large copper area, such as a ground plane.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
www.maximintegrated.com Maxim Integrated
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54
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Chip Information
PROCESS: BiCMOS
Ordering Information
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 3/15 Initial release —
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX11301
PIXI, 20-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
© 2015 Maxim Integrated Products, Inc.
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55
Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.