LT8640S-2/LT8643S-2
1
Rev 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
42V, 6A Synchronous
Step-Down Silent Switcher with
2.5µA Quiescent Current
The LT
®
8640S-2/LT8643S-2 synchronous step-down
regulator features Silent Switcher architecture designed
to minimize EMI emissions while delivering high efficiency
at high switching frequencies. Peak current mode control
with a 30ns minimum on-time allows high step-down
ratios even at high switching frequencies.The LT8643S-2
has external compensation to enable current sharing and
fast transient response at high switching frequencies.
Burst Mode operation enables ultralow standby current
consumption, forced continuous mode can control
frequency harmonics across the entire output load range,
or spread spectrum operation can further reduce EMI
emissions.
PACKAGE
SYNC/
MODE ≠ 0 VC COMP H-GRADE CLKOUT
INTERNAL
CAPS
LT8640 QFN Pulse-
Skipping Internal Yes No No
LT8640-1 QFN FCM Internal Yes No No
LT8640S LQFN FCM Internal No Yes Yes
LT8643S LQFN FCM External No Yes Yes
LT8640S-2 LQFN FCM Internal Yes Yes No
LT8643S-2 LQFN FCM External Yes Yes No
5V, 6A Step-Down Converter
APPLICATIONS
n Silent Switcher
®
Architecture
n Ultralow EMI Emissions
n Optional Spread Spectrum Modulation
n High Efficiency at High Frequency
n Up to 96% Efficiency at 1MHz, 12VIN to 5VOUT
n Up to 95% Efficiency at 2MHz, 12VIN to 5VOUT
n Wide Input Voltage Range: 3.4V to 42V
n 6A Maximum Continuous, 7A Peak Output
n Ultralow Quiescent Current Burst Mode
®
Operation
n 2.5µA IQ Regulating 12VIN to 3.3VOUT (LT8640S-2)
n Output Ripple < 10mVP-P
n External Compensation: Fast Transient Response
and Current Sharing (LT8643S-2)
n Fast Minimum Switch On-Time: 30ns
n Low Dropout Under All Conditions: 100mV at 1A
n Forced Continuous Mode
n Adjustable and Synchronizable: 200kHz to 3MHz
n Output Soft-Start and Tracking
n Small 24-Lead 4mm × 4mm LQFN Package
n Automotive and Industrial Supplies
n General Purpose Step-Down All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 8823345.
12VIN to 5VOUT Efficiency
EFFICIENCY
POWER LOSS
1MHz, L = 3.3µH
2MHz, L = 2.2µH
3MHz, L = 1µH
LOAD CURRENT (A)
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
60
65
70
75
80
85
90
95
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
EFFICIENCY (%)
POWER LOSS (W)
8640s2 TA01b
LT8640S-2
8640s2 TA01a
SW
BST
VIN
GND
VIN
GND
EN/UV
BIAS
RT
INTVCC
FB
GND
100µF
1µF 1M
VOUT
5V
6A
4.7µF
1µF 1µF
0.1µF
10pF
3.3µH
VIN
5.7V TO 42V
41.2k 243k
fSW = 1MHz
LT8640S-2/LT8643S-2
2
Rev 0
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN, EN/UV, PG ..........................................................42V
BIAS .......................................................................... 25V
FB, TR/SS . .................................................................4V
SYNC/MODE Voltage . ................................................6V
(Note 1)
ORDER INFORMATION
PART NUMBER PART MARKING* FINISH CODE PAD FINISH
PACKAGE
TYPE**
MSL
RATING TEMPERATURE RANGE
LT8640SEV-2#PBF
86402
e4 Au (RoHS) LQFN (Laminate Package
with QFN Footprint) 3
–40°C to 125°C
LT8640SIV-2#PBF –40°C to 125°C
LT8640SHV-2#PBF –40°C to 150°C
LT8643SEV-2#PBF
86432
–40°C to 125°C
LT8643SIV-2#PBF –40°C to 125°C
LT8643SHV-2#PBF –40°C to 150°C
• Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is identified by a label on the shipping
container.
• Pad finish code is per IPC/JEDEC J-STD-609.
• Recommended PCB Assembly and Manufacturing Procedures:
www.analog.com/umodule/pcbassembly
• Package and Tray Drawings: www.analog.com/packaging
Parts ending with PBF are RoHS and WEEE compliant. **The LT8640S-2/LT8643S-2 package has the same dimensions as a standard 4mm × 4mm QFN package.
LT8640S-2 LT8643S-2
2021222324 19
7 8 9 10 11 12
TOP VIEW
LQFN PACKAGE
24-LEAD (4mm × 4mm × 0.94mm)
JEDEC BOARD: θJA = 38°C/W, θJC(PAD) = 7°C/W (NOTE 3)
EXPOSED PAD (PINS 25 TO 28) ARE GND, SHOULD BE SOLDERED TO PCB
BIAS
INTVCC
GND
NC
VIN
VIN
RT
EN
GND
NC
VIN
VIN
18
17
16
15
14
13
1
2
3
4
5
6
BST
SW
SW
SW
SW
SW
FB
PG
GND
TR/SS
SYNC/MODE
CLKOUT
27
GND
25
GND
28
GND
26
GND
2021222324 19
7 8 9 10 11 12
TOP VIEW
LQFN PACKAGE
24-LEAD (4mm × 4mm × 0.94mm)
JEDEC BOARD: θJA = 38°C/W, θJC(PAD) = 7°C/W (NOTE 3)
EXPOSED PAD (PINS 25 TO 28) ARE GND, SHOULD BE SOLDERED TO PCB
BIAS
INTVCC
GND
NC
VIN
VIN
RT
EN
GND
NC
VIN
VIN
18
17
16
15
14
13
1
2
3
4
5
6
BST
SW
SW
SW
SW
SW
FB
PG
VC
TR/SS
SYNC/MODE
CLKOUT
27
GND
25
GND
28
GND
26
GND
Operating Junction Temperature Range (Note 2)
LT8640S-2E/LT8643S-2E .................. –40°C to 125°C
LT8640S-2I/LT8643S-2I .................... –40°C to 125°C
LT8640S-2H/LT8643S-2H ................. –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Maximum Reflow (Package Body) Temperature ..... 260°C
LT8640S-2/LT8643S-2
3
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage l3.0 3.4 V
VIN Quiescent Current in Shutdown VEN/UV = 0V
l
0.75
0.75
3
10
µA
µA
LT8640S-2 VIN Quiescent Current in Sleep
(Internal Compensation)
VEN/UV = 2V, VFB > 0.97V, VSYNC = 0V
l
1.7
1.7
4
10
µA
µA
LT8643S-2 VIN Quiescent Current in Sleep
(External Compensation)
VEN/UV = 2V, VFB > 0.97V, VSYNC = 0V, VBIAS = 0V
l
230
230
290
340
µA
µA
VEN/UV = 2V, VFB > 0.97V, VSYNC = 0V, VBIAS = 5V 19 25 µA
LT8643S-2 BIAS Quiescent Current in Sleep VEN/UV = 2V, VFB > 0.97V, VSYNC = 0V, VBIAS = 5V 200 260 µA
LT8640S-2 VIN Current in Regulation VOUT = 0.97V, VIN = 6V, ILOAD = 100µA, VSYNC = 0
VOUT = 0.97V, VIN = 6V, ILOAD = 1mA, VSYNC = 0
l
l
21
220
60
390
µA
µA
Feedback Reference Voltage VIN = 6V
VIN = 6V
l
0.964
0.958
0.970
0.970
0.976
0.982
V
V
Feedback Voltage Line Regulation VIN = 4.0V to 36V l0.004 0.02 %/V
Feedback Pin Input Current VFB = 1V –20 20 nA
LT8643S-2 Error Amp Transconductance VC = 1.25V 1.7 mS
LT8643S-2 Error Amp Gain 260
LT8643S-2 VC Source Current VFB = 0.77V, VC = 1.25V 350 µA
LT8643S-2 VC Sink Current VFB = 1.17V, VC = 1.25V 350 µA
LT8643S-2 VC Pin to Switch Current Gain 5 A/V
LT8643S-2 VC Clamp Voltage 2.6 V
BIAS Pin Current Consumption VBIAS = 3.3V, fSW = 2MHz 14 mA
Minimum On-Time ILOAD = 1.5A, SYNC = 0V
ILOAD = 1.5A, SYNC = 2V
l
l
30
30
50
45
ns
ns
Minimum Off-Time 80 110 ns
Oscillator Frequency RT = 221k
RT = 60.4k
RT = 18.2k
l
l
l
180
665
1.8
210
700
1.95
240
735
2.1
kHz
kHz
MHz
Top Power NMOS On-Resistance ISW = 1A 66 mΩ
Top Power NMOS Current Limit l7.5 10 12.5 A
Bottom Power NMOS On-Resistance VINTVCC = 3.4V, ISW = 1A 27 mΩ
SW Leakage Current VIN = 42V, VSW = 0V, 42V –1.5 1.5 µA
EN/UV Pin Threshold EN/UV Rising l0.94 1.0 1.06 V
EN/UV Pin Hysteresis 40 mV
EN/UV Pin Current VEN/UV = 2V –20 20 nA
PG Upper Threshold Offset from VFB VFB Falling l5 7.5 10.25 %
PG Lower Threshold Offset from VFB VFB Rising l–5.25 –8 –10.75 %
PG Hysteresis 0.2 %
PG Leakage VPG = 3.3V –40 40 nA
PG Pull-Down Resistance VPG = 0.1V l700 2000 Ω
SYNC/MODE Threshold SYNC/MODE DC and Clock Low Level Voltage
SYNC/MODE Clock High Level Voltage
SYNC/MODE DC High Level Voltage
l
l
l
0.7
2.2
0.9
1.2
2.55
1.4
2.9
V
V
V
LT8640S-2/LT8643S-2
4
Rev 0
For more information www.analog.com
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8640-2E/LT8643E is guaranteed to meet performance
specifications from 0°C to 125°C junction temperature. Specifications
over the –40°C to 125°C operating junction temperature range are assured
by design, characterization, and correlation with statistical process
controls. The LT8640-2I/LT8643I is guaranteed over the full –40°C to
125°C operating junction temperature range. The LT8640-2H/LT8643H is
guaranteed over the full –40°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes. Operating
lifetime is derated at junction temperatures greater than 125°C. The junction
temperature (TJ, in °C) is calculated from the ambient temperature (TA in
°C) and power dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 3: θ values determined per JEDEC 51-7, 51-12. See the Applications
Information section for information on improving the thermal resistance
and for actual temperature measurements of a demo board in typical
operating conditions.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Spread Spectrum Modulation
FrequencyRange
RT = 60.4k, VSYNC = 3.3V 22 %
Spread Spectrum Modulation Frequency VSYNC = 3.3V 3 kHz
TR/SS Source Current l1.2 1.9 2.6 µA
TR/SS Pull-Down Resistance Fault Condition, TR/SS = 0.1V 200 Ω
Output Sink Current in Forced Continuous
Mode
VFB = 1.01V, L = 6.8µH, RT = 60.4k 0.25 0.6 1.1 A
VIN to Disable Forced Continuous Mode VIN Rising 35 37 39 V
LT8640S-2/LT8643S-2
5
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
LT8640S-2 Low Load Efficiency at
3.3VOUT Efficiency vs Frequency
12VIN to 3.3VOUT Efficiency
vs Frequency
12VIN to 5VOUT Efficiency
vs Frequency Efficiency at 5VOUT
LT8640S-2 Low Load Efficiency
at 5VOUT
Efficiency at 3.3VOUT
LT8643S-2 Low Load Efficiency
at 5VOUT
LT8643S-2 Low Load Efficiency at
3.3VOUT
f
SW
= 1MHz
L = IHLP3232DZ–01, 4.7µH
V
IN
= 12V
V
IN
= 24V
V
IN
= 36V
LOAD CURRENT (mA)
0.1
1
10
100
1000
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
8640s2 G06
f
SW
= 1MHz
L = IHLP3232DZ–01, 4.7µH
V
IN
= 12V
V
IN
= 24V
V
IN
= 36V
LOAD CURRENT (mA)
0.1
1
10
100
1000
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
8640s2 G08
VIN = 12V
V
OUT
= 3.3V
I
LOAD
= 2A
L = IHLP3232DZ-01, 4.7µH
SWITCHING FREQUENCY (MHz)
0
0.5
1
1.5
2
2.5
3
80
82
84
86
88
90
92
94
96
EFFICIENCY (%)
Efficiency vs Frequency
8640s2 G09
EFFICIENCY
POWER LOSS
L = WE-LHMI1040
1MHz, L = 3.3µH
2MHz, L = 2.2µH
3MHz, L = 1µH
LOAD CURRENT (A)
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
60
65
70
75
80
85
90
95
100
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
EFFICIENCY (%)
POWER LOSS (W)
vs Frequency
8640s2 G01
EFFICIENCY
POWER LOSS
1MHz, L = 2.2µH
2MHz, L = 1µH
3MHz, L = 1µH
L = WE-LHMI1040
LOAD CURRENT (A)
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
60
65
70
75
80
85
90
95
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
EFFICIENCY (%)
POWER LOSS (W)
vs Frequency
8640s2 G02
f
SW
= 1MHz
L = IHLP3232DZ-01, 3.3µH
EFFICIENCY
POWER LOSS
V
IN
= 12V
V
IN
= 24V
V
IN
= 36V
LOAD CURRENT (A)
0
1
2
3
4
5
6
50
55
60
65
70
75
80
85
90
95
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
EFFICIENCY (%)
POWER LOSS (W)
8640s2 G03
f
SW
= 1MHz
L = IHLP3232DZ-01, 2.2µH
EFFICIENCY
POWER LOSS
V
IN
= 12V
V
IN
= 24V
V
IN
= 36V
LOAD CURRENT (A)
0
1
2
3
4
5
6
50
55
60
65
70
75
80
85
90
95
100
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
EFFICIENCY (%)
POWER LOSS (W)
Efficiency at 3.3V
OUT
8640s2 G04
f
SW
= 1MHz
L = IHLP3232DZ-01, 4.7µH
LOAD CURRENT (mA)
0.01
1
10
100
1000
20
30
40
50
60
70
80
90
EFFICIENCY (%)
OUT
8640s2 G05
V
IN
= 12V
V
IN
= 24V
V
IN
= 36V
f
SW
= 1MHz
L = IHLP3232DZ-01, 4.7µH
V
IN
= 12V
V
IN
= 24V
V
IN
= 36V
LOAD CURRENT (mA)
0.01
0.1
1
10
100
1000
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
Efficiency at 3.3V
OUT
8640s2 G07
LT8640S-2/LT8643S-2
6
Rev 0
For more information www.analog.com
Burst Mode Operation Efficiency
vs Inductor Value (LT8640S-2) Reference Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
EN Pin Thresholds
LT8640S-2 Load Regulation LT8640S-2 Line Regulation
LT8640S-2 No-Load Supply
Current
LT8643S-2 Load Regulation
LT8643S-2 Line Regulation
LT8643S-2 No-Load Supply
Current
V
OUT
= 5V
I
LOAD
= 10mA
L = IHLP3232DZ-01
V
IN
= 12V
V
IN
= 24V
INDUCTOR VALUE (µH)
1
2
3
4
5
6
7
8
65
70
75
80
85
90
95
100
EFFICIENCY (%)
vs Inductor Value
8640s2 G10
TEMPERATURE (°C)
0
25
50
75
REFERENCE VOLTAGE (mV)
8640s2 G11
EN RISING
EN FALLING
TEMPERATURE (°C)
0
25
50
75
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
EN THRESHOLD (V)
EN Pin Thresholds
8640s2 G12
V
OUT
= 5V
V
SYNC
= 0V
V
IN
= 12V
LOAD CURRENT (A)
0
1
2
3
4
5
6
–0.15
–0.10
0.05
0
0.05
0.10
0.15
CHANGE IN V
OUT
(%)
8640s2 G13
V
OUT
= 5V
I
LOAD
= 1A
INPUT VOLTAGE (V)
5
10
15
20
25
30
35
40
45
–0.08
–0.06
–0.04
–0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
CHANGE IN V
OUT
(%)
8640s2 G15
V
OUT
= 5V
I
LOAD
= 1A
INPUT VOLTAGE (V)
5
10
15
20
25
30
35
40
45
–0.15
–0.12
–0.09
–0.06
–0.03
0
0.03
0.06
0.09
0.12
0.15
CHANGE IN V
OUT
(%)
8640s2 G16
V
OUT
= 3.3V
L = 4.7µH
IN REGULATION
INPUT VOLTAGE (V)
0
5
10
15
20
25
30
35
40
45
1.0
1.5
2.0
2.5
3.0
3.5
4.0
INPUT CURRENT (µA)
8640s2 G17
V
OUT
= 5V
L = 4.7µH
IN REGULATION
INPUT VOLTAGE (V)
5
10
15
20
25
30
35
40
45
25
50
75
INPUT CURRENT (µA)
8640s2 G18
LOAD CURRENT (A)
0
1
2
3
4
5
6
–0.40
–0.30
–0.20
–0.10
0.00
0.10
0.20
0.30
0.40
CHANGE IN V
OUT
(%)
8640s2 G14
V
OUT
= 5V
V
SYNC
= 0V
V
IN
= 12V
LT8640S-2/LT8643S-2
7
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Dropout Voltage
Switching Frequency Burst Frequency LT8640S-2 Soft-Start Tracking
Minimum On-TimeSwitch Drop vs Switch Current
Top FET Current Limit vs Duty Cycle
Top FET Current Limit Switch Drop vs Temperature
DUTY CYCLE
0.1
0.3
0.5
0.7
0.9
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
CURRENT LIMIT (A)
8640s2 G19
5% DC
TEMPERATURE (°C)
0
25
50
75
8
9
10
11
12
CURRENT LIMIT (A)
8640s2 G20
TOP SWITCH
BOTTOM SWITCH
SWITCH CURRENT = 1A
TEMPERATURE (°C)
0
25
50
75
0
25
50
75
SWITCH DROP (mV)
8640s2 G21
TOP SWITCH
BOTTOM SWITCH
SWITCH CURRENT (A)
0
1
2
3
4
5
0
50
100
150
200
250
300
350
400
450
500
SWITCH DROP (mV)
8640s2 G22
V
IN
= 5V
V
OUT
SET TO REGULATE AT 5V
L = IHLP3232DZ-01, 1µH
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
DROPOUT VOLTAGE (mV)
8640s2 G23
I
LOAD
= 2A
V
fSW = 3MHz
OUT
= 0.97V
Burst Mode OPERATION
FORCED CONTINUOUS MODE
TEMPERATURE (°C)
0
25
50
75
20
24
28
32
36
40
44
MINIMUM ON–TIME (ns)
8640s2 G24
R
T
= 60.4k
TEMPERATURE (°C)
–50
–25
0
25
50
75
125
660
670
680
690
700
710
720
730
740
SWITCHING FREQUENCY (kHz)
Switching Frequency
8640s2 G25
FRONT PAGE APPLICATION
V
IN
= 12V
V
OUT
= 5V
LOAD CURRENT (mA)
0
0
1000
1200
SWITCHING FREQUENCY (kHz)
8640s2 G26
TR/SS VOLTAGE (V)
0
FB VOLTAGE (V)
0.8
1.0
1.2
0.6 1.0
8640s2 G27
0.6
0.4
0.2 0.4 0.8 1.2 1.4
0.2
0
LT8640S-2/LT8643S-2
8
Rev 0
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Soft-Start Current
PG High Thresholds PG Low Thresholds
TYPICAL PERFORMANCE CHARACTERISTICS
RT Programmed Switching
Frequency
Minimum Input Voltage Bias Pin Current Bias Pin Current
LT8643S-2 Error Amp Output
CurrentLT8643S-2 Soft-Start Tracking
TR/SS VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
FB VOLTAGE (V)
8640s2 G28
V
SS
= 0.5V
TEMPERATURE (°C)
0
25
50
75
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
TR/SS PIN CURRENT (µA)
Soft-Start Current
8640s2 G29
V
C
= 1.25V
FB PIN ERROR VOLTAGE (mV)
–200
–100
0
–500
–375
–250
–125
0
V
C
PIN CURRENT (µA)
8640s2 G30
FB RISING
FB FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
PG THRESHOLD OFFSET FROM V
REF
(%)
PG High Thresholds
8640s2 G31
FB RISING
FB FALLING
TEMPERATURE (°C)
0
25
50
75
–10.0
–9.5
–9.0
–8.5
–8.0
–7.5
–7.0
–6.5
–6.0
PG THRESHOLD OFFSET FROM V
REF
(%)
8640s2 G32
SWITCHING FREQUENCY (MHz)
0.2
RT PIN RESISTOR (kΩ)
150
200
250
1.8
8640s2 G33
100
50
125
175
225
75
25
00.6 11.4 2.2 2.6 3
TEMPERATURE (°C)
–50
–25
0
25
50
75
2.4
2.6
2.8
3.0
3.2
3.4
3.6
INPUT VOLTAGE (V)
Minimum Input Voltage
8640s2 G34
V
BIAS
= 5V
V
OUT
= 5V
I
LOAD
= 1A
f
SW
= 1MHz
INPUT VOLTAGE (V)
5
10
15
20
25
30
35
40
45
5.5
6.0
6.5
7.0
7.5
8.0
8.5
BIAS PIN CURRENT (mA)
8640s2 G35
V
BIAS
= 5V
V
OUT
= 5V
V
IN
= 12V
I
LOAD
= 1A
SWITCHING FREQUENCY (MHz)
0.2
0.6
1
1.4
1.8
2.2
2.6
3.0
0
5
10
15
20
25
BIAS PIN CURRENT (mA)
Bias Pin Current
8640s2 G36
LT8640S-2/LT8643S-2
9
Rev 0
For more information www.analog.com
Case Temperature Rise
TYPICAL PERFORMANCE CHARACTERISTICS
LT8640S-2 Transient Response;
Internal Compensation
Switching Waveforms
Switching Waveforms, Full
Frequency Continuous Operation
Switching Waveforms, Burst
Mode Operation
Switching Rising Edge
Case Temperature Rise vs 7A
Pulsed Load
LT8643S-2 Transient Response;
External Compensation
DC2530A DEMO BOARD
V
IN
= 12V, f
SW
= 1MHz
V
IN
= 24V, f
SW
= 1MHz
V
IN
= 12V, f
SW
= 2MHz
V
IN
= 24V, f
SW
= 2MHz
LOAD CURRENT (A)
0
1
2
3
4
5
6
0
10
20
30
40
50
60
70
80
CASE TEMPERATURE RISE (°C)
8640s2 G37
DC2530A DEMO BOARD
V
IN
= 12V
V
OUT
= 5V
f
SW
= 2MHz
STANDBY LOAD = 0.25A
1kHz PULSED LOAD = 7A
DUTY CYCLE OF 7A LOAD
0
0.2
0.4
0.6
0.8
1
0
10
20
30
40
50
60
70
80
90
CASE TEMPERATURE RISE (°C)
Pulsed Load
8640s2 G38
V
IN
= 12V
I
LOAD
= 2A
2ns/DIV
V
SW
2V/DIV
8640s2 G39
FRONT PAGE APPLICATION
12V
IN
TO 5V
OUT
AT 1A
500ns/DIV
I
L
1A/DIV
V
SW
5V/DIV
8640s2 G40
FRONT PAGE APPLICATION
12V
IN
TO 5V
OUT
AT 10mA
V
SYNC
= 0V
5µs/DIV
V
SW
5V/DIV
I
L
500mA/DIV
8640s2 G41
FRONT PAGE APPLICATION
36V
IN
TO 5V
OUT
AT 1A
500ns/DIV
V
SW
10V/DIV
I
L
1A/DIV
8640s2 G42
2A TO 4A TRANSIENT
12V
IN
, 5V
OUT
FRONT PAGE APPLICATION
f
SW
= 2MHz
C
OUT
= 100µF, C
LEAD
= 10pF
20µs/DIV
V
OUT
100mV/DIV
I
LOAD
2A/DIV
8640s2 G43
2A TO 4A TRANSIENT
12V
IN
, 5V
OUT
f
SW
= 2MHz
C
C
= 330pF, R
C
= 8.45k
C
OUT
= 100µF, C
LEAD
= 4.7pF
20µs/DIV
V
OUT
100mV/DIV
I
LOAD
2A/DIV
8640s2 G44
FRONT PAGE APPLICATION
LT8640S-2/LT8643S-2
10
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up Dropout Performance Start-Up Dropout Performance
LT8640S-2 Transient Response;
100mA to 1.1A Transient
LT8643S-2 Transient Response;
100mA to 1.1A Transient
FRONT PAGE APPLICATION
100mA TO 1.1A TRANSIENT
C
OUT
= 100µF
Burst Mode OPERATION
FCM
50µs/DIV
I
LOAD
1A/DIV
V
OUT
100mV/DIV
8640s2 G45
12V
IN
, 5V
OUT
, f
SW
= 1MHz
FRONT PAGE APPLICATION
C
C
= 330pF, R
C
= 6.49k, C
LEAD
= 4.7pF
100mA TO 1.1A TRANSIENT
12V
IN
, 5V
OUT
, f
SW
= 1MHz
C
OUT
= 100µF
Burst Mode OPERATION
FCM
50µs/DIV
I
LOAD
1A/DIV
V
OUT
100mV/DIV
8640s2 G46
VIN
2V/DIV
VOUT
2V/DIV
100ms/DIV
2.5Ω LOAD
(2A IN REGULATION)
8640s2 G47
VIN
VOUT
VIN
2V/DIV
VOUT
2V/DIV
100ms/DIV
20Ω LOAD
(250mA IN REGULATION)
8640s2 G48
VIN
VOUT
LT8640S-2/LT8643S-2
11
Rev 0
For more information www.analog.com
Radiated EMI Performance
(CISPR25 Radiated Emission Test with Class 5 Peak Limits)
Conducted EMI Performance
TYPICAL PERFORMANCE CHARACTERISTICS
VERTICAL POLARIZATION
PEAK DETECTOR
CLASS 5 PEAK LIMIT
SPREAD SPECTRUM MODE
FIXED FREQUENCY MODE
FREQUENCY (MHz)
0
200
1000
–5
0
5
10
15
20
25
30
35
40
45
50
AMPLITUDE (dBµV/m)
8640s2 G50a
DC2530A DEMO BOARD USING LT8640S
(WITH EMI FILTER INSTALLED)
14V INPUT TO 5V OUTPUT AT 4A, f
SW
= 2MHz
SPREAD SPECTRUM MODE
FIXED FREQUENCY MODE
FREQUENCY (MHz)
0
3
6
9
12
15
18
21
24
27
30
0
10
20
30
40
50
60
AMPLITUDE (dBµV)
Conducted EMI Performance
8640s2 G49
DC2530A DEMO BOARD USING LT8640S
(WITH EMI FILTER INSTALLED)
14V INPUT TO 5V OUTPUT AT 4A, f
SW
= 2MHz
HORIZONTAL POLARIZATION
PEAK DETECTOR
CLASS 5 PEAK LIMIT
SPREAD SPECTRUM MODE
FIXED FREQUENCY MODE
FREQUENCY (MHz)
0
1000
–5
0
5
10
15
20
25
30
35
40
45
50
AMPLITUDE (dBµV/m)
8640s2 G50b
LT8640S-2/LT8643S-2
12
Rev 0
For more information www.analog.com
PIN FUNCTIONS
BIAS (Pin 1): The internal regulator will draw current from
BIAS instead of VIN when BIAS is tied to a voltage higher
than 3.1V. For output voltages of 3.3V to 25V this pin
should be tied to VOUT. If this pin is tied to a supply other
than VOUT use a 1µF local bypass capacitor on this pin.
If no supply is available, tie to GND. However, especially
for high input or high frequency applications, BIAS should
be tied to output or an external supply of 3.3V or above.
INTVCC (Pin 2): Internal 3.4V Regulator Bypass Pin. The
internal power drivers and control circuits are powered
from this voltage. INTVCC maximum output current is
20mA. Do not load the INTVCC pin with external circuitry.
INTVCC current will be supplied from BIAS if BIAS > 3.1V,
otherwise current will be drawn from VIN. Voltage on
INTVCC will vary between 2.8V and 3.4V when BIAS is
between 3.0V and 3.6V. Place a low ESR ceramic capaci-
tor of at least 1µF from this pin to ground close to the IC.
GND (Pins 3, 16, Exposed Pad Pins 25–28): Ground.
Place the negative terminal of the input capacitor as close
to the GND pins as possible. The exposed pads should
be soldered to the PCB for good thermal performance. If
necessary due to manufacturing limitations Pins 25 to 28
may be left disconnected, however thermal performance
will be degraded.
NC (Pins 4, 15): No Connect. This pin is not connected
to internal circuitry and can be tied anywhere on the PCB,
typically ground.
VIN (Pins 5, 6, 13, 14): The VIN pins supply current to
the LT8640S-2/LT8643S-2 internal circuitry and to the
internal topside power switch. The LT8640S-2/LT8643S-2
requires the use of multiple VIN bypass capacitors. Two
small 1µF capacitors should be placed as close as pos-
sible to the LT8640S-2/LT8643S-2, one capacitor on each
side of the device (C
IN1
, C
IN2
). A third capacitor with a
larger value, 2.2µF or higher, should be placed near CIN1
or CIN2. See Applications Information section for sample
layout.
BST (Pin 7): This pin is used to provide a drive voltage,
higher than the input voltage, to the topside power switch.
Place a 0.1µF boost capacitor as close as possible to
the IC.
SW (Pins 8–12): The SW pins are the outputs of the inter-
nal power switches. Tie these pins together and connect
them to the inductor. This node should be kept small on
the PCB for good performance and low EMI.
EN/UV (Pin 17): The LT8640S-2/LT8643S-2 is shut down
when this pin is low and active when this pin is high. The
hysteretic threshold voltage is 1.00V going up and 0.96V
going down. Tie to VIN if the shutdown feature is not
used. An external resistor divider from VIN can be used
to program a VIN threshold below which the LT8640S-2/
LT8643S-2 will shut down.
RT (Pin 18): A resistor is tied between RT and ground to
set the switching frequency.
CLKOUT (Pin 19): In forced continuous mode, spread
spectrum, and synchronization modes, the CLKOUT pin
will provide a ~200ns wide pulse at the switch frequency.
The low and high levels of the CLKOUT pin are ground and
INTV
CC
respectively, and the drive strength of the CLKOUT
pin is several hundred ohms. In Burst Mode operation,
the CLKOUT pin will be low. Float this pin if the CLKOUT
function is not used.
SYNC/MODE (Pin 20): For the LT8640S-2/LT8643S-2,
this pin programs four different operating modes: 1)
Burst Mode operation. Tie this pin to ground for Burst
Mode operation at low output loads—this will result in
ultralow quiescent current. 2) Forced Continuous mode
(FCM). This mode offers fast transient response and
full frequency operation over a wide load range. Float
this pin for FCM. When floating, pin leakage currents
should be <1µA. See Block Diagram for internal pull-up
and pull-down resistance. 3) Spread spectrum mode.
Tie this pin high to INTV
CC
(~3.4V) or an external supply
of 3V to 4V for forced continuous mode with spread-
spectrum modulation. 4) Synchronization mode. Drive
this pin with a clock source to synchronize to an external
frequency. During synchronization the part will operate
in forced continuous mode.
LT8640S-2/LT8643S-2
13
Rev 0
For more information www.analog.com
TR/SS (Pin 21): Output Tracking and Soft-Start Pin. This
pin allows user control of output voltage ramp rate during
start-up. For the LT8640S-2, a TR/SS voltage below 0.97V
forces it to regulate the FB pin to equal the TR/SS pin volt-
age. When TR/SS is above 0.97V, the tracking function is
disabled and the internal reference resumes control of the
error amplifier. For the LT8643S-2, a TR/SS voltage below
1.6V forces it to regulate the FB pin to a function of the
TR/SS pin voltage. See plot in the Typical Performance
Characteristics section. When TR/SS is above 1.6V, the
tracking function is disabled and the internal reference
resumes control of the error amplifier. An internal 1.9µA
pull-up current from INTV
CC
on this pin allows a capacitor
to program output voltage slew rate. This pin is pulled to
ground with an internal 200Ω MOSFET during shutdown
and fault conditions; use a series resistor if driving from
a low impedance output. This pin may be left floating if
the tracking function is not needed.
GND (Pin 22, LT8640S-2 Only): Ground. Connect this pin
to system ground and to the ground plane.
VC (Pin 22, LT8643S-2 Only): The VC pin is the output of
the internal error amplifier. The voltage on this pin con-
trols the peak switch current. Tie an RC network from this
pin to ground to compensate the control loop.
PG (Pin 23): The PG pin is the open-drain output of an
internal comparator. PG remains low until the FB pin is
within ±8% of the final regulation voltage, and there are
no fault conditions. PG is also pulled low when EN/UV is
below 1V, INTVCC has fallen too low, VIN is too low, or
thermal shutdown. PG is valid when VIN is above 3.4V.
FB (Pin 24): The LT8640S-2/LT8643S-2 regulates the FB
pin to 0.970V. Connect the feedback resistor divider tap
to this pin. Also, connect a phase lead capacitor between
FB and VOUT. Typically, this capacitor is 4.7pF to 22pF.
Corner Pins: These pins are for mechanical support only
and can be tied anywhere on the PCB, typically ground.
PIN FUNCTIONS
LT8640S-2/LT8643S-2
14
Rev 0
For more information www.analog.com
BLOCK DIAGRAM
8640s2 BD
+
+
–
+
–
SLOPE COMP
INTERNAL 0.97V REF
OSCILLATOR
200kHz TO 3MHz
BURST
DETECT
3.4V
REG
M1
M2
CBST
COUT
VOUT
SW
8–12 L
BST
SWITCH LOGIC
AND
ANTI-SHOOT
THROUGH
ERROR
AMP
SHDN
±8%
VC
SHDN
THERMAL SHDN
INTVCC UVLO
VIN UVLO
SHDN
THERMAL SHDN
VIN UVLO
EN/UV
1V +
–
17
22
7
INTVCC 2
BIAS 1
VIN
13, 14
GND
3, 16, 25–28
GND
CLKOUT
LT8640S-2
ONLY
PG
VC
23
FB
R1C1
R3
OPT
RC
CC
R4
OPT
R2
RT
CSS
OPT
VOUT
24
TR/SS
1.9µA
21
RT
18
SYNC/MODE
20
VIN
5, 6
VIN
CIN1
CF
CIN3
19
CIN2
CVCC
INTVCC
60k
600k
LT8640S-2
ONLY
LT8643S-2 ONLY
22
LT8640S-2/LT8643S-2
15
Rev 0
For more information www.analog.com
OPERATION
The LT8640S-2/LT8643S-2 is a monolithic, constant fre-
quency, current mode step-down DC/DC converter. An
oscillator, with frequency set using a resistor on the RT
pin, turns on the internal top power switch at the begin-
ning of each clock cycle. Current in the inductor then
increases until the top switch current comparator trips
and turns off the top power switch. The peak inductor
current at which the top switch turns off is controlled
by the voltage on the internal VC node. The error ampli-
fier servos the VC node by comparing the voltage on the
VFB pin with an internal 0.97V reference. When the load
current increases it causes a reduction in the feedback
voltage relative to the reference leading the error amplifier
to raise the VC voltage until the average inductor current
matches the new load current. When the top power switch
turns off, the synchronous power switch turns on until the
next clock cycle begins or inductor current falls to zero.
If overload conditions result in more than 10A flowing
through the bottom switch, the next clock cycle will be
delayed until switch current returns to a safe level.
If the EN/UV pin is low, the LT8640S-2/LT8643S-2 is shut
down and draws 1µA from the input. When the EN/UV pin
is above 1V, the switching regulator will become active.
To optimize efficiency at light loads, the LT8640S-2/
LT8643S-2 operates in Burst Mode operation in light
load situations. Between bursts, all circuitry associated
with controlling the output switch is shut down, reducing
the input supply current to 1.7µA (LT8640S-2) or 230µA
(LT8643S-2 with BIAS = 0). In a typical application, 2.5µA
(LT8640S-2) or 120µA (LT8643S-2 with BIAS = 5VOUT)
will be consumed from the input supply when regulat-
ing with no load. The SYNC/MODE pin is tied low to use
Burst Mode operation and can be floated to use forced
continuous mode (FCM). If a clock is applied to the SYNC/
MODE pin, the part will synchronize to an external clock
frequency and operate in FCM.
The LT8640S-2/LT8643S-2 can operate in forced con-
tinuous mode (FCM) for fast transient response and full
frequency operation over a wide load range. When in FCM
the oscillator operates continuously and positive SW tran-
sitions are aligned to the clock. Negative inductor current
is allowed. The LT8640S-2/LT8643S-2 can sink current
from the output and return this charge to the input in this
mode, improving load step transient response.
To improve EMI, the LT8640S-2/LT8643S-2 can operate
in spread spectrum mode. This feature varies the clock
with a triangular frequency modulation of +20%. For
example, if the LT8640S-2/LT8643S-2’s frequency is pro-
grammed to switch at 2MHz, spread spectrum mode will
modulate the oscillator between 2MHz and 2.4MHz. The
SYNC/MODE pin should be tied high to INTV
CC
(~3.4V) or
an external supply of 3V to 4V to enable spread spectrum
modulation with forced continuous mode.
To improve efficiency across all loads, supply current
to internal circuitry can be sourced from the BIAS pin
when biased at 3.3V or above. Else, the internal circuitry
will draw current from VIN. The BIAS pin should be con-
nected to V
OUT
if the LT8640S-2/LT8643S-2 output is
programmed at 3.3V to 25V.
The VC pin optimizes the loop compensation of the
switching regulator based on the programmed switch-
ing frequency, allowing for a fast transient response. The
VC pin also enables current sharing and a CLKOUT pin
enables synchronizing other regulators to the LT8643S-2.
Comparators monitoring the FB pin voltage will pull the PG
pin low if the output voltage varies more than ±8% (typi-
cal) from the set point, or if a fault condition is present.
The oscillator reduces the LT8640S-2/LT8643S-2’s oper-
ating frequency when the voltage at the FB pin is low. This
frequency foldback helps to control the inductor current
when the output voltage is lower than the programmed
value which occurs during start-up or overcurrent condi-
tions. When a clock is applied to the SYNC/MODE pin, the
SYNC/MODE pin is floated, or held DC high, the frequency
foldback is disabled and the switching frequency will slow
down only during overcurrent conditions.
LT8640S-2/LT8643S-2
16
Rev 0
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APPLICATIONS INFORMATION
GROUND VIA VIN VIA VOUT VIA OTHER SIGNAL VIAS
8640s2
F01a
L
CIN2
CIN3
CIN1
CVCC
CBST
CSS
R2
C1
R1
RT
COUT
GROUND VIA VIN VIA VOUT VIA OTHER SIGNAL VIAS
8640s2
F01b
CVCC
L
CIN2
CIN3
CIN1
CSS
R2
RC
CC
C1
R1
RT
COUT
CF
CBST
(a) LT8640S-2 (b) LT8643S-2
Figure1. Recommended PCB Layouts for the LT8640S-2 and LT8643S-2
Low EMI PCB Layout
The LT8640S-2/LT8643S-2 is specifically designed to
minimize EMI emissions and also to maximize efficiency
when switching at high frequencies. For optimal perfor-
mance the LT8640S-2/LT8643S-2 requires the use of
multiple VIN bypass capacitors.
Two small 1µF capacitors should be placed as close as
possible to the LT8640S-2/LT8643S-2, one capacitor on
each side of the device (CIN1, CIN2). A third capacitor with
a larger value, 2.2µF or higher, should be placed near C
IN1
or CIN2.
See Figure1 for a recommended PCB layouts.
For more detail and PCB design files refer to the Demo
Board guide for the LT8640S-2/LT8643S-2.
Note that large, switched currents flow in the LT8640S-2/
LT8643S-2 VIN and GND pins and the input capacitors.
The loops formed by the input capacitors should be as
small as possible by placing the capacitors adjacent to the
VIN and GND pins. Capacitors with small case size such
as 0603 are optimal due to lowest parasitic inductance.
The input capacitors, along with the inductor and out-
put capacitors, should be placed on the same side of the
circuit board, and their connections should be made on
that layer. Place a local, unbroken ground plane under the
application circuit on the layer closest to the surface layer.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB and RT nodes small so that the ground
traces will shield them from the SW and BOOST nodes.
LT8640S-2/LT8643S-2
17
Rev 0
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APPLICATIONS INFORMATION
feedback resistor divider must be minimized as it appears
to the output as load current.
In order to achieve higher light load efficiency, more
energy must be delivered to the output during the sin-
gle small pulses in Burst Mode operation such that the
LT8640S-2/LT8643S-2 can stay in sleep mode longer
between each pulse. This can be achieved by using
a larger value inductor (i.e., 4.7µH), and should be
considered independent of switching frequency when
choosing an inductor. For example, while a lower induc-
tor value would typically be used for a high switching
frequency application, if high light load efficiency is
desired, a higher inductor value should be chosen. See
curve in Typical Performance Characteristics.
While in Burst Mode operation the current limit of the top
switch is approximately 900mA (as shown in Figure3),
resulting in low output voltage ripple. Increasing the out-
put capacitance will decrease output ripple proportionally.
As load ramps upward from zero the switching frequency
will increase but only up to the switching frequency
programmed by the resistor at the RT pin as shown in
Figure2.
The output load at which the LT8640S-2/LT8643S-2
reaches the programmed frequency varies based on input
voltage, output voltage and inductor choice. To select
low ripple Burst Mode operation, tie the SYNC/MODE pin
below 0.4V (this can be ground or a logic low output).
Figure2. SW Frequency vs Load Information
in Burst Mode Operation Figure3. Burst Mode Operation
FRONT PAGE APPLICATION
V
IN
= 12V
V
OUT
= 5V
LOAD CURRENT (mA)
0
0
1000
1200
SWITCHING FREQUENCY (kHz)
8640s2 F02
FRONT PAGE APPLICATION
12V
IN
TO 5V
OUT
AT 10mA
V
SYNC
= 0V
5µs/DIV
V
SW
5V/DIV
I
L
500mA/DIV
8640s2 F03
The exposed pads on the bottom of the package should be
soldered to the PCB to reduce thermal resistance to ambi-
ent. To keep thermal resistance low, extend the ground
plane from GND as much as possible, and add thermal
vias to additional ground planes within the circuit board
and on the bottom side.
Burst Mode Operation
To enhance efficiency at light loads, the LT8640S-2/
LT8643S-2 operates in low ripple Burst Mode operation,
which keeps the output capacitor charged to the desired
output voltage while minimizing the input quiescent cur-
rent and minimizing output voltage ripple. In Burst Mode
operation the LT8640S-2/LT8643S-2 delivers single small
pulses of current to the output capacitor followed by sleep
periods where the output power is supplied by the output
capacitor. While in sleep mode the LT8640S-2 consumes
1.7µA and the LT8643S-2 consumes 230µA.
As the output load decreases, the frequency of single
current pulses decreases (see Figure 2) and the per-
centage of time the LT8640S-2/LT8643S-2 is in sleep
mode increases, resulting in much higher light load effi-
ciency than for typical converters. By maximizing the
time between pulses, the LT8640S-2’s quiescent current
approaches 2.5µA for a typical application when there
is no output load. Therefore, to optimize the quiescent
current performance at light loads, the current in the
LT8640S-2/LT8643S-2
18
Rev 0
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APPLICATIONS INFORMATION
Forced Continuous Mode
The LT8640S-2/LT8643S-2 can operate in forced con-
tinuous mode (FCM) for fast transient response and
full frequency operation over a wide load range. When
in FCM, the oscillator operates continuously and posi-
tive SW transitions are aligned to the clock. Negative
inductor current is allowed at light loads or under large
transient conditions. The LT8640S-2/LT8643S-2 can
sink current from the output and return this charge to
the input in this mode, improving load step transient
response (see Figure4). At light loads, FCM operation
is less efficient than Burst Mode operation, but may
be desirable in applications where it is necessary to
keep switching harmonics out of the signal band. FCM
must be used if the output is required to sink current.
To enable FCM, float the SYNC/MODE pin. Leakage cur-
rent on this pin should be <1µA. See Block Diagram for
internal pull-up and pull-down resistance.
FCM is disabled if the VIN pin is held above 37V or if
the FB pin is held greater than 8% above the feedback
reference voltage. FCM is also disabled during soft-start
until the soft-start capacitor is fully charged. When FCM
is disabled in these ways, negative inductor current is
not allowed and the LT8640S-2/LT8643S-2 operates in
pulse-skipping mode.
For robust operation over a wide VIN and VOUT range, use
an inductor value greater than LMIN:
LMIN =VOUT
2 • fSW
• 1– VOUT
VIN,MAX
⎛
⎝
⎜⎞
⎠
⎟
Spread Spectrum Mode
The LT8640S-2/LT8643S-2 features spread spectrum
operation to further reduce EMI emissions. To enable
spread spectrum operation, the SYNC/MODE pin should
be tied high to INTVCC (~3.4V)or an external supply of 3V
to 4V. In this mode, triangular frequency modulation is
used to vary the switching frequency between the value
programmed by RT to approximately 20% higher than
that value. The modulation frequency is approximately
3kHz. For example, when the LT8640S-2/LT8643S-2 is
programmed to 2MHz, the frequency will vary from 2MHz
to 2.4MHz at a 3kHz rate. When spread spectrum opera-
tion is selected, Burst Mode operation is disabled, and the
part will run in forced continuous mode.
Synchronization
To synchronize the LT8640S-2/LT8643S-2 oscillator to an
external frequency, connect a square wave to the SYNC/
MODE pin. The square wave amplitude should have val-
leys that are below 0.4V and peaks above 1.5V (up to 6V)
with a minimum on-time and off-time of 50ns.
The LT8640S-2/LT8643S-2 will not enter Burst Mode
operation at low output loads while synchronized to an
external clock, but instead will run forced continuous
mode to maintain regulation. The LT8640S-2/LT8643S-2
may be synchronized over a 200kHz to 3MHz range. The
RT resistor should be chosen to set the LT8640S-2/
LT8643S-2 switching frequency equal to or below the
lowest synchronization input. For example, if the synchro-
nization signal will be 500kHz and higher, the RT should
be selected for 500kHz. The slope compensation is set
by the RT value, while the minimum slope compensation
required to avoid subharmonic oscillations is established
by the inductor size, input voltage and output voltage.
Since the synchronization frequency will not change the
slopes of the inductor current waveform, if the inductor
Figure4. LT8640S-2 Load Step Transient Response
with and without Forced Continuous Mode
FRONT PAGE APPLICATION
100mA TO 1.1A TRANSIENT
12VIN, 5VOUT, fSW = 1MHz
C
OUT
= 100µF
Burst Mode OPERATION
FCM
50µs/DIV
I
LOAD
1A/DIV
V
OUT
100mV/DIV
8640s2 F04
LT8640S-2/LT8643S-2
19
Rev 0
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APPLICATIONS INFORMATION
is large enough to avoid subharmonic oscillations at the
frequency set by RT, then the slope compensation will be
sufficient for all synchronization frequencies.
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistor
values according to:
R1=R2
V
OUT
0.970V –1
⎛
⎝
⎜⎞
⎠
⎟
(1)
Reference designators refer to the Block Diagram. 1%
resistors are recommended to maintain output voltage
accuracy.
For the LT8640S-2, if low input quiescent current and
good light-load efficiency are desired, use large resistor
values for the FB resistor divider. The current flowing in
the divider acts as a load current, and will increase the no-
load input current to the converter, which is approximately:
IQ=1.7µA +VOUT
R1+R2
⎛
⎝
⎜⎞
⎠
⎟VOUT
V
IN
⎛
⎝
⎜⎞
⎠
⎟1
n
⎛
⎝
⎜⎞
⎠
⎟
(2)
where 1.7µA is the quiescent current of the LT8640S-2
and the second term is the current in the feedback divider
reflected to the input of the buck operating at its light load
efficiency n. For a 3.3V application with R1= 1M and R2
= 412k, the feedback divider draws 2.3µA. With VIN =
12V and n = 80%, this adds 0.8µA to the 1.7µA quiescent
current resulting in 2.5µA no-load current from the 12V
supply. Note that this equation implies that the no-load
current is a function of VIN; this is plotted in the Typical
Performance Characteristics section.
When using large FB resistors, a 4.7pF to 22pF phase-lead
capacitor should be connected from VOUT to FB.
Setting the Switching Frequency
The LT8640S-2/LT8643S-2 uses a constant frequency
PWM architecture that can be programmed to switch from
200kHz to 3MHz by using a resistor tied from the RT pin
to ground. A table showing the necessary RT value for a
desired switching frequency is in Table 1.
The R
T
resistor required for a desired switching frequency
can be calculated using:
RT=
46.5
fSW
– 5.2
(3)
where RT is in kΩ and fSW is the desired switching fre-
quency in MHz.
Table 1. SW Frequency vs RT Value
fSW (MHz) RT (kΩ)
0.2 232
0.3 150
0.4 110
0.5 88.7
0.6 71.5
0.7 60.4
0.8 52.3
1.0 41.2
1.2 33.2
1.4 28.0
1.6 23.7
1.8 20.5
2.0 17.8
2.2 15.8
3.0 10.7
Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, and input voltage range. The
advantage of high frequency operation is that smaller
inductor and capacitor values may be used. The disad-
vantages are lower efficiency and a smaller input voltage
range.
The highest switching frequency (fSW(MAX)) for a given
application can be calculated as follows:
fSW(MAX) =
V
OUT
+V
SW(BOT)
tON(MIN) VIN – VSW(TOP) +VSW(BOT)
( )
(4)
where VIN is the typical input voltage, VOUT is the output
voltage, V
SW(TOP)
and V
SW(BOT)
are the internal switch
drops (~0.4V, ~0.15V, respectively at maximum load)
LT8640S-2/LT8643S-2
20
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APPLICATIONS INFORMATION
and tON(MIN) is the minimum top switch on-time (see the
Electrical Characteristics). This equation shows that a
slower switching frequency is necessary to accommodate
a high VIN/VOUT ratio.
For transient operation, VIN may go as high as the abso-
lute maximum rating of 42V regardless of the RT value,
however the LT8640S-2/LT8643S-2 will reduce switching
frequency as necessary to maintain control of inductor
current to assure safe operation.
The LT8640S-2/LT8643S-2 is capable of a maximum duty
cycle of approximately 99%, and the V
IN
-to-V
OUT
dropout
is limited by the RDS(ON) of the top switch. In this mode
the LT8640S-2/LT8643S-2 skips switch cycles, resulting
in a lower switching frequency than programmed by RT.
For applications that cannot allow deviation from the pro-
grammed switching frequency at low VIN/VOUT ratios use
the following formula to set switching frequency:
VIN(MIN) =
V
OUT
+V
SW(BOT)
1– fSW • tOFF(MIN)
– VSW(BOT) +VSW(TOP)
(5)
where VIN(MIN) is the minimum input voltage without
skipped cycles, VOUT is the output voltage, VSW(TOP) and
VSW(BOT) are the internal switch drops (~0.4V, ~0.15V,
respectively at maximum load), fSW is the switching
frequency (set by RT), and tOFF(MIN) is the minimum
switch off-time. Note that higher switching frequency will
increase the minimum input voltage below which cycles
will be dropped to achieve higher duty cycle.
Inductor Selection and Maximum Output Current
The LT8640S-2/LT8643S-2 is designed to minimize solu-
tion size by allowing the inductor to be chosen based on
the output load requirements of the application. During
overload or short-circuit conditions the LT8640S-2/
LT8643S-2 safely tolerates operation with a saturated
inductor through the use of a high speed peak-current
mode architecture.
A good first choice for the inductor value is:
L=
V
OUT
+V
SW(BOT)
fSW
⎛
⎝
⎜⎞
⎠
⎟• 0.7
(6)
where f
SW
is the switching frequency in MHz, V
OUT
is
the output voltage, VSW(BOT) is the bottom switch drop
(~0.15V) and L is the inductor value in µH.
To avoid overheating and poor efficiency, an inductor must
be chosen with an RMS current rating that is greater than
the maximum expected output load of the application.
In addition, the saturation current (typically labeled ISAT)
rating of the inductor must be higher than the load current
plus 1/2 of in inductor ripple current:
IL(PEAK) =ILOAD(MAX) +
1
2
ΔIL
(7)
where ∆IL is the inductor ripple current as calculated in
Equation 9 and ILOAD(MAX) is the maximum output load
for a given application.
As a quick example, an application requiring 3A output
should use an inductor with an RMS rating of greater than
3A and an ISAT of greater than 4A. During long duration
overload or short-circuit conditions, the inductor RMS
rating requirement is greater to avoid overheating of the
inductor. To keep the efficiency high, the series resistance
(DCR) should be less than 0.02Ω, and the core material
should be intended for high frequency applications.
The LT8640S-2/LT8643S-2 limits the peak switch cur-
rent in order to protect the switches and the system from
overload faults. The top switch current limit (ILIM) is 10A
at low duty cycles and decreases linearly to 7A at DC =
0.8. The inductor value must then be sufficient to supply
the desired maximum output current (IOUT(MAX)), which
is a function of the switch current limit (ILIM) and the
ripple current.
IOUT(MAX) =ILIM –
ΔI
L
2
(8)
LT8640S-2/LT8643S-2
21
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The peak-to-peak ripple current in the inductor can be
calculated as follows:
ΔIL=VOUT
L • fSW
• 1– VOUT
VIN(MAX)
⎛
⎝
⎜⎞
⎠
⎟
(9)
where fSW is the switching frequency of the LT8640S-2/
LT8643S-2, and L is the value of the inductor. Therefore,
the maximum output current that the LT8640S-2/
LT8643S-2 will deliver depends on the switch current
limit, the inductor value, and the input and output volt-
ages. The inductor value may have to be increased if the
inductor ripple current does not allow sufficient maxi-
mum output current (IOUT(MAX)) given the switching fre-
quency, and maximum input voltage used in the desired
application.
In order to achieve higher light load efficiency, more
energy must be delivered to the output during the sin-
gle small pulses in Burst Mode operation such that the
LT8640S-2/LT8643S-2 can stay in sleep mode longer
between each pulse. This can be achieved by using a
larger value inductor (i.e., 4.7µH), and should be consid-
ered independent of switching frequency when choosing
an inductor. For example, while a lower inductor value
would typically be used for a high switching frequency
application, if high light load efficiency is desired, a higher
inductor value should be chosen. See curve in Typical
Performance Characteristics.
The optimum inductor for a given application may differ
from the one indicated by this design guide. A larger value
inductor provides a higher maximum load current and
reduces the output voltage ripple. For applications requir-
ing smaller load currents, the value of the inductor may
be lower and the LT8640S-2/LT8643S-2 may operate
with higher ripple current. This allows use of a physically
smaller inductor, or one with a lower DCR resulting in
higher efficiency. Be aware that low inductance may result
in discontinuous mode operation, which further reduces
maximum load current.
For more information about maximum output current and
discontinuous operation, see Analog Devices Application
Note 44.
For duty cycles greater than 50% (VOUT/VIN > 0.5), a
minimum inductance is required to avoid sub-harmonic
oscillation. See Application Note 19.
Input Capacitors
The VIN of the LT8640S-2/LT8643S-2 should be bypassed
with at least three ceramic capacitors for best perfor-
mance. Two small ceramic capacitors of 1µF should be
placed close to the part; one on each side of the device
(CIN1, CIN2). These capacitors should be 0402 or 0603 in
size. For automotive applications requiring 2 series input
capacitors, two small 0402 or 0603 may be placed at
each side of the LT8640S-2/LT8643S-2 near the VIN and
GND pins.
A third, larger ceramic capacitor of 2.2µF or larger should
be placed close to CIN1 or CIN2. See layout section for
more detail. X7R or X5R capacitors are recommended for
best performance across temperature and input voltage
variations.
Note that larger input capacitance is required when a lower
switching frequency is used. If the input power source has
high impedance, or there is significant inductance due to
long wires or cables, additional bulk capacitance may be
necessary. This can be provided with a low performance
electrolytic capacitor.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank cir-
cuit. If the LT8640S-2/LT8643S-2 circuit is plugged into a
live supply, the input voltage can ring to twice its nominal
value, possibly exceeding the LT8640S-2/LT8643S-2’s
voltage rating. This situation is easily avoided (see Analog
Devices Application Note 88).
LT8640S-2/LT8643S-2
22
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Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LT8640S-2/LT8643S-2 to produce the DC output. In
this role it determines the output ripple, thus low imped-
ance at the switching frequency is important. The second
function is to store energy in order to satisfy transient
loads and stabilize the LT8640S-2/LT8643S-2’s control
loop. Ceramic capacitors have very low equivalent series
resistance (ESR) and provide the best ripple performance.
For good starting values, see the Typical Applications
section.
Use X5R or X7R types. This choice will provide low out-
put ripple and good transient response. Transient perfor-
mance can be improved with a higher value output capaci-
tor and the addition of a feedforward capacitor placed
between VOUT and FB. Increasing the output capacitance
will also decrease the output voltage ripple. A lower value
of output capacitor can be used to save space and cost
but transient performance will suffer and may cause loop
instability. See the Typical Applications in this data sheet
for suggested capacitor values.
When choosing a capacitor, special attention should be
given to the data sheet to calculate the effective capaci-
tance under the relevant operating conditions of voltage
bias and temperature. A physically larger capacitor or one
with a higher voltage rating may be required.
Ceramic Capacitors
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT8640S-2/LT8643S-2 due to their
piezoelectric nature. When in Burst Mode operation, the
LT8640S-2/LT8643S-2’s switching frequency depends on
the load current, and at very light loads the LT8640S-2/
LT8643S-2 can excite the ceramic capacitor at audio fre-
quencies, generating audible noise. Since the LT8640S-2/
LT8643S-2 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet to a
casual ear. If this is unacceptable, use a high performance
tantalum or electrolytic capacitor at the output. Low noise
ceramic capacitors are also available.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LT8640S-2/
LT8643S-2. As previously mentioned, a ceramic input
capacitor combined with trace or cable inductance
forms a high quality (underdamped) tank circuit. If the
LT8640S-2/LT8643S-2 circuit is plugged into a live sup-
ply, the input voltage can ring to twice its nominal value,
possibly exceeding the LT8640S-2/LT8643S-2’s rat-
ing. This situation is easily avoided (see Analog Devices
Technology Application Note 88).
Enable Pin
The LT8640S-2/LT8643S-2 is in shutdown when the EN
pin is low and active when the pin is high. The rising
threshold of the EN comparator is 1.0V, with 40mV of
hysteresis. The EN pin can be tied to VIN if the shutdown
feature is not used, or tied to a logic level if shutdown
control is required.
Adding a resistor divider from V
IN
to EN programs the
LT8640S-2/LT8643S-2 to regulate the output only when
VIN is above a desired voltage (see the Block Diagram).
Typically, this threshold, VIN(EN), is used in situations
where the input supply is current limited, or has a rel-
atively high source resistance. A switching regulator
draws constant power from the source, so source cur-
rent increases as source voltage drops. This looks like
a negative resistance load to the source and can cause
the source to current limit or latch low under low source
voltage conditions. The VIN(EN) threshold prevents the
regulator from operating at source voltages where the
problems might occur. This threshold can be adjusted by
setting the values R3 and R4 such that they satisfy the
following equation:
VIN(EN) =
R3
R4 +1
⎛
⎝
⎜⎞
⎠
⎟•1.0V
(10)
where the LT8640S-2/LT8643S-2 will remain off until
VIN is above VIN(EN). Due to the comparator’s hysteresis,
switching will not stop until the input falls slightly below
VIN(EN).
When operating in Burst Mode operation for light load
currents, the current through the VIN(EN) resistor network
can easily be greater than the supply current consumed
by the LT8640S-2/LT8643S-2. Therefore, the VIN(EN)
LT8640S-2/LT8643S-2
23
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resistors should be large to minimize their effect on effi-
ciency at low loads.
INTVCC Regulator
An internal low dropout (LDO) regulator produces the
3.4V supply from VIN that powers the drivers and the
internal bias circuitry. The INTV
CC
can supply enough cur-
rent for the LT8640S-2/LT8643S-2’s circuitry and must
be bypassed to ground with a minimum of 1µF ceramic
capacitor. Good bypassing is necessary to supply the high
transient currents required by the power MOSFET gate
drivers. To improve efficiency the internal LDO can also
draw current from the BIAS pin when the BIAS pin is
at 3.1V or higher. Typically the BIAS pin can be tied to
the output of the LT8640S-2/LT8643S-2, or can be tied
to an external supply of 3.3V or above. If BIAS is con-
nected to a supply other than V
OUT
, be sure to bypass
with a local ceramic capacitor. If the BIAS pin is below
3.0V, the internal LDO will consume current from VIN.
Applications with high input voltage and high switching
frequency where the internal LDO pulls current from VIN
will increase die temperature because of the higher power
dissipation across the LDO. Do not connect an external
load to the INTVCC pin.
Frequency Compensation (LT8643S-2 Only)
Loop compensation determines the stability and transient
performance, and is provided by the components tied to
the VC pin. Generally, a capacitor (CC) and a resistor (RC)
in series to ground are used. Designing the compensation
network is a bit complicated and the best values depend
on the application. A practical approach is to start with
one of the circuits in this data sheet that is similar to your
application and tune the compensation network to opti-
mize the performance. LTspice
®
simulations can help in
this process. Stability should then be checked across all
operating conditions, including load current, input voltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load.
Figure5 shows an equivalent circuit for the LT8643S-2
control loop. The error amplifier is a transconductance
amplifier with finite output impedance. The power section,
consisting of the modulator, power switches, and inductor,
is modeled as a transconductance amplifier generating an
output current proportional to the voltage at the VC pin.
Note that the output capacitor integrates this current, and
that the capacitor on the VC pin (CC) integrates the error
amplifier output current, resulting in two poles in the loop.
A zero is required and comes from a resistor RC in series
with CC. This simple model works well as long as the value
of the inductor is not too high and the loop crossover
frequency is much lower than the switching frequency. A
phase lead capacitor (C
PL
) across the feedback divider can
be used to improve the transient response and is required
to cancel the parasitic pole caused by the feedback node
to ground capacitance.
Figure5. Model for Loop Response
Output Voltage Tracking and Soft-Start
T
he LT8640S-2/LT8643S-2 allows the user to program
its output voltage ramp rate by means of the TR/SS pin.
An internal 1.9µA pulls up the TR/SS pin to INTVCC.
Putting an external capacitor on TR/SS enables soft
starting the output to prevent current surge on the input
supply. During the soft-start ramp the output voltage will
proportionally track the TR/SS pin voltage.
For output tracking applications, TR/ SS can be externally
driven by another voltage source. For the LT8640S-2, from
0V to 0.97V, the TR/SS voltage will override the internal
0.97V reference input to the error amplifier, thus regulat-
ing the FB pin voltage to that of TR/SS pin. When TR/SS
is above 0.97V, tracking is disabled and the feedback
voltage will regulate to the internal reference voltage. For
VC
gm = 5S
gm = 1.7mS
CURRENT MODE
POWER STAGE
LT8643S-2
150k
0.97V
FB
RC
R1
M2
M1
R2
CC
CF
8640s2 F05
+
–
CPL
C1
OUTPUT
LT8640S-2/LT8643S-2
24
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the LT8643S-2, from 0V to 1.6V, the TR/SS voltage will
override the internal 0.97V reference input to the error
amplifier, thus regulating the FB pin voltage to a func-
tion of the TR/SS pin. See plot in the Typical Performance
Characteristics section. When TR/SS is above 1.6V, track-
ing is disabled and the feedback voltage will regulate to
the internal reference voltage. The TR/SS pin may be left
floating if the function is not needed.
An active pull-down circuit is connected to the TR/SS pin
which will discharge the external soft-start capacitor in
the case of fault conditions and restart the ramp when the
faults are cleared. Fault conditions that clear the soft-start
capacitor are the EN/UV pin transitioning low, VIN voltage
falling too low, or thermal shutdown.
Paralleling (LT8643S-2 Only)
To increase the possible output current, two LT8643S-2s
can be connected in parallel to the same output. To do
this, the VC and FB pins are connected together, and each
LT8643S-2’s SW node is connected to the common out-
put through its own inductor. The CLKOUT pin of one
LT8643S-2 should be connected to the SYNC/MODE pin
of the second LT8643S-2 to have both devices operate
in the same mode. During FCM, spread spectrum, and
synchronization modes, both devices will operate at the
same frequency. Figure6 shows an application where two
LT8643S-2 are paralleled to get one output capable of up
to 12A.
Output Power Good
When the LT8640S-2/LT8643S-2’s output voltage is
within the ±8% window of the regulation point, the out-
put voltage is considered good and the open-drain PG pin
goes high impedance and is typically pulled high with an
external resistor. Otherwise, the internal pull-down device
will pull the PG pin low. To prevent glitching both the
upper and lower thresholds include 0.2% of hysteresis.
PG is valid when VIN is above 3.4V.
The PG pin is also actively pulled low during several fault
conditions: EN/UV pin is below 1V, INTVCC has fallen too
low, VIN is too low, or thermal shutdown.
Shorted and Reversed Input Protection
The LT8640S-2/LT8643S-2 will tolerate a shorted output.
Several features are used for protection during output
short-circuit and brownout conditions. The first is the
switching frequency will be folded back while the output
is lower than the set point to maintain inductor current
control. Second, the bottom switch current is monitored
such that if inductor current is beyond safe levels switch-
ing of the top switch will be delayed until such time as the
inductor current falls to safe levels.
Frequency foldback behavior depends on the state of the
SYNC pin: If the SYNC pin is low the switching frequency
will slow while the output voltage is lower than the pro-
grammed level. If the SYNC pin is connected to a clock
source, floated or tied high, the LT8640S-2/LT8643S-2
will stay at the programmed frequency without foldback
and only slow switching if the inductor current exceeds
safe levels.
There is another situation to consider in systems where
the output will be held high when the input to the
LT8640S-2/LT8643S-2 is absent. This may occur in bat-
tery charging applications or in battery-backup systems
where a battery or some other supply is diode ORed
with the LT8640S-2/LT8643S-2’s output. If the VIN pin
is allowed to float and the EN pin is held high (either
by a logic signal or because it is tied to VIN), then the
LT8640S-2/LT8643S-2’s internal circuitry will pull its qui-
escent current through its SW pin. This is acceptable if
the system can tolerate several µA in this state. If the EN
pin is grounded the SW pin current will drop to near 1µA.
RC
R1
L1
R2
CC
8640s2 F06
C1 COUT
V
OUT
12A
LT8643S-2
L2
SW
FB
VC
CLKOUT
LT8643S-2
FB
SW
SYNC/MODE
VC
Figure6. Paralleling Two LT8643S-2s
LT8640S-2/LT8643S-2
25
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However, if the V
IN
pin is grounded while the output is held
high, regardless of EN, parasitic body diodes inside the
LT8640S-2/LT8643S-2 can pull current from the output
through the SW pin and the V
IN
pin, which may dam
-
age the IC. Figure7 shows a connection of the VIN and
EN/UV pins that will allow the LT8640S-2/LT8643S-2
to run only when the input voltage is present and that
protects against a shorted or reversed input.
load current can be decreased to reduce the temperature
to an acceptable level. Figure8 shows examples of how
case temperature rise can be managed by reducing VIN,
switching frequency, or load.
The LT8640S-2/LT8643S-2’s internal power switches
are capable of safely delivering up to 7A of peak out-
put current. However, due to thermal limits, the package
can only handle 7A loads for short periods of time. This
time is determined by how quickly the case temperature
approaches the maximum junction rating. Figure9 shows
an example of how case temperature rise changes with
the duty cycle of a 1kHz pulsed 7A load.
The LT8640S-2/LT8643S-2’s top switch current limit
decreases with higher duty cycle operation for slope com-
pensation. This also limits the peak output current the
LT8640S-2/LT8643S-2 can deliver for a given application.
See curve in Typical Performance Characteristics.
Figure7. Reverse VIN Protection
VIN
V
IN
D1
LT8640S-2
LT8643S-2
EN/UV
8640s2
F07
GND
Figure8. Case Temperature Rise
Figure9. Case Temperature Rise vs 7A Pulsed Load
DC2530A DEMO BOARD
V
IN
= 12V, f
SW
= 1MHz
V
IN
= 24V, f
SW
= 1MHz
V
IN
= 12V, f
SW
= 2MHz
V
IN
= 24V, f
SW
= 2MHz
LOAD CURRENT (A)
0
1
2
3
4
5
6
0
10
20
30
40
50
60
70
80
CASE TEMPERATURE RISE (°C)
8640s2 F08
DC2530A DEMO BOARD
V
IN
= 12V
V
OUT
= 5V
f
SW
= 2MHz
STANDBY LOAD = 0.25A
1kHz PULSED LOAD = 7A
DUTY CYCLE OF 7A LOAD
0
0.2
0.4
0.6
0.8
1
0
10
20
30
40
50
60
70
80
90
CASE TEMPERATURE RISE (°C)
Pulsed Load
8640s2 F09
Thermal Considerations and Peak Output Current
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT8640S-2/LT8643S-2. The ground pins on the bottom
of the package should be soldered to a ground plane.
This ground should be tied to large copper layers below
with thermal vias; these layers will spread heat dissipated
by the LT8640S-2/LT8643S-2. Placing additional vias
can reduce thermal resistance further. The maximum load
current should be derated as the ambient temperature
approaches the maximum junction rating. Power dissipa-
tion within the LT8640S-2/LT8643S-2 can be estimated
by calculating the total power loss from an efficiency
measurement and subtracting the inductor loss. The die
temperature is calculated by multiplying the LT8640S-2/
LT8643S-2 power dissipation by the thermal resistance
from junction to ambient.
The internal overtemperature protection monitors the
junction temperature of the LT8640S-2/LT8643S-2. If
the junction temperature reaches approximately 180°C,
the LT8640S-2/LT8643S-2 will stop switching and indi-
cate a fault condition until the temperature drops about
10°C cooler
.
Temperature rise of the LT8640S-2/LT8643S-2 is worst
when operating at high load, high VIN, and high switch-
ing frequency. If the case temperature is too high for a
given application, then either V
IN
, switching frequency, or
LT8640S-2/LT8643S-2
26
Rev 0
For more information www.analog.com
Figure10. 5V, 6A Step-Down Converter with Soft-Start and Power Good
Figure11. 3.3V, 6A Step-Down Converter with Soft-Start and Power Good
TYPICAL APPLICATIONS
* VC pin and components only apply to LT8643S-2.
VIN
VIN
EN/UV
CLKOUT
LT8640S-2
LT8643S-2
8640s2 F10
BST
SYNC/MODE
VC* PG
SW
TR/SS BIAS
INTVCC FB
RT GND
0.1µF
4.7pF (LT8643S-2)
10pF (LT8640S-2) 100µF
1210
X5R/X7R
330pF
1M
100k
VOUT
5V
6A
1µF
0603
1µF
0603
4.7µF
VIN
5.7V TO 42V
10nF
41.2k
1µF
3.3µH
6.49k
243k
GNDGND
fSW = 1MHz
L: XEL6030
VIN
VIN
EN/UV
CLKOUT
LT8640S-2
LT8643S-2
8640s2 F11
BST
SYNC/MODE
VC* PG
SW
TR/SS BIAS
INTVCC FB
RT GND
0.1µF
4.7pF (LT8643S-2)
10pF (LT8640S-2) 100µF
1210
X5R/X7R
330pF
1M
100k
VOUT
3.3V
6A
1µF
0603
1µF
0603
4.7µF
VIN
4V TO 42V
10nF
41.2k
1µF
2.2µH
8.45k
412k
GNDGND
fSW = 1MHz
L: XEL6030
LT8640S-2/LT8643S-2
27
Rev 0
For more information www.analog.com
Figure13. 2MHz 5V, 6A Step-Down Converter with Spread Spectrum
TYPICAL APPLICATIONS
Figure12. Ultralow EMI 5V, 6A Step-Down Converter with Spread Spectrum
* VC pin and components only apply to LT8643S-2.
VIN
VIN
EN/UV
LT8640S-2
LT8643S-2
8640s2 F13
BST
SYNC/MODE
VC*SW
BIAS
INTVCC FB
RT GND
0.1µF
4.7pF (LT8643S-2)
10pF (LT8640S-2) 100µF
1210
X5R/X7R
330pF
1M
VOUT
5V
6A
1µF
0603
1µF
0603
4.7µF
VIN
5.7V TO 42V
17.8k
1µF
1.5µH
8.45k
243k
GNDGND
fSW = 2MHz
L: XEL6030
PINS NOT USED IN
THIS CIRCUIT:
CLKOUT, PG, TR/SS
PINS NOT USED IN
THIS CIRCUIT:
CLKOUT, PG, TR/SS
LT8640S-2
LT8643S-2
SW
BST
BIAS
FB
V
IN
5.7V TO 42V
GND
RT
VC*
EN/UV
V
OUT
5V
6A
100µF
1210
X5R/X7R
4.7pF (LT8643S-2)
10pF (LT8640S-2)
17.8k
330pF
8.45k
1M
243k
1.5µH
0.1µF
f
SW
= 2MHz
L: XEL6030
FB1 BEAD: WE-MPSB 100Ω 8A 1812
10µF
1210
BEAD
10µF
1210
10µF
1210
1µF
0603
V
IN
GND
1µF
0603
V
IN
GND
SYNC/MODE
INTV
CC
1µF
8640s2 F12
LT8640S-2/LT8643S-2
28
Rev 0
For more information www.analog.com
* VC pin and components only apply to LT8643S-2.
Figure14. 2MHz 3.3V, 6A Step-Down Converter with Spread Spectrum
Figure15. 12V, 6A Step-Down Converter
TYPICAL APPLICATIONS
VIN2
VIN1
EN/UV
LT8640S-2
8640s2 F15
BST
PINS NOT USED IN THIS CIRCUIT:
CLKOUT, PG, SYNC/MODE
TR/SS
SW
BIAS
INTVCC FB
RT GND
0.1µF
4.7pF 47µF
1210
X5R/X7R
10nF
1M
VOUT
12V
6A
1µF
0603
1µF
0603
4.7µF
VIN
12.7V TO 42V
41.2k
1µF
4.7µH
88.7k
GND2GND1
fSW = 1MHz
L: XEL6060
VIN
VIN
EN/UV
LT8640S-2
LT8643S-2
8640s2 F14
BST
SYNC/MODE
VC*SW
BIAS
INTVCC FB
RT GND
0.1µF
4.7pF (LT8643S-2)
10pF (LT8640S-2) 100µF
1210
X5R/X7R
220pF
1M
VOUT
3.3V
6A
1µF
0603
1µF
0603
4.7µF
VIN
4V TO 42V
17.8k
1µF
1µH
16.2k
412k
GNDGND
fSW = 2MHz
L: XEL6030
PINS NOT USED IN
THIS CIRCUIT:
CLKOUT, PG, TR/SS
LT8640S-2/LT8643S-2
29
Rev 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
LQFN Package
24-Lead (4mm × 4mm × 0.94mm)
(Reference LTC DWG # 05-08-1511 Rev C)
DETAIL B
A
PACKAGE TOP VIEW
5
PAD “A1”
CORNER
Y
X
aaa Z2×
24b
PACKAGE BOTTOM VIEW
4
6
SEE NOTES
E
D
b
0.375
e
e
b
E1
D1
DETAIL B
SUBSTRATE
MOLD
CAP
// bbb Z
Z
H2
H1
DETAIL A
DETAIL C
SUGGESTED PCB LAYOUT
TOP VIEW
0.0000
0.0000
0.7500
1.2500
0.2500
0.2500
0.7500
1.2500
1.2500
0.7500
0.2500
0.2500
1.2500
0.7500
DETAIL A
7
SEE NOTES
PIN 1 NOTCH
0.283 × 45°
19 24
12 7
1
6
18
13
aaa Z
2×
MX YZccc
MX YZccc
MX YZeee
MZfff
PACKAGE
OUTLINE
0.25 ±0.05 0.375
0.375
0.70 ±0.05
4.50 ±0.05
4.50 ±0.05
LGA 24 0317 REV C
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
LTXXXXXX
0.375
0.20
0.20
1.125
1.125
0.20
0.20
1.125
1.125
ddd Z
24×
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
MIN
0.85
0.01
0.30
0.22
NOM
0.94
0.02
0.40
0.25
4.00
4.00
2.45
2.45
0.50
0.24
0.70
MAX
1.03
0.03
0.50
0.28
0.10
0.10
0.10
0.10
0.15
0.08
NOTES
DIMENSIONS
Z
A1
DETAIL C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. PRIMARY DATUM -Z- IS SEATING PLANE
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
5
4
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
6 THE EXPOSED HEAT FEATURE IS SEGMENTED AND ARRANGED
IN A MATRIX FORMAT. IT MAY HAVE OPTIONAL CORNER RADII
ON EACH SEGMENT
7 CORNER SUPPORT PAD CHAMFER IS OPTIONAL
e
L
e/2
LT8640S-2/LT8643S-2
30
Rev 0
For more information www.analog.com
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PART DESCRIPTION COMMENTS
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LT8610A/
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ISD < 1µA, MSOP-16E
LT8610AC 42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-
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VIN(MIN) = 3V, VIN(MAX) = 42V, VOUT(MIN) = 0.8V, IQ = 2.5µA,
ISD < 1µA, MSOP-16E
LT8610 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-
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VIN(MIN) = 3V, VIN(MAX) = 42V, VOUT(MIN) = 0.8V, IQ = 2.5µA,
ISD < 1µA, 6mm × 6mm QFN-40
VIN2
VIN1
EN/UV
LT8640S-2
8640s2 TA02
BST
PINS NOT USED IN THIS CIRCUIT:
CLKOUT, PG, SYNC/MODE
TR/SS
SW
BIAS
INTVCC FB
RT GND
0.1µF
1µF 10pF
EXTERNAL
SOURCE >3.1V
OR GND 100µF
1210
X5R/X7R
10nF
866k
VOUT
1.8V
6A
1µF
0603
1µF
0603
4.7µF
VIN
3.4V TO 22V
(42V TRANSIENT)
17.8k
1µF
1µH
1M
GND2GND1
fSW = 2MHz
L: XEL6030
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