Factsheet 02.100
July 2018
These specifications are subject to change without notice. 07/10/2018
© 2018 Greenliant 2 S71445-F
Industrial Grade
™
1.0 GENERAL DESCRIPTION
Each SATA NANDrive contains an integrated SATA NAND flash memory controller and up to eight discrete
NAND flash die in a BGA package. Refer to Figure 2-1 for the SATA NANDrive block diagram.
1.1 Optimized SAT A NANDr ive
The heart of SATA NANDri ve is the SATA NAN D f las h
memory controller which translates standard SATA
signals into flash m edia data and control signals. The
following components contribute to SATA NANDrive’s
operation.
1.1.1 Microcontroller Unit (MCU)
The MCU translates SATA commands into data and
control signals required for flash media operation.
1.1.2 Internal Direct Memory Access (DMA)
SATA NANDrive uses internal DMA allowing instant
data transfer from/to buffer to/from flash media. This
implementation eliminates microcontroller overhead
associated with the traditional, firmware-based
approach, thereby increasing the data transfer rate.
1.1.3 Power Management Unit (PMU)
The PMU controls the power consumption of SATA
NANDrive. The PMU dramatically reduces the power
consum ption of SATA NAN Drive b y putting the par t of
the circuitry that is not in operation into sleep mode. 3)
The Flash File System handles inadvertent power
interrupts and has auto-recovery capability to ensure
SATA NANDrive firmware integrity. For regular power
management, the host must send a
STANDBY_IMMEDIATE (E0h), IDLE_IMMEDIATE
(E1h), STANDBY (E2h) or IDLE (E3h) command and
wait for comm and ready before powering do wn SAT A
NANDrive.
3) For management of the Sleep Mode, refer to “SATA
NANDrive Applicat i on Design Guide.”
1.1.4 Embedded Flash File System
The embedded flash file system is an integral part of
SATA NANDrive. It contains MCU firmware that
performs the following tasks:
1. Translates host side signals into flash media
writes and reads
2. Provides flash media wear leveling to spread the
flash writes across all memory address space to
increase the longevity of flash media
3. Keeps track of data file structures
4. Manages system security for the selected
protection zo nes
1.1.5 Error Correction Code (ECC)
High performance is achieved through optimized
hardware error detection and correction.
1.1.6 Serial Communication Interface (SCI)
The Seria l Comm unication Inter face (SCI) is desi gned
for error reporting. During the product development
stage, it is recommended to provide the SCI port on
the PCB to aid in design validation.
1.1.7 Multi-tasking Interface
The multi-tasking interface enables fast, sequential
write performance by allowing concurrent Read,
Program and Erase operati ons to m ultiple flash m edia.
1.2 SMT Reflow Consideration
The SATA NANDrive family utilizes standard NAND
flash for data storage. Because the high temperature
in a surface-mount solder ing ref low process may alter
the content on NAND flash, it is recommended to
program SATA NANDrive after the reflow process.
1.3 Advanced NAND Management
SATA NANDrive’s integrated controller uses
advanced wear-leveling algorithms to substantially
increase the longevity of NAND flash media. Wear
caused by data writes is evenly distributed in all or
select bloc ks in the device that pre vents “hot spots ” in
locations th at are pr o gram med and eras ed extensively.
This effective wear-leveling technique results in
optimized device endurance, enhanced data retention
and higher reliability required by long-life applications.