ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
AX88190
PCMCIA Fast Ethernet MAC Controller
ASIX
ASIX AX88190
100BASE-TX/FX PCMCIA
Fast Ethernet MAC Controller
Data Sheets (May/27/’99)
DOCUMENT NO.: AX190-1d.DOC
First Released: Oct. 2 1998
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Always contact ASIX for possible updates
before starting a design.
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CONTENTS
1.0 INTRODUCTION..........................................................................................................................................5
1.1 GENERAL DESCRIPTION:................................................................................................................................5
1.2 FEATURES .....................................................................................................................................................5
1.3 AX88190 BLOCK DIAGRAM:..........................................................................................................................6
1.4 AX88190 SYSTEM DIAGRAM.........................................................................................................................6
1.5 AX88190 PIN CONNECTION DIAGRAM...........................................................................................................7
2.0 SIGNAL DESCRIPTION...............................................................................................................................8
2.1 PCMCIA BUS INTERFACE SIGNALS GROUP ....................................................................................................8
2.2 EEPROM SIGNALS GROUP............................................................................................................................9
2.3 MII INTERFACE SIGNALS GROUP .....................................................................................................................9
2.4 MODEM INTERFACE PINS GROUP ...................................................................................................................10
2.5 SRAM INTERFACE PINS GROUP ....................................................................................................................10
2.6 MISCELLANEOUS PINS GROUP ....................................................................................................................... 11
2.7 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE............................................................11
3.0 MEMORY AND I/O MAPPING ................................................................................................................12
3.1 EEPROM MEMORY MAPPING .....................................................................................................................12
3.2 ATTRIBUTE MEMORY MAPPING.................................................................................................................... 12
3.3 I/O MAPPING...............................................................................................................................................13
3.4 SRAM MEMORY MAPPING.......................................................................................................................... 13
4.0 REGISTERS OPERATION.........................................................................................................................14
4.1 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF LAN.......................................................................14
4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)..........................................15
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)..................................... 16
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write).................................. 16
4.2 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF MODEM................................................................17
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write).................................. 17
4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write).............................18
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write)..........................18
4.3 REGISTERS OPERATION................................................................................................................................19
4.3.1 Command Register (CR) Offset 00H (Read/Write)............................................................................... 21
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write) ......................................................................21
4.3.3 Interrupt mask register (IMR) Offset 0FH (Write) ............................................................................... 22
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)......................................................................22
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write)................................................................ 22
4.3.6 Transmit Status Register (TSR) Offset 04H (Read) .............................................................................. 23
4.3.7 Receive Configuration (RCR) Offset 0CH (Write) ............................................................................... 23
4.3.8 Receive Status Register (RSR) Offset 0CH (Read)...............................................................................23
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)...................................................................................23
4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write).............................................................24
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write).............................................................24
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) ............................................ 24
4.3.13 Test Register (TR) Offset 15H (Write)................................................................................................ 24
5.0 PCMCIA DEVICE ACCESS FUNCTIONS...............................................................................................25
5.1 ATTRIBUTE MEMORY ACCESS FUNCTION FUNCTIONS..................................................................................... 25
5.2 I/O ACCESS FUNCTION FUNCTIONS................................................................................................................25
6.0 ELECTRICAL SPECIFICATION AND TIMINGS ..................................................................................26
6.1 ABSOLUTE MAXIMUM RATINGS....................................................................................................................26
6.2 GENERAL OPERATION CONDITIONS ..............................................................................................................26
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6.3 DC CHARACTERISTICS................................................................................................................................. 26
6.4 A.C. TIMING CHARACTERISTICS...................................................................................................................27
6.4.1 XTAL / CLOCK.................................................................................................................................... 27
6.4.2 Reset Timing........................................................................................................................................27
6.4.3 Attribute Memory Read Timing............................................................................................................28
6.4.4 Attribute Memory Write Timing ...........................................................................................................29
6.4.5 I/O Read Timing .................................................................................................................................. 30
6.4.6 I/O Write Timing..................................................................................................................................31
6.4.7 MII Timing...........................................................................................................................................32
7.0 PACKAGE INFORMATION......................................................................................................................33
APPENDIX A: APPLICATION NOTE 1.........................................................................................................34
A.1 USING CRYSTAL .........................................................................................................................................34
A.2 USING OSCILLATOR ....................................................................................................................................34
A.3 DUAL POWER (5V AND 3.3V) APPLICATION.................................................................................................. 35
A.4 SINGLE POWER (3.3V) APPLICATION ............................................................................................................35
APPENDIX B: APPLICATION NOTE 2.........................................................................................................36
B.1 ADVANCE APPLICATION FOR USING CRYSTAL ..............................................................................................36
ERRATA OF AX88190 V1 ................................................................................................................................37
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FIGURES
Fig - 1 AX88190 Block Diagram............................................................................................................................6
Fig - 2 AX88190 System Block Diagram ................................................................................................................6
Fig - 3 AX88190 Pin Connection Diagram.............................................................................................................7
TABLES
Tab - 1 PCMCIA bus interface signals group.........................................................................................................8
Tab - 2 EEPROM bus interface signals group........................................................................................................9
Tab - 3 MII interface signals group........................................................................................................................9
Tab - 4 Modem interface signals group................................................................................................................10
Tab - 5 SRAM Interface pins group......................................................................................................................10
Tab - 6 Miscellaneous pins group.........................................................................................................................11
Tab - 7 Power on Configuration Setup Table........................................................................................................11
Tab - 8 EEPROM Memory Mapping ....................................................................................................................12
Tab - 9 Attribute Memory Mapping......................................................................................................................12
Tab - 10 I/O Address Mapping.............................................................................................................................13
Tab - 11 Local Memory Mapping.........................................................................................................................13
Tab - 12 PCMCIA Function Configuration Register Mapping of LAN..................................................................14
Tab - 13 PCMCIA Function Configuration Register Mapping of MODEM...........................................................17
Tab - 14 Page 0 of MAC Core Registers Mapping................................................................................................19
Tab - 15 Page 1 of MAC Core Registers Mapping................................................................................................20
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1.0 Introduction
1.1 General Description:
l The AX88190 Fast Ethernet Controller is a high performance and highly integrated PCMCIA bus
Ethernet Controller chip.
l The AX88190 contains a 16 bit PCMCIA interfaces to host CPU and compliant with PC Card
Standard – February 1995.
l The AX88190 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard.
l The AX88190 support 10Mbps/100Mbps media-independent interface (MII) to simplify the design.
l The AX88190 is built in interface to connect FAX/MODEM chipset with parallel bus interface.
1.2 Features
l Single chip PCMCIA bus Fast Ethernet MAC Controller.
l NE2000 register level compatible instruction
l Compliant with 16 bit PC Card Standard - February 1995.
l Support both 10Mbps and 100Mbps data rate.
l Full-duplex or half-duplex operation supported for both 10Mbps and 100Mbps operation.
l Provides a MII port for both 10/100Mbps operation.
l Support 256/512 bytes EEPROM (used for saving CIS)
l Support automatic loading of Ethernet ID, CIS and Adapter Configuration from EEPROM on power-
on initialization
l External and internal loop-back capability.
l IEEE 802.3u 100BASE-T, TX, and T4 Compatible.
l 128 pin LQFP low profile package.
l Dual 5V and 3.3V CMOS process with 5V I/O tolerance. Or pure 3.3V operation.
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1.3 AX88190 Block Diagram:
Fig - 1 AX88190 Block Diagram
1.4 AX88190 System Diagram
Fig - 2 AX88190 System Block Diagram
MAC
Core
SRAM
Arbiter
Remote
DMA
FIFOs
NE2000
Registers
PCMCIA Interface
STA
SEEPROM
LOADER I/F
SD[15:0]
SA[9:0]
Ctl BUS
MII I/F
SMDC
SMDIO
MEMD[15:0]
MEMA[15:1]
EECS
EECK
EEDI
EEDO
MODEM
I/F
AX88190
PHY/TxRxMODEM
DAA
MAGNETIC
RJ45RJ11
PCMCIA I/F
EEPROM
SRAM
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1.5 AX88190 Pin Connection Diagram
The AX88190 is housed in the 128-pin plastic light quad flat pack. Fig - 3 shows the AX88190
pin connection diagram.
Fig - 3 AX88190 Pin Connection Diagram
MPWDN
123
118
122
78
70
54
41
32
24
12
8
MEMD[0]
LVDD
117
75
57
42
26
31
21
SA[1]
MRESET#
VSS
MINT
107
105
66
65
63
60
25
16
13
3
7
VSS
MRDY
LCLK/XTALIN
HVDD
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
LVDD
68
58
56
55
45
23
VSS
53
116
113
59
36
34
1
VSS
124
108
HVDD
PPWDN
MAUDIO
MDCS#
28
22
9
HVDD
LVDD
VSS
126
119
110
121
79
74
80
72
46
29
52
10
MRIN#
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
VSS
IOIS16#
VSS
40
37
50
18
14
AX88190
PCMCIA
10/100BASE MAC
CONTROLLER
103
104
82
91
81
86
93
94
84
87
95
96
90
88
92
85
89
83
98
97
99
100
102
101
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
LVDD
RX_CLK
CRS
COL
RX_DV
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
MEMD[10]
MEMD[11]
MEMD[12]
MEMD[13]
MEMD[14]
MEMD[15]
MEMA[1]
RX_ER
MEMA[2]
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]
MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
MEMA[15]
MEMRD#
MEMWR#
SD[0]
SD[1]
SD[2]
SD[3]
SA[0]
SA[3]
SA[2]
SA[5]
SA[4]
SA[6]
SA[7]
SA[9]
SA[8]
IREQ#
WE#
IORD#
IOWR#
OE#
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[6]
SD[4]
SD[5]
SD[7]
WAIT#
RESET
INPACK#
CE2#
CE1#
TXD[0]
TXD[1]
TXD[2]
TXD[3]
XTALOUT
EEDI
EEDO
EECK
EECS
STSCHG#
SPKR#
REG#
LVDD
LVDD
VSS
VSS
VSS
VSS
HVDD
VSS
64
CLKO25M
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2.0 Signal Description
The following terms describe the AX88190 pin-out:
All pin names with the “#” suffix are asserted low.
The following abbreviations are used in following Tables.
IInput PU Pull Up
OOutput PD Pull Down
I/O Input/Output PPower Pin
OD Open Drain
2.1 PCMCIA Bus Interface Signals Group
SIGNAL TYPE PIN NO. DESCRIPTION
SA[9:0] I10 – 1 System Address : Signals SA[9:0] are address bus input lines which
enable direct address of up to 64K memory and I/O spaces on card.
SD[15:0] I/O 20 – 23,
25 – 38,
30 – 33,
35 – 38
System Data Bus : Signals SD[15:0] constitute the bi-directional data
bus.
IREQ# O12 Interrupt Request : IREQ# is asserted to indicate the host system that
the PC Card device requires host software service.
WAIT# O125 Wait : This signal is set low to insert wait states during Remote DMA
transfer.
REG# I123 Attribute Memory and I/O Space Select : When the REG# signal is
asserted, access is limited to Attribute Memory and to the I/O space.
IORD# I15 I/O Read : The host asserts IORD# to read data from AX88190 I/O
space.
IOWR# I14 I/O Write : The host asserts IOWR# to write data into AX88190 I/O
space.
OE# I16 Output Enable : The OE# line is used to gate Memory Read data from
memory on PC Card
WE# I13 Write Enable : The WE# signal is used for strobing Memory Write
data into the memory on PC Card.
IOIS16# O120 I/O is 16 Bit Port : The IOIS16# is asserted when the address at the
socket corresponds to an I/O address to which the card responds, and
the I/O port addressed is capable of 16-bit access.
INPACK# O124 Input Port Acknowledge : The signal is asserted when the AX88190 is
selected and can respond to and I/O read cycle at the address on the
address bus.
CE1#-CE2#I18, 17 Card Enable : The CE1# enables even numbered address bytes and
CE2# enables odd numbered address bytes
BVD1_STSCHG# O121 Battery Voltage Detect 1 / Status Change
BVD2_SPKR# O122 Battery Voltage Detect 2 / Audio speaker out
Tab - 1 PCMCIA bus interface signals group
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2.2 EEPROM Signals Group
SIGNAL TYPE PIN NO. DESCRIPTION
EECS O106 EEPROM Chip Select : EEPROM chip select signal.
EECK O107 EEPROM Clock : Signal connected to EEPROM clock pin.
EEDI O108 EEPROM Data In : Signal connected to EEPROM data input pin.
EEDO I/PU 109 EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab - 2 EEPROM bus interface signals group
2.3 MII interface signals group
SIGNAL TYPE PIN NO. DESCRIPTION
RXD[3:0] I90 – 87 Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
CRS I85 Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
RX_DV I83 Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
RX_ER I82 Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
RX_CLK I86 Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
COL I84 Collision : this signal is driven by PHY when collision is detected.
TX_EN O95 Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
TXD[3:0] O99 – 96 Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
TX_CLK I94 Collision : this signal is driven by PHY when collision is detected.
MDC O92 Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
MDIO I/O/PU 91 Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
Tab - 3 MII interface signals group
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2.4 Modem interface pins group
Signal Name Type Pin No. Description
MRDY I/PU 118 Modem Ready : MRDY low indicates that modem is initializing the
modem after reset signal asserted or the modem is at SLEEP/STOP
mode.
MRESET#O117 Modem Reset :This signal asserts low to reset the modem chipset.
MDCS#O111 Modem Chip Select : This signal connected to modem chip select pin.
MPWDN O116 Modem Power Down : Rockwell modem chipset, this signal asserts
low to let modem chipset into power down mode. AT&T modem
chipset, this signal asserts high to let modem chipset into power down
mode.
MINT I/PD 112 Modem Interrupt : This signal driven by modem chipset to active
interrupt.
MRIN# I/PU 115 Ring Input :This signal is driven by DAA’s ring detect circuit. When
a telephone ringing signal is being received.
MAUDIO I/PD 113 Modem Audio : This signal is passed to PCMCIA interface via SPKR.
Tab - 4 Modem interface signals group
2.5 SRAM Interface pins group
SIGNAL TYPE PIN NO. DESCRIPTION
MEMA[15:1] O43, 45 – 48,
50 –53’
55 – 58,
60 – 61
SRAM Address :
MEMD[15:0] I/O/PU 62 – 63,
65 – 68,
70 – 74,
76 – 80
SRAM Data :
MEMRD#O42 SRAM Read
MEMWR#O41 SRAM Write
Tab - 5 SRAM Interface pins group
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2.6 Miscellaneous pins group
SIGNAL TYPE PIN NO. DESCRIPTION
LCLK/XTALIN I103 CMOS Local Clock : A 25Mhz clock, +/- 100 ppm, 40%-60% duty
cycle.
Crystal Oscillator Input : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT.
XTALOUT O104 Crystal Oscillator Output : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
CLKO25M O101 Clock Output 25MHz : This clock is source from LCLK/XTALIN.
PPWDN O114 Phy Power Down : This pin connects to PHY chip power down mode
control input.
RESET I/PD 127 Reset
Reset is active high then place AX88190 into reset mode immediately.
During Falling edge the AX88190 loads the EEPROM data.
LVDD P44, 54,
100, 110,
126, 128
Power Supply : +3.3V DC.
HVDD P19, 29, 64,
75 Power Supply : +5V DC.
Note : for pure 3.3V single power solution, all the HVDD pin can
connect to +3.3V. Care should be taken that HVDD input power must
be greater or equal ( > = ) than LVDD.
VSS P11, 24, 34,
39, 40, 49,
59, 69, 81,
93, 102, 105,
119
Power Supply : +0V DC or Ground Power.
Tab - 6 Miscellaneous pins group
2.7 Power on configuration setup signals cross reference table
Signal Name Share with Description
EEPROM SIZE MEMD[6] EEPROM SIZE = 0 : Test mode.
EEPROM SIZE = 1 : Normal operation. (Default)
MPD_SET MEMD[5] MPD_SET = 0 : MPWDN pin active high.
MPD_SET = 1 : MPWDN pin active low.
PPD_SET MEMD[4] PPD_SET = 0 : PPWDN pin active high.
PPD_SET = 1 : PPWDN pin active low.
TEST MEMD[3] TEST = 0 : Test mode.
TEST = 1 : Normal operation. (Default)
All of the above signals are pull-up for default values.
Tab - 7 Power on Configuration Setup Table
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3.0 Memory and I/O Mapping
There are four memory or I/O mapping used in AX88190.
1. EEPROM Memory Mapping
2. Attribute Memory Mapping
3. I/O Mapping
4. Local Memory Mapping
3.1 EEPROM Memory Mapping
EEPROM OFFSET HIGH BYTE LOW BYTE
00H RESERVED WORD COUNT
01H CFH CFL
02H NODE-ID1 NODE ID 0
03H NODE ID 3 NODE ID 2
04H NODE ID 5 NODE ID 4
05H CHECKSUM RESERVED
06H – 10H RESERVED RESERVED
10H – FFH CIS CIS
Tab - 8 EEPROM Memory Mapping
3.2 Attribute Memory Mapping
ATTRIBUTE MEMORY
OFFSET CONTENTS
0000H
03BFH CIS
03C0H LCOR
03C2H LCCSR
03C4H -
03C6H -
03CAH LIOBASE0
03CCH LIOBASE1
03CEH
03DFH RESERVED
03E0H MCOR
03E2H MCCSR
03E4H -
03E6H -
03EAH MIOBASE0
03ECH MIOBASE1
03EEH
03FFH RESERVED
Tab - 9 Attribute Memory Mapping
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3.3 I/O Mapping
SYSTEM I/O OFFSET FUNCTION
0000H
001FH MAC CORE REGISTER
Tab - 10 I/O Address Mapping
3.4 SRAM Memory Mapping
OFFSET FUNCTION
0000H
03BFH CIS *1
03C0H LCOR *1
03C2H LCCSR *1
03C4H -
03C6H -
03CAH LIOBASE0 *1
03CCH LIOBASE1 *1
03CEH
03DFH RESERVED
03E0H MCOR *1
03E2H MCCSR *1
03E4H -
03E6H -
03EAH MIOBASE0 *1
03ECH MIOBASE1 *1
03EEH
03FFH RESERVED
0400H NODE ID 0
0401H NODE ID 1
0402H NODE ID 2
0403H NODE ID 3
0404H NODE ID 4
0405H NODE ID 5
0406H
07FFH RESERVED
0800H
FFFFH 62K X 8
SRAM BUFFER
Tab - 11 Local Memory Mapping
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4.0 Registers Operation
There are four register sets in AX88190 :
1. The PCMCIA function configuration registers of LAN.
2. The PCMCIA function configuration registers of MODEM.
3. The MAC core register.
4. The special registers.
4.1 PCMCIA Function Configuration Register Set of LAN
REGISTER NAME OFFSET
LCOR CONFIGURATION OPTION REGISTER 3C0H
LCSR CONFIGURATION AND STATUS REGISTER 3C2H
LIOBASE0 I/O BASED REGISTER 0 3CAH
LIOBASE1 I/O BASED REGISTER 1 3CCH
Tab - 12 PCMCIA Function Configuration Register Mapping of LAN
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4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H
(Read/Write)
FIELD R/W/C DESCRIPTION
7R/W Software Reset
Assert this bit will reset the LAN function of AX88190. Return a 0 to this bit will leave the
LAN function of AX88190 in a post-reset state as same as that following a hardware reset.
The value of this bit is 0 at power-on.
6R/W Level IRQ
This bit should be set to 1, the AX88190 always generates Level Mode Interrupt.
5:0 R/W Function Configuration Index
These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.
On multifunction PC Card,
Bit 5, Bit 4 : MODEM I/O base registers
Bit 5 Bit 4 MODEM I/O base
0 0 Decided by MIOBASE registers ( See section 4.2.3 )
0 1 2f8H
1 0 3e8H
1 1 2e8H
Bit 3 : Enable Power Down mode
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will go into power down
mode. At power down mode AX88190 will disable MAC transmitting and receiving
operation. But the host interface will not be affected.
Bit 2 : Enable IREQ# Routing
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will generate interrupt request
via IREQ# signal. If this bit is set to 0, the LAN will not generate interrupt request via
IREQ# line.
Bit 1 : Enable Base and Limit Registers
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified by
the Base and Limit registers are passed to LAN function. If this bit is set to 0,all I/O
addresses are passed to LAN function.
Bit 0 : Enable Function
If this bit is set to 0, the LAN function is disabled.
If this bit is set to 1, the LAN function is enabled.
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4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H
(Read/Write)
FIELD R/W/C DESCRIPTION
7:3 -Reserved
2R/W PPwrDwn : PHY power down setting
While this bit set to 1, PPWDN pin (pin 114) will be active to force PHY chip into power
down mode. As for PPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross reference table.
1RIntr : Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
0RIntrAck : Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH
(Read/Write)
The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to
access the LAN specific registers (MAC Core Registers).
I/O Base Register 0
FIELD R/W/C DESCRIPTION
7:0 R/W Base I/O address bit 7 – 0.
I/O Base Register 1
FIELD R/W/C DESCRIPTION
7:0 R/W Base I/O address bit 15 – 8.
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4.2 PCMCIA Function Configuration Register Set of MODEM
REGISTER NAME OFFSET
MCOR CONFIGURATION OPTION REGISTER 3E0H
MCSR CONFIGURATION AND STATUS REGISTER 3E2H
MIOBASE0 I/O BASED REGISTER 0 3EAH
MIOBASE1 I/O BASED REGISTER 1 3ECH
Tab - 13 PCMCIA Function Configuration Register Mapping of MODEM
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H
(Read/Write)
FIELD R/W/C DESCRIPTION
7R/W Software Reset
Assert this bit will reset the MODEM function of AX88190. Return a 0 to this bit will
leave the MODEM function of AX88190 in a post-reset state as same as that following a
hardware reset. The value of this bit is 0 at power-on.
6R/W Level IRQ
This bit should be set to 1, the AX88190 always generates Level Mode Interrupt.
5:0 R/W Function Configuration Index
These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.
On multifunction PC Card,
Bit 5, Bit4 : Reserved
Bit 3 : IREQ# route to STSCHG#
If bit 0 of MCOR is set to 0, this bit is ignored.
If both bit 0 and bit 2 of MCOR are set to 1 and this bit is set to 1, the MODEM will route
interrupt request to STSCHG# signal. If this bit is set to 0, the MODEM will generate
interrupt request via IREQ# line.
Bit 2 : Enable IREQ# Routing
If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1, the MODEM will generate interrupt
request via IREQ# signal. If this bit is set to 0, the MODEM will not generate interrupt
request via IREQ# line.
Bit 1 : Enable Base and Limit Registers
If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified
by the Base and Limit registers are passed to MODEM function. If this bit is set to 0,all
I/O addresses are passed to LAN function.
Bit 0 : Enable Function
If this bit is set to 0, the MODEM function is disabled.
If this bit is set to 1, the MODEM function is enabled.
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4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H
(Read/Write)
FIELD R/W/C DESCRIPTION
7:3 -Reserved
2R/W MPwrDwn : Modem power down setting
While this bit set to 1, MPWDN pin (pin 116) will be active to force modem chip into power
down mode. As for MPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross reference table.
1RIntr : Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
0RIntrAck : Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH
(Read/Write)
The I/O Base registers (MIOBASE0 and MIOBASE1) determine the base address of the I/O range used to
access the MODEM specific registers.
I/O Base Register 0
FIELD R/W/C DESCRIPTION
7:0 R/W Base I/O address bit 7 – 0.
I/O Base Register 1
FIELD R/W/C DESCRIPTION
7:0 R/W Base I/O address bit 15 – 8.
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4.3 Registers Operation
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the
Command Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET READ WRITE
00H Command Register
( CR ) Command Register
( CR )
01H Page Start Register
( PSTART ) Page Start Register
( PSTART )
02H Page Stop Register
( PSTOP ) Page Stop Register
( PSTOP )
03H Boundary Pointer
( BNRY ) Boundary Pointer
( BNRY )
04H Transmit Status Register
( TSR ) Transmit Page Start Address
( TPSR )
05H Number of Collisions Register
( NCR ) Transmit Byte Count Register 0
( TBCR0 )
06H Current Page Register
( CPR ) Transmit Byte Count Register 1
( TBCR1 )
07H Interrupt Status Register
( ISR ) Interrupt Status Register
( ISR )
08H Current Remote DMA Address 0
( CRDA0 ) Remote Start Address Register 0
( RSAR0 )
09H Current Remote DMA Address 1
( CRDA1 ) Remote Start Address Register 1
( RSAR1 )
0AH Reserved Remote Byte Count 0
( RBCR0 )
0BH Reserved Remote Byte Count 1
( RBCR1 0
0CH Receive Status Register
( RSR ) Receive Configuration Register
( RCR )
0DH Frame Alignment Errors
( CNTR0 ) Transmit Configuration Register ( TCR )
0EH CRC Errors
( CNTR1 ) Data Configuration Register
( DCR )
0FH Missed Packet Errors
( CNTR2 ) Interrupt Mask Register
( IMR )
10H
11H Data Port Data Port
12H IFGS1 IFGS1
13H IFGS2 IFGS2
14H MII/EEPROM Access MII/EEPROM Access
15H -Test Register
16H Inter-frame Gap (IFG)Inter-frame Gap (IFG)
17H
to
1EH
Reserved Reserved
1FH Reset Reset
Tab - 14 Page 0 of MAC Core Registers Mapping
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PAGE 1 (PS1=0,PS0=1)
OFFSET READ WRITE
00H Command Register
( CR ) Command Register
( CR )
01H Physical Address Register 0
( PARA0 ) Physical Address Register 0
( PAR0 )
02H Physical Address Register 1
( PARA1 ) Physical Address Register 1
( PAR1 )
03H Physical Address Register 2
( PARA2 ) Physical Address Register 2
( PAR2 )
04H Physical Address Register 3
( PARA3 ) Physical Address Register 3
( PAR3 )
05H Physical Address Register 4
( PARA4 ) Physical Address Register 4
( PAR4 )
06H Physical Address Register 5
( PARA5 ) Physical Address Register 5
( PAR5 )
07H Current Page Register
( CPR ) Current Page Register
( CPR )
08H Multicast Address Register 0
( MAR0 ) Multicast Address Register 0
( MAR0 )
09H Multicast Address Register 1
( MAR1 ) Multicast Address Register 1
( MAR1 )
0AH Multicast Address Register 2
( MAR2 ) Multicast Address Register 2
( MAR2 )
0BH Multicast Address Register 3
( MAR3 ) Multicast Address Register 3
( MAR3 )
0CH Multicast Address Register 4
( MAR4 ) Multicast Address Register 4
( MAR4 )
0DH Multicast Address Register 5
( MAR5 ) Multicast Address Register 5
( MAR5 )
0EH Multicast Address Register 6
( MAR6 ) Multicast Address Register 6
( MAR6 )
0FH Multicast Address Register 7
( MAR7 ) Multicast Address Register 7
( MAR7 )
10H
11H Data Port Data Port
12H Inter-frame Gap Segment 1
IFGS1 Inter-frame Gap Segment 1
IFGS1
13H Inter-frame Gap Segment 2
IFGS2 Inter-frame Gap Segment 2
IFGS2
14H MII/EEPROM Access MII/EEPROM Access
15H -Test Register
16H Inter-frame Gap (IFG)Inter-frame Gap (IFG)
17H
to
1EH
Reserved Reserved
1FH Reset Reset
Tab - 15 Page 1 of MAC Core Registers Mapping
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4.3.1 Command Register (CR) Offset 00H (Read/Write)
FIELD NAME DESCRIPTION
7:6 PS1,PS0 PS1,PS0 : Page Select
The two bit selects which register page is to be accessed.
PS1 PS0
0 0 page 0
0 1 page 1
5:3 RD2,RD1
,RD0 RD2,RD1,RD0 : Remote DMA Command
These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88195 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address are not restored to the starting address if the
Remote DMA is aborted.
RD2 RD1 RD0
0 0 0 Not allowed
0 0 1 Remote Read
0 1 0 Remote Write
0 1 1 Not allowed
1 X X Abort / Complete Remote DMA
2TXP TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
1START START :
This bit is used to active AX88195 operation.
0STOP STOP : Stop AX88195
This bit is used to stop the AX88195 operation.
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD NAME DESCRIPTION
7RST Reset Status :
Set when AX88195 enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.
6RDC Remote DMA Complete
Set when remote DMA operation has been completed
5 CNT Counter Overflow
Set when MSB of one or more of the Tally Counters has been set.
4OVW OVERWRITE : Set when receive buffer ring storage resources have been exhausted.
3TXE Transmit Error
Set when packet transmitted with one or more of the following errors
n Excessive collisions
n FIFO Under-run
2RXE Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
1PTX Packet Transmitted
Indicates packet transmitted with no error
0PRX Packet Received
Indicates packet received with no error.
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4.3.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD NAME DESCRIPTION
7-Reserved
6RDCE DMA Complete Interrupt Enable. Default “low” disabled.
5CNTE Counter Overflow Interrupt Enable. Default “low” disabled.
4OVWE Overwrite Interrupt Enable. Default “low” disabled.
3TXEE Transmit Error Interrupt Enable. Default “low” disabled.
2RXEE Receive Error Interrupt Enable. Default “low” disabled.
1 PTXE Packet Transmitted Interrupt Enable. Default “low” disabled.
0PRXE Packet Received Interrupt Enable. Default “low” disabled.
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD NAME DESCRIPTION
7RDCR Remote DMA always completed
6:2 -Reserved
1BOS Byte Order Select
0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80X86).
1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(68K)
0WTS Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD NAME DESCRIPTION
7FDU Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
6PD Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
5RLO Retry of late collision
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
4:3 -Reserved
2:1 LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode 0 0 0 Normal operation
Mode 1 0 1 Internal NIC loop-back
Mode 2 1 0 PHYcevisor loop-back
0CRC Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
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4.3.6 Transmit Status Register (TSR) Offset 04H (Read)
FIELD NAME DESCRIPTION
7OWC Out of window collision
6:4 -Reserved
3ABT Transmit Aborted
Indicates the AX88195 aborted transmission because of excessive collision.
2COL Transmit Collided
Indicates that the transmission collided at least once with another station on the network.
1-Reserved
0PTX Packet Transmitted
Indicates transmission without error.
4.3.7 Receive Configuration (RCR) Offset 0CH (Write)
FIELD NAME DESCRIPTION
7-Reserved
6INTT Interrupt Trigger Mode
Must be setting to “1”.
5MON Monitor Mode
0 : Normal Operation
1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not
buffered into memory.
4PRO PRO : Promiscuous Mode
Enable the receiver to accept all packets with a physical address.
3AM AM : Accept All Multicast
Enable the receiver to accept all packets with a multicast address.
2AB AB : Accept Broadcast
Enable the receiver to accept broadcast packet.
1AR AR : Accept Runt
Enable the receiver to accept runt packet.
0SEP SEP : Save Error Packet
Enable the receiver to accept and save packets with error.
4.3.8 Receive Status Register (RSR) Offset 0CH (Read)
FIELD NAME DESCRIPTION
7-Reserved
6DIS Receiver Disabled
5PHY Multicast Address Received.
4MPA Missed Packet
3FO FIFO Overrun
2FAE Frame alignment error.
1CR CRC error.
0PRX Packet Received Intact
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD NAME DESCRIPTION
7-Reserved
6:0 IFG Inter-frame Gap. Default value 15H.
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4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD NAME DESCRIPTION
7-Reserved
6:0 IFG Inter-frame Gap Segment 1. Default value 1cH.
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD NAME DESCRIPTION
7-Reserved
6:0 IFG Inter-frame Gap Segment 2. Default value 11H.
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H
(Read/Write)
FIELD NAME DESCRIPTION
7EECLK EECLK
EEPROM Clock
6EEO EEO
EEPROM Data Out
5EEI EEI
EEPROM Data In
4EECS EECS
EEPROM Chip Select
3MDO MDO
MII Data Out
2MDI MDI
MII Data In
1MDIR MII STA MDIO signal Direction
MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit
let MDIO as output signal.
0MDC MDC
MII Clock
4.3.13 Test Register (TR) Offset 15H (Write)
FIELD NAME DESCRIPTION
7:5 -Reserved
4TF16T Test for Collision
3TPE Test pin Enable
2:0 IFG Select Test Pins Output
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5.0 PCMCIA Device Access Functions
The AX88190 , as a PCMCIA I/O device , needs support both Attribute Memory access function
and I/O access function. The Access methods are described as the following sections.
5.1 Attribute Memory access function functions.
Attribute Memory Read function
Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode XHHX X X High-Z High-Z
Byte Access (8 bits) L
LH
HL
LL
HL
LH
HHigh-Z
High-Z Even-Byte
Not Valid
Word Access (16 bits) L L L XLHNot Valid Even-Byte
Odd Byte Only Access L L HXLHNot Valid High-Z
Attribute Memory Write function
Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode XHHX X X X X
Byte Access (8 bits) L
LH
HL
LL
HH
HL
LX
XEven-Byte
X
Word Access (16 bits) L L L XHLXEven-Byte
Odd Byte Only Access L L HXHLX X
5.2 I/O access function functions.
I/O Read function
Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode XHHX X X High-Z High-Z
Byte Access (8 bits) L
LH
HL
LL
HL
LH
HHigh-Z
High-Z Even-Byte
Odd-Byte
Word Access (16 bits) L L L L L HOdd-Byte Even-Byte
I/O Inhibit HX X X LHHigh-Z High-Z
Odd Byte Only Access L L HXLHOdd-Byte High-Z
I/O Write function
Function Mode REG# CE2# CE1# SA0 IORD# IOWR# SD[15:8] SD[7:0]
Standby Mode XHHX X X X X
Byte Access (8 bits) L
LH
HL
LL
HH
HL
LX
XEven-Byte
Odd-Byte
Word Access (16 bits) L L L L HLOdd-Byte Even-Byte
I/O Inhibit HXXXHLX X
Odd Byte Only Access L L HXHLOdd-Byte X
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6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description SYM Min Max Units
Operating Temperature Ta 0+85 °C
Storage Temperature Ts -55 +150 °C
Supply Voltage HVdd -0.3 +6 V
Supply Voltage LVdd -0.3 +4.6 V
Input Voltage HVin
LVin -0.3
-0.3 HVdd+0.5
LVdd+0.5 V
V
Output Voltage HVout
LVin -0.3
-0.3 HVdd+0.5
LVdd+0.5 V
V
Lead Temperature (soldering 10 seconds maximum) Tl -55 +220 °C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.2 General Operation Conditions
Description SYM Min Tpy Max Units
Operating Temperature Ta 0 25 +75 °C
Supply Voltage HVdd
LVdd +4.75V
+2.70
+3.00
+5.00V
+3.00
+3.30
+5.25V
+3.30
+3.60
V
V
V
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.3 DC Characteristics
(Vdd=5.0V, Vss=0V, Ta=0°C to 75°C)
Description SYM Min Tpy Max Units
Low Input Voltage Vil -0.8 V
High Input Voltage Vih 2-V
Low Output Voltage Vol -0.4 V
High Output Voltage Voh Vdd-0.4 -V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -1 +1 uA
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 75°C)
Description SYM Min Tpy Max Units
Low Input Voltage Vil -0.8 V
High Input Voltage Vih 1.9 -V
Low Output Voltage Vol -0.4 V
High Output Voltage Voh Vdd-0.4 -V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -1 +1 uA
Description SYM Min Tpy Max Units
Power Consumption (Dual power) DPt5v
DPt3v 22
40 mA
mA
Power Consumption (Single power 3.3V) SPt3v TBD mA
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6.4 A.C. Timing Characteristics
6.4.1 XTAL / CLOCK
LCLK/XTALIN
Tr Tf Tlow
CLK25M Tod
Symbol Description Min Typ. Max Units
Tcyc CYCLE TIME 40 ns
Thigh CLK HIGH TIME 16 20 24 ns
Tlow CLK LOW TIME 16 20 24 ns
Tr/TfCLK SLEW RATE 1-4ns
Tod LCLK/XTALIN TO CLK25M OUT DELAY 10
6.4.2 Reset Timing
LCLK
RESET
Symbol Description Min Typ. Max Units
Trst Reset pulse width 100 - - LClk
Tcyc
Thigh
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6.4.3 Attribute Memory Read Timing
TcR
Ta(A) Th(A)
A[9:0], REG#
Ta(CE) Tv(A)
Tsu(CE)
CE#
Tsu(A) Ta(OE) Th(CE)
OE#
Tv(WT-OE) Tw(WT) Tdis(CE)
WAIT#
Ten(OE) Tv(WT) Tdis(OE)
D[15:0] DATA Valid
Symbol Description Min Typ. Max Units
TcR READ CYCLE TIME 300 - - ns
Ta(A) ADDRESS ACCESS TIME - - 120 ns
Ta(CE) CARD ENABLE ACCESS TIME - - 100 ns
Ta(OE) OUTPUT ENABLE ACCESS TIME - - 100 ns
Tdis(OE) OUTPUT DISABLE TIME FROM OE# 0.5 - - ns
Ten(OE) OUTPUT ENABLE TIME FROM OE# - - 100 ns
Tv(A) DATA VALID FROM ADDRESS CHANGE 0- - ns
Tsu(A) ADDRESS SETUP TIME 30 - - ns
Th(A) ADDRESS HOLD TIME 20 - - ns
Tsu(CE) CARD ENABLE SETUP TIME 0- - ns
Th(CE) CARD ENABLE HOLD TIME 20 - - ns
Tv(WT-OE) WAIT# VALID FROM OE# - - 10 ns
Tw(WT) WAIT# PULSE WIDTH - - 200 ns
Tv(WT) DATA SETUP FOR WAIT# RELEASED 100 - - ns
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6.4.4 Attribute Memory Write Timing
TcW
A[9:0], REG#
Tsu(CE-WEH)
CE# Tsu(CE)
Tsu(A-WEH) Th(CE)
OE#
Tsu(A) Tw(WE) Trec(WE)
WE#
Tv(WT-WE) Tv(WT)
Tw(WT) Th(OE-WE)
WAIT#
Tsu(OE-WE) Tsu(D-WEH) Th(D)
D[15:0](Din) DATA Input Establish
Tdis(WE) Ten(OE)
Tdis(OE) Ten(WE)
D[15:0](Dout)
Symbol Description Min Typ. Max Units
TcW WRITE CYCLE TIME 250 - - ns
Tw(WE) WRITE PULSE WIDTH 150 - - ns
Tsu(A) ADDRESS SETUP TIME 30 - - ns
Tsu(A-WEH) ADDRESS SETUP TIME FOR WE# 180 - - ns
Tsu(CE-WEH) CARD ENABLE SETUP TIME FOR WE# 180 - - ns
Tsu(D-WEH) DATA SETUP TIME FOR WE# 80 - - ns
Th(D) DATA HOLD TIME 30 - - ns
Trec(WE) WRITE RECOVER TIME 30 - - ns
Tdis(WE) OUTPUT DISABLE TIME FROM WE# - - 5ns
Tdis(OE) OUTPUT DISABLE TIME FROM OE# - - 5ns
Ten(WE) OUTPUT ENABLE TIME FROM WE# 5- - ns
Ten(OE) OUTPUT ENABLE TIME FROM OE# 5- - ns
Tsu(OE-WE) OUTPUT ENABLE SETUP TIME FROM OE# 10 - - ns
Th(OE-WE) OUTPUT ENABLE HOLD TIME FROM OE# 10 - - ns
Tsu(CE) CARD ENABLE SETUP TIME 0- - ns
Th(CE) CARD ENABLE HOLD TIME 20 - - ns
Tv(WT-WE) WAIT# VALID FROM WE# - - 15 ns
Tw(WT) WAIT# PULSE WIDTH - - 200 ns
Tv(WT) WE# HIGH FROM WAIT# RELEASED 0- - ns
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6.4.5 I/O Read Timing
A[9:0]
ThA
TsuREG ThREG
REG#
TsuCE ThCE
CE#
Tw
IORD#
TsuA TdrINPACK
INPACK#
TdfINPACK TdrIOIS16
IOIS16#
TdfIOIS16 Td Tdr(WT)
WAIT#
TdfWT Tw(WT) Th
D[15:0] DATA Valid
Symbol Description Min Typ. Max Units
TdDATA DELAY AFTER IORD# - - 50 ns
ThDATA HOLD FOLLOWING IORD# 0.5 - - ns
TwIORD# WIDTH TIME 165 - - ns
TsuA ADDRESS SETUP BEFORE IORD# 70 - - ns
ThA ADDRESS HOLD BEFORE IORD# 20 - - ns
TsuCE CE# SETUP BEFORE IORD# 5- - ns
ThCE CE# HOLD BEFORE IORD# 20 - - ns
TsuREG REG# SETUP BEFORE IORD# 5- - ns
ThREG REG# HOLD BEFORE IORD# 0- - ns
TdfINPACK INPACK# DELAY FALLING FROM IORD# 0-10 ns
TdrINPACK INPACK# DELAY RISING FROM IORD# - - 10 ns
TdfIOIS16 IOIS16# DELAY FALLING FROM ADDRESS* - - 10 ns
TdrIOIS16 IOIS16# DELAY RISING FROM ADDRESS* - - 0ns
TdfWT WAIT# DELAY FALLING FROM IORD# - - 5ns
Tdr(WT) DATA DELAY FROM WAIT# RISING - - 0us
Tw(WT) WAIT# WIDTH TIME - - 100 ns
* Note : The address includes REG# and CE1# signal
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6.4.6 I/O Write Timing
A[9:0]
ThA
TsuREG ThREG
REG#
TsuCE ThCE
CE#
Tw
IOWR#
TsuA TdrIOIS16
IOIS16#
TdfIOIS16 TdrIOWR
WAIT#
TdfWT Tw(WT) Th
Tsu
D[15:0] DATA
Symbol Description Min Typ. Max Units
Tsu DATA SETUP BEFORE IOWR# 60 - - ns
ThDATA HOLD FOLLOWING IOWR# 30 - - ns
TwIOWR# WIDTH TIME 165 - - ns
TsuA ADDRESS SETUP BEFORE IOWR# 70 - - ns
ThA ADDRESS HOLD BEFORE IOWR# 20 - - ns
TsuCE CE# SETUP BEFORE IOWR# 5- - ns
ThCE CE# HOLD BEFORE IOWR# 20 - - ns
TsuREG REG# SETUP BEFORE IOWR# 5- - ns
ThREG REG# HOLD BEFORE IOWR# 0- - ns
TdfIOIS16 IOIS16# DELAY FALLING FROM ADDRESS* - - 10 ns
TdrIOIS16 IOIS16# DELAY RISING FROM ADDRESS* - - 0ns
TdfWT WAIT# DELAY FALLING FROM IOWR# - - ** ns
Tw(WT) WAIT# WIDTH TIME - - ** ns
TdrIOWR IOWR# HIGH FROM WAIT# HIGH 0- - us
*Note : The address includes REG# and CE1# signal
** Note : There is no wait state while I/O Write operation
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6.4.7 MII Timing
Ttclk Ttch Ttcl
TXCLK
Ttv Tth
TXD<3:0>
TXEN
Trclk Trch Trcl
RXCLK
Trs Trh
RXD<3:0>
RXDV
Trs1
RXER
Symbol Description Min Typ. Max Units
Ttclk Cycle time(100Mbps) -40 -ns
Ttclk Cycle time(10Mbps) -400 -ns
Ttch high time(100Mbps) 14 -26 ns
Ttch high time(10Mbps) 140 -260 ns
Trch low time(100Mbps) 14 -26 ns
Trch low time(10Mbps) 140 -260 ns
Ttv Clock to data valid - - 20 ns
Tth Data output hold time 5- - ns
Trclk Cycle time(100Mbps) -40 -ns
Trclk Cycle time(10Mbps) -400 -ns
Trch high time(100Mbps) 14 -26 ns
Trch high time(10Mbps) 140 -260 ns
Trcl low time(100Mbps) 14 -26 ns
Trcl low time(10Mbps) 140 -260 ns
Trs data setup time 6- - ns
Trh data hold time 10 - - ns
Trs1 RXER data setup time 10 - - ns
AX88190 PRELIMINARY
ASIX ELECTRONICS CORPORATION
33
CONFIDENTIAL
7.0 Package Information
be
D
Hd
E
He
pin 1
A2 A1
L
L1
θ
A
MILIMETERSYMBOL
MIN. NOM MAX
A1 0.1
A2 1.3 1.4 1.5
A1.7
b0.155 0.16 0.26
D13.90 14.00 14.10
E13.90 14.00 14.10
e0.40
Hd 15.60 16.00 16.40
He 15.60 16.00 16.40
L0.30 0.50 0.70
L1 1.00
θ0 10
AX88190 PRELIMINARY
ASIX ELECTRONICS CORPORATION
34
CONFIDENTIAL
Appendix A: Application Note 1
A.1 Using Crystal
AX88190 To PHY
CLKO25M
XTALIN XTALOUT
25MHz
Crystal
8pf 2Mohm 8pf
Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing,
please refer to the suggest circuit provided by crystal supplier.
A.2 Using Oscillator
AX88190 To PHY
CLKO25M
XTALIN XTALOUT
NC
3.3V Power OSC 25MHz
AX88190 PRELIMINARY
ASIX ELECTRONICS CORPORATION
35
CONFIDENTIAL
A.3 Dual power (5V and 3.3V) application
+5V +5V
+3.3V
(option for core logic)
+5V HVdd +5V
+3.3V LVdd +5V
A.4 Single power (3.3V) application
+3.3V +3.3V
+3.3V HVdd +3.3V
+3.3V LVdd +3.3V
AX88190
PHY/TxRxMODEM
DAA
MAGNETIC
RJ45RJ11
+5V PCMCIA I/F
EEPROM
SRAM
AX88190
PHY/TxRxMODEM
DAA
MAGNETIC
RJ45RJ11
+3.3V PCMCIA I/F
EEPROM
SRAM
AX88190 PRELIMINARY
ASIX ELECTRONICS CORPORATION
36
CONFIDENTIAL
Appendix B: Application Note 2
B.1 Advance Application for Using Crystal
Date: May 21, 1999
Condition: In short cable, AX88190 +AH 101 Phyceiver can’t link to BCM 5308
Switch.
Conclusion: 1. After measuring and verifying, we found it’s relevant to clock source.
2. We ascertain the problem is caused by matching issues between
crystal and capacitor.
Solution: Change the value of capacitors beside crystal as below:
Note: The capacitors may be various depend on the specification of crystal. While
designing, please refer to the circuit provided by crystal supplier.
XIN XOUT
Y1
25MHZ
C22
18p C23
18p
R4
2M
AX88190 PRELIMINARY
ASIX ELECTRONICS CORPORATION
37
CONFIDENTIAL
Errata of AX88190 V1
1. OE# synchronous problem result in PC hang
Solution : Using hardware CKT to pre-sync OE# signal as below.
2. Interrupt Status can’t always clean up
Solution : Using software to do clean and check iteration until clean up.
Ex : IOBASE=300 ; Clear Tx/Rx interrupt.
Mov dx,307h
ClrISR : Mov al,3 ; clear Tx/Rx interrupt
Out dx,al ; output to clear ISR
In al,dx ; read ISR
Test al,3 ; Check ISR cleared or not
Jz ClrISRDone ; Clear ok
Mov al,0 ; if not, clear again
Out dx,al
Jmp ClrISR
ClrISRDone: …; clear successful
3. CE1# Bus decoder problem
Solution : Dis-connect AX88190 CE1# (pin 18) from PCMCIA connector CE1#
(pin 7). And connect AX88190 CE1# (pin 18) to logic “0” always
enable this signal.
From PCMCIA
Connector
Pin 9
From AX88190
Pin 101
To AX88190
Pin 16
Jumper for future use
CLK25M
OE_# OE_M#
U1B
74F74
D
12
CLK
11 Q9
Q8
PR 10
CL
13
U1A
74F74
D
2
CLK
3Q5
Q6
PR 4
CL
1
U2A
74F86
1
23
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
AX88190
PCMCIA Fast Ethernet MAC Controller
ASIX
190LU1A.SCH 1.0
PCMCIA BUS & AX88190 & MEMORY
ASIX ELECTRONICS CORPORATION
B
1 3Tuesday, December 15, 1998
Title
Size Document Number Rev
Date: Sheet of
RXD3
RXD2
RXD1
RXD0
CRS
COL
RXDV
RXER
MDC
MDIO
TXEN
TXD0
TXD1
TXD2
TXD3
VDD
GND
RESET#
PCLK
TXCLK
RXCLK
|LINK
(OPTION FOR TEST)
(AX88190 APPLICATION USED LUC6612)
|190LU1A1.SCH
MEMRD# MA11
MA12 GND
MA10 MD15
MA9 MD14
MA14 MD13
GND GND SA0 LVDD MEMWR# MD12
SD3 GND SA1 RESET VDD MD11
SD4 SD11 SA2 LVDD MA15 GND
SD5 SD12 SA3 WAIT# MA13 MD10
SD6 SD13 SA4 INPACK# MA8 MD9
SD7 SD14 SA5 REG# MA7 MD8
SD15 SA6 SPKR# MA6 MA1
CE2# SA7 STSCHG# MA5 MA2
OE# SA8 IOIS16# MA4 MA3
IORD# SA9 GND
SA9 IOWR# GND
SA8 IREQ#
WE#
IOWR# MEMRD# MA11
WE# IORD# MA12 GND
IREQ# OE_M# MA10 MD7
VDD VDD CE2# MA9 MD6
MA14 MD5
VDD LVDD MEMWR# MD4
SD15 EEDO VDD MD3
SD14 EEDI MA15 GND
SA7 SD13 EESK MA13 MD2
SA6 SD12 EECS MA8 MD1
SA5 RESET GND GND MA7 MD0
SA4 WAIT# SD11 XOUTMA6 MA1
SA3 INPACK# SD10 XIN MA5 MA2
SA2 REG# SD9 GND MA4 MA3
SA1 SPKR# SD8
SA0 STSCHG# VDD LVDD
SD0 SD8 SD7
SD1 SD9 SD6
SD2 SD10 SD5
IOIS16# GND
GND GND SD4
GND
SD3
SD2 GND
SD1
SD0
GND
GND
MEMWR#
MEMRD# PCLK
EECS VDD MA15
EESK LVDD
EEDI MA14
EEDO GND MA13
MA12
MA11 GND
GND MD0
MA10 MD1
MA9 MD2
MA8 MD3
MA7 MD4
LVDD VDD
XIN XOUTMA6 MD5
MA5 MD6
MA4 MD7 OE# OE_M#
MA3 MD8
GND MD9
MA2 GND
MA1 MD10
MD15 MD11
MD14 MD12
VDD MD13
VDD
VDD LVDD GND
GND LVDD
GND
U1
PCMCIA
GND
1
D3
2
D4
3
D5
4
D6
5
D7
6
CE1#
7
A10
8
OE#
9
A11
10
A9
11
A8
12
A13
13
A14
14
WE#
15
IREQ#
16
VCC
17
VPP1
18
A16
19
A15
20
A12
21
A7
22
A6
23
A5
24
A4
25
A3
26
A2
27
A1
28
A0
29
D0
30
D1
31
D2
32
IOIS16#
33
GND
34
GND 35
CD1# 36
D11 37
D12 38
D13 39
D14 40
D15 41
CE2# 42
VS1# 43
IORD# 44
IOWR# 45
A17 46
A18 47
A19 48
A20 49
A21 50
VCC 51
VPP2 52
A22 53
A23 54
A24 55
A25 56
VS2# 57
RESET 58
WAIT# 59
INPACK# 60
REG# 61
SPKR# 62
STSCHG# 63
D8 64
D9 65
D10 66
CD2# 67
GND 68
U2
AX88190
SA[0]
1
SA[1]
2
SA[2]
3
SA[3]
4
SA[4]
5
SA[5]
6
SA[6]
7
SA[7]
8
SA[8]
9
SA[9]
10
VSS
11
IREQ#
12
WE#
13
IOWR#
14
IORD#
15
OE#
16
CE2#
17
CE1#
18
HVDD
19
SD[15]
20
SD[14]
21
SD[13]
22
SD[12]
23
VSS
24
SD[11]
25
SD[10]
26
SD[9]
27
SD[8]
28
HVDD
29
SD[7]
30
SD[6]
31
SD[5]
32
SD[4]
33
VSS
34
SD[3]
35
SD[2]
36
SD[1]
37
SD[0]
38
VSS
39
VSS
40
MEMWR#
41
MEMRD#
42
LVDD
44
MEMA[14]
45
MEMA[13]
46
MEMA[12]
47
MEMA[11]
48
MEMA[10]
50
MEMA[9]
51
MEMA[8]
52
MEMA[7]
53
LVDD
54
MEMA[6]
55
MEMA[5]
56
MEMA[4]
57
MEMA[3]
58
VSS
59
MEMA[2]
60
MEMA[1]
61
MEMD[15]
62
MEMD[14]
63
HVDD
64
MEMA[15]
43
VSS
49
MEMD[13] 65
MEMD[12] 66
MEMD[11] 67
MEMD[11] 68
VSS 69
MEMD[9] 70
MEMD[8] 71
MEMD[7] 72
MEMD[6] 73
MEMD[5] 74
HVDD 75
MEMD[4] 76
MEMD[3] 77
MEMD[2] 78
MEMD[1] 79
MEMD[0] 80
VSS 81
RX_ER 82
COL 84
CRS 85
RX_CLK 86
RXD[0] 87
RXD[1] 88
RXD[2] 89
RXD[3] 90
MDIO 91
MDC 92
VSS 93
TX_CLK 94
TX_EN 95
TXD[0] 96
TXD[1] 97
TXD[2] 98
TXD[3] 99
LVDD 100
CLKO25M 101
VSS 102
LCLK/XTALIN 103
XTALOUT 104
VSS 105
EECS 106
LVDD 128
RESET 127
LVDD 126
WAIT# 125
INPACK# 124
REG# 123
SPKR# 122
STSCHG# 121
IOIS16# 120
VSS 119
MRDY 118
MRESET# 117
MPWDN 116
MRIN# 115
PPWDN 114
MAUDIO 113
MINT 112
MDCS# 111
LVDD 110
EEDO 109
EEDI 108
EECK 107
RX_DV 83
C1
4.7u/16V
+
C2
4.7u/16V
+
Y1
25MHZ
R1
10K
C3
0.01u
C4
0.01u
C5
0.01u
C6
0.1u
C7
0.1u
C8
0.1u
C9
0.1u
C10
0.1u
C11
0.1u
C12
4.7u/16V
+
C13
0.01u
C14
0.1u
C15
0.1u
C16
0.1u
C17
0.1u
C18
0.1u
C19
0.1u
C20
4.7u/16V
+
R2
20 C21
8p
U4
IS61C256AH
#OE
22
A11
23
A9
24
A8
25
A13
26
#WE
27
VCC
28
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A10 21
#CE 20
I/O7 19
I/O6 18
I/O5 17
I/O4 16
I/O3 15
GND 14
I/O2 13
I/O1 12
I/O0 11
A0 10
A1 9
A2 8
U5
IS61C256AH
#OE
22
A11
23
A9
24
A8
25
A13
26
#WE
27
VCC
28
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A10 21
#CE 20
I/O7 19
I/O6 18
I/O5 17
I/O4 16
I/O3 15
GND 14
I/O2 13
I/O1 12
I/O0 11
A0 10
A1 9
A2 8
U6A
74F86
1
23
U7A
74F74
D
2
CLK
3Q5
Q6
PR 4
CL
1
U7B
74F74
D
12
CLK
11 Q9
Q8
PR 10
CL
13
U8
93C56R
CS
1
SK
2
DI
3
DO
4GND 5
NC 6
NC 7
VCC 8
R4
0
C22
8p
R6
2M C23
8p
U9
XC62FP
TAB
4
VIN
2
VSS
1VOUT3
C24
0.1u
C25
0.1u
C26
0.1u
C27
0.1u
C28
4.7u/16V
+
C29
0.01u
AX88190 PRELIMINARY
ASIX ELECTRONICS CORPORATION
39
CONFIDENTIAL
190LU1A1.SCH 1.0
LUCENT LUC6612 PHY
ASIX ELECTRONICS CO.
B
2 3Tuesday, December 15, 1998
Title
Size Document Number Rev
Date: Sheet of
MDIO MDC
TXEN
TXD3
TXD2 TXD1
TXD0
RXD3
RXD2
RXD1
RXD0
PCLK
RXER
RXDV
COL
CRS
VDD
GND
RESET#
TXCLK
RXCLK
BY PASS CAP WITH DIGITAL POWER SUPPLY
BY PASS CAP WITH ANALOG POWER SUPPLY
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
Set PHY ADDRESS TO 10000
To PCMJ15 Connect
VDDA GND
GND RDP
GND RDN
LLED VDDA
ALED
VDD GND PAD4 VDD
GND
TDP FLED
TDN SLED
GND FLED SLED
VDDA VDD
GND ALED
GND
VDDA LLED GND
GND
GND VDD
PAD4 GND
GND
VDDPLL FLED FDLED
SLED SPLED
GND
GND GND ALED ACLED
LLED LILED
VDD
GND GND
VDD
VDD
GND
VDD VDDA
TDP
TDN GND
RDP
RDN
SPLED VDD VDDPLL
LILED
GND
ACLED
FDLED
CHASSIS
U10
LUC6612
VCCBG
1ISET_100
2
GNDBG
3
LED_LINK/PHAD0
4
LED_ACT/PHAD1
5
VCCIOA
6
GNDIOA
7
TD+
8
TD-
9
GNDT
10
VCCT
11
CLKREF
12
GNDBT
13
VCCBT
14
TEST0
15
TEST1
16
PHAD4
17 PCSEN#
18
TEST2
19
VCCPLL
20
LSCLK1
21
LSCLK2
22
GNDPLL
23
ISET_10
24
MDIO
25
MDC
26
RESET#
27
RX_EN
28
TX_ER/TXD4
29
TX_EN
30
TXD3
31
TXD2
32 TXD1 33
TXD0 34
VCCDIGA 35
GNDDIGA 36
RXD3 37
RXD2 38
RXD1 39
RXD0 40
GNDIOC 41
CRS 42
COL 43
RX_CLK 44
RX_DV 45
RX_ER/RXD4 46
TX_CLK 47
GNDDIGB 48
VCCDIGB 49
MODE0 50
MODE1 51
MODE2 52
GNDIOB 53
VCCIOB 54
LED_FDX/PHAD3 55
LED_SPD/PHAD2 56
BGREF1 57
BGREF0 58
GNDREC 59
VCCREC 60
VCCEQAP 61
RD- 62
RD+ 63
GNDEQAP 64
L1
FB
R7
24.9K
R8 22.1K
R10
4.7K
R11 24.9k
R12 24.9K
U11
14ST9012P
CT
1
TD+
2
TD-
3
RD+
5
RD-
6
CT
7CT8
RX- 9
RX+10
TX- 12
TX+13
CT14 J1
PCMJ15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R13
49.9 R14
49.9
R15
49.9 R16
49.9
C31
0.01u
R17
220
R18
220
R19
75 R20
75 R21
75 R22
75
C32
8p
R23
33
R24
33 C33
8p
R25 10K
R26 10K
R27 10K
R28 10K
R29 10K
R30 510
R31 510
R32 510
R33 510
L2
FB C34
0.1u
C35
0.01u
C36
0.01u
C37
0.01u
C38
4.7u/16V
+
C39
0.01u
C40
0.1u
C41
0.1u
C42
0.1u
C43
0.1u
C44
0.1u
C45
4.7u/16V
+
C46
0.1u
C47
0.1u
C48
0.1u
C49
0.1u
C50
0.1u
C51
0.01u
C52
0.1u
C53
0.01u/2KV
C30
1000p
AX88190 PRELIMINARY
ASIX ELECTRONICS CORPORATION
40
CONFIDENTIAL
190LED.SCH 1.0
RJ45 & LED
ASIX ELECTRONICS CORPORATION
A
3 3Tuesday, December 15, 1998
Title
Size Document Number Rev
Date: Sheet of
LILED
SPLED
ACLED
FDLED
CHASSIS
J2
RJ45N
1
2
3
6
4
5
7
8
J3
CON12
1
2
3
4
5
6
7
8
9
10
11
12
D1 LED
D2 LED
D3 LED
D4 LED
C54
0.01
