Data Sheet 1 V 2.2, 2004-03-09
Features
• Micro power design
• 2.4 V to 5.5 V battery operation
• High sensitivity and high stability of the
magnetic switching points
• High resistance to mechanical stress
• Digital output signal
• Switching for both poles of a magnet (omnipolar)
• Not suitable for automotive application
Functional Description
The TLE4913 is an Integrated Hall-Effect Sensor designed specifically to meet the
requirements of low-power devices. e.g. as an On/Off switch in Cellular Flip-Phones, with
battery operating voltages of 2.4V – 5.5V.
Precise magnetic switching points and high temperature stability are achieved through the
unique design of the internal circuit.
An onboard clock scheme is used to reduce the average operating current of the IC.
During the operate phase the IC compares the actual magnetic field detected with the
internally compensated switching points. The output Q is switched at the end of each
operating phase.
During the Stand-by phase the output stage is latched and the current consumption of the
device reduced to some µA.
The IC switching behaviour is Omnipolar, i.e. it can be switched on with either the North or
South pole of a magnet.
Type Marking Ordering Code Package
TLE 4913 13s
013 Q62705K 619 SC 59-3-x
Low Power Hall Switch TLE 4913
SC59-3-x
Data Sheet 2 V 2.2, 2004-03-09
AEP02801_13
3
GND
V
S
Q
12
Top View
Sensitive Area
13
y m
s
month
year
Figure 1 Pin Configuration (top view)
Pin Definitions and Functions
Pin Symbol Function
1 VS Supply Voltage
2 Q Open Drain Input
3 Gnd Ground
Data Sheet 3 V 2.2, 2004-03-09
AEB02800_13
Chopped
Amplifier
Hall
Probe
Latch
Active Error
Compensation
Oscillator
&
Sequencer
Threshold
Generator
Bias and
Compensation
Circuits
V
S
1
3GND
Comparator
with
Hysteresis
2Q
Decision
Logic
Figure 2 Block Diagram
Circuit Description
The Low Power Hall IC Switch comprises a Hall probe, bias generator, compensation
circuits, oscillator, output latch and an n-channel open drain output transistor.
The bias generator provides currents for the Hall probe and the active circuits.
Compensation circuits stabilize the temperature behavior and reduce technology variations.
The Active Error Compensation rejects offsets in signal stages and the influence of
mechanical stress to the Hall probe caused by molding and soldering processes and other
thermal stresses in the package. This chopper technique together with the threshold
generator and the comparator ensures high accurate magnetic switching points.
Very low power consumption is achieved with a timing scheme controlled by an oscillator
and a sequencer. This circuitry activates the sensor for 50 µs (typical operating time) sets
the output state after sequential questioning of the switch points and latches it with the
beginning of the following standby phase (max. 200 ms). In the standby phase the average
current is reduced to typical 4 µA. Because of the long standby time compared to the
operating time the overall averaged current is only slightly higher than the standby current.
The output transistor can sink up to 1 mA with a maximal saturation voltage VQSAT.
Data Sheet 4 V 2.2, 2004-03-09
Absolute Maximum Ratings
Parameter Symbol Limit Values Unit Notes
min. max.
Supply Voltage VS – 0.3 5.5 V
Supply Current IS – 1 2.5 mA
Output Voltage VQ – 0.3 5.5 V
Output Current IQ – 1 2 mA
Junction temperature Tj – 40 150 °C
Storage temperature TS – 40 150 °C
Magnetic Flux Density B – unlimited mT
Thermal Resistance
P-SC59-3-x
Rth JA – 35 K/W
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ESD Protection
Human Body Model (HBM) tests according to:
EOS/ESD Association Standard S5.1-1993 and Mil. Std. 883D method 3015.7
Parameter Symbol Limit Values Unit Notes
Min. Max.
ESD Voltage VESD ± 4 kV
R = 1.5 kΩ,
C = 100 pF;
T = 25 °C
Data Sheet 5 V 2.2, 2004-03-09
Operating Range
Parameter Symbol Limit Values Unit Notes
Min. typ. max.
Supply voltage VS 2.4 2.7 5.5 V 1)
Output voltage VQ – 0.3 2.7 5.5 V
Ambient Temperature TA – 40 25 85 °C
1) A Ceramic Bypass Capacitor of 100 nF at VS to GND is highly recommended.
AC/DC Characteristics
Parameter Symbol Limit Values Unit Notes
Min. typ. Max.
Averaged Supply Current ISAVG 1 4 20 µA
Averaged Supply
Current
during Operating Time
ISOPAVG 0.5 1.1 2.5 mA
Transient Peak Supply
Current
during Operating Time
ISOPT – – 2.5 mA
t < 100 ns
Supply Current
during Standby Time
ISSTB 1 3.5 20 µA
Output Saturation Voltage VQSAT – 0.13 0.4 V IQ = 1 mA
Output Leakage Current IQLEAK – 0.01 1 µA
Output Rise Time tr – 0.5 1 µs RL = 2.7 kΩ;
CL = 10 pF
Output Fall Time tf – 0.1 1 µs RL = 2.7 kΩ;
CL = 10 pF
Operating Time top 15 50 93
1) 2) µs
Standby Time tstb – 130 240
3) ms
Duty Cycle top / tstb – 0.039 – %
Start-up Time of IC tstu – 6 12 µs 4)
1) for VS=3.5V the max. Operating Time top max = 85µs
2) includes the Start-up Time tstu
3) for VS=3.5V the max. Standby Time tstb max = 220ms
4) initial power on time. VS must be applied in this time ( typ. 6µs to max. 12µs ) to get already a valid output
state after the first operating phase (typ. 56µs). For rise times of VS > 12µs, the output state is valid after the
second operating phase (includes one standby phase), e.g. happens only when the battery in flip phones is
changed.
Data Sheet 6 V 2.2, 2004-03-09
Magnetic Characteristics
Parameter Symbol Limit Values Unit Notes
min. typ. max.
Operate Points
(Output on)
BOPS
BOPN
2
– 5
3.5
– 3.5
5
- 2
mT
mT
1)
Release Points
(Output off)
BRPS
BRPN
1,2
– 4.2
2.7
– 2.6
4.2
- 1,2
mT
mT
1)
Hysteresis BHYS 0.2 0.8 1,6 mT
1) Positive magnetic fields are related to the approach of a magnetic south pole to the branded side of package
Note: The listed AC/DC and magnetic characteristics are ensured over the operating range
of the integrated circuit. Typical characteristics specify mean values expected over
the production spread. If not other specified, typical characteristics apply at Tj = 25 °C
and VS = 2.7 V
Data Sheet 7 V 2.2, 2004-03-09
AET02802-17
I
S
t
I
SAVG
I
SSTB
Operating
Time
Standby Time
Latch
Output
t
op
50
µ
s
t
stb
130 ms
I
SOPAVG
Figure 3 Timing Diagram
VQ as function of the applied B-Field
Figure 4 Output – Signal TLE 4913
Data Sheet 8 V 2.2, 2004-03-09
All curves reflect typical values at the given parameters for TA in °C and VS in V.
Magnetic Switching Points versus Magnetic Switching Points versus
Temperature (VS=2.7V) Supply Voltage VS (TA=20°C)
-40 -20 020 40 60 80 100
-5
-4
-3
-2
-1
0
1
2
3
4
5
B[mT]
OPS
B
B RPS
RPN
B
B
OPN
T [°C]
2.5 33.5 44.5 55.5 6
-5
-4
-3
-2
-1
0
1
2
3
4
5
B[mT]
BRPN
BOPN
BRPS
OPS
B
VS [V]
Supply current ISOPAVG during Operating Supply current ISOPAVG during Operating
Time versus Temperature (VS=2.7V) Time versus Supply Voltage VS (TA=20°C)
-40 -20 020 40 60 80 100
0.5
1
1.5
2
2.5
I [m A ]
T [°C]
SOPA VG
I
2.5 33.5 44.5 55.5 6
0
0.5
1
1.5
2
2.5
I [mA]
S
V [V]
SOPAVG
I
Data Sheet 9 V 2.2, 2004-03-09
Supply current ISSTB during Standby Supply current ISSTB during Standby
Time versus Temperature (VS=2.7V) Time versus Supply Voltage VS (TA=20°C)
-40 -20 020 40 60 80 100
0
2
4
6
8
10
12
14
16
18
20
I [µA ]
T [°C]
SSTB
I
2.5 33.5 44.5 55.5 6
0
2
4
6
8
10
12
14
16
18
20
I [µA]
SSTB
I
S
V [V]
Output Saturation voltage VQSAT Standby Time tstb versus Temperature
versus Temperature ( IQ=1mA ) (VS = 2.7V)
-40 -20 020 40 60 80 100
0
20
40
60
80
100
120
140
160
200
V[mV]
VQSAT
T [°C]
-40 -20 020 40 60 80 100
100
110
120
130
140
150
160
170
180
t
stb
t [ms]
T [°C]
Data Sheet 10 V 2.2, 2004-03-09
Top View Marking on P-SC 59-3-x package
corresponds to pin 1 of device
Position in Tape: pin 1
opposite of feed hole side
13 s
3
12
Direction of Unreeling
ym
Package Pieces / Reel ∅Reel
P-SC59-3-x 3.000 180 mm
Figure 5 Marking and Tape Loading Orientation
Figure 6 Foot Print Reflow Soldering
Data Sheet 11 V 2.2, 2004-03-09
Package Dimensions
coplanarity : 0.10mm
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book ”Package Information”.
SMD = Surface Mounted Device
P-SC 59-3-x - Package
Data Sheet 12 V 2.2, 2004-03-09
TLE4913
Revision History: 2004-03-09 V 2.2
Previous Version: 2003-07-16
Page Subjects (major changes since last revision)
4 ESD Level adapted to ±4 kV
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Edition 2002-08-22
Published by Infineon Technologies AG
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All Rights Reserved.
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