RClamp0514M RailClamp Low Capacitance TVS Diode Array PROTECTION PRODUCTS - RailClamp Description PRELIMINARY Features RailClamps are ultra low capacitance TVS arrays designed to protect high speed data interfaces. This series has been specifically designed to protect sensitive components which are connected to high-speed data and transmission lines from overvoltage caused by ESD (electrostatic discharge), CDE (Cable Discharge Events), and EFT (electrical fast transients). The RClampTM0514M has a typical capacitance of only 0.70pF (I/O to I/O). This means it can be used on circuits operating in excess of 2GHz without signal attenuation. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (15kV air, 8kV contact discharge). These devices are in a MSOP 10L package and feature a lead-free, matte tin finish. They are compatible with both lead free and SnPb assembly techniques. They are designed for easy PCB layout by allowing the traces to run straight through the device. The combination of small size, low capacitance, and high level of ESD protection makes them a flexible solution for protecting high-speed HDMI and DVI video interfaces. ESD protection for high-speed data lines to IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-5 (Lightning) 5A (8/20s) IEC 61000-4-4 (EFT) 40A (5/50ns) Array of surge rated diodes with internal TVS Diode Small package saves board space Protects four I/O lines and one Vcc line Low capacitance: 0.7pF typical (Line-to-Line) Low clamping voltage Low operating voltage: 5.0V Solid-state silicon-avalanche technology Mechanical Characteristics JEDEC MSOP 10L package Molding compound flammability rating: UL 94V-0 Marking : Marking code and date code Packaging : Tape and Reel per EIA 481 Lead Finish: Matte Tin RoHS/WEEE Compliant Applications Circuit Diagram High Definition Multi-Media Interface (HDMI) Digital Visual Interface (DVI) 10/100/1000 Ethernet Monitors and Flat Panel Displays Notebook Computers Set Top Box Projection TV Schematic & PIN Configuration NC Line 1 1 Pin 3 Line 2 NC Pin 1 Pin 4 Pin 6 GND Vcc Pin 9 Line 3 NC NC Line 4 Pin 8 MSOP-10L (Top View) Revision 08/31/2005 1 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Absolute Maximum Rating R ating Symbol Value Units Peak Pulse Power (tp = 8/20s) Pp k 125 Watts Peak Pulse Current (tp = 8/20s) IP P 5 A ESD p er IEC 61000-4-2 (Air) ESD p er IEC 61000-4-2 (Contact) VESD 15 8 kV TJ -55 to +125 C TSTG -55 to +150 C Op erating Temp erature Storage Temp erature Electrical Characteristics (T=25oC) Parameter Symbol Conditions Reverse Stand-Off Voltage VRWM Pi n 3 to 8 Reverse Breakdown Voltage V BR It = 1mA Pi n 3 to 8 Reverse Leakage Current IR VRWM = 5V, T=25C Pi n 3 to 8 1 A Clamp ing Voltage VC IPP = 1A, tp = 8/20s Any I/O p in to ground 15 V Clamp ing Voltage VC IPP = 5A, tp = 8/20s Any I/O p in to ground 20 V Junction Cap acitance Cj VR = 0V, f = 1MHz Between I/O p ins 0.9 pF Junction Cap acitance Cj VR = 0V, f = 1MHz Any I/O p in to ground 1.4 pF 2005 Semtech Corp. 2 Minimum Typical Maximum Units 5 V 6 V 0.70 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 10 110 90 % of Rated Power or IPP Peak Pulse Power - PPP (kW) 100 1 0.1 80 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 0 1000 25 Pulse Waveform Percent of I PP 80 16 Clamping Voltage -VC (V) 90 e-t 50 40 td = IPP/2 30 100 125 150 18 Waveform Parameters: tr = 8s td = 20s 100 60 75 Clamping Voltage vs. Peak Pulse Current 110 70 50 Ambient Temperature - TA (oC) Pulse Duration - tp (s) Line to Line 14 12 Line to Gnd 10 8 6 Waveform Parameters: tr = 8s td = 20s 4 20 2 10 0 0 0 5 10 15 20 25 0 30 1 2 3 4 5 6 Peak Pulse Current - IPP (A) Time (s) Normalized Capacitance vs. Reverse Voltage Forward Voltage vs. Forward Current 1.5 3.5 2.5 CJ(VR) / CJ(VR=0) Forward Voltage (V) 3 2 1.5 1 Waveform Parameters: tr = 8s td = 20s 0.5 1 Line to Line Line to Ground 0.5 0 f = 1 MHz 0 1 2 3 4 5 6 0 7 0 Peak Pulse Current (A) 2005 Semtech Corp. 3 1 2 3 Reverse Voltage - VR (V) 4 5 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Typical Characteristics (Con't) Insertion Loss S21 - I/O to I/O CH1 S21 LOG Insertion Loss S21 - I/O to GND 6 dB / REF 0 dB CH1 S21 1 LOG 6 dB / REF 0 dB 1: .23330 dB 900 MHz 1: .31740 dB 900 MHz 2: -.24620 dB 1.8 GHz 2: -.77300 dB 1.8 GHz 3: -2.1013 dB 2.5 GHz 3: -4.0112 dB 2.5 GHz 0 dB 0 dB 1 2 2 3 3 -6 dB -6 dB -12 dB -12 dB -18 dB -18 dB -24 dB -24 dB -30 dB -30 dB -36 dB 1 MHz 10 MHz 100 MHz -36 dB 3 1 GHz GHz STOP 3000. 000000 MHz START . 030 MHz 1 MHz START . 030 MHz 10 MHz 100 MHz 3 1 GHz GHz STOP 3000. 000000 MHz Analog Cross Talk CH1 S21 LOG 20 dB /REF 0 dB START . 030 MHz 2005 Semtech Corp. STOP 3000. 000000 MHz 4 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Applications Information Device Connection Options for Protection of Four High-Speed Data Lines Figure 1. Flow through Layout for two Line Pairs The RClamp0514M TVS is designed to protect four data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Line 1 Line 2 Line 1 Line 2 1 Gnd Vcc Flow Through Layout The RClamp0514M is designed for have ease of PCB layout by allowing the traces to run straight through the device. Figure 1 shows the proper way to design the PCB board trace in order to use the flow through layout for two line pairs. The solid line represents the PCB trace. Note that the PCB traces are used to connect the pin pairs for each line (pin 1 to pin 10, pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6). For example, line 1 enters at pin 1 and exits at Pin 10 and the PCB trace connects pin 1 and 10 together. This is true for lines 2, 3, and 4. The negative reference (Gnd) is connected at pin 8. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference is connected at pin 3. The options for connecting the positive reference are as follows: Line 3 Line 3 Line 4 Line 4 Figure 2. Data Line and Power Supply Protection Using Vcc as reference Line 1 Line 2 Vcc 1 Line 1 Line 2 Gnd Line 3 Line 3 Line 4 Line 4 Figure 3. Data Line Pr otection Using Int ernal TTV VS Pro Internal Diode as Reference 1. Figure 2 shows the connection scheme to protect both data lines and the power line by connecting pin 3 directly to the positive supply rail (VCC). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail. 2. In applications where no positive supply reference is available, or complete supply isolation is desired, figure 3 shows how the internal TVS may be used as the reference. In this case, pin 3 is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop). Line 1 Line 2 NC Line 3 Line 4 1 Line 1 Line 2 Gnd Line 3 Line 4 This ease of layout coupled with the low capacitance and clamping voltage of the RClamp0514M makes it the superior choice to protect two high speed line pairs. 2005 Semtech Corp. 5 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Applications Information (continued) ESD Protection With RailClamps RailClamps are optimized for ESD protection using the rail-to-rail topology. Along with good board layout, these devices virtually eliminate the disadvantages of using discrete components to implement this topology. ConPIN sider Descriptions the situation shown in Figure 4 where discrete diodes or diode arrays are configured for rail-to-rail protection on a high speed line. During positive duration ESD events, the top diode will be forward biased when the voltage on the protected line exceeds the reference voltage plus the VF drop of the diode. For negative events, the bottom diode will be biased when the voltage exceeds the VF of the diode. At first approximation, the clamping voltage due to the characteristics of the protection diodes is given by: VC = VCC + VF VC = -VF Figure 4 - "RailTo-Rail" Pr o tection TTopology opology "Rail-T Pro (First Approximation) (for positive duration pulses) (for negative duration pulses) However, for fast rise time transient events, the effects of parasitic inductance must also be considered as shown in Figure 5. Therefore, the actual clamping voltage seen by the protected circuit will be: VC = VCC + VF + LP diESD/dt (for positive duration pulses) VC = -VF - LG diESD/dt (for negative duration pulses) ESD current reaches a peak amplitude of 30A in 1ns for a level 4 ESD contact discharge per IEC 61000-4-2. Therefore, the voltage overshoot due to 1nH of series inductance is: Figure 5 - The Effects of Parasitic Inductance When Using Discrete Components to Implement RailTo-Rail Pr o t ection Rail-T Pro V = LP diESD/dt = 1X10-9 (30 / 1X10-9) = 30V Example: Consider a VCC = 5V, a typical VF of 30V (at 30A) for the steering diode and a series trace inductance of 10nH. The clamping voltage seen by the protected IC for a positive 8kV (30A) ESD pulse will be: VC = 5V + 30V + (10nH X 30V/nH) = 335V This does not take into account that the ESD current is directed into the supply rail, potentially damaging any components that are attached to that rail. Also note 2005 Semtech Corp. To-Rail Pr Figure 6 - RailRail-T Pro otection Using p TTV V S Arra ys RailClam RailClamp Arrays 6 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Applications Information (continued) that it is not uncommon for the VF of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. It is also possible that the power dissipation capability of the discrete diode will be exceeded, thus destroying the device. The RailClamp is designed to overcome the inherent disadvantages of using discrete signal diodes for ESD suppression. The RailClamp's integrated TVS diode helps to mitigate the effects of parasitic inductance in the power supply connection. During an ESD event, the current will be directed through the integrated TVS diode to ground. The maximum voltage seen by the protected IC due to this path will be the clamping voltage of the device. Circuit Board Layout Recommendations for Suppression of ESD. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: z Place the device near the input terminals or connectors to restrict transient coupling. z Minimize the path length between the TVS and the protected line. z Minimize all conductive loops including power and ground loops. z The ESD transient return path to ground should be kept as short as possible. z Never run critical signals near board edges. z Use ground planes whenever possible. Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small compared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint. 2005 Semtech Corp. 7 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Applications Information The HDMI Compliance Test Specification (CTS) requires sink (receiver) ports maintain a differential impedance of 100 Ohms +/- 15%. The measurement is taken using a Time Domain Reflectometry (TDR) method that utilizes a pulse with a risetime <= 200ps. ESD protection devices have an inherent junction capacitance. Even a small amount of added capacitance on an HDMI port will cause the impedance of the differential pair to drop. As such, some form of compensation to the layout will be required to bring the differential pairs back within the required 100 Ohm +/- 15% range. The higher the added capacitance, the more extreme the modifications will need to be. If the added capacitance is too high, compensation may not even be possible. The RClamp0514M presents <1pF capacitance between the pairs while being rated to handle >8kV ESD contact discharges (>15kV air discharge) as outlined in IEC 61000-4-2. As such, it is possible to make minor adjustments to the board layout parameters to compensate for the added capacitance of the RClamp0514M. Figure 7 shows how to implement the RClamp0514M in an HDMI application (transmitter and receiver). Figure 8 shows impedance test results using a Semtech evaluation board with layout compensation. As shown, the device meets the HDMI CTS impedance requirements. B A X-axis Y-axis A 1.640 99.3 C B 1.796 105.3 C 1.953 98.7 (nsec) (Ohm) Figure 8 - TDR Measurement using Semtech Evaluation Board 1 1 1 1 Figure 7 - HDMI Schematic 2005 Semtech Corp. 8 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Applications Information Spice Model RClamp0514M Spice Model & Parameters I/O Line nH Figure 9 - RClamp0514M Spice Model Table 1 - R Clamp0514M Spice Parameters 2005 Semtech Corp. Parameter Unit D1 (LCR D) D2 (LCR D) D3 (T VS) IS Amp 4.01E-18 4.01E-18 3.39E-15 BV Volt 180 20 7.66 VJ Volt 0.68 0.67 0.61 RS Ohm 0.38 0.548 0.637 IB V A mp 1E-3 1E-3 1E-3 CJO Farad 0.7E-12 0.7E-12 190E-12 TT sec 2.541E-9 2.541E-9 2.541E-9 M -- 0.01 0.01 0.23 N -- 1.1 1.1 1.1 EG eV 1.11 1.11 1.11 9 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Outline Drawing --MSOP SO-8 10L Outline e A DIM D N SIDE VIEW 2X E/2 H 12 c GAGE PLANE B 0.25 L (L1) D DETAIL aaa C SEATING PLANE A2 C A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc A E E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS SEE DETAIL 01 DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .043 .000 .006 .030 .037 .007 .011 .003 .009 .114 .118 .122 .114 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 0 8 .004 .003 .010 1.10 0.00 0.15 0.75 0.95 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0 8 0.10 0.08 0.25 A A A1 bxN bbb C A-B D NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP 10L X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70 P NOTES: 1. 2005 Semtech Corp. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 10 www.semtech.com RClamp0514M PRELIMINARY PROTECTION PRODUCTS Marking Codes 514M XXXX * XXXX = Date Code ** Dot indicates Pin 1 Ordering Information Part Number Lead Finish Qty per Reel Reel Size RClamp 0514M.TBT Matte Sn 500 7 Inch Note: Lead finish is lead-free matte tin. RailClamp and RClamp are marks of Semtech Corporation. Contact Information Semtech Corporation Protection Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2005 Semtech Corp. 11 www.semtech.com