RCLAMP0514M.TBT - SEMTECH - Datasheet.Live

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PROTECTION PRODUCTS - RailClamp





RClamp0514M

RailClamp





Low Capacitance TVS Diode Array

Description Features

Circuit Diagram Schematic & PIN Configuration

Revision 08/31/2005

RailClamps are ultra low capacitance TVS arrays

designed to protect high speed data interfaces. This

series has been specifically designed to protect sensi-

tive components which are connected to high-speed

data and transmission lines from overvoltage caused

by ESD (electrostatic discharge), CDE (Cable Discharge

Events), and EFT (electrical fast transients).

The RClampTM0514M has a typical capacitance of only

0.70pF (I/O to I/O). This means it can be used on

circuits operating in excess of 2GHz without signal

attenuation. They may be used to meet the ESD

immunity requirements of IEC 61000-4-2, Level 4

(±15kV air, ±8kV contact discharge).

These devices are in a MSOP 10L package and feature a

lead-free, matte tin finish. They are compatible with both

lead free and SnPb assembly techniques. They are de-

signed for easy PCB layout by allowing the traces to run

straight through the device. The combination of small

size, low capacitance, and high level of ESD protection

makes them a flexible solution for protecting high-speed

HDMI and DVI video interfaces. Applications

Mechanical Characteristics

High Definition Multi-Media Interface (HDMI)

Digital Visual Interface (DVI)

10/100/1000 Ethernet

Monitors and Flat Panel Displays

Notebook Computers

Set Top Box

Projection TV

ESD protection for high-speed data lines to

IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)

IEC 61000-4-5 (Lightning) 5A (8/20µs)

IEC 61000-4-4 (EFT) 40A (5/50ns)

Array of surge rated diodes with internal TVS Diode

Small package saves board space

Protects four I/O lines and one Vcc line

Low capacitance: 0.7pF typical (Line-to-Line)

Low clamping voltage

Low operating voltage: 5.0V

Solid-state silicon-avalanche technology

JEDEC MSOP 10L package

Molding compound flammability rating: UL 94V-0

Marking : Marking code and date code

Packaging : Tape and Reel per EIA 481

Lead Finish: Matte Tin

RoHS/WEEE Compliant

MSOP-10L (Top View)

Line 1

Vcc

Line 3

NC Line 4

GND

Line 2

Pin 3

Pin 1 Pin 4 Pin 6 Pin 9

Pin 8

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RClamp0514M

Absolute Maximum Rating

Electrical Characteristics (T=25oC)

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RClamp0514M

Typical Characteristics

Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve

100

110

0 25 50 75 100 125 150

Ambient Temperature - TA (oC)

% of Rated Power or IPP

Clamping Voltage vs. Peak Pulse CurrentPulse Waveform

Forward Voltage vs. Forward Current Normalized Capacitance vs. Reverse Voltage

100

110

0 5 10 15 20 25 30

Time (µs)

Percent of I PP

e-t

td = IPP/2

Waveform

Parameters:

tr = 8µs

td = 20µs

0.01

0.1

0.1 1 10 100 1000

Pulse Duration - tp (µs)

Peak Pulse Power - PPP (kW)

0123456

Peak Pulse Current - IPP (A)

Clamping Voltage -VC (V)

Waveform

Parameters:

tr = 8µs

td = 20µs

Line to Gnd

Line to Line

0.5

1.5

2.5

3.5

01234567

Peak Pulse Current (A)

Forward Voltage (V)

Waveform

Parameters:

tr = 8µs

td = 20µs

0.5

1.5

012345

Reverse Voltage - VR (V)

CJ(VR) / CJ(VR=0)

f = 1 MHz

Line to Ground

Line to Line

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RClamp0514M

Insertion Loss S21 - I/O to I/O

Typical Characteristics (Con’t)

START

030 MHz 3

STOP 000

000 000 MHz

CH1 S21 LOG 6 dB / REF 0 dB

1: .23330 dB

900 MHz

2: -.24620 dB

1.8 GHz

3: -2.1013 dB

2.5 GHz

0 dB

-6 dB

-12 dB

-18 dB

-24 dB

-30 dB

-36 dB 1

GHz

100

MHz

GHz

MHz

Analog Cross Talk

2 3

START

030 MHz 3

STOP 000

000 000 MHz

CH1 S21 LOG 6 dB / REF 0 dB

1: .31740 dB

900 MHz

2: -.77300 dB

1.8 GHz

3: -4.0112 dB

2.5 GHz

0 dB

-6 dB

-12 dB

-18 dB

-24 dB

-30 dB

-36 dB 1

GHz

100

MHz

GHz

MHz

Insertion Loss S21 - I/O to GND

START

030 MHz 3

STOP 000

000 000 MHz

CH1 S21 LOG 20 dB / REF 0 dB

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RClamp0514M

Device Connection Options for Protection of Four

High-Speed Data Lines

The RClamp0514M TVS is designed to protect four

data lines from transient over-voltages by clamping

them to a fixed reference. When the voltage on the

protected line exceeds the reference voltage (plus

diode VF) the steering diodes are forward biased,

conducting the transient current away from the

sensitive circuitry.

Flow Through Layout

The RClamp0514M is designed for have ease of PCB

layout by allowing the traces to run straight through the

device. Figure 1 shows the proper way to design the PCB

board trace in order to use the flow through layout for

two line pairs. The solid line represents the PCB trace.

Note that the PCB traces are used to connect the pin

pairs for each line (pin 1 to pin 10, pin 2 to pin 9, pin 4

to pin 7, pin 5 to pin 6). For example, line 1 enters at

pin 1 and exits at Pin 10 and the PCB trace connects pin

1 and 10 together. This is true for lines 2, 3, and 4. The

negative reference (Gnd) is connected at pin 8. This pin

should be connected directly to a ground plane on the

board for best results. The path length is kept as short

as possible to minimize parasitic inductance. The

positive reference is connected at pin 3. The options for

connecting the positive reference are as follows:

1. Figure 2 shows the connection scheme to protect

both data lines and the power line by connecting pin

3 directly to the positive supply rail (VCC). In this

configuration the data lines are referenced to the

supply voltage. The internal TVS diode prevents

over-voltage on the supply rail.

2. In applications where no positive supply reference is

available, or complete supply isolation is desired,

figure 3 shows how the internal TVS may be used as

the reference. In this case, pin 3 is not connected.

The steering diodes will begin to conduct when the

voltage on the protected line exceeds the working

voltage of the TVS (plus one diode drop).

This ease of layout coupled with the low capacitance and

clamping voltage of the RClamp0514M makes it the

superior choice to protect two high speed line pairs.

Figure 2. Data Line and Power Supply ProtectionFigure 2. Data Line and Power Supply Protection

Figure 2. Data Line and Power Supply Protection

Using Vcc as referenceUsing Vcc as reference

Using Vcc as reference

Figure 3. Data Line PrFigure 3. Data Line Pr

Figure 3. Data Line Proo

ott

tection Using Intection Using Int

ection Using Intection Using Int

ection Using Internal Ternal T

ernal Ternal T

ernal TVV

VSS

Diode as ReferenceDiode as Reference

Diode as Reference

Applications Information

1Line 1

Gnd

Line 2

Line 3

Line 4

Line 1

Line 2

Line 3

Line 4

Vcc

1Line 1

Gnd

Line 2

Line 3

Line 4

Line 1

Line 2

Line 3

Line 4

Line 1

Vcc

Line 2

Line 3

Line 4

Line 1

Gnd

Line 2

Line 3

Line 4

Figure 1. Flow through Layout for two Line PairsFigure 1. Flow through Layout for two Line Pairs

Figure 1. Flow through Layout for two Line Pairs

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RClamp0514M

PIN Descriptions

ESD Protection With RailClamps





RailClamps are optimized for ESD protection using the

rail-to-rail topology. Along with good board layout, these

devices virtually eliminate the disadvantages of using

discrete components to implement this topology. Con-

sider the situation shown in Figure 4 where discrete

diodes or diode arrays are configured for rail-to-rail

protection on a high speed line. During positive duration

ESD events, the top diode will be forward biased when

the voltage on the protected line exceeds the reference

voltage plus the VF drop of the diode. For negative

events, the bottom diode will be biased when the voltage

exceeds the VF of the diode. At first approximation, the

clamping voltage due to the characteristics of the protec-

tion diodes is given by:

VC = VCC + VF(for positive duration pulses)

VC = -VF(for negative duration pulses)

However, for fast rise time transient events, the effects of

parasitic inductance must also be considered as shown

in Figure 5. Therefore, the actual clamping voltage seen

by the protected circuit will be:

VC = VCC + VF + LP diESD/dt (for positive duration pulses)

VC = -VF - LG diESD/dt (for negative duration pulses)

ESD current reaches a peak amplitude of 30A in 1ns for

a level 4 ESD contact discharge per IEC 61000-4-2.

Therefore, the voltage overshoot due to 1nH of series

inductance is:

V = LP diESD/dt = 1X10-9 (30 / 1X10-9) = 30V

Example:

Consider a VCC = 5V, a typical VF of 30V (at 30A) for the

steering diode and a series trace inductance of 10nH.

The clamping voltage seen by the protected IC for a

positive 8kV (30A) ESD pulse will be:

VC = 5V + 30V + (10nH X 30V/nH) = 335V

This does not take into account that the ESD current is

directed into the supply rail, potentially damaging any

components that are attached to that rail. Also note

Figure 4 - “Rail-Figure 4 - “Rail-

Figure 4 - “Rail-TT

To-Rail” Pro-Rail” Pr

o-Rail” Pro-Rail” Pr

o-Rail” Proo

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tection Tection T

ection Tection T

ection Topologyopology

opologyopology

opology

(First Approximation)(First Approximation)

(First Approximation)

Figure 5 - The Effects of Parasitic InductanceFigure 5 - The Effects of Parasitic Inductance

Figure 5 - The Effects of Parasitic Inductance

When Using Discrete Components to ImplementWhen Using Discrete Components to Implement

When Using Discrete Components to Implement

Rail-Rail-

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To-Rail Pro-Rail Pr

o-Rail Pro-Rail Pr

o-Rail Proo

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tectionection

ectionection

ection

Figure 6 - Rail-Figure 6 - Rail-

Figure 6 - Rail-TT

To-Rail Pro-Rail Pr

o-Rail Pro-Rail Pr

o-Rail Proo

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tection Usingection Using

ection Usingection Using

ection Using

RailClamRailClam

RailClamp Tp T

p Tp T

p TVV

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Applications Information (continued)

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RClamp0514M

Applications Information (continued)

that it is not uncommon for the VF of discrete diodes to

exceed the damage threshold of the protected IC. This is

due to the relatively small junction area of typical dis-

crete components. It is also possible that the power

dissipation capability of the discrete diode will be ex-

ceeded, thus destroying the device.

The RailClamp is designed to overcome the inherent

disadvantages of using discrete signal diodes for ESD

suppression. The RailClamp’s integrated TVS diode

helps to mitigate the effects of parasitic inductance in

the power supply connection. During an ESD event, the

current will be directed through the integrated TVS diode

to ground. The maximum voltage seen by the protected

IC due to this path will be the clamping voltage of the

device.

Circuit Board Layout Recommendations for Suppres-

sion of ESD.

Good circuit board layout is critical for the suppression of

ESD induced transients. The following guidelines are

recommended:

zPlace the device near the input terminals or connec-

tors to restrict transient coupling.

zMinimize the path length between the TVS and the

protected line.

zMinimize all conductive loops including power and

ground loops.

zThe ESD transient return path to ground should be

kept as short as possible.

zNever run critical signals near board edges.

zUse ground planes whenever possible.

Matte Tin Lead Finish

Matte tin has become the industry standard lead-free

replacement for SnPb lead finishes. A matte tin finish

is composed of 100% tin solder with large grains.

Since the solder volume on the leads is small com-

pared to the solder paste volume that is placed on the

land pattern of the PCB, the reflow profile will be

determined by the requirements of the solder paste.

Therefore, these devices are compatible with both

lead-free and SnPb assembly techniques. In addition,

unlike other lead-free compositions, matte tin does not

have any added alloys that can cause degradation of

the solder joint.

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RClamp0514M

Applications Information

The HDMI Compliance Test Specification (CTS) requires

sink (receiver) ports maintain a differential impedance

of 100 Ohms +/- 15%. The measurement is taken

using a Time Domain Reflectometry (TDR) method that

utilizes a pulse with a risetime <= 200ps.

ESD protection devices have an inherent junction

capacitance. Even a small amount of added capaci-

tance on an HDMI port will cause the impedance of

the differential pair to drop. As such, some form of

compensation to the layout will be required to bring

the differential pairs back within the required 100

Ohm +/- 15% range. The higher the added capaci-

tance, the more extreme the modifications will need to

be. If the added capacitance is too high, compensa-

tion may not even be possible. The RClamp0514M

presents <1pF capacitance between the pairs while

being rated to handle >8kV ESD contact discharges

(>15kV air discharge) as outlined in IEC 61000-4-2.

As such, it is possible to make minor adjustments to

the board layout parameters to compensate for the

added capacitance of the RClamp0514M. Figure 7

shows how to implement the RClamp0514M in an

HDMI application (transmitter and receiver). Figure 8

shows impedance test results using a Semtech evalua-

tion board with layout compensation. As shown, the

device meets the HDMI CTS impedance requirements.

Figure 7 - HDMI Schematic

Figure 8 - TDR Measurement using Semtech

Evaluation Board

A B C

X-axis 1.640 1.796 1.953 (nsec)

Y-axis 99.3 105.3 98.7 (Ohm)

A C

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RClamp0514M

Applications Information Spice Model

RClamp0514M Spice Model & Parameters

Figure 9 - RClamp0514M Spice Model

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TTces9-E145.29-E145.29-E145.2

M--10.010.032.0

N--1.11.11.1

GEVe11.111.111.1

I/O Line

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RClamp0514M

Outline Drawing - SO-8

Land Pattern - MSOP 10L

Outline Drawing -MSOP 10L

bbb C A-B D

PLANE

aaa C

SEATING

INDICATOR

ccc C

2X N/2 TIPS

PIN 1

2X E/2

bxN

SIDE VIEW

SEE DETAIL A

DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS

OR GATE BURRS.

DATUMS AND TO BE DETERMINED AT DATUM PLANE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

-B-

NOTES:

2. -A- -H-

REFERENCE JEDEC STD MO-187, VARIATION BA.4.

DETAIL

0.25

PLANE

GAGE

(L1)

0°

.010

.004

.016

.003

.024

(.037)

.000

.030

0.25

0.10

8° 0° -8°

0.60

(.95)

.032

.009

0.40

0.08

.043

.006

.037 0.75

0.00

0.80

0.23

0.95

1.10

0.15

.193 BSC

.020 BSC

.003

.114

.118

.007 -

0.08

3.00

4.90 BSC

0.50 BSC

.122

2.90

.011 0.17

3.10

0.27

DIM

ccc

bbb

aaa

MILLIMETERS

NOM

INCHES

DIMENSIONS

MIN NOM MAX MIN MAX

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.

CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR

COMPANY'S MANUFACTURING GUIDELINES ARE MET.

NOTES:

(C)

.063

.224

.011

.020

.098

(.161)

5.70

1.60

0.30

0.50

2.50

(4.10)

MILLIMETERS

DIMENSIONS

DIM INCHES

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PRELIMINARY

PROTECTION PRODUCTS

RClamp0514M

Contact Information

Semtech Corporation

Protection Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805)498-2111 FAX (805)498-3804

Marking Codes

Ordering Information

514M

XXXX

* XXXX = Date Code

** Dot indicates Pin 1

Note: Lead finish is lead-free matte tin.

RailClamp and RClamp are marks of Semtech Corporation.

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