1
Software Chip Erase
The enti re device c an be erased at one
time by using a 6-byte softw are code.
The software chip erase code consists of
6-byte load commands to specific
address locations with specific data pat-
terns. Once the code has been entered,
the device will s et each byte to the hig h
state (FFH). After the software chip
erase has been initiated, the dev ice will
internally time the erase operation so
that no exter nal cloc ks are requ ired . The
maximum time required to erase the
whol e chip is tEC (20 ms). The softwa re
data protec tion is s till enabl ed even after
the software chip erase is performed.
Note: 1. Please refer to individual data sheets for the minimum and maximum values of the
tAS, tAH, tDS, tDH, tWP
, tBLC, and tWPH parameters.
Chip Erase Software Algorithm(1)(3)
Notes: 1. Data Format: (Hex); Address Format: (Hex).
2. After loading the 6-byte code, no b yte loads are allowed until the completion of the
erase cycle. The erase cycle w ill time itself to completion in 20 ms ( m ax).
3. The fl ow di agr a m sho wn is for a x8 part. F o r a x16 pa rt, the d ata sho uld be 1 6 bits
long (e.g., the data to be loaded should be AAAA for step 1 in the algorithm).
Chip Erase Cycle Characteristics
Symbol Parameter
tEC Chip Erase Cycle Time 20 ms Max
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 10(2)
TO
ADDRESS 5555
Parallel
EEPROMs
Application
Note
CMOS E2PROM
Rev. 0544B–10/98
Software Chip
Erase
EEPROMs
2
Chip Erase Cycle Waveforms
Note: 1. OE mu st be high only when WE and CE are both low.
EEPROMs
3
© Atmel Corpo ration 1998.
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0544B–05/98/xM
