DM74LS193CW - Fairchild Semiconductor Corporation

September 1986

Revised March 2000

DM74LS193 Synchronous 4-Bit Binar y Counter wit h Dual Clock

DM74LS193

Synchronous 4-Bit Binary Counter with Dual Clock

General Descript ion

The DM74LS193 circuit is a synchronous up/down 4-bit

binary c ounter. Synchronou s oper ation i s pro vided b y ha v-

ing all fl ip -flo ps clocked si m ulta neo usl y, so that th e outputs

change together when so instructed by the steering logic.

This mode of operation eliminates the output counting

spikes normally associated with asynchronous (ripple-

clock) counters.

The outputs of the four master-slave flip-flops are triggered

by a LOW-to-HIGH level transition of either count (clock)

input. The direction of counting is determined by which

count input is pulsed while the other count input is held

HIGH.

The counter is fully programmable; that is, each output may

be pres et to e ithe r le vel b y en ter ing the de sired data at t he

inputs while the load input is LOW. The output w ill change

indepen dently of the count pulses. This feat ure allows t he

counters to be use d as modulo-N dividers by simply modi-

fying the count length with the preset inputs.

A clear input has been provided which, when taken to a

high level, forces all output s to the low level; independe nt

of the count and load inputs. The clear, count, and load

inputs are buff ere d to lowe r the dr i ve req uire me nts of cloc k

drivers, etc., required for long words.

These c oun ter s we re d esigned to b e cascaded wi tho ut the

need for external circuitry. Both borrow and carry outputs

are available to cascade both the up and down counting

functions. The borrow output produces a pulse equal in

width to the count down input when the counter underflows.

Simila rly, the carry outp ut produces a pulse equal in width

to the count d ow n in pu t w hen an o verf l ow con dit ion exis ts .

The coun ters can then be easily cascaded by feeding the

borrow and carry o utputs to th e count dow n and count up

inputs respectively of the succeeding counte r.

Features

■Fully independent clear input

■Synchronous operation

■Cascading circuitry provided internally

■Individual preset each flip-flop

Ordering Code:

Connection Diagram

Order Number Package Number Package Description

DM74LS193M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

DM74LS193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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DM74LS193

Logic Diagram

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DM74LS193

Timing Diagram

Note A: Clear ove rrides load, data, and count inputs

Note B: When counting up, count-down input must be HIGH; when counting down, count-up input must be HIGH.

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DM74LS193

Absolute Maximum Ratings(Note 1) Note 1: The “Abs olute Maxim um Ratings ” are those valu es beyond w hich

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are no t gua rant eed at the absolute maximum rati n gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Note 2: CL = 15 pF, RL = 2 kΩ, IA = 25°C and VCC = 5V.

Note 3: CL = 50 pF, RL = 2 kΩ, IA = 25°C and VCC = 5V.

Note 4: TA = 25°C an d VCC = 5V.

DC Electrical Characteristics

Note 5: All typic als are at VCC = 5V, TA = 25°C.

Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 7: ICC is meas ured wit h all outpu t s o pen, CLEA R and LOAD input s g rounded, and all ot her inputs at 4. 5V.

Operati ng Free Air Temperature Range −0°C to +70°C

Supply Voltage 7V

Input Voltage 7V

Storage Temperature Range −65°C to +125°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

fCLK Clock Frequency (Note 2) 0 25 MHz

Clock Frequency (Note 3)

tWPulse Width of any Input (Note 4) 20 ns

tSU Data Setup Time (Note 4) 20 ns

tHData Hold Time (Note 4) 0 ns

tEN Enable Time to Clock (Note 4) 40 ns

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 5)

VIInput Clamp Voltage VCC = Min, I I = −18 mA −1.5 V

VOH HIGH Level Output VCC =Min, IOH =Max 2.5 3.4 V

Voltage VIL = Max, VIH = Min 2.7 3.4

VOL LOW Level Output VCC =Min, IOL =Max 0.25 0.4

Voltage VIL = Max, VIH = Min 0.35 0.5 V

IOL =4mA,V

CC =Min 0.25 0.4

IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

IOS Short Circuit VCC = Max −20 −100 mA

Output Current (Note 6) −20 −100

ICC Supply Current VCC = Max (Note 7) 19 34 mA

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DM74LS193

AC Electrical Characteristics

From (Input) RL = 2 kΩ

Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units

MinMaxMinMax

fMAX Maximum Clock Frequency 25 20 MHz

tPLH Propagation Delay Time Count Up 26 30 ns

LOW-to-HIGH Level Output to Carry

tPHL Propagation Delay Time Count Up 24 36 ns

HIGH-to-LOW Level Output to Carry

tPLH Propagation Delay Time Count Down 24 29 ns

LOW-to-HIGH Level Output to Borrow

tPHL Propagation Delay Time Count Down 24 32 ns

HIGH-to-LOW Level Output to Borrow

tPLH Propagation Delay Time Either Count 38 45 ns

LOW-to-HIGH Level Output to Any Q

tPHL Propagation Delay Time Either Count 47 54 ns

HIGH-to-LOW Level Output to Any Q

tPLH Propagation Delay Time Load to 40 41 ns

LOW-to-HIGH Level Output Any Q

tPHL Propagation Delay Time Load to 40 47 ns

HIGH-to-LOW Level Output Any Q

tPHL Propagation Delay Time Clear to 35 44 ns

HIGH-to-LOW Level Output Any Q

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DM74LS193

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0150” Narrow Body

Package Number M16A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

7 www.fairchildsemi.com

DM74LS193 Synchronous 4-Bit Binar y Counter wit h Dual Clock

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.

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[Information as of 1-Aug-2000]

DM74LS193

Synchronous 4-Bit Up/Down Binary Counter with Dual Clock

Generic P/N 74LS193

Contents

General Description

Features

Datasheet

Availability, Models, Samples & Pricing

General Description

PDF

Contact Fairchild

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Fairchild P/N DM74LS193 - Synchronous 4-Bit Up/Down Binary Counter with Dual Clockfile:////roarer/root/data13/imaging/BIT...4/08032000/FAIR/08022000/DM74LS193.html

The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided

by having all flip-flops clocked simultaneously, so that the outputs change together when so instructed by

the steering logic. This mode of operation eliminates the output counting spikes normally associated with

asynchronous (ripple-clock) counters.

The outputs of the four master-slave flip-flops are triggered by a LOW-to-HIGH level transition of either

count (clock) input. The direction of counting is determined by which count input is pulsed while the other

count input is held HIGH.

The counter is fully programmable; that is, each output may be preset to either level by entering the desired

data at the inputs while the load input is LOW. The output will change independently of the count pulses.

This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with

the preset inputs.

A clear input has been provided which, when taken to a high level, forces all outputs to the low level;

independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive

requirements of clock drivers, etc., required for long words.

These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry

outputs are available to cascade both the up and down counting functions. The borrow output produces a

pulse equal in width to the count down input when the counter underflows.

Similarly, the carry output produces a pulse equal in width to the count down input when an overflow

condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the

count down and count up inputs respectively of the succeeding counter.

Features

Fully independent clear input

Synchronous operation

Cascading circuitry provided internally

Individual preset each flip-flop

Datasheet

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DM74LS193 Synchronous 4-Bit Up/Down Binary Counter with Dual Clock

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29-JUL-00)

Availability, Models, Samples & Pricing

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Part Number Grade Package Status Models Budgetary

Pricing Std

Pack

Size

Package

Marking

Type #

pins SPICE IBIS Quantity $US ea

DM74LS193MX Comm SOIC 16 Full

Production N/A N/A 1-24

25-99

100-1000

$0.6670

$0.50

$0.40 N/A

$Y&Z&2&T

DM74LS193M

DM74LS193M Comm SOIC 16 Full

Production N/A N/A 1-24

25-99

100-1000

$0.6670

$0.50

$0.40 N/A

$Y&Z&2&T

DM74LS193M

DM74LS193N Comm MDIP 16 Full

Production N/A N/A 1-24

25-99

100-1000

$0.5560

$0.4170

$0.3330 N/A

$Y&Z&4&T&P

DM74LS193N

DM74LS193CW Comm wafer Preliminary N/A N/A N/A N/A

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