MC14094BDR2 - ON Semiconductor

June, 2011 − Rev. 8

1Publication Order Number:

MC14094B/D

MC14094B

8-Stage Shift/Store Register

with Three-State Outputs

The MC14094B combines an 8−stage shift register with a data latch

for each stage and a 3−state output from each latch.

Data is shifted on the positive clock transition and is shifted from the

seventh stage to two serial outputs. The QS output data is for use in

high−speed cascaded systems. The QS output data is shifted on the

following negative clock transition for use in low−speed cascaded systems.

Data from each stage of the shift register is latched on the negative

transition of the strobe input. Data propagates through the latch while

strobe is high.

Outputs of the eight data latches are controlled by 3−state buffers which

are placed in the high−impedance state by a logic Low on Output Enable.

Features

•3−State Outputs

•Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

•Input Diode Protection

•Data Latch

•Dual Outputs for Data Out on Both Positive and

Negative Clock Transitions

•Useful for Serial−to−Parallel Data Conversion

•Pin−for−Pin Compatible with CD4094B

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

MC14094BCP

AWLYYWWG

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

14094BG

AWLYWW

14

094B

ALYWG

G

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Indicator

SOEIAJ−16

F SUFFIX

CASE 966

MC14094B

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

16

1

16

1

16

1

16

MC14094B

http://onsemi.com

2

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q7

Q6

Q5

OUTPUT

ENABLE

VDD

QS

Q′S

Q8

Q1

CLOCK

DATA

STROBE

VSS

Q4

Q3

Q2

PIN ASSIGNMENT

TRUTH TABLE

Clock

Output

Enable Strobe Data

Parallel Outputs Serial Outputs

Q1 QNQS* Q′S

0 X X Z Z Q7 No Chg.

0 X X Z Z No Chg. Q7

1 0 X No Chg. No Chg. Q7 No Chg.

1 1 0 0 QN−1 Q7 No Chg.

1 1 1 1 QN−1 Q7 No Chg.

1 1 1 No Chg. No Chg. No Chg. Q7

Z = High Impedance X = Don’t Care

* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.

ORDERING INFORMATION

Device Package Shipping†

MC14094BCPG PDIP−16

(Pb−Free)

500 Units / Rail

MC14094BDG SOIC−16

(Pb−Free)

48 Units / Rail

MC14094BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

MC14094BDTR2G TSSOP−16* 2500 Units / Tape & Reel

MC14094BFG SOEIAJ−16

(Pb−Free)

50 Units / Rail

MC14094BFELG SOEIAJ−16

(Pb−Free)

2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC14094B

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ (2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

−

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

−

ÎÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎÎ

−

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

±0.1

ÎÎÎÎ

−

ÎÎÎ

±0.00001

ÎÎÎÎ

±0.1

ÎÎÎ

−

ÎÎÎ

±1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

5.0

ÎÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

5.0

10

20

ÎÎÎÎ

−

ÎÎÎ

0.005

0.010

0.015

ÎÎÎÎ

5.0

10

20

ÎÎÎ

−

ÎÎÎ

150

300

600

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (3) (4)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

ÎÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (4.1 mA/kHz) f + IDD

IT = (14 mA/kHz) f + IDD

IT = (140 mA/kHz) f + IDD

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

3−State Output Leakage Current

ÎÎÎÎ

ITL

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

±0.1

ÎÎÎÎ

−

ÎÎÎ

±0.0001

ÎÎÎÎ

±0.1

ÎÎÎ

−

ÎÎÎ

±3.0

ÎÎÎ

mA

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14094B

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ (6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Time

tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

tTLH, tTHL = (0.6 ns/pF) CL + 20 ns

tTLH, tTHL = (0.4 ns/pF) CL + 20 ns

ÎÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time (Figure 1)

Clock to Serial out QS

tPLH, tPHL = (0.90 ns/pF) CL + 305 ns

tPLH, tPHL = (0.36 ns/pF) CL + 107 ns

tPLH, tPHL = (0.26 ns/pF) C L + 82 ns

Clock to Serial out Q’S

tPLH, tPHL = (0.90 ns/pF) CL + 350 ns

tPLH, tPHL = (0.36 ns/pF) CL + 149 ns

tPLH, tPHL = (0.26 ns/pF) CL + 62 ns

Clock to Parallel out

tPLH, tPHL = (0.90 ns/pF) CL + 375 ns

tPLH, tPHL = (0.35 ns/pF) CL + 177 ns

tPLH, tPHL = (0.26 ns/pF) CL + 122 ns

Strobe to Parallel out

tPLH, tPHL = (0.90 ns/pF) CL + 245 ns

tPLH, tPHL = (0.36 ns/pF) C L + 127 ns

tPLH, tPHL = (0.26 ns/pF) CL + 87 ns

Output Enable to Output

tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns

tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns

tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns

tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns

tPLZ, tPZH = (0.36 ns/pF) CL + 77 ns

tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns

ÎÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

350

125

95

ÎÎÎÎ

600

250

190

ÎÎÎ

ns

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

230

110

75

ÎÎÎÎ

460

220

150

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

420

195

135

ÎÎÎÎ

840

390

270

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

290

145

100

ÎÎÎÎ

580

290

200

ÎÎÎÎÎ

tPHZ,

tPZL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

140

75

55

ÎÎÎÎ

280

150

110

ÎÎÎÎÎ

tPLZ,

tPZH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

225

95

70

ÎÎÎÎ

450

190

140

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Setup Time

Data in to Clock

ÎÎÎÎÎ

tsu

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

125

55

35

ÎÎÎÎ

60

30

20

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Hold Time

Clock to Data

ÎÎÎÎÎ

th

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

0

20

ÎÎÎÎ

– 40

– 10

0

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Width, High

ÎÎÎÎÎ

tWH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

200

100

83

ÎÎÎÎ

100

50

40

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Rise and Fall Time

ÎÎÎÎÎ

tr(cl)

tf(cl)

ÎÎÎÎ

5

10

15

ÎÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎÎ

15

5.0

4.0

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Frequency

ÎÎÎÎÎ

fcl

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

2.5

5.0

6.0

ÎÎÎÎ

1.25

2.5

3.0

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Strobe Pulse Width

ÎÎÎÎÎ

tWL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

200

80

70

ÎÎÎÎ

100

40

35

ÎÎÎÎ

−

ÎÎÎ

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14094B

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5

3−STATE TEST CIRCUIT

FOR tPHZ AND tPZH

VSS

FOR tPLZ AND tPZL

VDD

R1

OUTPUT

50 pF

O.E.

CLOCK

ST

DATA

Figure 1.

R1 = 1 k = tPHL, tPLH

R1 = 10 k = tPHZ, tPZH, tPLZ, tPZL

REGISTER STAGE 1

BLOCK DIAGRAM

LATCH 1 3-STATE BUFFER 1

15

2

SERIAL

DATA IN

OUTPUT

ENABLE

CLOCK CLOCK STROBE

CLOCK

CLOCK CLOCK

CLOCK

STROBE STROBE

STROBE

VDD

4

5

6

7

14

13

12

11

10

9

Q1

Q2

Q′S

Q3

Q4

Q5

Q6

Q7

Q8

QS

2

3

4

5

6

7

8

REGISTER STAGE 2

REGISTER STAGE 3

REGISTER STAGE 4

REGISTER STAGE 5

REGISTER STAGE 6

REGISTER STAGE 7

REGISTER STAGE 8

LATCH 2

LATCH 3

LATCH 4

LATCH 5

LATCH 6

LATCH 7

LATCH 8

3-STATE BUFFER2

3-STATE BUFFER3

3-STATE BUFFER4

3-STATE BUFFER5

3-STATE BUFFER6

3-STATE BUFFER7

3-STATE BUFFER8

CLOCK CLOCK STROBE STROBE CLOCK

CLOCK CLOCK

CLOCK

STROBE

CLOCK

STROBE

3

1*Input Protection Diodes

*

MC14094B

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6

10

DYNAMIC TIMING DIAGRAM

3

15

CLOCK

2DATA IN

1STROBE

OUTPUT

ENABLE

NQ1 ³ Q7

9QS

Q′S

tWH

50%

tsu th

tWL

50%

trtf

90%

10%

50% 50%

tPZL

tPZH

tPHZ

tPHL tPLH

tPLH tPLZ

10%

90%

10%

90%90%

90%

10%

50%

tPHL

tPLH

tTHL

tTLH

tPLH tPHL

MC14094B

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7

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

MC14094B

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8

PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

16

89

8X

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC14094B

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9

PACKAGE DIMENSIONS

TSSOP−16

DT SUFFIX

CASE 948F−01

ISSUE B

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

18

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

ÉÉÉ

DETAIL E

F

M

L

2X L/2

−U−

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V S

T

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

N

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC14094B

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10

PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

CASE 966−01

ISSUE A

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005) 0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

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