a Dual Channel, 12-Bit, 80MSPS A/D Converter with Analog Input Signal Conditioning PRELIMINARY DATA AD13280 PERFORMANCE FEATURES Dual, 80 MSPS minimum sample rate - Channel-channel matching, +/-1% gain error - 90dB Channel-Channel isolation - DC-Coupled Signal conditioning 80dB Spurious-Free Dynamic Range Selectable Bipolar Inputs (+/- 1V and +/- 0.5V ranges) Integral Single Pole Low Pass Nyquist Filter Two's Complement Output Format 3.3 or 5V CMOS-Compatible Outputs 1.75W per Channel Industrial and Military Grade APPLICATIONS Radar Processing (optimized for I/Q Baseband operation) Phased Array Receivers MultiChannel, Multimode Receivers GPS Anti-Jamming Receivers Communications Receivers PRODUCT DESCRIPTION The AD13280 is a complete dual channel signal processing solution including on board amplifiers, references, ADCs and output termination components to provide optimized system performance. The AD13280 has onchip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 12-bit, 80MSPS performance. The AD13280 uses innovative high-density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching, impedance control, and performance while still maintaining excellent isolation, and providing for significant board area savings. Multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. The AD13280 also offers the user a choice of Analog Input Signal ranges to further minimize additional external signal conditioning, while still remaining general purpose. The AD13280 operates with +/- 5.0V for the Analog signal conditioning with a separate +5.0V supply for the Analog to Digital conversion, and +3.3V digital supply for the output stage. Each channel is completely independent allowing operation with independent Encode and Analog Inputs, and maintaining minimal crosstalk and interference. The AD13280 is packaged in a 68-lead Ceramic Gull Wing Package. Manufacturing is done on Analog Devices, Inc. Mil38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (-40C to 85C). The components are manufactured using Analog Devices, Inc. high-speed complimentary bipolar process (XFCB). PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 80 MSPS. 2. Input signal conditioning included; gain and impedance match 3. Single-ended, differential, or off-module filter options 4. Fully tested/characterized full channel performance 5. Compatible with 14-bit (up to) 80MSPS family Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 1 TARGET SPECIFICATIONS AD13280 Electrical Characteristics (AVCC=5V; AVEE =-5V; DVCC=+3.3V applies to each ADC with Front-End Amplifier unless otherwise noted.) Parameter Temp Test Level Mil SubGroup AD13280BZ Min RESOLUTION DC ACCURACY3 No Missing Codes Offset Error Typ Max 12 IV I VI V I VI I VI Full Full V V Full Full IV IV Full V 100 MHz DIFFERENTIAL ANALOG INPUT Analog Signal Input Range A+IN to A-IN and B+IN to B-IN Input Impedance Capacitance Analog Input Bandwidth Full +25C +25C Full V V V V 1 618 7 50 V pF MHz ENCODE INPUT (ENC, ENC) 3 Differential Input Voltage Differential Input Resistance Differential Input Capacitance Full +25C +25C IV V V 12 10 2.5 VP P K pF SWITCHING PERFORMANCE Maximum Conversion Rate4 Minimum Conversion Rate4 Aperture Delay (t A) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulse Width High at Max Conversion Rate ENCODE Pulse Width Low at Max Conversion Rate Output Delay (t OD) Encode, Rising to Data Ready, Rising Delay Full Full +25C +25C +25C +25C +25C Full Full VI IV V IV V IV IV V V 4,5,6 12 12 12 4.75 4.75 +25C -40C +85C +25C -40C +85C +25C -40C +85C I II II I II II I II II 4 5 6 4 5 6 4 5 6 68 65 68 67.5 64 67.5 63 61 63 70 +25C -40C +85C +25C -40C +85C +25C -40C +85C I II II I II II I II II 4 5 6 4 5 6 4 5 6 67.5 64 67.5 65 63 65 54 52.5 54 69 Gain Error Channel Match SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 AMP-IN-X-2 Input Resistance AMP-IN-X-1 AMP-IN-X-2 nalog Input Bandwidth2 SNR3 , 5 Analog Input @ 10MHz Analog Input @ 21MHz Analog Input @ 37MHz SINAD3,6 Analog Input @ 10MHz Diff Analog Input @ 21MHz Analog Input @ 37MHz 1 2,3 1 2,3 -2.2 -2.2 -1.0 -1.7 -5.0 -1.0 -3.0 Guaranteed 2.2 1.0 0.5 .05 2.0 .01 1.0 Bits Full +25C Full Full +25C Full +25C Full Offset Error Channel Match Gain Error1 1,2,3 1 2.3 Units +2.2 +2.2 +1.0 +0.2 +5.0 +1.0 +3.0 0.5 1.0 12 12 99 198 100 200 V V 101 202 0.4 80 20 12 1.5 250 0.3 6.25 6.25 7.6 10 70 68 68.5 59 %FS %FS %FS %FS %FS % % 500 7 7 MSPS MSPS ns ps ps rms ns ns ns ns dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 2 TARGET SPECIFICATIONS AD13280 Electrical Characteristics (AVCC=5V; AVEE =-5V; DVCC=+3.3V applies to each ADC with Front-End Amplifier unless otherwise noted) Test Level Mil SubGroup Min +25C -40C +85C +25C -40C +85C +25C -40C +85C I II II I II II I II II 4 5 6 4 5 6 4 5 6 75 69 75 68 66 68 56 54 56 SINGLE-ENDED ANALOG INPUT Passband ripple to 10MHz Passband ripple to 25MHz +25C +25C DIFFERENTIAL ANALOG INPUT Passband ripple to 10MHz Passband ripple to 25MHz Parameter SPURIOUS-FREE DYNAMIC RANGE 3,7 Analog Input @ 10MHz Temp AD13280BZ Typ Max Units 80 dBFS 79 dBFS 62 dBFS V V .05 0.1 dB dB +25C +25C V V 0.3 .82 dB dB +25C -40C +85C +25C I II II V 4 5 6 4 80 dbc 77 dbc +25C V 4 60 dbc CHANNEL-TO-CHANNEL ISOLATION 9 +25C IV 12 TRANSIENT RESPONSE +25C V Analog Input @ 21MHz Analog Input @ 37MHz TWO-TONE LINEARITY8 f IN = 9.1MHz and 10.1MHz f 1 and f2 are -7dB f IN = 19.1MHz and 20.7MHz f 1 and f2 are -7dB f IN = 36MHz and 37MHz f 1 and f2 are -7dB DIGITAL OUTPUTS10 Logic Compatibility DVCC = +3.3V Logic "1" Voltage Logic "0" Voltage DVCC = +5V Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY AVCC Supply Voltage 12 I (AVCC) Current AVEE Supply Voltage 12 I (AVEE ) Current DVCC Supply Voltage 12 I (DVCC) Current I CC (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rjection Ratio (PSRR) 75 71 75 90 dB 25 nS CMOS Full Full I I Full Full V V Full Full Full Full Full Full Full Full Full IV I IV I IV I I I I 1,2,3 1,2,3 2.8 DVCC-0.2 0.2 0.5 DVCC-0.3 0.35 Two's Complement 4.75 1,2,3 -5.25 1,2,3 3.135 1,2,3 1,2,3 1,2,3 7,8 +5.0 294 -5.0 41 3.3V 34 369 3.57 0.001 NOTES 1. Gain tests are performed on AMP-IN-X-1input voltage range. 2. Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3dB. 3. All AC specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1Vpp, AMP-IN-X-2 = GND 4. Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50% 5%. 5. Analog Input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 80MSPS. SNR is reported in dBFS, related back to converter full scale. 6. Analog Input signal power at -1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80MSPS. SINAD is reported in dBFS, related back to converter full scale. 7. Analog Input signal at -1 dBFS; SFDR is ratio of converter fullscale to worst spur. 8. Both input tones at -7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. 9. Channel to Channel Isolation tested with A channel grounded and a Fullscale signal applied to B channel. 10. Digital output logic levels: DVCC = 3.3V, CLOAD = 10pF. Capacitive loads > 10pF will degrade performance. 11. For differential input: +IN = 1Vpp and -IN = 1Vpp (signals are 180 out of phase). For single-ended input: +IN = 2Vpp and = -IN = GND. 12. Supply voltage recommended operating range V V V V 5.25 308 -4.75 49 3.465 42 399 3.8 0.02 V mA V mA V mA mA W %FSR/%Vs Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 3 AD13280 ABSOLUTE MAXIMUM RATINGS1 Parameter ELECTRICAL 1 AVCC Voltage AVEE Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL 2 Operating Temperature (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Min Max Units 0 -7 0 VEE -10 0 7 0 7 VCC 10 VC C 4 10 V V V V mA V V mA +85 +175 +300 +150 C C C C -10 -40 -65 Notes: 1 Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for "Z" package: JC 2.2C/W; JA 24.3C/W TEST LEVEL I II III IV V VI 100% Production Tested 100% Production Tested at +25C, and sample tested at specified temperatures. AC testing done on sample basis Sample Tested only Parameter is guaranteed by design and characterization testing Parameter is a typical value only 100% production tested at temperature at 25C: sample tested at temperature extremes Ordering Guide Model AD13280BZ Temperature Range (case) -40 C to +85C Package Description 68-Lead Ceramic Leaded Chip Carrier Package Option* Z-68A AD13280BF -40 C to +85C 68-Lead Ceramic Leaded Chip Carrier with non-conductive tie-bar Z-68A 5962-005300HXA -40 C to +85C 68-Lead Ceramic Leaded Chip Carrier Z-68A AD13280/PCB +25C Evaluation Board with AD13280BZ Caution: ESD (electrostatic discharge) senstive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD13280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 4 AD13280 PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1, 35 2,3,9,10,13,16 4 5 6 7 8 11 12 14 15 17 18,19,37,38 20-25, 28-33 26,27 34 36 39-42,45-52 43,44 53 54,57,60,61,67,68 55 56 58 59 62 63 64 65 66 SHIELD AGNDA A-IN A+IN AMP-OUT-A AMP-IN-A-1 AMP-IN-A-2 -5VAA AVC C ENCODEA ENCODEA DVC C NC D0A-D11A DNGDA DROUTA DROUTB D0B-D11B DGNDB DVC C AGNDB ENCODEB ENCODEB -5VAB AVC C AMP-IN-B-2 AMP-IN-B-1 AMP-OUT-B B+IN B-IN Internal Ground Shield between channels A Channel Analog Ground. A and B grounds should be connected as close to the device as possible Inverting Differential Input (Gain = 1) Non-Inverting Differential Input (Gain = 1) Single-ended amplifier output (Gain = 2) Analog Input for A side ADC (nominally 0.5V) Analog Input for A side ADC (nominally 1.0V) Analog Negative Supply Voltage (nominally -5.0V or -5.2V) Analog Positive Supply Voltage (nominally +5.0V) Complement of Encode; differential input Encode Input; conversion initiated on rising edge Digital Positive Supply Voltage (nominally +5.0V/+3.3V) No Connect Digital Outputs for ADC A. D0 (LSB) A Channel Digital Ground Data Ready A Output Data Ready B Output Digital Outputs for ADC B. D0 (LSB) B Channel Digital Ground Digital Positive Supply Voltage (nominally +5.0V/+3.3V) B Channel Analog Ground. A and B grounds should be connected as close to the device as possible Encode Input; conversion initiated on rising edge Complement of Encode; differential input Analog Negative Supply Voltage (nominally -5.0V or -5.2V) Analog Positive Supply Voltage (nominally +5.0V) Analog Input for B side ADC (nominally 1.0V) Analog Input for B side ADC (nominally 0.5V) Single-ended amplifier output (Gain = 2) Non-Inverting Differential Input (Gain = 1) Inverting Differential Input (Gain =1) AGNDA AMP-IN-A-2 AMP-IN-A-1 AMP-OUT-A A+IN A-IN AGNDA AGNDA SHIELD AGNDB AGNDB B-IN B+IN AMP-OUT-B AMP-IN-B-1 AMP-IN-B-2 AGNDB PIN CONFIGURATION 68-Lead Leaded Ceramic Chip Carrier 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 AGN DA 10 60 AGN DB P IN 1 59 -5VAB -5VAA 11 AV C C 12 58 AV CC AGN DA 13 57 EN CODEA 14 AGN DB 56 ENCODEB EN CODEA 1 5 55 ENCODEB AD13280 AGND A 16 54 D VC C 17 AGN DB 53 DV CC NC 1 8 52 D11B-MSB Top View (Not to Scale) NC 19 D0A (LSB) 20 51 D10B 50 D9B D 1A 21 49 D8B D 2A 22 48 D7B D 3A 23 47 D6B D 4A 2 4 46 D5B D5A 45 25 D4B 44 DGNDB 31 32 33 34 35 36 37 38 39 40 D6A D7A D8A D9A D10A D11A-MSB DROUTA SHIELD DROUTB NC D0B (LSB) D1B 41 42 43 DGNDB 30 D3B 29 D2B 28 NC 27 DGNDA DGNDA 26 Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 5 AD13280 Encode = 80MSPS Ain = 5MHz (-1dBFS) SNR = 69.4 dBFS SFDR = 81.9 dBc Encode = 80MSPS Ain = 10MHz (-1dBFS) SNR = 69.19 dBFS SFDR = 79.55 dBc TPC 1. Single Tone @ 5 MHz TPC 2. Single Tone @ 10 MHz Y R NA L I IM ICA L E HN R P EC TA T DA Encode = 80MSPS Ain = 20MHz (-1dBFS) SNR = 69.31 dBFS SFDR = 73.32 dBc TPC 3. Single Tone @ 20 MHz Encode = 80MSPS Ain = 37MHz (-1dBFS) SNR = 68.38 dBFS SFDR = 57.81 dBc TPC 4. Single Tone @ 37 MHz Encode = 80MSPS Ain = 9MHz & 10MHz (-7dBFS) SFDR = 82.77 dBc Encode = 80MSPS Ain = 19MHz & 20MHz (-7dBFS) SFDR = 74.41 dBc TPC 5. Two Tone @ 9/10 MHz TPC 6. Two Tone @ 19/20 MHz 6 Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. AD13280 Encode = 80MSPS DNL max = .688 Codes DNL min = .385 Codes Encode = 80MSPS INL max = .856Codes INL min = .873Codes Y R NA L I A M I C L NI E PR ECH TA T DA TPC 7. Differential Nonlinearity TPC 8. Integral Nonlinearity Encode = 80MSPS Roll-off = .0459db TPC 9. Passband Ripple to 25MHz 7 Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. AD13280 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a differential crossing of ENCODE and ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and defferential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. May be reported in dB (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. May be reported in dB (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Transient Response The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Differential Nonlinerity The deviation of any code from a ideal 1 LSB step. Encode Plus Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic "1" state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE command and the time when all output data bits are within valid logic levels. Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 8 AD13280 tA N + 3 N AIN N + 1 N + 2 N + 4 tE N C ENC, E N C tEN C H N tE N C L N +1 N + 2 N + 3 N + 4 tE _ D R N - 3 D[13:0] N - 2 tO D N - 1 N DRY Figure 1. Timing Diagram D VC C CU R REN T MI RR OR AMP-IN-X-1 100 D VC C VR E F AMP-IN-X-2 To AD8037 DR _O UT 100 C U RR EN T MIR R OR Figure 2. Single-Ended Input Stage Figure 3. Digital Output Stage DV CC CURRENT MIRROR LOADS AVCC A VCC A VCC AVCC 10k DV CC 10k VR EF D0-D11 ENCODE ENCODE 10k 100 10k LOADS Figure 4 . ENCODE Inputs CURRENT MIRROR Figure 5. Digital Output Stage Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 9 AD13280 THEORY OF OPERATION The AD13280 is a high-dynamic range 12-bit, 80MHz pipline delay (3 pipelines) analog-to-digital converter. The custom analog input section provides input ranges of 1 and 2 vp-p and input impedance configurations of 50, 100 and 200 ohms. The AD13280 employs four monolithic ADI components per channel (AD8037, AD8138, AD8031, and a custom ADC IC), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 12-bit analog-to-digital converter. In the single ended input configuration the input signal is passed through a precision laser trimmed resistor divider allowing the user to externally select operation with a full scale signal of 0.5V, or 1.0V by choosing the proper input terminal for the application. The result of the resistor divider is to apply a full-scale input approximately 0.4V to the non-inverting input of the internal AD8037 amplifier. The AD13280 analog input includes an AD8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifiers inputs and outputs. The AD8037 amplifier provides a high input impedance and gain for driving the AD8138 in a singleended to differential amplifier configuration. The AD8138 has a -3dB bandwidth at 300MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help balance the differential inputs to the custom ADC maximizing the performance of the device. The AD8031 provides the buffer for the internal reference analog-todigital comverter. The internal reference voltage of the custom ADC is designed to track the offsets and drifts and is used to ensure matching over an extended temperature range of operation. The reference voltage is connected to the output common mode input on the AD8138. This reference voltage sets the output common mode on the AD8138 at 2.4V, which is the mid-supply level for the ADC. The custom ADC has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4V and should swing 0.55V around this reference. Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2V peak-to-peak. Both analog inputs are buffered prior to the first track-and-hold. USING THE DIFFERENTIAL INPUT Each channel of the AD13280 was designed with two optional differential inputs, A+IN, A-IN and B+IN, B-IN. The inputs provide system designers with the ability to bypass the AD8037 amplifier and drive the AD8138 directly. The AD8138 differential ADC driver can be deployed in either a single-ended or differential input configuration. The differential analog inputs have a nominal input impedance of 620 ohms and nominal full-scale input range of 1.2Vp-p. The AD8138 amplifier drives a differential filter and the custom analog-to-digital converter. The differential input configuration provides the lowest even-order harmonics and signal-to-noise (SNR) performance improvement of up to 3dB (SNR = 73dBFS). Exceptional care was taken in the layout of the differential input signal paths. The differential input transmission line characteristics are matched and balanced. Equal attention to system level signal paths must be provided in order to realize significant performance improvements. APPLYING THE AD13280 Encoding the AD13280 The AD13280 encode signal must be a high quality, extremely low phase noise source, to prevent degradation of performance. Maintaining 12-bit accuracy at 80MSPS places a premium on encode clock phase noise. SNR performance can easily degrade 3 dB to 4 dB with 37MHz input signals when using a high-jitter clock source. See Analog Devices' Application Note AN-501, "Aperture Uncertainty and ADC System Performance" for complete details. For optimum performance, the AD13280 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Shown below is one preferred method for clocking the AD13280. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD13280 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD13280, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limited resistor (typically 100 ) is placed in the series with the primary. 0.1mF The custom ADC digital outputs drive 100 ohm series resistors (Figure 5.) The result is a 12-bit parallel digital CMOS-compatible word, coded as two's complement. USING THE SINGLE-ENDED INPUT The AD13280 has been designed with the user's ease of operation in mind. Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. The standard inputs are 0.5V and 1.0V. The user can select the input impedance of the AD13280 on any input by using the other inputs as alternate locations for the GND. The following chart summarizes the impedance options available at each input location. AMP-IN-X-1 = 100 when AMP-IN-X-2 open AMP-IN-X-1 = 50 when AMP-IN-X-2 is shorted to GND AMP-IN-X-2 = 200 when AMP-IN-X-1 open Each channel has two analog inputs AMP-IN-A-1 and AMP-IN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1 or AMP-IN-B-1 when an input of .5V fullscale is desired. Use AMP-IN-A-2 or AMPIN-B-2 when 1V fullscale is desired. Each channel has an AMP-OUT which must be tied to either a non-inverting or inverting input of a differential amplifier with the remaining input grounded. For example, Side A, AMP-OUT-A (Pin 6) must be tied to A+IN (Pin 5) with A-IN (Pin 5) tied to ground for non-inverting operation or AMP-OUT-A (pin 6) tied to A-IN (Pin 4) with A+IN (Pin 5) tied to ground for inverting operation. CLOCK SOURCE T1-4T ENCODE 100V AD13280 ENCODE HSMS2812 DIODES Figure 6: Crystal Clock Oscillator - Differential Encode If a low jitter ECL/PECL clock is available, another option is to accouple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola. VT 0.1mF ENCODE ECL/ PEC L AD13280 0.1m F ENCODE VT Figure 7. Differential ECL for Encode Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 10 AD13280 Jitter Consideration The signal-to-noise ratio (SNR) for any ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. 2 SNR = -20 x log (1 + ) 2N 1/2 VNOISE RMS 2N + (2 x x ANALOG x t j RMS) 2 + (1) fANALOG = analog input frequency tj RMS = rms jitter of the encode (rms sum of encode source and internal encode circuitry) = average DNL of the ADC (typically 0.50 LSB) N = Number of bits in the ADC VNOISE RMS = V rms noise referred to the analog input of the ADC (typically 5 LSB) For a 12-bit analog-to-digital converter like the AD13280, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD13280 as jitter increases. The chart is derived from the above equation. For a complete discussion of aperture jitter, please consult Analog Devices' Application Note AN-501, "Aperture Uncertainty and ADC System Performance. Power Supplies Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be "received" by the AD13280. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors. The AD13280 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5V. The AD13280 is specified for DVCC = 3.3V as this is a common supply for digital ASICs. Output Loading Care must be taken when designing the data receivers for the AD13280 . The digital outputs drive an internal series resistor (e.g. 100) followed by a gate like 75LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure. The digital outputs of the AD13280 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10pF. Therefore, as each bit switches, 10 mA (10 pF X 1 v /1 ns) of dynamic current per bit will flow in or out of the device. A full scale transition can cause up to 140 mA (14 bits X 10 mA/bit) of transient current through the output stages. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD13280. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads. AD13280 SNR vs. Clock Jitter 71.0 70.0 69.0 68.0 SNR (-dBFS) 67.0 66.0 65.0 64.0 63.0 62.0 61.0 60.0 59.0 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 58.0 Clock Jitter (ps) Ain = 5 MHz Ain = 10 MHz Ain = 20 MHz Ain = 37 MHz Figure 8. SNR vs Jitter Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 11 AD13280 LAYOUT INFORMATION The schematic of the evaluation board (Figure 9.) represents a typical implementation of the AD13280. The pinout of the AD13280 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. Care should be taken when placing the digital output runs. Because the digital outputs have such a high-slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate. EVALUATION BOARD The AD13280 evaluation board (Figure 10.) is designed to provide optimal performance for evaluation of the AD13280 analog-to-digital converter. The board encompasses everything needed to insure the highest level of performance for evaluating the AD13280. The board requires an analog input signal, encode clock and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and out clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD13280. The digital outputs of the AD13280 are powered via banana jacks with 3.3V. Contact the factory if additional layout or applications assistance is required. Figure 9. Evaluation Board Mechanical Layout Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 12 AD13280 Figure 10a. Evaluation Board Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 13 AD13280 Figure 10b. Evaluation Board Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 14 AD13280 Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 15 AD13280 Figure 11a. Top Silk Figure 11b. Top Layer Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 16 AD13280 Figure 11c. GND1 Figure 11d. GND2 Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 17 AD13280 Figure 11e. Bottom Silk Figure 11f. Bottom Layer Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 18 AD13280 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier (Z-68A) Y R NA L I IM ICA L E HN R P EC TA T DA Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission. 19 AD13280 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier with Non-Conductive Tie-Bar (Z-68A) Y R NA L I IM ICA L E HN R P EC TA T DA 20 Rev. Pr E This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.