5962-005300HXA - Analog Devices, Inc.

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

PRELIMINARY DATA AD13280

PERFORMANCE FEATURES

Dual, 80 MSPS minimum sample rate

- Channel-channel matching, +/-1% gain error

- 90dB Channel-Channel isolation

- DC-Coupled Signal conditioning

80dB Spurious-Free Dynamic Range

Selectable Bipolar Inputs

(+/- 1V and +/- 0.5V ranges)

Integral Single Pole Low Pass Nyquist Filter

Two’s Complement Output Format

3.3 or 5V CMOS-Compatible Outputs

1.75W per Channel

Industrial and Military Grade

APPLICATIONS

Radar Processing

(optimized for I/Q Baseband operation)

Phased Array Receivers

MultiChannel, Multimode Receivers

GPS Anti-Jamming Receivers

Communications Receivers

PRODUCT DESCRIPTION

The AD13280 is a complete dual channel signal process-

ing solution including on board amplifiers, references,

ADCs and output termination components to provide

optimized system performance. The AD13280 has on-

chip track-and-hold circuitry and utilizes an innovative

multipass architecture to achieve 12-bit, 80MSPS

performance. The AD13280 uses innovative high-density

circuit design and laser-trimmed thin-film resistor

networks to achieve exceptional channel matching, impedance

control, and performance while still maintaining excellent

isolation, and providing for significant board area savings.

Multiple options are provided for driving the analog input,

including single-ended, differential, and optional series filtering.

The AD13280 also offers the user a choice of Analog Input

Signal ranges to further minimize additional external signal

conditioning, while still remaining general purpose.

The AD13280 operates with +/- 5.0V for the Analog signal

conditioning with a separate +5.0V supply for the Analog to

Digital conversion, and +3.3V digital supply for the output

stage. Each channel is completely independent allowing

operation with independent Encode and Analog Inputs, and

maintaining minimal crosstalk and interference.

The AD13280 is packaged in a 68-lead Ceramic Gull Wing

Package. Manufacturing is done on Analog Devices, Inc. Mil-

38534 Qualified Manufacturers Line (QML) and components

are available up to Class-H (-40°C to 85°C). The components

are manufactured using Analog Devices, Inc. high-speed

complimentary bipolar process (XFCB).

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 80 MSPS.

2. Input signal conditioning included; gain and impedance

match

3. Single-ended, differential, or off-module filter options

4. Fully tested/characterized full channel performance

5. Compatible with 14-bit (up to) 80MSPS family

aDual Channel, 12-Bit, 80MSPS A/D Converter

with Analog Input Signal Conditioning

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recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

TARGET SPECIFICATIONS AD13280

Electrical Characteristics (AVCC=5V; AV EE=-5V; DVCC=+3.3V applies to each ADC with Front-End Amplifier unless otherwise noted.)

Mil AD13280BZ

Parameter Temp Test Sub- Min Typ Max Units

Level Group

RESOLUTION 12 Bits

DC ACCURACY3

No Missing Codes Full IV 1,2,3 Guaranteed

Offset Error +25°CI1-2.2 ±2.2 +2.2 %FS

Full VI 2.3 -2.2 ±1.0 +2.2 %FS

Offset Error Channel Match Full V-1.0 ±0.5 +1.0 %FS

Gain Error1+25°CI1-1.7 ±.05 +0.2 %FS

Full VI 2,3 -5.0 ±2.0 +5.0 %FS

Gain Error Channel Match +25°CI1-1.0 ±.01 +1.0 %

Full VI 2,3 -3.0 ±1.0 +3.0 %

SINGLE-ENDED ANALOG INPUT

Input Voltage Range

AMP-IN-X-1 Full V±0.5 V

AMP-IN-X-2 Full V±1.0 V

Input Resistance

AMP-IN-X-1 Full IV 12 99 100 101 Ω

AMP-IN-X-2 Full IV 12 198 200 202 Ω

Αnalog Input Bandwidth2Full V100 MHz

DIFFERENTIAL ANALOG INPUT

Analog Signal Input Range

A+IN to A-IN and B+IN to B-IN Full V±1 V

Input Impedance +25°CV618 Ω

Capacitance +25°CV7pF

Analog Input Bandwidth Full V50 MHz

ENCODE INPUT (ENC, ENC)3

Differential Input Voltage Full IV 12 0.4 VPP

Differential Input Resistance +25°CV10 KΩ

Differential Input Capacitance +25°CV2.5 pF

SWITCHING PERFORMANCE

Maximum Conversion Rate4Full VI 4,5,6 80 MSPS

Minimum Conversion Rate4Full IV 12 20 MSPS

Aperture Delay (tA)+25°CV1.5 ns

Aperture Delay Matching +25°CIV 12 250 500 ps

Aperture Uncertainty (Jitter) +25°CV0.3 ps rms

ENCODE Pulse Width High at Max Conversion Rate +25°CIV 12 4.75 6.25 7ns

ENCODE Pulse Width Low at Max Conversion Rate +25°CIV 12 4.75 6.25 7ns

Output Delay (tOD)Full V7.6 ns

Encode, Rising to Data Ready, Rising Delay Full V10 ns

SNR3,5

Analog Input @ 10MHz +25°CI468 70 dBFS

-40°CII 565 dBFS

+85°CII 668 dBFS

Analog Input @ 21MHz +25°CI467.5 70 dBFS

-40°CII 564 dBFS

+85°CII 667.5 dBFS

Analog Input @ 37MHz +25°CI463 68 dBFS

-40°CII 561 dBFS

+85°CII 663 dBFS

SINAD3,6

Analog Input @ 10MHz Diff +25°CI467.5 69 dBFS

-40°CII 564 dBFS

+85°CII 667.5 dBFS

Analog Input @ 21MHz +25°CI465 68.5 dBFS

-40°CII 563 dBFS

+85°CII 665 dBFS

Analog Input @ 37MHz +25°CI454 59 dBFS

-40°CII 552.5 dBFS

+85°CII 654 dBFS

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

TARGET SPECIFICATIONS AD13280

Electrical Characteristics (AVCC=5V; AV EE=-5V; DVCC=+3.3V applies to each ADC with Front-End Amplifier unless otherwise noted)

Mil AD13280BZ

Parameter Temp Test Sub- Min Typ Max Units

Level Group

SPURIOUS-FREE DYNAMIC RANGE3,7

Analog Input @ 10MHz +25°CI475 80 dBFS

-40°CII 569

+85°CII 675

Analog Input @ 21MHz +25°CI468 79 dBFS

-40°CII 566

+85°CII 668

Analog Input @ 37MHz +25°CI456 62 dBFS

-40°CII 554

+85°CII 656

SINGLE-ENDED ANALOG INPUT

Passband ripple to 10MHz +25°CV.05 dB

Passband ripple to 25MHz +25°CV0.1 dB

DIFFERENTIAL ANALOG INPUT

Passband ripple to 10MHz +25°CV0.3 dB

Passband ripple to 25MHz +25°CV.82 dB

TWO-TONE LINEARITY8

fIN = 9.1MHz and 10.1MHz +25°CI475 80 dbc

f1 and f2 are -7dB -40°CII 571

+85°CII 675

fIN = 19.1MHz and 20.7MHz +25°CV477 dbc

f1 and f2 are -7dB

fIN = 36MHz and 37MHz +25°CV460 dbc

f1 and f2 are -7dB

CHANNEL-TO-CHANNEL ISOLATION9+25°CIV 12 90 dB

TRANSIENT RESPONSE +25°CV25 nS

DIGITAL OUTPUTS10

Logic Compatibility CMOS

DVCC = +3.3V

Logic "1" Voltage Full I1,2,3 2.8 DVCC-0.2 V

Logic "0" Voltage Full I1,2,3 0.2 0.5 V

DVCC = +5V

Logic "1" Voltage Full VDVCC-0.3 V

Logic "0" Voltage Full V0.35 V

Output Coding Two's Complement

POWER SUPPLY

AVCC Supply Voltage12 Full IV 4.75 +5.0 5.25 V

I (AVCC) Current Full I1,2,3 294 308 mA

AVEE Supply Voltage12 Full IV -5.25 -5.0 -4.75 V

I (AVEE) Current Full I1,2,3 41 49 mA

DVCC Supply Voltage12 Full IV 3.135 3.3V 3.465 V

I (DVCC) Current Full I1,2,3 34 42 mA

ICC (Total) Supply Current per Channel Full I1,2,3 369 399 mA

Power Dissipation (Total) Full I1,2,3 3.57 3.8 W

Power Supply Rjection Ratio (PSRR) Full I7,8 0.001 0.02 %FSR/%Vs

NOTES

1. Gain tests are performed on AMP-IN-X-1input voltage range.

2. Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3dB.

3. All AC specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1Vpp, AMP-IN-X-2 = GND

4. Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50% ±5%.

5. Analog Input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed).

Encode = 80MSPS. SNR is reported in dBFS, related back to converter full scale.

6. Analog Input signal power at -1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics.

Encode = 80MSPS. SINAD is reported in dBFS, related back to converter full scale.

7. Analog Input signal at -1 dBFS; SFDR is ratio of converter fullscale to worst spur.

8. Both input tones at -7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product.

9. Channel to Channel Isolation tested with A channel grounded and a Fullscale signal applied to B channel.

10. Digital output logic levels: DVCC = 3.3V, CLOAD = 10pF. Capacitive loads > 10pF will degrade performance.

11. For differential input: +IN = 1Vpp and -IN = 1Vpp (signals are 180° out of phase). For single-ended input: +IN = 2Vpp and = -IN = GND.

12. Supply voltage recommended operating range

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

Caution: ESD (electrostatic discharge) senstive device. Electrostatic charges as high

as 4000 V readily accumulate on the human body and test equipment and can discharge

without detection. Although the AD13280 features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high energy electrostatic discharges.

Therefore, proper ESD precautions are recommended to avoid performance degradation

or loss of functionality.

ABSOLUTE MAXIMUM RATINGS1

Parameter Min Max Units

ELECTRICAL1

AVCC Voltage 0 7 V

AVEE Voltage -7 0V

DVCC Voltage 0 7 V

Analog Input Voltage VEE VCC V

Analog Input Current -10 10 mA

Digital Input Voltage (ENCODE) 0VCC V

ENCODE, ENCODE Differential Voltage 4V

Digital Output Current -10 10 mA

ENVIRONMENTAL2

Operating Temperature (Case) -40 +85 °C

Maximum Junction Temperature +175 °C

Lead Temperature (Soldering, 10 sec) +300 °C

Storage Temperature Range (Ambient) -65 +150 °C

Notes:

1Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired.

Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect

device reliability.

2Typical thermal impedance for "Z" package: θJC 2.2°C/W; θJA 24.3°C/W

TEST LEVEL

I100% Production Tested

II 100% Production Tested at +25°C, and sample tested at specified temperatures. AC testing done on sample basis

III Sample Tested only

IV Parameter is guaranteed by design and characterization testing

VParameter is a typical value only

VI 100% production tested at temperature at 25°C: sample tested at temperature extremes

AD13280

Ordering Guide

Temperature Package Package

Model Range (case) Description Option*

AD13280BZ -40°C to +85°C68-Lead Ceramic Z-68A

Leaded Chip Carrier

AD13280BF -40°C to +85°C68-Lead Ceramic Z-68A

Leaded Chip Carrier

with non-conductive

tie-bar

5962-005300HXA -40°C to +85°C68-Lead Ceramic Z-68A

Leaded Chip Carrier

AD13280/PCB +25°C Evaluation Board

with AD13280BZ

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recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

PIN CONFIGURATION

68-Lead Leaded Ceramic Chip Carrier

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1, 35 SHIELD Internal Ground Shield between channels

2,3,9,10,13,16 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible

4A-IN Inverting Differential Input (Gain = 1)

5A+IN Non-Inverting Differential Input (Gain = 1)

6AMP-OUT-A Single-ended amplifier output (Gain = 2)

7AMP-IN-A-1 Analog Input for A side ADC (nominally ± 0.5V)

8AMP-IN-A-2 Analog Input for A side ADC (nominally ± 1.0V)

11 -5VAA Analog Negative Supply Voltage (nominally -5.0V or -5.2V)

12 AVCC Analog Positive Supply Voltage (nominally +5.0V)

14 ENCODEA Complement of Encode; differential input

15 ENCODEA Encode Input; conversion initiated on rising edge

17 DVCC Digital Positive Supply Voltage (nominally +5.0V/+3.3V)

18,19,37,38 NC No Connect

20-25, 28-33 D0A-D11A Digital Outputs for ADC A. D0 (LSB)

26,27 DNGDA A Channel Digital Ground

34 DROUTA Data Ready A Output

36 DROUTB Data Ready B Output

39-42,45-52 D0B-D11B Digital Outputs for ADC B. D0 (LSB)

43,44 DGNDB B Channel Digital Ground

53 DVCC Digital Positive Supply Voltage (nominally +5.0V/+3.3V)

54,57,60,61,67,68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device as possible

55 ENCODEB Encode Input; conversion initiated on rising edge

56 ENCODEB Complement of Encode; differential input

58 -5VAB Analog Negative Supply Voltage (nominally -5.0V or -5.2V)

59 AVCC Analog Positive Supply Voltage (nominally +5.0V)

62 AMP-IN-B-2 Analog Input for B side ADC (nominally ± 1.0V)

63 AMP-IN-B-1 Analog Input for B side ADC (nominally ± 0.5V)

64 AMP-OUT-B Single-ended amplifier output (Gain = 2)

65 B+IN Non-Inverting Differential Input (Gain = 1)

66 B-IN Inverting Differential Input (Gain =1)

AD13280

123456789 6768 6566 6364 6162

3736 3938 4140 43422827 3029 3231 3433 35

H I

GN D A

GN D B

DGNDB

D GN D B

D0A(LSB)

AGNDA

- I

GN D A

AGNDA

-5VAA

GN D B

AGNDB

ENCODEA

D2A

D3A

D4A

D5A

D 6

D 7

D 8

D 9

D 1

D GN D A

D 0

( L

)

D 1

D 2

D 3

D4B

D5B

D6B

D7B

D8B

D11B-MSB

D10B

D9B

AD13280

Top View

(Not toScale)

PIN1

D1A

+ I

- O U T - A

- I

N - A

-1

- I

N - A

-2

ENCODEA

DGNDA

D 1

- M

D R O U T A

H I

D R O U T B

N C

AGNDB

-5VAB

ENCODEB

AVCC

ENCODEB

GN D B

-I

+ I

-O U T - B

-I

N -B

- 1

- I

N - B

-2

AVCC

DVCC DVCC

AD13280

TPC 1. Single Tone @ 5 MHz TPC 2. Single Tone @ 10 MHz

TPC 3. Single Tone @ 20 MHz TPC 4. Single Tone @ 37 MHz

Encode = 80MSPS

Ain = 5MHz (-1dBFS)

SNR = 69.4 dBFS

SFDR = 81.9 dBc

TPC 6. Two Tone @ 19/20 MHzTPC 5. Two Tone @ 9/10 MHz

Encode = 80MSPS

Ain = 10MHz (-1dBFS)

SNR = 69.19 dBFS

SFDR = 79.55 dBc

Encode = 80MSPS

Ain = 20MHz (-1dBFS)

SNR = 69.31 dBFS

SFDR = 73.32 dBc

Encode = 80MSPS

Ain = 37MHz (-1dBFS)

SNR = 68.38 dBFS

SFDR = 57.81 dBc

Encode = 80MSPS

Ain = 19MHz & 20MHz (-7dBFS)

SFDR = 74.41 dBc

Encode = 80MSPS

Ain = 9MHz & 10MHz (-7dBFS)

SFDR = 82.77 dBc

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

PRELIMINARY

TECHNICAL

DATA

AD13280

TPC 8. Integral Nonlinearity

TPC 9. Passband Ripple to 25MHz

TPC 7. Differential Nonlinearity

Encode = 80MSPS

DNL max = .688 Codes

DNL min = .385 Codes

Encode = 80MSPS

INL max = .856Codes

INL min = .873Codes

Encode = 80MSPS

Roll-off = .0459db

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

PRELIMINARY

TECHNICAL

DATA

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

AD13280

DEFINITION OF SPECIFICATIONS

Analog Bandwidth

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Aperture Delay

The delay between a differential crossing of ENCODE and

ENCODE command and the instant at which the analog input is

sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog

Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog input

port. The resistance is measured statically and the capacitance

and defferential input impedances are measured with a network

analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the

converter to generate a full-scale response. Peak differential

voltage is computed by observing the voltage from the other pin,

which is 180 degrees out of phase. Peak-to-peak differential is

computed by rotating the inputs phase 180 degrees and taking

the peak measurement again. The difference is then computed

between both peak measurements.

Differential Nonlinerity

The deviation of any code from a ideal 1 LSB step.

Encode Plus Width/Duty Cycle

Pulse width high is the minimum amount of time that the

ENCODE pulse should be left in logic “1” state to achieve rated

performance; pulse width low is the minimum time ENCODE

pulse should be left in low state. At a given clock rate, these

specs define an acceptable Encode duty cycle.

Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the

worst harmonic component.

Integral Nonlinearity

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a “best straight line”

determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed

limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and

ENCODE command and the time when all output data bits are

within valid logic levels.

Overvoltage Recovery Time

The amount of time required for the converter to recover to

0.02% accuracy after an analog input signal of the specified

percentage of full scale is reduced to midscale.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in power

supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to

the rms value of the sum of all other spectral components, including

harmonics but excluding dc. May be reported in dB (i.e., degrades

as signal level is lowered) or in dBFS (always related back to

converter full scale).

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to

the rms value of the sum of all other spectral components, excluding

the first five harmonics and dc. May be reported in dB (i.e.,

degrades as signal level is lowered) or in dBFS (always related back

to converter full scale).

Spurious-Free Dynamic Range

The ratio of the rms signal amplitude to the rms value of the peak

spurious spectral component. The peak spurious component may or

may not be a harmonic.

Transient Response

The time required for the converter to achieve 0.02% accuracy when

a one-half full-scale step function is applied to the analog input.

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of the

worst third order intermodulation product; reported in dBc.

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

AD13280

Figure 2. Single-Ended Input Stage Figure 3. Digital Output Stage

Figure 4 . ENCODE Inputs Figure 5. Digital Output Stage

Figure 1. Timing Diagram

LOADS

10kΩ

ENCODE

10kΩ

ENCODE

AVCC AVCC

AVCC

VREF

DVCC

CURRENT

MIRROR

DR_OUT

CURRENT

MIRROR

VREF

DVCC

CURRENT

MIRROR

D0-D11

CURRENT

MIRROR

100Ω

ENC, ENC

D[13:0]

DRY

N - 1 NN - 2N - 3

tOD

tE_DR

tEN C tENCHtENCL

N +1N N + 2N + 3N + 4

AIN

N + 1

N + 2

N + 3

N + 4

100Ω

ToAD8037

AMP-IN-X-1

AMP-IN-X-2

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recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

THEORY OF OPERATION

The AD13280 is a high-dynamic range 12-bit, 80MHz pipline delay (3

pipelines) analog-to-digital converter. The custom analog input section

provides input ranges of 1 and 2 vp-p and input impedance configura-

tions of 50, 100 and 200 ohms.

The AD13280 employs four monolithic ADI components per channel

(AD8037, AD8138, AD8031, and a custom ADC IC), along with

multiple passive resistor networks and decoupling capacitors to fully

integrate a complete 12-bit analog-to-digital converter.

In the single ended input configuration the input signal is passed

through a precision laser trimmed resistor divider allowing the user to

externally select operation with a full scale signal of ±0.5V, or ±1.0V by

choosing the proper input terminal for the application. The result of the

resistor divider is to apply a full-scale input approximately 0.4V to the

non-inverting input of the internal AD8037 amplifier.

The AD13280 analog input includes an AD8037 amplifier featuring an

innovative architecture that maximizes the dynamic range capability on

the amplifiers inputs and outputs. The AD8037 amplifier provides a

high input impedance and gain for driving the AD8138 in a single-

ended to differential amplifier configuration. The AD8138 has a -3dB

bandwidth at 300MHz and delivers a differential signal with the lowest

harmonic distortion available in a differential amplifier. The AD8138

differential outputs help balance the differential inputs to the custom

ADC maximizing the performance of the device.

The AD8031 provides the buffer for the internal reference analog-to-

digital comverter. The internal reference voltage of the custom ADC is

designed to track the offsets and drifts and is used to ensure matching

over an extended temperature range of operation. The reference voltage

is connected to the output common mode input on the AD8138. This

reference voltage sets the output common mode on the AD8138 at 2.4V,

which is the mid-supply level for the ADC.

The custom ADC has complementary analog input pins, AIN and AIN.

Each analog input is centered at 2.4V and should swing ±0.55V around

this reference. Since AIN and AIN are 180 degrees out of phase, the

differential analog input signal is 2.2V peak-to-peak. Both analog

inputs are buffered prior to the first track-and-hold.

The custom ADC digital outputs drive 100 ohm series resistors (Figure

5.) The result is a 12-bit parallel digital CMOS-compatible word, coded

as two’s complement.

USING THE SINGLE-ENDED INPUT

The AD13280 has been designed with the user’s ease of operation in

mind. Multiple input configurations have been included on board to

allow the user a choice of input signal levels and input impedance. The

standard inputs are ±0.5V and ±1.0V. The user can select the input

impedance of the AD13280 on any input by using the other inputs as

alternate locations for the GND. The following chart summarizes the

impedance options available at each input location.

AMP-IN-X-1 = 100Ω when AMP-IN-X-2 open

AMP-IN-X-1 = 50Ω when AMP-IN-X-2 is shorted to GND

AMP-IN-X-2 = 200Ω when AMP-IN-X-1 open

Each channel has two analog inputs AMP-IN-A-1 and AMP-IN-A-2 or

AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1 or AMP-IN-B-1

when an input of ±.5V fullscale is desired. Use AMP-IN-A-2 or AMP-

IN-B-2 when ±1V fullscale is desired. Each channel has an AMP-OUT

which must be tied to either a non-inverting or inverting input of a

differential amplifier with the remaining input grounded. For example,

Side A, AMP-OUT-A (Pin 6) must be tied to A+IN (Pin 5) with A-IN

(Pin 5) tied to ground for non-inverting operation or AMP-OUT-A (pin

6) tied to A-IN (Pin 4) with A+IN (Pin 5) tied to ground for inverting

operation.

AD13280

USING THE DIFFERENTIAL INPUT

Each channel of the AD13280 was designed with two optional

differential inputs, A+IN, A-IN and B+IN, B-IN. The inputs provide

system designers with the ability to bypass the AD8037 amplifier and

drive the AD8138 directly. The AD8138 differential ADC driver can be

deployed in either a single-ended or differential input configuration.

The differential analog inputs have a nominal input impedance of 620

ohms and nominal full-scale input range of 1.2Vp-p. The AD8138

amplifier drives a differential filter and the custom analog-to-digital

converter. The differential input configuration provides the lowest

even-order harmonics and signal-to-noise (SNR) performance

improvement of up to 3dB (SNR = 73dBFS). Exceptional care was

taken in the layout of the differential input signal paths. The differential

input transmission line characteristics are matched and balanced. Equal

attention to system level signal paths must be provided in order to

realize significant performance improvements.

APPLYING THE AD13280

Encoding the AD13280

The AD13280 encode signal must be a high quality, extremely low

phase noise source, to prevent degradation of performance. Maintaining

12-bit accuracy at 80MSPS places a premium on encode clock phase

noise. SNR performance can easily degrade 3 dB to 4 dB with 37MHz

input signals when using a high-jitter clock source. See Analog

Devices’ Application Note AN-501, “Aperture Uncertainty and ADC

System Performance” for complete details. For optimum performance,

the AD13280 must be clocked differentially. The encode signal is

usually ac-coupled into the ENCODE and ENCODE pins via a

transformer or capacitors. These pins are biased internally and require

no additional bias.

Shown below is one preferred method for clocking the AD13280. The

clock source (low jitter) is converted from single-ended to differential

using an RF transformer. The back-to-back Schottky diodes across the

transformer secondary limit clock excursions into the AD13280 to

approximately 0.8 V p-p differential. This helps prevent the large

voltage swings of the clock from feeding through to the other portions

of the AD13280, and limits the noise presented to the ENCODE inputs.

A crystal clock oscillator can also be used to drive the RF transformer if

an appropriate limited resistor (typically 100Ω ) is placed in the series

with the primary.

Figure 6: Crystal Clock Oscillator - Differential Encode

If a low jitter ECL/PECL clock is available, another option is to ac-

couple a differential ECL/PECL signal to the encode input pins as

shown below. A device that offers excellent jitter performance is the

MC100LVEL16 (or same family) from Motorola.

Figure 7. Differential ECL for Encode

ENCODE

AD13280

T1-4T

HSMS2812

CLOCK

SOURCE

0.1mF

100V

ENCODE

ENCODEAD13280

0.1mF

ECL/

PECL

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AD13280

Jitter Consideration

The signal-to-noise ratio (SNR) for any ADC can be predicted. When

normalized to ADC codes, Equation 1 accurately predicts the SNR

based on three terms. These are jitter, average DNL error, and thermal

noise. Each of these terms contributes to the noise within the converter.

SNR = -20 x log + (2 x

x t

j RMS

)

(1 +

)

NOISE RMS

2½

(1)

SNR = -20 x log + (2 x

ANALOG

x t

j RMS

)

(1 +

)

(1 +

)

NOISE RMS

2½

(1)

SNR = -20 x log + (2 x

x t

j RMS

)

(1 +

)

NOISE RMS

2½

(1)

SNR = -20 x log + (2 x

ANALOG

x t

j RMS

)

(1 +

)

(1 +

)

NOISE RMS

2½

(1)

fANALOG = analog input frequency

tj RMS = rms jitter of the encode (rms sum of encode

source and internal encode circuitry)

ε= average DNL of the ADC (typically 0.50 LSB)

N= Number of bits in the ADC

VNOISE RMS = V rms noise referred to the analog

input of the ADC (typically 5 LSB)

For a 12-bit analog-to-digital converter like the AD13280, aperture jitter

can greatly affect the SNR performance as the analog frequency is

increased. The chart below shows a family of curves that demonstrates

the expected SNR performance of the AD13280 as jitter increases. The

chart is derived from the above equation.

For a complete discussion of aperture jitter, please consult Analog

Devices' Application Note AN-501, "Aperture Uncertainty and ADC

System Performance.

Figure 8. SNR vs Jitter

Power Supplies

Care should be taken when selecting a power source. Linear supplies

are strongly recommended. Switching supplies tend to have radiated

components that may be "received" by the AD13280. Each of the

power supply pins should be decoupled as closely to the package as

possible using 0.1 µF chip capacitors.

The AD13280 has separate digital and analog power supply pins. The

analog supplies are denoted AVCC and the digital supply pins are

denoted DVCC. AVCC and DV CC should be separate power supplies.

This is because the fast digital output swings can couple switching

current back into the analog supplies. Note that AVCC must be held

within 5% of 5V. The AD13280 is specified for DVCC = 3.3V as this is

a common supply for digital ASICs.

Output Loading

Care must be taken when designing the data receivers for the AD13280 .

The digital outputs drive an internal series resistor (e.g. 100Ω) followed

by a gate like 75LCX574. To minimize capacitive loading, there should

only be one gate on each output pin. An example of this is shown in the

evaluation board schematic shown in Figure. The digital outputs of the

AD13280 have a constant output slew rate of 1 V/ns. A typical CMOS

gate combined with a PCB trace will have a load of approximately

10pF. Therefore, as each bit switches, 10 mA (10 pF X 1 v ÷ 1ns) of

dynamic current per bit will flow in or out of the device. A full scale

transition can cause up to 140 mA (14 bits X 10 mA/bit) of transient

current through the output stages. These switching currents are

confined between ground and the DVCC pin. Standard TTL gates should

be avoided since they can appreciably add to the dynamic switching

currents of the AD13280. It should also be noted that extra capacitive

loading will increase output timing and invalidate timing specifications.

Digital output timing is guaranteed with 10 pF loads.

AD13280 SNR vs. Clock Jitter

58.0

59.0

60.0

61.0

62.0

63.0

64.0

65.0

66.0

67.0

68.0

69.0

70.0

71.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

Clock Jitter (ps)

SNR (-dBFS)

Ain = 5 MHz Ain = 10 MHz Ain = 20 MHz Ain = 37 MHz

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

LAYOUT INFORMATION

The schematic of the evaluation board (Figure 9.) represents a typical

implementation of the AD13280. The pinout of the AD13280 is very

straightforward and facilitates ease of use and the implementation of

high frequency/high resolution design practices. It is recommended that

high quality ceramic chip capacitors be used to decouple each supply

pin to ground directly at the device. All capacitors can be standard high

quality ceramic chip capacitors.

Care should be taken when placing the digital output runs. Because the

digital outputs have such a high-slew rate, the capacitive loading on the

digital outputs should be minimized. Circuit traces for the digital

outputs should be kept short and connect directly to the receiving gate.

Internal circuitry buffers the outputs of the ADC through a resistor

network to eliminate the need to externally isolate the device from the

receiving gate.

EVALUATION BOARD

The AD13280 evaluation board (Figure 10.) is designed to provide

optimal performance for evaluation of the AD13280 analog-to-digital

converter. The board encompasses everything needed to insure the

highest level of performance for evaluating the AD13280. The board

requires an analog input signal, encode clock and power supply inputs.

The clock is buffered on-board to provide clocks for the latches. The

digital outputs and out clocks are available at the standard 40-pin

connectors J1 and J2.

Power to the analog supply pins is connected via banana jacks. The

analog supply powers the associated components and the analog section

of the AD13280. The digital outputs of the AD13280 are powered via

banana jacks with 3.3V. Contact the factory if additional layout or

applications assistance is required.

AD13280

Figure 9. Evaluation Board Mechanical Layout

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AD13280

Figure 10a. Evaluation Board

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Rev. Pr E

AD13280

Figure 10b. Evaluation Board

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recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

AD13280

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recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

AD13280

Figure 11a. Top Silk

Figure 11b. Top Layer

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AD13280

Figure 11c. GND1

Figure 11d. GND2

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AD13280

Figure 11e. Bottom Silk

Figure 11f. Bottom Layer

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recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E

PRELIMINARY

TECHNICAL

DATA

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Ceramic Leaded Chip Carrier

(Z-68A)

AD13280

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Ceramic Leaded Chip Carrier with Non-Conductive Tie-Bar

(Z-68A)

AD13280

PRELIMINARY

TECHNICAL

DATA

This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most

recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

Rev. Pr E