MT16VDDT12864AY-262XX - Micron Technology, Inc.

‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

pdf: 09005aef80739fa5, source: 09005aef807397e5

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

DDR SDRAM

UNBUFFERED DIMM

MT16VDDT3264A – 256MB

MT16VDDT6464A – 512MB

MT16VDDT12864A – 1GB

MT16VDDT25664A – 2GB

(

ADVANCE

)

‡

For the latest data sheet, please refer to the Micron Web

site: www.micron.com/products/modules

Features

• 184-pin, dual in-line memory module (DIMM)

• Fast data transfer rates: PC2100 or PC2700

• Utilizes 266 MT/s and 333 MT/s DDR SDRAM

components

• 256MB (32 Meg x 64), 512MB (64 Meg x 64), 1GB

(128 Meg x 64), and 2GB (256 Meg x 64)

•V

DD = VDDQ = +2.5V

•V

DDSPD = +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data—i.e., source-synchronous data

capture

• Differential clock inputs (CK and CK#)

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.6µs (256MB), 7.8125µs (512MB, 1GB, and 2GB)

maximum average periodic refresh interval

• Serial Presence Detect (SPD) with EEPROM

• Programmable READ CAS latency

• Gold edge contacts

Figure 1: 184-Pin DIMM (MO-206)

NOTE: 1. Consult Micron for product availability.

2. CL = CAS (READ) Latency.

OPTIONS MARKING

•Package

184-pin DIMM (standard) G

184-pin DIMM (lead-free)1Y

• Memory Clock, Speed, CAS Latency2

6ns/166MHz (333 MT/s) CL = 2.5 -335

7.5ns/133 MHz (266 MT/s) CL = 2 -2621

7.5ns/133 MHz (266 MT/s) CL = 2 -26A1

7.5ns/133 MHz (266 MT/s) CL = 2.5 -265

•PCB

Standard 1.25in. (31.75mm) See page 2 note

Low-Profile 1.20in. (30.48mm) See page 2 note

Standard 1.25in. (31.75mm)

Low-Profile 1.15in. (29.21mm)

Table 1: Address Table

256MB 512MB 1GB 2GB

Refresh Count 4K 8K 8K 8K

Row Addressing 4K (A0–A11) 8K (A0–A12) 8K (A0–A12) 16K (A0–A13)

Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Device Configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)

Column Addressing 1K (A0–A9) 1K (A0–A9) 2K (A0–A9, A11) 2K (A0–A9, A11)

Module Rank Addressing 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#)

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 2: Part Numbers and Timing Parameters

PART NUMBER MODULE

DENSITY

CONFIGURATION MODULE

BANDWIDTH

MEMORY CLOCK/

DATA RATE

LATENCY

(CL - tRCD - tRP)

MT16VDDT3264AG-335__ 256MB 32 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3

MT16VDDT3264AY-335__ 256MB 32 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3

MT16VDDT3264AG-262__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT16VDDT3264AY-262__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT16VDDT3264AG-26A__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT16VDDT3264AY-26A__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT16VDDT3264AG-265__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT16VDDT3264AY-265__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT16VDDT6464AG-335__ 512MB 64 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3

MT16VDDT6464AY-335__ 512MB 64 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3

MT16VDDT6464AG-262__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT16VDDT6464AY-262__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT16VDDT6464AG-26A__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT16VDDT6464AY-26A__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT16VDDT6464AG-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT16VDDT6464AY-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT16VDDT12864AG-335__ 1GB 128 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3

MT16VDDT12864AY-335__ 1GB 128 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3

MT16VDDT12864AG-262__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT16VDDT12864AY-262__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT16VDDT12864AG-26A__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT16VDDT12864AY-26A__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT16VDDT12864AG-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT16VDDT12864AY-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT16VDDT25664AG-335__ 2GB 256 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3

MT16VDDT25664AY-335__ 2GB 256 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3

MT16VDDT25664AG-262__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT16VDDT25664AY-262__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT16VDDT25664AG-26A__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT16VDDT25664AY-26A__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT16VDDT25664AG-265__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT16VDDT25664AY-265__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for

current revision codes. Example: MT16VDDT6464AG-265A1.

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Pin 115 is No Connect for 256MB, or A12 for 512MB, 1GB, 2GB.

2. Pin 167 is No Connect (NC) for 256MB, 512MB, and 1GB, or A13 for 2GB.

Figure 2: Pin Locations: 184-Pin DIMM

Table 3: Pin Assignment

(184-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 24 DQ17 47 DNU 70 VDD

2DQ025 DQS2 48 A0 71 NC

3VSS 26 VSS 49 DNU 72 DQ48

4DQ127 A9 50 VSS 73 DQ49

5DQS028 DQ18 51 DNU 74 VSS

6DQ229 A7 52 BA1 75 CK2#

DD 30 VDDQ 53 DQ32 76 CK2

8 DQ3 31 DQ19 54 VDDQ 77 VDDQ

9NC32 A5 55 DQ33 78 DQS6

10 NC 33 DQ24 56 DQS4 79 DQ50

11 VSS 34 VSS 57 DQ34 80 DQ51

12 DQ8 35 DQ25 58 VSS 81 VSS

13 DQ9 36 DQS3 59 BA0 82 NC

14 DQS1 37 A4 60 DQ35 83 DQ56

15 VDDQ 38 VDD 61 DQ40 84 DQ57

16 CK1 39 DQ26 62 VDDQ 85 VDD

17 CK1# 40 DQ27 63 WE# 86 DQS7

18 VSS 41 A2 64 DQ41 87 DQ58

19 DQ10 42 VSS 65 CAS# 88 DQ59

20 DQ11 43 A1 66 VSS 89 VSS

21 CKE0 44 DNU 67 DQS5 90 NC

22 VDDQ 45 DNU 68 DQ42 91 SDA

23 DQ16 46 VDD 69 DQ43 92 SCL

Table 4: Pin Assignment

(184-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

93 VSS 116 VSS 139 VSS 162 DQ47

94 DQ4 117 DQ21 140 DNU 163 NC

95 DQ5 118 A11 141 A10 164 VDDQ

96 VDDQ 119 DM2 142 DNU 165 DQ52

97 DM0 120 VDD 143 VDDQ 166 DQ53

98 DQ6 121 DQ22 144 DNU 1672NC/A13

99 DQ7 122 A8 145 VSS 168 VDD

100 VSS 123 DQ23 146 DQ36 169 DM6

101 NC 124 VSS 147 DQ37 170 DQ54

102 NC 125 A6 148 VDD 171 DQ55

103 NC 126 DQ28 149 DM4 172 VDDQ

104 VDDQ 127 DQ29 150 DQ38 173 NC

105 DQ12 128 VDDQ 151 DQ39 174 DQ60

106 DQ13 129 DM3 152 VSS 175 DQ61

107 DM1 130 A3 153 DQ44 176 VSS

108 VDD 131 DQ30 154RAS#177DM7

109 DQ14 132 VSS 155 DQ45 178 DQ62

110 DQ15 133 DQ31 156 VDDQ 179 DQ63

111 CKE1 134 DNU 157 S0# 180 VDDQ

112 VDDQ 135 DNU 158 S1# 181 SA0

113 NC 136 VDDQ 159 DM5 182 SA1

114 DQ20 137 CK0 160 VSS 183 SA2

115 NC/A12 138 CK0# 161 DQ46 184 VDDSPD

U1 U2 U3 U4 U6 U7 U8 U9

U19 U18 U17 U16 U14 U13 U12 U11

U10

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1 PIN 52 PIN 53 PIN 92

Front View

Back View

Indicates a VDD or VDDQ pin Indicates a VSS pin

Low-Profile 1.15in. (29.21mm)

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1 PIN 52 PIN 53 PIN 92

Indicates a VDD or VDDQ pin Indicates a VSS pin

Front View

Back View

U1 U2 U3 U4 U6 U7 U8 U9

U19

U10 U11 U12 U13 U15 U16 U17 U18

Standard 1.25in. (31.75mm)

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

63, 65, 154 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

16, 17, 75, 76, 137, 138 CK0, CK0#, CK1,

CK1#, CK2, CK2#

Input Clock: CK, CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the

positive edge of CK,and negative edge of CK#. Output data

(DQs and DQS) is referenced to the crossings of CK and CK#.

21, 111 CKE0, CKE1 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates

the internal clock, input buffers and output drivers. Taking

CKE LOW provides PRECHARGE POWER-DOWN and SELF

REFRESH operations (all device banks idle), or ACTIVE POWER-

DOWN (row ACTIVE in any device bank). CKE is synchronous

for POWER-DOWN entry and exit, and for SELF REFRESH entry.

CKE is asynchronous for SELF REFRESH exit and for disabling

the outputs. CKE must be maintained HIGH throughout read

and write accesses. Input buffers (excluding CK, CK# and CKE)

are disabled during POWER-DOWN. Input buffers (excluding

CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input

but will detect an LVCMOS LOW level after VDD is applied and

until CKE is first brought HIGH. After CKE is brought HIGH, it

becomes an SSTL_2 input only.

157, 158 S0#, S1# Input Chip Selects: S# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when S# is registered HIGH. S# is considered part of

the command code.

52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied.

27, 29, 32, 37, 41, 43, 48,

115 (512MB, 1GB, 2GB), 118,

122, 125, 130, 141, 167 (2GB)

A0–A11

(256MB)

A0–A12

(512MB, 1GB)

A0–A13

(2GB)

Input Address Inputs: Provide the row address for ACTIVE

commands, and the column address and auto precharge bit

(A10) for READ/WRITE commands, to select one location out of

the memory array in the respective device bank. A10 sampled

during a PRECHARGE command determines whether the

PRECHARGE applies to one device bank (A10 LOW, device

bank selected by BA0, BA1) or all device banks (A10 HIGH). The

address inputs also provide the op-code during a MODE

during the LOAD MODE REGISTER command.

5, 14, 25, 36, 56, 67, 78, 86 DQS0–DQS7 Input/

Output

Data Strobe: Output with READ data, input with WRITE data.

DQS is edge-aligned with READ data, centered in WRITE data.

Used to capture data.

97, 107, 119, 129, 149, 159,

169, 177

DM0–DM7 Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH

blocks WRITE operation. DM lines do not affect READ

operation.

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

2, 4, 6, 8, 12, 13, 19, 20, 23,

24, 28, 31, 33, 35, 39, 40, 53,

55, 57, 60, 61, 64, 68, 69, 72,

73, 79, 80, 83, 84, 87, 88, 94,

95, 98, 99, 105, 106, 109, 110,

114, 117, 121, 123, 126, 127,

131, 133, 146, 147, 150, 151,

153, 155, 161, 162, 165, 166,

170, 171, 174, 175, 178, 179

DQ0–DQ63 Input/

Output

Data I/Os: Data bus.

92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

181,182, 183 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to

configure the presence-detect device.

91 SDA Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-

detect device.

REF Supply SSTL_2 reference voltage.

15, 22, 30, 54, 62, 77, 96, 104,

112, 128, 136, 143, 156, 164,

172, 180

VDDQ Supply DQ Power Supply: +2.5V ±0.2V.

7, 38, 46, 70, 85, 108, 120,

148, 168

VDD Supply Power Supply: +2.5V ±0.2V.

3, 11, 18, 26, 34, 42, 50, 58,

66, 74, 81, 89, 93, 100, 116,

124, 132, 139, 145, 152, 160,

176

VSS Supply Ground.

184 VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V.

44, 45, 47, 49, 51, 134, 135,

140, 142, 144

DNU — Do Not Use: These pins are not connected on these modules,

but are assigned pins on other modules in this product family.

9, 10, 71, 82, 90, 101, 102,

103, 113, 115 (256MB), 163,

167 (256MB, 512MB, 1GB),

173

NC — No Connect: These pins should be left unconnected.

Table 5: Pin Descriptions (Continued)

Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 3: Functional Block Diagram – Standard PCB

BA0, BA1

A0-A11 (256MB)

A0-A12 (512MB, 1GB)

A0-A13 (2GB)

RAS#

CAS#

WE#

CKE1

CKE0

BA0, BA1: DDR SDRAMS

A0-A11: DDR SDRAMS

A0-A12: DDR SDRAMS

A0-A13: DDR SDRAMS

RAS#: DDR SDRAMS

CAS#: DDR SDRAMS

WE#: DDR SDRAMS

CKE0: DDR SDRAMS U1, U3, U6, U8, U11, U13, U14, U16

CKE1: DDR SDRAMS U2, U4, U5, U7, U10, U12, U15, U17

VREF

VSS

DDR SDRAMS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U13

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U14

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U16

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

S0#

U17

U15

S1#

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

U12

DM CS# DQS

DM2

DQS2

DM6

DQS6

DM CS# DQS

U11 U7

DM CS# DQS

DM CS# DQS DM CS# DQS

DM3

DQS3

DM7

DQS7

DM CS# DQS

U10

DM CS# DQS

VDDQ

VDD DDR SDRAMS

DDR SDRAMS

U4, U6,

U13, U15

CK0

CK0#

120

U1-U3,

U16-U18

CK1

CK1#

120

U7-U12

CK2

CK2#

120

VDDSPD SPD/EEPROM

3pF

SA0

SERIAL PD

U19 SDA

SA1

SA2

SCL

NOTE:

1. All resistor values are 22Ω unless otherwise specified.

2. Per industry standard, Micron modules utilize various component speed

grades, as referenced in the module part number guide at

www.micron.com/numberguide.

Standard modules use the following SDRAM devices:

MT46V16M8TG (256MB); MT46V32M8TG (512MB); MT46V64M8TG (1GB);

MT46V128M8TG (2GB)

Lead-free modules use the following SDRAM devices:

MT46V16M8P (256MB); MT46V32M8P (512MB); MT46V64M8P (1GB);

MT46V128M8P (2GB)

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 4: Functional Block Diagram – Low-Profile PCB

SA0

SERIAL PD

U10 SDA

SA1

SA2

BA0, BA1

A0-A11 (256MB)

A0-A12 (512MB, 1GB)

RAS#

BA0, BA1: DDR SDRAMS

A0-A11: DDR SDRAMS

A0-A12: DDR SDRAMS

RAS#: DDR SDRAMS

CAS#: DDR SDRAMS

CKE0: DDR SDRAMS U1–U4, U6–U9

CKE1: DDR SDRAMS U11, U14, U16–U19

WE#: DDR SDRAMS

CAS#

CKE0

CKE1

WE#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

S0#

SCL

U11

U12

U13

U16

S1#

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

U17

DM CS# DQS

DM2

DQS2

DM6

DQS6

DM CS# DQS

U8 U18

DM CS# DQS

DM CS# DQS DM CS# DQS

DM3

DQS3

DM7

DQS7

U14

DM CS# DQS

U19

DM CS# DQS

DDR

SDRAM

X 4

CK0

CK0#

DDSPD

DDQ

REF

VSS

SPD

DDR SDRAMS

DDR

SDRAM

X 6

CK1

CK1#

DDR

SDRAM

X 6

CK2

CK2#

120

3pF

120

3pF

120

3pF

NOTE:

1. All resistor values are 22Ω unless otherwise specified.

2. Per industry standard, Micron modules utilize various component speed

grades, as referenced in the module part number guide at

www.micron.com/numberguide.

Standard modules use

MT46V16M8TG for 256MB; MT46V32M8TG for 512MB; MT46V64M8TG

for 1GB

Lead-free modules use

MT46V16M8P for 256MB; MT46V32M8P for 512MB; MT46V64M8P for

1GB

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

General Description

The MT16VDDT3264A, MT16VDDT6464A,

MT16VDDT12864A, and MT16VDDT25664A are high-

speed CMOS, dynamic random-access, 256MB,

512MB, 1GB and 2GB memory modules organized in

x64 configuration. DDR SDRAM modules use inter-

nally configured quad-bank DDR SDRAM devices.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. Double data

rate architecture is essentially a 2n-prefetch architec-

ture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or

write access for the DDR SDRAM module effectively

consists of a single 2n-bit wide, one-clock-cycle data

transfer at the internal DRAM core and two corre-

sponding n-bit wide, one-half-clock-cycle data trans-

fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at

the receiver. DQS is an intermittent strobe transmitted

by the DDR SDRAM during READs and by the memory

controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for

WRITEs.

DDR SDRAM modules operate from differential

clock inputs (CK and CK#); the crossing of CK going

HIGH and CK# going LOW will be referred to as the

positive edge of CK. Commands (address and control

signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and out-

put data is referenced to both edges of DQS, as well as

to both edges of CK.

Read and write accesses to DDR SDRAM modules

are burst oriented; accesses start at a selected location

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with the

registration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the device bank and row to be

accessed (BA0, BA1 select devices bank; A0–A11 select

device row for 256MB; A0–A12 select device row for

512MB, 1GB; A0–A13 select device row for 2GB). The

address bits registered coincident with the READ or

WRITE command are used to select the device bank

and the starting device column location for the burst

access.

DDR SDRAM modules provide for programmable

READ or WRITE burst lengths of 2, 4, or 8 locations. An

auto precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end of

the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,

thereby providing high effective bandwidth by hiding

row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-

patible with the JEDEC Standard for SSTL_2. All out-

puts are SSTL_2, Class II compatible. For more

information regarding DDR SDRAM operation, refer to

the 128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM com-

ponent data sheets.

Serial Presence-Detect Operation

DDR SDRAM modules incorporate serial presence-

detect (SPD). The SPD function is implemented using

a 2,048-bit EEPROM. This nonvolatile storage device

contains 256 bytes. The first 128 bytes can be pro-

grammed by Micron to identify the module type and

various SDRAM organizations and timing parameters.

The remaining 128 bytes of storage are available for

use by the customer. System READ/WRITE operations

between the master (system logic) and the slave

EEPROM device (DIMM) occur via a standard I2C bus

using the DIMM’s SCL (clock) and SDA (data) signals,

together with SA (2:0), which provide eight unique

DIMM/EEPROM addresses. Write protect (WP) is tied

to ground on the module, permanently disabling hard-

ware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition

includes the selection of a burst length, a burst type, a

CAS latency and an operating mode, as shown in

Figure 5, Mode Register Definition Diagram, on page 9.

The mode register is programmed via the MODE REG-

ISTER SET command (with BA0 = 0 and BA1 = 0) and

will retain the stored information until it is pro-

grammed again or the device loses power (except for

bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-

rectly. The mode register must be loaded (reloaded)

when all device banks are idle and no bursts are in

progress, and the controller must wait the specified

time before initiating the subsequent operation. Vio-

lating either of these requirements will result in

unspecified operation.

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Mode register bits A0–A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-

leaved), A4–A6 specify the CAS latency, and A7–A11

(256MB) or A7–A12 (512MB, 1GB), or A7–A13 (2GB)

specify the operating mode.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Table 6, Burst

Definition Table, on page 10.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Figure 5, Mode Register Definition

Diagram. The burst length determines the maximum

number of column locations that can be accessed for a

given READ or WRITE command. Burst lengths of 2, 4,

or 8 locations are available for both the sequential and

the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1–Ai when the burst length is set to two,

by A2-Ai when the burst length is set to four and by A3-

Ai when the burst length is set to eight (where Ai is the

most significant column address bit for a given config-

uration; see Note 5, of Table 6, Burst Definition Table,

on page 10). The remaining (least significant) address

bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to

both READ and WRITE bursts.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS

Latency Diagram.

Figure 5: Mode Register Definition

Diagram

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A12 A11

BA0

BA1

Burst LengthCAS Latency BT0*0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA0 and BA1) must be “0, 0” to select the

base mode register (vs. the extended mode register).

512MB and 1GB Modules

256MB Module

M3 = 0

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

M6-M0

M8 M7

Operating Mode

A10A12 A11BA0BA1

10111214

* M15 and M14 (BA1 and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M12 M11

A13

M13

* M14 and M13 (BA0 and BA1) must be “0, 0” to select the

base mode register (vs. the extended mode register).

2GB Module

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. For a burst length of two, A1–Ai select the two-data-

element block; A0 selects the first access within the

block.

2. For a burst length of four, A2–Ai select the four-data-

element block; A0–A1 select the first access within the

block.

3. For a burst length of eight, A3–Ai select the eight-data-

element block; A0–A2 select the first access within the

block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

5. i = 9 for 256MB, 512MB;

i = 9, 11 for 1GB, 2GB.

Figure 6: CAS Latency Diagram

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m. Figure 7,

CAS Latency (CL) Table, indicates the operating fre-

quencies at which each CAS latency setting can be

used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7–A11

(256MB), A7–A12 (512MB, 1GB), or A7–A13 (2GB) each

set to zero, and bits A0–A6 set to the desired values. A

DLL reset is initiated by issuing a MODE REGISTER

SET command with bits A7 and A9–A11 (256MB), A7

and A9–A12 (512MB, 1GB), or A7 and A9–A13

(2GB)each set to zero, bit A8 set to one, and bits A0–A6

set to the desired values. Although not required by the

Micron device, JEDEC specifications recommend

when a LOAD MODE REGISTER command is issued to

reset the DLL, it should always be followed by a LOAD

MODE REGISTER command to select normal operat-

ing mode.

All other combinations of values for A7–A11

(256MB), A7–A12 (512MB, 1GB), or A7–A13 (2GB) are

reserved for future use and/or test modes. Test modes

Table 6: Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 7: CAS Latency (CL) Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

SPEED CL = 2 CL = 2.5

-335 75 ≤ f ≤ 133 75 ≤ f ≤ 167

-262 75 ≤ f ≤ 133 75 ≤ f ≤ 133

-26A 75 ≤ f ≤ 133 75 ≤ f ≤ 133

-265 75 ≤ f ≤ 100 75 ≤ f ≤ 133

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T0 T1 T2 T2n T3 T3n

DON’T CARETRANSITIONING DATA

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

and reserved states should not be used because

unknown operation or incompatibility with future ver-

sions may result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable and out-

put drive strength. These functions are controlled via

the bits shown in Figure 7, Extended Mode Register

Definition Diagram. The extended mode register is

programmed via the LOAD MODE REGISTER com-

mand to the mode register (with BA0 = 1 and BA1 = 0)

and will retain the stored information until it is pro-

grammed again or the device loses power. The

enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time before

initiating any subsequent operation. Violating either

of these requirements could result in unspecified oper-

ation.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled,

200 clock cycles with CKE HIGH must occur before a

READ command can be issued.

Figure 7: Extended Mode Register

Definition Diagram

NOTE:

1. BA1 and BA0 (E13 and E12 for 256MB, E14 and E13 for

512MB, 1GB, or E15 and E14 for 2GB) must be “0, 1” to

select the Extended Mode Register (vs. the base Mode

2. QFC# is not supported.

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Operating Mode

A10

A11A12

BA1 BA0

1314

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Operating Mode

A10

A11

BA1 BA0

256MB Module

512MB and 1GB Modules

Operating Mode

Reserved

–

Valid

–

DLL

Enable

Disable

DLL

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

Drive Strength

Normal

E2 E0

E1,

Operating Mode

A10A11A12BA1 BA0

1011121415

E3E4

–

E6 E5

E7E8E9

–

E10E11

–

E12

–

E13

A13

2GB Module

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Commands

Table 8, Commands Truth Table, and Table 9, DM

Operation Truth Table, provide a general reference of

available commands. For a more detailed description

of commands and operations, refer to the 128Mb,

256Mb, 512Mb, or 1Gb DDR SDRAM component data

sheets.

NOTE:

1. DESELECT and NOP are functionally interchangeable.

2. BA0–BA1 provide device bank address and A0–A11 (256MB), A0–A12 (512MB, 1GB), or A0–A13 (2GB) provide row

address.

3. BA0–BA1 provide device bank address; A0–A9 (256MB, 512MB) or A0–A9, A11(1GB, 2GB), provide column address; A10

HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–

BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (256MB), A0–A12

(512MB, 1GB), or A0–A13 (2GB) provide the op-code to be written to the selected mode register.

Table 8: Commands Truth Table

CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) HXXX X 1

NO OPERATION (NOP) LHHH X 1

ACTIVE (Select bank and activate row) L L H H Bank/Row 2

READ (Select bank and column, and start READ burst) L H L H Bank/Col 3

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3

BURST TERMINATE LHHL X 4

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LLLH X 6, 7

LOAD MODE REGISTER LLLLOp-Code 8

Table 9: DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION) DM DQS

WRITE Enable LValid

WRITE Inhibit HX

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

Voltage on VDD Supply

Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VDDQ Supply

Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VREF and Inputs

Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on I/O Pins

Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V

Operating Temperature

TA (ambient) . . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C

Storage Temperature (plastic) . . . . . .-55°C to +150°C

Short Circuit Output Current. . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1–5, 14, 48; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C

PARAMETER/CONDITION

SYMBOL

MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V 32, 36

I/O Supply Voltage VDDQ 2.3 2.7 V 32, 36, 39

I/O Reference Voltage VREF

0.49

Q0.51

V6, 39

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 25

Input Low (Logic 0) Voltage VIL(DC)-0.3VREF - 0.15 V 25

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤

1.35V (All other pins not under test = 0V)

Command/

Address, RAS#,

CAS#, WE#

-32 32

µA 47

CKE, S# -16 16

CK0, CK0# -8 8

CK1, CK1#

CK2, CK2#

-12 12

DM -4 4

OUTPUT LEAKAGE CURRENT

(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

DQ, DQS IOZ -10 10 µA 47

OUTPUT LEVELS

High Current (V

OUT

= V

Q-0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

IOH -16.8 – mA 33, 34

IOL 16.8 – mA

Table 11: AC Input Operating Conditions

Notes: 1–5, 14, 48, 49; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 – V 12, 25, 35

Input Low (Logic 0) Voltage VIL(AC)–VREF - 0.310 V 12, 25, 35

I/O Reference Voltage VREF(AC)

0.49

Q0.51

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 12: IDD Specifications and Conditions – 256MB

DDR SDRAM components only

Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYM -335 -262

-26A/

-265 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

(MIN);

CK =

CK (MIN); DQ, DM and DQS inputs changing once per clock

cyle; Address and control inputs changing once every two clock cycles

IDD0a1,024 904 864 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and

control inputs changing once per clock cycle

IDD1a1,104 984 984 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)

IDD2Nb48 48 48 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK

MIN; CKE = HIGH; Address and other control inputs changing once

per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb720 720 640 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;

Power-down mode; tCK = tCK (MIN); CKE = LOW

IDD3Pb400 400 320 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

andDQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

IDD3Nb800 800 720 mA 40

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank

active; Address and control inputs chan-ging once per clock cycle; tCK

= tCK (MIN); IOUT = 0mA

IDD4Ra1,144 1,064 1,024 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice

per clock cycle

IDD4Wa1,144 1,024 1,024 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b4,240 3,520 3,520 mA 20, 24,

tREFC = 15.625µs IDD5Ab80 80 80 mA

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b48 48 32 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL = 4)

with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and

control inputs change only during Active READ, or WRITE commands

IDD7a2,864 2,664 2,624 mA 20, 43

NOTE:

a: Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b: Value calculated reflects all module ranks in this operating condition.

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 13: IDD Specifications and Conditions – 512MB

DDR SDRAM Components only

Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYM -335 -262

-26A/

-265 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles

IDD0a1,032 1,032 992 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read

Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN);

IOUT = 0mA; Address and control inputs changing once per

clock cycle

IDD1a1,392 1,312 1,192 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode; tCK = tCK (MIN); CKE =

(LOW)

IDD2Pb64 64 64 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control

inputs changing once per clock cycle. VIN = VREF for DQ,

DQS, and DM

IDD2Fb800 720 720 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank active; Power-down mode; tCK = tCK (MIN); CKE =

LOW

IDD3Pb480 400 400 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One

device bank; Active-Precharge; tRC = tRAS (MAX);

tCK = tCK (MIN); DQ, DM andDQS inputs changing twice per

clock cycle; Address and other control inputs changing once

per clock cycle

IDD3Nb960 800 800 mA 40

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

One bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4Ra1,432 1,232 1,232 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

One device bank active; Address and control inputs

changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and

DQS inputs changing twice per clock cycle

IDD4Wa1,432 1,232 1,232 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b4,080 3,760 3,760 mA 20, 44

tREFC = 7.8125µs IDD5Ab96 96 96 mA 20, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b64 64 64 mA 9

OPERATING CURRENT: Four device bank interleaving READs

(BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK

(MIN); Address and control inputs change only during Active

READ, or WRITE commands

IDD7a3,312 2,832 2,832 mA 20, 43

NOTE:

a: Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b: Value calculated reflects all module ranks in this operating condition.

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 14: IDD Specifications and Conditions – 1GB

DDR SDRAM Components only

Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2VV

MAX

PARAMETER/CONDITION SYM -335 -262

-26A/

-265 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge; tRC =

tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once

per clock cyle; Address and control inputs changing once every two

clock cycles

IDD0a1,080 1,080 960 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and

control inputs changing once per clock cycle

IDD1a1,320 1,320 1,200 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)

IDD2Pb80 80 80 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =

tCK MIN; CKE = HIGH; Address and other control inputs changing

once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb720 720 640 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank

active; Power-down mode; tCK = tCK (MIN); CKE = LOW

IDD3Pb560 560 480 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

andDQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

IDD3Nb800 800 720 mA 40

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4Ra1,360 1,360 1,200 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

IDD4Wa1,440 1,280 1,120 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b4,640 4,640 4,480 mA 20, 44

tREFC = 7.8125µs IDD5Ab160 160 160 mA 20, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b80 80 80 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL = 4)

with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and

control inputs change only during Active READ, or WRITE

commands

IDD7a3,280 3,240 2,840 mA 20, 43

NOTE:

a: Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b: Value calculated reflects all module ranks in this operating condition.

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 15: IDD Specifications and Conditions – 2GB

DDR SDRAM Components only

Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2VV

MAX

PARAMETER/CONDITION SYM -335 -262

-26A/

-265 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge; tRC =

tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once

per clock cyle; Address and control inputs changing once every two

clock cycles

IDD0a1,080 1,080 1,240 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and

control inputs changing once per clock cycle

IDD1a1,320 1,320 1,520 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)

IDD2Pb80 80 160 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =

tCK MIN; CKE = HIGH; Address and other control inputs changing

once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb720 720 960 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank

active; Power-down mode; tCK = tCK (MIN); CKE = LOW

IDD3Pb560 560 480 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

andDQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

IDD3Nb720 720 720 mA 40

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4Ra1,360 1,360 1,680 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

IDD4Wa1,280 1,280 1,760 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b4,640 4,640 5,280 mA 20, 44

tREFC = 7.8125µs IDD5Ab160 160 160 mA 20, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b80 80 144 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL = 4)

with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and

control inputs change only during Active READ, or WRITE

commands

IDD7a3,280 3,240 3,960 mA 20, 43

NOTE:

a: Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b: Value calculated reflects all module ranks in this operating condition.

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 16: Capacitance

Note: 11; notes appear on pages 20–23

PARAMETER SYMBOL MIN MAX UNITS

Input/Output Capacitance: DQ, DQS, DM CIO 810 pF

Input Capacitance: Command and Address CI132 48 pF

Input Capacitance: S#, CKE CI116 24 pF

Input Capacitance: CK0, CK0# CI211 15 pF

Input Capacitance: CK1, CK1#; CK2, CK2# CI312 18 pF

Table 17: DDR SDRAM Component Electrical Characteristics and Recommended

AC Operating Conditions

Notes: 1–5, 13-15, 29, 48, 49; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -335 -262 -26A/-265

UNITS NOTES

PARAMETER

SYMBOL

MIN MAX MIN MAX MIN MAX

Access window of DQs from CK/

CK#

tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26

Clock cycle time CL = 2.5 tCK (2.5) 6 13 7.5 13 7.5 13 ns 41, 46

CL = 2 tCK (2) 7.5 13 7.5/10 13 7.5/10 13 ns 41, 46

DQ and DM input hold time relative to DQS tDH 0.45 0.5 0.5 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.45 0.5 0.5 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 1.75 ns 27

Access window of DQS from CK/

CK#

tDQSCK -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns

DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group,

per access

tDQSQ 0.45 0.5 0.5 ns 22, 23

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising -

setup time

tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK rising -

hold time

tDSH 0.2 0.2 0.2 tCK

Half clock period tHP tCH,tCL tCH,tCL tCH,tCL ns 31

Data-out high-impedance window from CK/CK# tHZ +0.70 +0.75 +0.75 ns 16, 37

Data-out low-impedance window from CK/CK# tLZ -0.70 -0.75 -0.75 ns 16, 37

Address and control input hold time (fast slew

rate)

tIHF0.75 0.90 .90 ns 12

Address and control input setup time (fast slew

rate)

tISF0.75 0.90 .90 ns 12

Address and control input hold time (slow slew

rate)

tIHS0.80 1 1 ns 12

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Address and control input setup time (slow slew

rate)

tISS0.80 1 1 ns 12

Address and Control input pulse width (for

each input)

tIPW 2.2 2.2 2.2 ns

LOAD MODE REGISTER command cycle time tMRD 12 15 15 ns

DQ-DQS hold, DQS to first DQ to go non-valid,

per access

tQH tHP -

tQHS

tHP -

tQHS

tHP -

tQHS

ns 22, 23

Data hold skew factor tQHS 0.55 0.75 0.75 ns

ACTIVE to PRECHARGE command tRAS 42 70,000 40

120,000

ns 31, 49

ACTIVE to READ with Auto precharge

command tRAP 15 15 20 ns

ACTIVE to ACTIVE/AUTO REFRESH command

period

tRC 60 60 65 ns

AUTO REFRESH command period 256MB,

512MB, 1GB tRFC

75 75 75 ns 44

2GB 120 120 120 ns

ACTIVE to READ or WRITE delay tRCD 15 15 20 ns

PRECHARGE command period tRP 15 15 20 ns

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 38

DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 38

ACTIVE bank a to ACTIVE bank b command tRRD 12 15 15 ns

DQS write preamble tWPRE 0.25 0.25 0.25 tCK

DQS write preamble setup time tWPRES 0 0 0 ns 18, 19

DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 17

Write recovery time tWR 15 15 15 ns

Internal WRITE to READ command delay tWTR 111

tCK

Data valid output window na tQH -tDQSQ tQH -tDQSQ tQH -tDQSQ ns 22

REFRESH to REFRESH command

interval

256MB

tREFC

140.6 140.6 140.6 µs 21

512MB, 1GB,

2GB

70.370.370.3µs21

Average periodic refresh interval 256MB

tREFI

15.615.615.6µs21

512MB, 1GB,

2GB

7.8 7.8 7.8 µs 21

Terminating voltage delay to VDD tVTD 000ns

Exit SELF REFRESH to non-READ command tXSNR 75 75 75 ns

Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK

Table 17: DDR SDRAM Component Electrical Characteristics and Recommended

AC Operating Conditions (Continued)

Notes: 1–5, 13-15, 29, 48, 49; notes appear on pages 20–23; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -335 -262 -26A/-265

UNITS NOTES

PARAMETER

SYMBOL

MIN MAX MIN MAX MIN MAX

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Notes

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC

characteristics may be conducted at nominal ref-

erence/supply voltage levels, but the related spec-

ifications and device operation are guaranteed for

the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and IDD tests may use a VIL-to-VIH

swing of up to 1.5V in the test environment, but

input timing is still referenced to VREF (or to the

crossing point for CK/CK#), and parameter speci-

fications are guaranteed for the specified AC input

levels under normal use conditions. The mini-

mum slew rate for the input signals used to test

the device is 1V/ns in the range between VIL(AC)

and VIH(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level, and will remain in that

state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmit-

ting device and to track variations in the DC level

of the same. Peak-to-peak noise (non-common

mode) on VREF may not exceed ±2 percent of the

DC value. Thus, from VDDQ/2, VREF is allowed

±25mV for DC error and an additional ±25mV for

AC noise. This measurement is to be taken at the

nearest VREF bypass capacitor.

7. VTT is not applied directly to the device. VTT is a

system supply for signal termination resistors, is

expected to be set equal to VREF and must track

variations in the DC level of VREF.

8. IDD is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time at CL = 2 for -262, and -26A, CL =

2.5 for -335 and -265 with the outputs open.

9. Enables on-chip refresh and address counters.

10. IDD specifications are tested after the device is

properly initialized, and is averaged at the defined

cycle rate.

11. This parameter is sampled. VDD = +2.5V ±0.2V,

VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA =

25°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) =

0.2V. DM input is grouped with I/O pins, reflecting

the fact that they are matched in loading.

12. For slew rates less than 1 V/ns and greater than or

equal to 0.5 V/ns. If slew rate is less than 0.5 V/ns,

timing must be derated: tIS has an additional 50ps

per each 100mV/ns reduction in slew rate from

500mV/ns, while tIH is unaffected. If slew rate

exceeds 4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and

CK# cross; the input reference level for signals

other than CK/CK# is VREF.

14. Inputs are not recognized as valid until VREF stabi-

lizes. Exception: during the period before VREF

stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is

VTT.

16. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

parameters are not referenced to a specific voltage

level, but specify when the device output is no

longer driving (HZ) or begins driving (LZ).

17. The intent of the Don’t Care state after completion

of the postamble is the DQS-driven signal should

either be high, low, or high-Z and that any signal

transition within the input switching region must

follow valid input requirements. That is, if DQS

transitions high [above VIHDC (MIN)] then it must

not transition low (below VIHDC) prior to

tDQSH(MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LOW) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

20. MIN (tRC or tRFC) for IDD measurements is the

smallest multiple of tCK that meets the minimum

absolute value for the respective parameter. tRAS

(MAX) for IDD measurements is the largest multi-

ple of tCK that meets the maximum absolute

value for tRAS.

21. The refresh period 64ms. This equates to an aver-

age refresh rate of 15.625µs (256MB) or 7.8125µs

(512MB, 1GB, 2GB). However, an AUTO REFRESH

command must be asserted at least once every

Output

OUT

)

Reference

Point

Ω

30pF

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

140.6µs (256MB) or 70.3µs (512MB, 1GB, 2GB);

burst refreshing or posting by the DRAM control-

ler greater than eight refresh cycles is not allowed.

22. The valid data window is derived by achieving

other specifications: tHP (tCK/2), tDQSQ, and tQH

(tQH = tHP - tQHS). The data valid window derates

directly porportional with the clock duty cycle

and a practical data valid window can be derived.

The clock is allowed a maximum duty cycle varia-

tion of 45/55, beyond which functionality is

uncertain. Figure 8, Derating Data Valid Window

tHP - tQHS, shows derating curves for duty cycles

ranging between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.

24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during

REFRESH command period (tRFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

AC level through to the target AC level, VIL (AC)

or VIH (AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to

maintain at least the target DC level, VIL (DC)

or VIH (DC).

26. JEDEC specifies CK and CK# input slew rate must

be ≥ 1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/

DM/DQS slew rate is less than 0.5V/ns, timing

must be derated: 50ps must be added to tDS and

tDH for each 100mv/ns reduction in slew rate. If

slew rate exceeds 4V/ns, functionality is uncer-

tain.

28. VDD must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same

amount.

30. tHP min is the lesser of tCL minimum and tCH

minimum actually applied to the device CK and

CK# inputs, collectively during bank active.

Figure 8: Derating Data Valid Window

tHP - tQHS

3.750 3.700 3.650 3.600 3.550

3.500 3.450

3.400 3.350 3.300 3.250

2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55

Clock Duty Cycle

-262/-26A/-265 @

CK = 10ns

-262/-26A/-265 @

CK = 7.5ns

-335 @

CK = 6ns

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

31. READs and WRITEs with auto precharge are not

allowed to be issued until tRAS (MIN) can be satis-

fied prior to the internal precharge command

being issued.

32. Any positive glitch in the nominal voltage must be

less than 1/3 of the clock and not more than

+400mV or 2.9V, whichever is less. Any negative

glitch must be less than 1/3 of the clock cycle and

not exceed either 300mV or 2.2V, whichever is

more positive. However, the DC average cannot be

below 2.3V minimum.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 9,

Pull-Down Characteristics.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-

ture is expected, but not guaranteed, to lie

within the inner bounding lines of the V-I

curve of Figure 9, Pull-Down Characteristics.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 10,

Pull-Up Characteristics.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve of Figure

10, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current

should be between 0.71 and 1.4, for device

drain-to-source voltages from 0.1V to 1.0 Volt,

and at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity

±10 percent, for device drain-to-source volt-

ages from 0.1V to 1.0V.

34. The voltage levels used are derived from a mini-

mum VDD level and the referenced test load. In

practice, the voltage levels obtained from a prop-

erly terminated bus will provide significantly dif-

ferent voltage values.

35. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a

pulse width ≤ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. VIL undershoot:

VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the

pulse width can not be greater than 1/3 of the

cycle rate.

36. VDD and VDDQ must track each other.

37. tHZ (MAX) takes precedence over tDQSCK (MAX)

+ tRPST (MAX) condition. tLZ (MIN) will prevail

over tDQSCK (MIN) + tRPRE (MAX) condition.

38. tRPST end point and tRPRE begin point are not

referenced to a specific voltage level but specify

when the device output is no longer driving

(tRPST), or begins driving (tRPRE).

39. During initialization, VDDQ, VTT, and VREF must

be equal to or less than VDD + 0.3V. Alternatively,

VTT may be 1.35V maximum during power up,

even if VDD/VDDQ are 0V, provided a minimum of

42Ω of series resistance is used between the VTT

supply and the input pin.

40. For -335, -262, -26A and -265 speed grades, IDD3N

is specified to be 35mA per DDR SDRAM at 100

MHz.

Figure 9: Pull-Down Characteristics Figure 10: Pull-Up Characteristics

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

41. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As

such, future die may not reflect this option.

42. Random addressing changing and 50 percent of

data changing at every transfer.

43. Random addressing changing and 100 percent of

data changing at every transfer.

44. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the

time the AUTO REFRESH command is registered,

CKE must be active at each rising clock edge, until

tREF later.

45. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q is

similar to IDD2F except IDD2Q specifies the

address and control inputs to remain stable.

Although IDD2F, IDD2N, and IDD2Q are similar,

IDD2F is “worst case.”

46. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.

This is followed by 200 clock cycles.

47. Leakage number reflects the worst case leakage

possible through the module pin, not what each

memory device contributes.

48. When an input signal is HIGH or LOW, it is

defined as a steady state logic HIGH or logic LOW.

49. The -335 speed grade will operate with tRAS (MIN)

= 40ns and tRAS (MAX) = 120,000ns at any slower

frequency.

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Initialization

To ensure device operation the DRAM must be ini-

tialized as described below:

1. Simultaneously apply power to VDD and VDDQ.

2. Apply VREF and then VTT power.

3. Assert and hold CKE at a LVCMOS logic low.

4. Provide stable CLOCK signals.

5. Wait at least 200µs.

6. Bring CKE high and provide at least one NOP or

DESELECT command. At this point the CKE input

changes from a LVCMOS input to a SSTL2 input

only and will remain a SSTL_2 input unless a

power cycle occurs.

7. Perform a PRECHARGE ALL command.

8. Wait at least tRP time, during this time NOPs or

DESELECT commands must be given.

9. Using the LMR command program the Extended

Mode Register (E0 = 0 to enable the DLL and E1 =

0 for normal drive or E1 = 1 for reduced drive, E2

through En must be set to 0; where n = most sig-

nificant bit).

10. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

11. Using the LMR command program the Mode Reg-

ister to set operating parameters and to reset the

DLL. Note at least 200 clock cycles are required

between a DLL reset and any READ command.

12. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

13. Issue a PRECHARGE ALL command.

14. Wait at least tRP time, only NOPs or DESELECT

commands are allowed.

15. Issue an AUTO REFRESH command (Note this

may be moved prior to step 13).

16. Wait at least tRFC time, only NOPs or DESELECT

commands are allowed.

17. Issue an AUTO REFRESH command (Note this

may be moved prior to step 13).

18. Wait at least tRFC time, only NOPs or DESELECT

commands are allowed.

19. Although not required by the Micron device,

JEDEC requires a LMR command to clear the DLL

bit (set M8 = 0). If a LMR command is issued the

same operating parameters should be utilized as

in step 11.

20. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

21. At this point the DRAM is ready for any valid com-

mand. Note 200 clock cycles are required between

step 11 (DLL Reset) and any READ command.

Figure 11: Initialization Flow Diagram

and V

Q Ramp

Apply V

REF

and V

CKE must be LVCMOS Low

Apply stable CLOCKs

Bring CKE High with a NOP command

Wait at least 200us

PRECHARGE ALL

Assert NOP or DESELECT for tRP time

Configure Extended Mode Register

Configure Load Mode Register and reset DLL

Assert NOP or DESELECT for tMRD time

PRECHARGE ALL

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRFC time

Optional LMR command to clear DLL bit

Assert NOP or DESELECT for tMRD time

DRAM is ready for any valid command

Step

Assert NOP or DESELECT commands for tRFC

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRP time

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 12: Component Case Temperature vs. Air Flow

NOTE:

1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across the module.

2. The component case temperature measurements shown above were obtained experimentally. The typical system to be

used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered

memory modules. Case temperatures charted represent worst-case component locations on modules installed in the

internal slots of the system.

3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from

its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard

for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test

chamber.

4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic soft-

ware application developed for internal use by Micron Technology, Inc.

100

0.0

0.5

1.0

2.0

Air Flow (meters/sec)

Degrees Celsius

Ambient Temperature = 25º C

Tmax

- memory stress software

Tave

- 3D gaming software

Tave

- memory stress software

Minimum Air Flow

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (as

shown in Figure 13, Data Validity, and Figure 14, Defi-

nition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (as shown in Fig-

ure 15, Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and

its slave address. If both the device and a WRITE oper-

ation have been selected, the SPD device will respond

with an acknowledge after the receipt of each subse-

quent eight-bit word. In the read mode the SPD device

will transmit eight bits of data, release the SDA line and

monitor the line for an acknowledge. If an acknowl-

edge is detected and no stop condition is generated by

the master, the slave will continue to transmit data. If

an acknowledge is not detected, the slave will termi-

nate further data transmissions and await the stop

condition to return to standby power mode.

Figure 13: Data Validity Figure 14: Definition of Start and Stop

Figure 15: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

SCL

SDA

START

BIT

STOP

BIT

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 16: SPD EEPROM Timing Diagram

Table 18: EEPROM Device Select Code

The most significant bit (b7) is sent first

SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 1010SA2SA1SA0RW

Protection Register Select Code 0110SA2SA1SA0RW

Table 19: EEPROM Operating Modes

MODE RW BIT WC BYTES INITIAL SEQUENCE

Current Address Read 1V

IH or VIL 1START, Device Select, RW = ‘1’

Random Address Read 0V

IH or VIL 1START, Device Select, RW = ‘0’, Address

IH or VIL 1reSTART, Device Select, RW = ‘1’

Sequential Read 1V

IH or VIL ≥ 1 Similar to Current or Random Address Read

Byte Write 0V

IL 1START, Device Select, RW = ‘0’

Page Write 0V

IL ≤ 16 START, Device Select, RW = ‘0’

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising

edge of SDA.

2. This parameter is sampled.

3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA

remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 20: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SUPPLY VOLTAGE VDDSPD 2.3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD × 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD +0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10µA

STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB –30µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2mA

Table 21: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF 300 ns 2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequency fSCL 400 KHz

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 22: Serial Presence-Detect Matrix (256MB, 512MB, and 1GB)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31

BYTE DESCRIPTION ENTRY (VERSION)

MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A

0Number of SPD Bytes Used by Micron 128 80 80 80

1Total Number of Bytes in SPD Device 256 08 08 08

2Fundamental Memory Type SDRAM DDR 07 07 07

3Number of Row Addresses on

Assembly

12, 13 0C 0D 0D

4Number of Column Addresses on

Assembly

10, 11 0A 0A 0B

5Number of Physical Ranks on DIMM 20222

6Module Data Width 64 40 40 40

7Module Data Width (Continued) 0000000

8Module Voltage Interface Levels SSTL 2.5V 04 04 04

9SDRAM Cycle Time, tCK, (CAS Latency

= 2.5) (See note 1)

6ns (-335)

7ns (-262/-26A)

7.5ns (-265)

10 SDRAM Access From Clock, tAC

(CAS Latency = 2.5)

0.7ns (-335)

0.75ns (-262/-26A/-265)

11 Module Configuration Type None 00 00 00

12 Refresh Rate/Type 15.62µs, 7.8µs/SELF 80 82 82

13 SDRAM Device Width (Primary DDR

SDRAM)

8080808

Error-Checking DDR SDRAM Data Width

None 00 00 00

15 Minimum Clock Delay, Back-to-Back

Random Column Access

1 clock 01 01 01

16 Burst Lengths Supported 2, 4, 8 0E 0E 0E

Number of Banks on DDR SDRAM Device

4040404

18 CAS Latencies Supported 2, 2.5 0C 0C 0C

19 CS Latency 0010101

20 WE Latency 1020202

21 SDRAM Module Attributes Unbuffered/Diff.

Clock

20 20 20

22 SDRAM Device Attributes: General Fast/Concurrent AP C0 C0 C0

23 SDRAM Cycle Time, tCK

(CAS Latency = 2)

7.5ns (-335/-262/-26A)

10ns (-265

24 SDRAM Access From CK, tAC

(CAS Latency = 2)

0.7ns (-335)

0.75ns (-262/-26A/-265)

25 SDRAM Cycle Time, tCK

(CAS Latency = 1.5)

N/A 00 00 00

26 SDRAM Access From CK, tAC

(CAS Latency = 1.5)

N/A 00 00 00

27 Minimum Row Precharge Time, tRP

(see note 4)

18ns (-335)

15ns (-262)

20ns (-26A/-265)

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

28 Minimum Row Active to Row Active,

tRRD

12ns (-335)

15ns (-262/-26A/-265)

29 Minimum Ras# to CAS# Delay, tRCD

(see note 4)

18ns (-335)

15ns (-262)

20ns (-26A/-265)

30 Minimum RAS# Pulse Width, tRAS,

(see note 2)

42ns (-335)

45ns (-262/-26A/-265)

31 Module Rank Density 128MB, 256MB,

512MB

20 40 80

32 Address and Command Setup Time,

tIS, (see note 3)

0.8ns (-335)

1.0ns (-262-26A/-265)

33 Address and Command Hold Time,

tIH, (see note 3)

0.8ns (-335)

1.0ns (-262/-26A/-265)

34 Data/Data Mask Input Setup Time,

tDS

0.45ns (-335)

0.5ns (-262/-26A/-265)

35 Data/Data Mask Input

Hold Time, tDH

0.45ns (-335)

0.5ns (-262/-26A/-265)

36-40 Reserved 00 00 00

41 Min Active Auto Refresh Time, tRC 60ns (-335/-262)

65ns (-26A/-265)

42 Minimum Auto Refresh to Active/

Auto Refresh Command Period, tRFC

72ns (-335)

75ns (-262/-26A/-265)

43 SDRAM Device Max Cycle Time,

tCKMAX

12ns (-335)

13ns (-262/-26A/-265)

44 SDRAM Device Max DQS-DQ Skew

Time, tDQSQ

0.45ns (-335)

0.5ns (-262/-26A/-265)

45 SDRAM Device Max Read Data Hold

Skew Factor, tQHS

0.55ns (-335)

0.75ns (-262/-26A/-265)

46-61 Reserved 00 00 00

47 DIMM Height Standard/Low-Profile 01/11 01/11 01/11

46-61 Reserved 00 00 00

62 SPD Revision Release 1.0 10 10 10

63 Checksum For Bytes 0-62 -335

-262

-26A

-265

05/15

98/A8

C5/D5

F5/05

28/38

BB/CB

E8/F8

18/28

69/79

FC/0C

29/39

59/69

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C

65-71 Manufacturer’s JEDEC ID Code (Continued) FF FF FF

72 Manufacturing Location 01–12 01–0C 01–0C 01–0C

73-90 Module Part Number (ASCII) Variable Data Variable Data Variable Data

91 PCB Identification Code Variable Data Variable Data Variable Data

92 Identification Code (Continued) 0000000

93 Year of Manufacture in BCD Variable Data Variable Data Variable Data

Table 22: Serial Presence-Detect Matrix (256MB, 512MB, and 1GB) (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31

BYTE DESCRIPTION ENTRY (VERSION)

MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

2. The value of tRAS used for -26A/-265 modules is calculated from tRC - tRP. Actual device spec. value is 40 ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-

mum slew rate is met.

4. The value of tRP, tRCD and tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR

SDRAM device specification is 15ns.

94 Week of Manufacture in BCD Variable Data Variable Data Variable Data

95-98 Module Serial Number Variable Data Variable Data Variable Data

99-127 Manufacturer-Specific Data (RSVD) –– –

Table 22: Serial Presence-Detect Matrix (256MB, 512MB, and 1GB) (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31

BYTE DESCRIPTION ENTRY (VERSION)

MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 23: Serial Presence-Detect Matrix (2GB)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31

BYTE DESCRIPTION ENTRY (VERSION)

MT16VDDT25664A

0Number of SPD Bytes Used by Micron 128 80

1Total Number of Bytes in SPD Device 256 08

2Fundamental Memory Type SDRAM DDR 07

3Number of Row Addresses on Assembly 14 0E

4Number of Column Addresses on Assembly 11 0B

5Number of Physical Ranks on DIMM 202

6Module Data Width 64 40

7Module Data Width (Continued) 000

8Module Voltage Interface Levels SSTL 2.5V 04

9SDRAM Cycle Time, tCK, (CAS Latency = 2.5) (See note

6ns (-335)

7ns (-262/-26A)

7.5ns (-265)

10 SDRAM Access From Clock, tAC, (CAS Latency = 2.5) 0.7ns (-335)

0.75ns (-262/-26A/-265)

11 Module Configuration Type None 00

12 Refresh Rate/Type 15.62µs, 7.8µs/SELF 82

13 SDRAM Device Width (Primary DDR SDRAM) 808

14 Error-Checking DDR SDRAM Data Width None 00

15 Minimum Clock Delay, Back-to-Back Random Column

Access

1 clock 01

16 Burst Lengths Supported 2, 4, 8 0E

Number of Banks on DDR SDRAM Device

404

18 CAS Latencies Supported 2, 2.5 0C

19 CS Latency 001

20 WE Latency 102

21 SDRAM Module Attributes Unbuffered/Diff. Clock 20

22 SDRAM Device Attributes: General Fast/Concurrent AP C0

23 SDRAM Cycle Time, tCK, (CAS Latency = 2)

7.5ns (-335/-262/-26A)

10ns (-265)

24 SDRAM Access From CK, tAC, (CAS Latency = 2) 0.7ns (-335)

0.75ns (-262/-26A/-265)

25 SDRAM Cycle Time, tCK, (CAS Latency = 1.5) N/A 00

26 SDRAM Access From CK, tAC, (CAS Latency = 1.5) N/A 00

27 Minimum Row Precharge Time, tRP (see note 4) 18ns (-335)

15ns (-262)

20ns (-26A/-265)

28 Minimum Row Active to Row Active, tRRD 12ns (-335)

15ns (-262/-26A/-265)

29 Minimum Ras# to CAS# Delay, tRCD (see note 4) 18ns (-335)

15ns (-262)

20ns (-26A/-265)

30 Minimum RAS# Pulse Width, tRAS, (see note 2) 42ns (-335)

45ns (-262/-26A/-265)

31 Module Rank Density 1GB 01

32 Address and Command Setup Time, tIS, (see note 3) 0.8ns (-335)

1.0ns (-262-26A/-265)

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

2. The value of tRAS used for -26A/-265 modules is calculated from tRC - tRP. Actual device spec. value is 40 ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-

mum slew rate is met.

4. The value of tRP, tRCD and tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR

SDRAM device specification is 15ns.

33 Address and Command Hold Time, tIH, (See note 2) 0.8ns (-335)

1.0ns (-262/-26A/-265)

34 Data/Data Mask Input Setup Time, tDS 0.45ns (-335)

0.5ns (-262/-26A/-265)

35 Data/Data Mask Input Hold Time, tDH 0.45ns (-335)

0.5ns (-262/-26A/-265)

36-40 Reserved 00

41 Min Active Auto Refresh Time tRC 60ns (-335/-262)

65ns (-26A/-265)

42 Minimum Auto Refresh to Active/ Auto Refresh

Command Period, tRFC

120ns (all speed grades) 78

43 SDRAM Device Max Cycle Time tCKMAX 12ns (-335)

13ns (-262/-26A/-265)

44 SDRAM Device Max DQS-DQ Skew Time tDQSQ 0.45ns (-335)

0.5ns (-262/-26A/-265)

45 SDRAM Device Max Read Data Hold Skew Factor

tQHS

0.55ns (-335)

0.75ns (-262/-26A/-265)

46-61 Reserved 00

47 DIMM Height Standard/Low-Profile 01/11

46-61 Reserved 00

62 SPD Revision Release 1.0 10

63 Checksum For Bytes 0-62 -335

-262

-26A

-265

1B/2B

AB/BB

D8/E8

1C/2C

64 Manufacturer’s JEDEC ID Code MICRON 2C

65-71 Manufacturer’s JEDEC ID Code (Continued) FF

72 Manufacturing Location 01–12 01–0C

73-90 Module Part Number (ASCII) Variable Data

91 PCB Identification Code Variable Data

92 Identification Code (Continued) 000

93 Year of Manufacture in BCD Variable Data

94 Week of Manufacture in BCD Variable Data

95-98 Module Serial Number Variable Data

99-127 Manufacturer-specific Data (RSVD) –

Table 23: Serial Presence-Detect Matrix (2GB) (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31

BYTE DESCRIPTION ENTRY (VERSION)

MT16VDDT25664A

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 17: 184-PIN DDR DIMM Dimensions – Standard PCB

NOTE:

All dimensions are in inches (millimeters); or typical where noted.

1.256 (31.9)

1.244 (31.6)

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

PIN 92

FRONT VIEW

BACK VIEW

0.054 (1.37)

0.046 (1.17)

5.256 (133.50)

5.244 (133.20)

2.55 (64.77)

1.95 (49.53)

PIN 184 PIN 93

0.150 (3.80) 0.150 (3.80)

TYP.

0.394 (10.00)

TYP.

0.157 (4.00)

MAX

0.035 (0.90) R

U10 U11 U12 U13 U15 U16 U17 U18

U1 U2 U3 U4 U6 U7 U8 U9

U19

MAX

MIN

256MB, 512MB, 1GB, 2GB (x64, DR)

184-PIN DDR SDRAM UDIMM

pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice..

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 18: 184-PIN DDR DIMM Dimensions – Low-Profile PCB

NOTE:

All dimensions arein inches (millimeters); or typical where noted.

Data Sheet Designation

Advance: This datasheet contains initial descrip-

tions of products still under development. The

Advance designation applies to MT16VDDT25664A

only.

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete

power supply and temperature range for production

devices. Although considered final, these specifica-

tions are subject to change, as further product devel-

opment and data characterization sometimes occur.

The Released designation applies to MT16VDDT3264A,

MT16VDDT6464A, and MT16VDDT12864A only.

U1 U2 U3 U4 U6 U7 U8 U9

U10

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65) TYP.

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

0.035 (0.90) R

PIN 92

FRONT VIEW

BACK VIEW

5.256 (133.50)

5.244 (133.20)

2.55 (64.77)

TYP.

1.95 (49.53)

TYP.

PIN 184 PIN 93 0.150 (3.80)

TYP.

0.394 (10.00)

TYP.

1.156 (29.36)

1.144 (29.06)

0.054 (1.37)

0.046 (1.17)

0.125 (3.18)

MAX

U19 U18 U17 U16 U14 U13 U12 U11

MAX

MIN