8190747
SA14-4652-02
Revised 07/95
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 12
IBM043614PQK
32K X 36 BURST SRAM
Features
• 32K x 36 Organization
• 0.5µCMOS Technology
• Supports PowerPCTM Processor Operation
• Single +3.3V ±5% Power Supply and Ground
• 5V Tolerant I/O
• LVTTL I/O Compatible
• Fast OE times: 4, 5, 6ns
• Common I/O
• Registered Addresses, Data Ins and Control
Signals
• Asynchronous Output Enable
• Self-Timed Write Operation and Byte Write
Capability
• Low Power Dissipation
- 960 mW Active at 66MHz
- 90 mW Standby
• 100 Pin Thin Quad Flat Pack
Description
IBM Microelectronics 1M SRAM is a Synchronous
Burstable, high performance CMOS Static RAM that
is versatile, wide I/O, and achieves 8 nsec access. A
single clock is used to initiate the read/write opera-
tion and all internal operations are self-timed. At the
rising edge of the Clock, all Addresses, Data Ins and
Control Signals are registered internally. Burst mode
operation, is accomplished by integrating input reg-
isters, internal 2-bit burst counter and high speed
SRAM in a single chip. Burst reads are initiated with
either ADSP or ADSC being LOW with a valid
address during the rising edge of clock. Data from
this address plus the three subsequent addresses
will be output. The chip is operated with a single
+3.3 V power supply and is compatible with LVTTL
I/O interfaces.
IBM043612PQK32K x 36Burst (Pentium), TQFP package.
IBM043614PQK
32K X 36 BURST SRAM
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 12
8190747
SA14-4652-02
Revised 07/95
X36 TQFP Pin Array Layout
Pin Description
A0-A14 Address input ADSP Address Status Processor
DQa - DQd Data Input/Output (0-8,9-17,18-26,27-35) ADSC Address Status Controller
CLK Clock ADV Burst Advance Control
WEa Write Enable, Byte a (0 to 8) CS ADSP Gated Chip Select
WEb Write Enable, Byte b (9 to 17) VDD Power Supply (+3.3V)
WEc Write Enable, Byte c (18 to 26) VSS Ground
WEd Write Enable, Byte d (27 to 35) VDDQ Output Power Supply (+3.3V)
OE Output Enable NC No Connect
CS2, CS2 Chip Selects
DQ18 1
DQ19 2
DQ20 3
VDDQ 4
VSS 5
DQ21 6
DQ22 7
DQ23 8
DQ24 9
VSS 10
VDDQ 11
DQ25 12
DQ26 13
NC 14
VDD 15
NC 16
VSS 17
DQ27 18
DQ28 19
VDDQ 20
VSS 21
DQ29 22
DQ30 23
DQ31 24
DQ32 25
VSS 26
VDDQ 27
DQ33 28
DQ34 29
DQ35 30
NC 31
A5 32
A4 33
A3 34
A2 35
A1 36
A0 37
NC 38
NC 39
VSS 40
VDD 41
NC 42
NC 43
A10 44
A11 45
A12 46
A13 47
A14 48
NC 49
NC 50
80 DQ17
79 DQ16
78 DQ15
77 VDDQ
76 VSS
75 DQ14
74 DQ13
73 DQ12
72 DQ11
71 VSS
70 VDDQ
69 DQ10
68 DQ9
67 VSS
66 NC
65 VDD
64 NC
63 DQ8
62 DQ7
61 VDDQ
60 VSS
59 DQ6
58 DQ5
57 DQ4
56 DQ3
55 VSS
54 VDDQ
53 DQ2
52 DQ1
51 DQ0
100 A6
99 A7
98 CS
97 CS2
96 WEd
95 WEc
94 WEb
93 WEa
92 CS2
81 VDD
90 VSS
89 CLK
88 NC
87 NC
86 OE
85 ADSC
84 ADSP
83 ADV
82 A8
81 A9
IBM043614PQK
32K X 36 BURST SRAM
8190747
SA14-4652-02
Revised 07/95
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 12
Block Diagram
Ordering Information
Part Number Organization Speed Leads Notes
IBM043614PQK-8 32K x 36 8 ns Access / 15 ns Cycle 100 pin TQFP
IBM043614PQK-9 32K x 36 9 ns Access / 15 ns Cycle 100 pin TQFP
IBM043614PQK-10 32K x 36 10 ns Access / 15 ns Cycle 100 pin TQFP
IBM043614PQK-11 32K x 36 11 ns Access / 15 ns Cycle 100 pin TQFP
32K x 36 Array
A0 - A14
Row
Address
Register
Column
Address
Register
Burst
Binary
Counter
Byte
Write
Register
Clear
Byte
Write
Register
Select
Registers
ADSP
A2 - A9
A10 - A14
SA0
SA1
A0
A1
ADSC
CLK
ADV
CS
WEa
WEb
OE
Byte
Write
Register
Byte
Write
Register
WEc
WEd
DQ0 -
DQ9 -
DQ18 - DQ26
DQ27 - DQ35
DQ17
DQ8
CS
CS2
CS2
IBM043614PQK
32K X 36 BURST SRAM
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 12
8190747
SA14-4652-02
Revised 07/95
Burst SRAM Clock Truth Table
CLK CS2 CS2 CS ADSP ADSC ADV WE OE DQ Operation
L→HHXLLXXXXHIZDeselected Cycle
L→HXLLLXXXXHIZDeselected Cycle
L→HH X X X L X X X HIZ Deselected Cycle
L→HX L X X L X X X HIZ Deselected Cycle
L→HLHLLXXXLQ
Read from External
Address, Begin Burst
L→HLHLLXXXHHIZ
Read from External
Address, Begin Burst
L→HLHLHLXHLQ
Read from External
Address, Begin Burst
L→HLHLHLXLXD
Write to External
Address, Begin Burst
L→HXXXHHLHLQ
Read from next Add.,
Continue Burst
L→HXXXHHLLXD
Write to next Add.,
Continue Burst
L→HXXXHHHHLQ
Read from Current
Add., Suspend Burst
L→HXXXHHHLXD
Write to Current Add.,
Suspend Burst
L→HX X H X L X X X HIZ Deselect Cycle
L→HXXHXHLHLQ
Read from next Add.,
Continue Burst
L→HXXHXHLLXD
Write to next Add.,
Continue Burst
L→HXXHXHHHLQ
Read from current
Add., Suspend Burst
L→HXXHXHHLXD
Write to current Add.,
Suspend Burst
1. For a write operation preceded by a read cycle, OE must be HIGH early enough to allow Input Data Setup, and must be kept HIGH
through Input Data Hold Time.
2. WE refers to WEa, WEb, WEc, WEd.
3. ADSP is gated by CS, and CS is used to block ADSP when CS = VIH, as required in applications using Processor Address Pipelin-
ing.
4. All Addresses, Data In and Control signals are registered on the rising edge of CLK.
Burst Sequence Truth Table
External Address A14-A2 (A1,A0) Notes
(0,0) (0,1) (1,0) (1,1)
1st Access A14-A2 (0,0) (0,1) (1,0) (1,1)
2nd Access A14-A2 (0,1) (1,0) (1,1) (0,0)
3rd Access A14-A2 (1,0) (1,1) (0,0) (0,1)
4th Access A14-A2 (1,1) (0,0) (0,1) (1,0)
IBM043614PQK
32K X 36 BURST SRAM
8190747
SA14-4652-02
Revised 07/95
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 12
Write Enable Truth Table
WEa WEb WEc WEd Byte Written Notes
H H H H Read All Bytes
L L L L Write All Bytes
LHHH
Write Byte A (DIN 0 - 8)
HLHH
Write Byte B (DIN 9 - 17)
HHLH
Write Byte C (DIN 18 - 26)
HHHL
Write Byte D (DIN 27 - 35)
Absolute Maximum Ratings
Parameter Symbol Rating Units Notes
Power Supply Voltage VDD -0.5 to 4.6 V 1
Input Voltage VIN -0.5 to 6.0 V 1
Output Voltage VOUT -0.5 to VDD+0.5 V1
Operating Temperature TOPR 0 to +70 °C1
Storage Temperature TSTG -55 to +125 °C1
Power Dissipation PD2.0 W 1
Short Circuit Output Current IOUT 50 mA 1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Recommended DC Operating Conditions (TA=0 to 70°C)
Parameter Symbol Min. Typ. Max. Units Notes
Supply Voltage VDD 3.135 3.3 3.465 V 1,4
Input High Voltage VIH 2.2 — 5.5 V 1,2,4
Input Low Voltage VIL -0.3 — 0.8 V 1,3,4
Output Current IOUT —5 8mA4
1. All voltages referenced to GND. All VDD(Q) and VSS(Q) pins must be connected.
2. VIH(Max)DC = 5.5 V, VIH(Max)AC = 6.0 V (pulse width ≤ 4.0ns)
3. VIL(Min)DC = - 0.3 V, VIL(Min)AC= -1.5 V (pulse width ≤ 4.0ns)
4. Input voltage levels are tested to the following DC conditions: 1 microsecond cycle and 200 ns set-up and hold times.
Capacitance (TA=0 to +70°C, VDD=3.3V ±5%, f=1MHz)
Parameter Symbol Test Condition Max Units Notes
Input Capacitance CIN VIN = 0V 5pF
Data I/O Capacitance (DQ0-DQ35) COUT VOUT = 0V 5pF
IBM043614PQK
32K X 36 BURST SRAM
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 12
8190747
SA14-4652-02
Revised 07/95
DC Electrical Characteristics (TA= 0 to +70°C, VDD=3.3V ±5%)
Parameter Symbol Min. Max. Units Notes
Operating Current
Average Power Supply Operating Current
(OE = VIH, IOUT = 0) IDD15 — 275 mA 2,3
Standby Current
Power Supply Standby Current
(CS2 = VIH or CS2 = VIL or CS = VIH
All other inputs = VIH or VIL, IOUT. = 0, Clock @ 66 MHz)) ISB — 25 mA 1,3
Input Leakage Current
Input Leakage Current, any input
(VIN = 0 &VDD)ILI —+1µA 4
Output Leakage Current
(VOUT =0 &VDD, OE = VIH)ILO —+1µA
Output High Level
Output “H” Level Voltage (IOH=-8mA @ 2.4V) VOH 2.4 — V
Output Low Level
Output “L” Level Voltage (IOL=+8mA @ 0.4V) VOL — 0.4 V
1. ISB = Stand-by Current
2. IDD = Selected Current
3. IOUT = Chip Output Current
4. The input leakage current for 5.5V inputs is 200 µA f or Clk, Chip Selects, and Output Enable. Other inputs ha ve100 µA of leakage
current at 5.5V
AC Test Conditions (TA=0 to +70°C, VDD=3.3V ±5%)
Parameter Symbol Conditions Units Notes
Input Pulse High Level VIH 3.0 V
Input Pulse Low Level VIL 0.0 V
Input Rise Time TR2.0 ns
Input Fall Time TF2.0 ns
Input and Output Timing Reference Level 1.5 V
Output Load Conditions 1
1. See AC Test Loading figure 1 on page 8.
IBM043614PQK
32K X 36 BURST SRAM
8190747
SA14-4652-02
Revised 07/95
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 12
AC Characteristics (TA=0 to +70°C, VDD=3.3V ±5%, Units in nsec)
Parameter Symbol -8 -9 -10 -11 Notes
Min. Max. Min. Max. Min. Max. Min. Max.
Cycle Time tCYCLE 15.0 — 15.0 — 15.0 — 15.0 —
Clock Pulse High tCH 3.0 — 3.0 — 3.0 — 3.0 —
Clock Pulse Low tCL 3.0 — 3.0 — 3.0 — 3.0 —
Clock to Output Valid tCQ — 8.0 — 9.0 — 10.0 — 11.0 3
Address Status Controller Setup Time tADSCS 2.5 — 2.5 — 2.5 — 2.5 —
Address Status Controller Hold Time tADSCH 0.5 — 0.5 — 0.5 — 0.5 —
Address Status Processor Setup Time tADSPS 2.5 — 2.5 — 2.5 — 2.5 —
Address Status Processor Hold Time tADSPH 0.5 — 0.5 — 0.5 — 0.5 —
Advance Setup Time tADVS 2.5 — 2.5 — 2.5 — 2.5 —
Advance Hold Time tADVH 0.5 — 0.5 — 0.5 — 0.5 —
Address Setup Time tAS 2.5 — 2.5 — 2.5 — 2.5 —
Address Hold Time tAH 0.5 — 0.5 — 0.5 — 0.5 —
Chip Selects Setup Time tCSS 2.5 — 2.5 — 2.5 — 2.5 —
Chip Selects Hold Time tCSH 0.5 — 0.5 — 0.5 — 0.5 —
Write Enables Setup Time tWES 2.5 — 2.5 — 2.5 — 2.5 —
Write Enables Hold Time tWEH 0.5 — 0.5 — 0.5 — 0.5 —
Data In Setup Time tDS 2.5 — 2.5 — 2.5 — 2.5 —
Data In Hold Time tDH 0.5 — 0.5 — 0.5 — 0.5 —
Data Out Hold Time tCQX 3.0 — 3.0 — 3.0 — 3.0 — 3
Clock High to Output High Z tCHZ — 5.0 — 5.0 — 5.5 — 5.5 1,2,4
Clock High to Output Active tCLZ 2.5 — 2.5 — 2.5 — 2.5 — 1,2,4
Output Enable to High Z tOHZ 2.0 5.0 2.0 5.5 2.0 6.0 2.0 6.5 1,4
Output Enable to Low Z tOLZ 0.25 — 0.25 — 0.25 — 0.25 — 1,4
Output Enable to Output Valid tOQ — 4.0 — 5.0 — 5.0 — 6.0 3
1. Transitions are measured ± 200 mV from steady state voltage.
2. At any given voltage and temperature, Tchz (max) is always less than Tclz (min) for a given device and from device to device. For
any read cycle preceded by a write or deselect cycle, the data bus will transition glitch-free from HIZ to new RAM data.
3. See AC Test Loading figure 1 on page 8.
4. See AC Test Loading figure 2 on page 8.
IBM043614PQK
32K X 36 BURST SRAM
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 12
8190747
SA14-4652-02
Revised 07/95
AC Test Loading
50 Ω
VL = 1.5 V
50 Ω
DQ
Fig. 1 Test Equivalent Load
0.0
0.5
1.0
1.5
2.0
2.5
3.0
015 4530 75 105
picoFarads
-0.5
-1.0
60 90
nanoseconds
The derating curve above is for a purely capacitive load on the output driver. For example, a
part specified at 8 ns access time will behave as though it has an 8.5 ns access time if a 30
pF load with no DC component was attached to the output driver. The access times guaran-
teed in the datasheets are based on a 50 ohm terminated test load. For unterminated loads
the derating curve should be used. This curve is based on nominal process conditions with
worst case parameters Vdd = 3.14 V, Ta = 70° C.
30 pF
Output Capacitive Load Derating Curve
351 Ω
DQ
Fig. 2 Test Equivalent Load
5 pF
+ 3.3 V
317 Ω
IBM043614PQK
32K X 36 BURST SRAM
8190747
SA14-4652-02
Revised 07/95
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 12
Timing Diagram (Burst Read)
CLK
OE
A1 A2
ADDR
ADV
ADSC
ADSP
WEa, WEb
WEc, WEd
CS2
DQ
tcycle tCH tCL
tADSPS tADSPH
tADSCS tADSCH
tADVS tADVH
tAS tAH tAH
tAS
tWEH
tWES
tCSH
tCSS
tCSS tCSH
tOLZ tOQ
tCQ
Q1(A) Q2(A) Q2(B) Q2(C)
tCQX
tCQ
Q2(D)
tOHZ
tCQ
tCQX
CS2
CS
Notes:
1. Q1(A) and Q2(A) refer to data read from address A1 and A2.
2. Q2(B), Q2(C) and Q2(D) refer to read from subsequent internal burst counter addresses.
IBM043614PQK
32K X 36 BURST SRAM
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 12
8190747
SA14-4652-02
Revised 07/95
Timing Diagram (Burst Write)
CLK
OE
A2
ADDR
ADV
ADSC
ADSP
CS2
DQ
tcycle tCH tCL
A1
D1(A) D2(A) D2(B) D2(B)
tADSPS tADSPH
tADSCH
tADSCS
tADVH
tADVS tADVH
tADVS
tAH
tAS
tAS tAH
tWEH
tWES
tCSS tCSH
tOHZ
tDH
tDS
tCHZ tDS tDH tDS
tDS tDH
tDH
tCSS tCSH
CS2
CS
Notes:
1. D1(A) and D2(A) refer to data written to address A1 and A2.
2. D2(B) refers to data written to a subsequent internal burst counter address.
3. WEa, WEb, WEc and WEd are don’t cares when ADSP is sampled LOW.
tCLZ
WEa, WEb
WEc, WEd
IBM043614PQK
32K X 36 BURST SRAM
8190747
SA14-4652-02
Revised 07/95
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 12
100 Pin TQFP Package Diagram
Note: All dimensions in Millimeters
20.00 ± 0.10
22.00 ± 0.20
14.00 ± 0.10
16.00 ± 0.20
Pin 1 I.D.
6˚± 4˚
1.60 MAX
0.25
0.60 +0.15/-0.10
Standoff Lead Coplanarity
Seating
Plane
0.10 Max
Rad 0.20 Typ 0.05/0.15(Min/Max)
0˚- 7˚
12˚ Typ
12˚ Typ
1.40 ±0.10
0.05/0.15 (Min/Max)
1.60 Max
0.65 Basic
0.30 ± 0.05
IBM043614PQK
32K X 36 BURST SRAM
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 12
8190747
SA14-4652-02
Revised 07/95
Revision Log
Rev Contents of Modification
5/94 Initial Release of the 32K x 36 (8/9/11) TQFP BURST MODE Application Spec.
3/95 Updated -8, -9, -11; Added -10 Specifications
7/95 Removed Preliminary classification.
