R EM MICROELECTRONIC-MARIN SA V6118 2, 4 and 8 Multiplex LCD Driver Typical Operating Configuration Features n n n n n n n n n n n n V6118 2 is 2 way multiplex with 2 rows and 38 columns V6118 4 is 4 way multiplex with 4 rows and 36 columns V6118 8 is 8 way multiplex with 8 rows and 32 columns Low dynamic current, 150 mA max. o Low standby current, 1 mA max. at 25 C Voltage bias and mux signal generation on chip Display refresh on chip, 40 x 8 RAM for display storage Display RAM addressable as 8, 40 bit words Column driver only mode to have 40 column outputs Crossfree cascadable for large LCD applications Separate logic and LCD supply voltage pins Wide power supply range, VDD: 2 to 6 V, VLCD: 2 to 8 V n BLANK function for LCD blanking on power up etc. n Voltage bias inputs for applications with large pixel sizes n Bit mapped n Serial input / output n Very low external component count o o n -40 C to +85 C temperature range n No busy states n LCD updating synchronized to the LCD refresh signal n QFP52 and TAB packages 32 column outputs 8 row outputs V6118 8 VLCD FR DI DO CLK STR VDD COL VSS VLCD FR DI CLK STR VDD VSS Description The V6118 is a universal low multiplex LCD driver. The version V6118 2 drives two ways multiplex (two blackplanes) LCD, the version V6118 4, four way multiplex LCD, and the V6118 8, eight way multiplex LCD. The display refresh is handled on chip via a 40 x 8 bit RAM which holds the LCD content driven by the driver. LCD pixels (or segments) are addressed on a one to one basis with the 40 x 8 bit RAM ( a set bit corresponds to an activated LCD pixel). The V6118 has very low dynamic current consumption, 150 mA max., making it particularly attractive for portable and battery powered applications. The wide operating range on both the logic (VDD) and the LCD (VLCD) supply voltages offers much application flexibility. The LCD bias generation is internal. The voltage bias levels can also be provided externally for applications having large pixels sizes. The V6118 can be used as a column only driver for cascading in large display applications. In the column only mode, 40 column outputs are available to address the display. A BLANK function is provided to blank the LCD, useful at power up to hold the display blank until the microprocessor has updated the display RAM. Fig. 1 Pin Assignment S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 QFP52 S1 V3 V2 V1 VLCD FR DI DO CLK STR VDD COL VSS Applications 40 39 V6118 13 14 27 26 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 n Balances and scales n Automotive displays n Utility meters n Large displays (public information panels etc.) n Pagers n Portable, battery operated products n Telephones 52 1 See Fig.15 for the TAB pinout 1 Fig. 2 R V6118 Absolute Maximum Ratings Parameter Handling Procedures Symbol Supply voltage range LCD supply voltage range Voltage at DI, DO, CLK STR, FR, COL Voltage at V1 to V3, S1 to S40 Storage temperature range Power dissipation Electrostatic discharge max. to MIL-STD-883C method 3015 Max. soldering conditions This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level. Conditions VDD VLCD VLOGIC -0.3 V to +8 V -0.3 V to +9 V -0.3 V to VDD+0.3V VDISP TSTO PMAX -0.3 to VLCD+0.3V o - 65 to +150 C 100 mW VSMAX TS 1000 V 250 oC x 10 s Operating Conditions Parameter Symbol Min. Typ. Max. Units Operating temperature Logic supply voltage LCD supply voltage Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. TA VDD VLCD -40 2 2 5 5 O +85 6 8 C V V Table 2 Electrical Characteristics o VDD = 5.0 V + 10%, VLCD = 2 to 7 V and TA = -40 to +85 C, unless otherwise specified Parameter Dynamic supply current Dynamic supply current Dynamic supply current Dynamic supply current Standby supply current Control Signals DI, CLK, STR, FR and COL Input leakage Input capacitance Low level input voltage High level input voltage for DI, STR, FR and COL High level input voltage for CLK 1) Symbol ILCD IDD IDD IDD ISS IIN CIN VIL Test Conditions Min. 1) See note 1) o See note at TA = + 25 C 1) See note 2) See note 3) o See note at TA = + 25 C 0 < VIN < VDD o at TA = + 25 C VIH VIH Data Output DO High level output voltage Low level output voltage VOH VOL IH = 4 mA IL = 4 mA Driver Outputs S1...S40 4) Driver impedance 4) Driver impedance 4) Driver impedance 5) Bias impedance V1, V2, V3 5) Bias impedance V1, V2, V3 5) Bias impedance V1, V2, V3 DC output component ROUT ROUT ROUT RBIAS RBIAS RBIAS VDC IOUT = 10 A, VLCD = 7 V IOUT = 10 A, VLCD = 3 V IOUT = 10 A, VLCD = 2 V IOUT = 10 A, VLCD = 7 V IOUT = 10 A, VLCD = 3 V IOUT = 10 A, VLCD = 2 V See tables 4a and 4b, VLCD = 5 V Typ. Max. 100 0.1 3 200 0.1 150 1 12 250 1 A A A A A 1 8 100 0 0.8 nA pF V 2.0 3.0 VDD VDD V V 0.4 V V 2.4 0.5 1.2 9 16 18 30 1.5 2.5 30 50 All outputs open, STR at VSS, FR = 400 Hz, all other inputs at VDD. 2) All outputs open, STR at VSS, FR = 400 Hz, fCLK = 1 MHz, all other inputs at VDD. 3) All outputs open, all inputs at VDD. 4) This is the impedance between the voltage bias level pins (V1, V2, or V3) and the output pins S1 to S40 when a given voltage bias level is driving the outputs (S1 to S40). 5) This is the impedance seen at the segment pin. Outputs measured one at a time. 2 Units 20 25 kW kW kW kW kW kW mV Table 3 R V6118 Column Drivers Outputs S1 to S40 S1 to S40 FR polarity logic 1 logic 0 COL logic 0 logic 0 Column data logic 1 logic 1 Measured | Sx* - VSS | | VLCD - Sx* | S1 to S40 S1 to S40 logic 1 logic 0 logic 0 logic 0 logic 0 logic 0 | VLCD - Sx* | | Sx* - VSS | Guaranteed | VLCD - Sx* | = | Sx* - VSS | 25mV | VLCD - Sx* | = | Sx* - VSS | 25 mV * Sx = the output no. (i.e. S1 to S40) Table 4a Row Drivers Outputs S1 to Sn* S1 to Sn* FR polarity logic 1 logic 0 COL logic 1 logic 1 Row data logic 1 logic 1 Measured | VLCD - Sx | | Sx - VSS | S1 to Sn* S1 to Sn* logic 1 logic 0 logic 1 logic 1 logic 0 logic 0 | Sx - VSS | | VLCD - Sx | Guaranteed | VLCD - Sx | = | Sx - VSS | 25mV | VLCD - Sx | = | Sx - VSS | 25 mV * n = the V6118 version no. (i.e. 2, 4 or 8) Table 4b Timing Characteristics VDD = 5.0 V 10%, VLCD = 2 to 8 V, and TA = -40 to +85oC Parameter Symbol Test Conditions Min. Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width CLK falling to STR rising STR falling to CLK falling tCH tCL tCR tCF tDS tDH tPD tSTR tP tD 120 120 Typ. Max. 200 200 1) 20 1) 30 CLOAD = 50 pF 100 100 10 200 2) 128/256/512 FFR FR frequency (Vers. 2/4/8) tDS + tDH minimum must be 100 ns. If tDS = 20 ns then tDH 80 ns. 2) V6118n. FR = n times the desired LCD refresh rate where n is the V6118 version number. Units ns ns ns ns ns ns ns ns ns ns Hz 1) Table 5a VDD = 2 to 6 V, VLCD = 2 to 8 V, and TA = -40 to +85oC Parameter Symbol Test Conditions Min. Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width CLK falling to STR rising STR falling to CLK falling FR frequency (Vers. 2/4/8) tCH tCL tCR tCF tDS tDH tPD tSTR tP tD 500 500 1) 2) FFR Typ. Max. 200 200 1) 100 1) 150 CLOAD = 50 pF 400 500 10 1 128/256/512 2) tDS + tDH minimum must be 500 ns. If tDS = 100 ns then tDH 400 ns. V6118n, FR = n times the desired LCD refresh rate where n is the V6118 version number. 3 Units ns ns ns ns ns ns ns ns ns ms Hz Table 5b R V6118 Timing Waveforms t CH t CF t CL t CR CLK DI t DS t DH DO t PD STR tD t STR tP Fig. 3 V6118 Data Transfer Cycle, COL Inactive V6118 as a row and column driver (COL inactive) 40 bit load cycle, RAM address provided by address bit 1 to (n*) CLK .. .. DI .. .. Address Bits V6118 2 V6118 4 V6118 8 Addr.1 to Addr.n* 10 01 Col(40-n*), Col(39-n*) ... Col1, addr.(n*) ... addr.1 1) STR * n = the V6118 version number (i.e. 2,4, or 8) 1000 0100 0010 0001 10000000 01000000 00100000 00010000 00001000 00000100 00000010 00000001 Display RAM Addr. 10000000 01000000 00100000 00010000 00001000 00000100 00000010 00000001 LCD row 1) Row1 Row2 Row3 Row4 Row5 Row6 Row7 Row8 A set address bit corresponds to a write enabled RAM address, the same data can be written to more than one RAM address by setting the required address bits. Fig. 4 V6118 Data Transfer Cycle, COL Active V6118 as a column driver only (COL active) 48 bit load cycle, RAM address provided by address bits 1 to 8 CLK DI .. .. Address Bits V6118 2 V6118 4 V6118 8 Addr. 1 to Addr.8 .. .. 10000000 01000000 Col40, Col39 ... Col1, addr.8 ... addr.2, addr.1 STR 1) 10000000 01000000 00100000 00010000 10000000 01000000 00100000 00010000 00001000 00000100 00000010 00000001 Display RAM Addr. 10000000 01000000 00100000 00010000 00001000 00000100 00000010 00000001 LCD row 1) Row1 Row2 Row3 Row4 Row5 Row6 Row7 Row8 A set address bit corresponds to a write enabled RAM address,the same data can be written to more than one RAM address by setting the required address bits. Fig. 5 4 R V6118 Block Diagram FR STR FR Q CLK 0 STR 0 1 COL X Q Qo Gating DI 8 bit shift register 40 bit shift register DI 1) 8 bit sequencer 10000000 8 write enable lines 8 x 40 bit display RAM 8 read enable lines STR 40 bit display latch COL Gating COL FR 40 display driver outputs VLCD V1 V2 LCD waveform generator S 1. . . S 40 V3 STR VSS 1) When logic "1" the STR input forces the display RAM addr. 10000000 (which corresponds to row 1) to be selected by the 8 bit sequences. Cascaded V6118s are synchronized in this way. The LCD picture is rebuilt starting from row 1 each time data is written to the display RAM. 5 Fig. 6 R V6118 Pin Description Name S1...S40 V3 V2 V1 VLCD FR DI DO CLK STR VDD COL VSS Name Function LCD outputs, see table 7 1)2) LCD voltage bias level 3 LCD voltage bias level 21) LCD voltage bias level 11) Power supply for the LCD AC input signal for LCD driver outputs Serial data input Serial data output Data clock input Data strobe, blank, synchronize input Power supply for logic Column only driver mode Supply GND S1 S2 S3 S4 S5 S6 S7 S8 S9...S40 COL Inactive COL Active V6118 2 V6118 4 V6118 8 Row1 Row1 Row1 Row2 Row2 Row2 Col1 Row3 Row3 Col2 Row4 Row4 Col3 Col1 Row5 Col4 Col2 Row6 Col5 Col3 Row7 Col6 Col4 Row8 Col7....38 Col5....36 Col1....32 Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col 9....40 Table 7 Table 6 The V6118 has internal voltage bias level generation. When driving large pixels, an external resistor divider chain can be connected to the voltage bias level inputs to obtain enhanced display contrast (see Fig. 12, 13 and 14). The external resistor divider ratio should be in accordance with the internal resistor ratio (see table 8). 2) V3 is connected internally on the V6118 4. 1) LCD Voltage Bias Levels VOP (*) VOFF (rms) LCD Drive Type LCD Bias Configuration V6118 2 n=2 1:2MUX Alt + Pleshko V6118 4 n=4 1:4 MUX 1/3 Bias V6118 8 n=8 1:8 MUX 1/4Bias 4 5 levels 1+ VON (rms) VOFF (rms) VLCD 0.43 R V1 R V2 R 5 levels V3 Vss 2n 1- 1 n = 3.69 +1 = 2.41 n - 1 n 0.43 R VLCD R V1 R V2 3 1+ 4 levels 8 n = 1.73 R Vss VLCD R V1 R V2 R 3 n = 3.4 n + 15 = 1.446 n+3 V3 Vss R (*) VOP = VLCD - VSS Table 8 6 R V6118 Row and Column Multiplexing Waveform V6118 2 VOP = VLCD - VSS, VSTATE = VCOL - VROW TFRAME =2/(FR frequency) VDD FR VSS State1 State2 VLCD Row1 Row2 V1 V2 V3 VSS VLCD V1 V2 V3 VSS Col1 Col2 VLCD V1 V2 V3 VSS VLCD V1 V2 V3 VSS 2.43VOP/2.86 VOP/2.86 0.43VOP/2.86 State1* 0 -0.43VOP/2.86 -VOP/2.86 -2.43VOP/2.86 2.43VOP/2.86 VOP/2.86 0.43VOP/2.86 State2* 0 -0.43VOP/2.86 -VOP/2.86 -2.43VOP/.86 Fig. 7 *See Table 8 7 R V6118 Row and Column Multiplexing Waveform V6118 4 VOP = VLCD - VSS, VSTATE = VCOL - VROW TFRAME = 4/(FR frequency) State 1 State 2 VDD FR VSS VLCD V1 Row1 V2 VSS VLCD V1 Row2 V2 VSS VLCD V1 Col1 V2 VSS VLCD V1 Col2 V2 VSS VOP 2VOP/3 State1* VOP/3 0 VOP/3 2VOP/3 VOP VOP 2VOP/3 VOP/3 State2* 0 VOP/3 2VOP/3 VOP Fig. 8 * See Table 8 8 R V6118 Row and Column Multiplexing Waveform V6118 8 VOP = VLCD - VSS, VSTATE = VCOL - VROW TFRAME =8/(FR frequency) State2 State1 VDD FR VSS Row1 VLCD V1 V2 V3 VSS Row2 VLCD V1 V2 V3 VSS Col1 VLCD V1 V2 V3 VSS Col2 VLCD V1 V2 V3 VSS VOP 3VOP/4 2VOP/4 VOP/4 State1* 0 VOP/4 2VOP/4 3VOP/4 VOP VOP 3VOP/4 2VOP/4 VOP/4 0 State2* VOP/4 2VOP/4 3VOP/4 VOP * See Table 8 Fig. 9 9 R V6118 Functional Description The display RAM word length is 40 bits (see Fig. 6). Each LCD row has a corresponding display RAM address which provides the column data (on or off) when the row is selected (on). When downloading data to the V6118 any display RAM address can be chosen, there is no display RAM addressing sequence (see Fig. 4 and 5). The same data can be written to more than one display RAM address. If more than one address bit is set, then more than one display RAM address is write enabled, and so the same data is written to more than one address. This feature can be useful to flash the LCD on and off under software control. If the address bits are all zero then no display RAM address is write enabled and no data is written to the display RAM on the falling edge of STR. Use address 0 to synchronize cascaded V6118s without updating the display RAM. Supply Voltage VLCD, VDD, VSS The voltage between VDD and VSS is the supply voltage for the logic and the interface. The voltage between VLCD and VSS is the supply voltage for the LCD and is used for the generation of the internal LCD bias levels. The internal LCD bias levels have a maximum impedance of 25 kW for a VLCD voltage from 3 to 8 V. Without external connections to the V1, V2, and V3 bias level inputs, the V6118 can drive most medium sized LCD (pixel area 2 up to 4'000 mm ). For displays with a wide variation in pixel sizes the configuration shown in Fig. 13 can give enhanced contrast by giving faster pixel switching times. On changing the row polarity (see Fig. 7, 8 and 9 ) the parallel capacitors lower the impedance of the bias level generation to the peak current, giving faster pixel charge times and thus a higher RMS "on" value. A higher RMS "on" value can give better contrast. If for a given LCD size and operating voltage, the "off" pixels appear "on", or there is poor contrast, then an external bias level generation circuit can be used with the V6118. An external bias level generation circuit can lower the bias level impedance and hence improve the LCD contrast (see Fig. 12). The optimum values of R, Rx, and C, vary according to the LCD size used and VLCD. They are best determined through actual experimentation with the LCD. 2 For LCD with very large average pixel size up to 10'000 mm , the bias level configuration shown in Fig. 14 should be used. When V6118s are cascaded, connect the V1, V2, and V3 bias inputs are shown in Fig. 10. The pixel load is averaged across all the cascaded drivers. This will give enhanced display contrast as the effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6118 are cascaded as shown in Fig. 10, then the maximum bias level impedance becomes 12.5 KW for a VLCD voltage from 3 to 8 V. Table 8 shows the relationship between V1, V2, and V3 for the multiplex rates 2, 4 and 8. Note that VLCD > V1 > V2 > V3 for the V6118 2 and V6118 8, and for the V6118 4, VLCD>V1>V2. CLK Input The CLK is used to clock the DI serial data into the shift register and to clock the DO serial data out. Loading and shifting of the data occurs at the falling edge of this clock, outputting of the data at the rising edge (see Fig. 3). When cascading devices, all CLK lines should be tied together (see Fig. 10). STR Input The STR input is used to write to the display RAM, blank the LCD, and synchronize cascaded V6118s. The STR input writes the data loaded into the shift register, on the DI input, to the display RAM on the falling edge of the STR signal. The display RAM address is given by the address bits (see Fig. 4 and 5). The STR input when high blanks the LCD by disconnecting the internal voltage bias generation from the VSS potential. Segment outputs S1 to S40 (rows and columns) are pulled up to VLCD. The delay to driving the LCD with VLCD on S1 to S40, is dependent on the capacitive load of the LCD and is typically 1 s. An LCD pixel responds to RMS voltage and takes approximately 100 ms to turn on or off. The delay from putting STR high to the LCD being blank is dependent on the LCD off time and is typically 100 ms. In applications which have a long STR pulse width (10 s), the LCD is driven by VLCD on both the rows and columns during this time. As the time is short (1 A), it will have zero measurable effect on the RMS "on" value (over 100 ms) of an LCD pixel and also zero measurable effect on the pixel DC component. Such STR pulses will not be visible to the human eye on an LCD. Data Input/ Output The data input pin, DI, is used to load serial data into the V6118. The serial data word length is 40 bits when COL is inactive, and 48 bits when it is active. Data is loaded in inverse numerical order, the data for bit 40 (bit 48 when COL is active) is loaded first with the data for bit 1 last. The column data bits are loaded first and then the address bits (see Fig. 4 and 5). The data output pin, DO, is used in cascaded applications (see Fig. 10). DO transfers the data to the next cascaded chip. The data at DO is equal to the data at DI delayed by 40 clock periods, when COL is inactive and 48 clock periods when COL is active. In order to cascade V6118s, the DO of one chip must be connected to DI of the following chip (see Fig. 10). In cascaded applications the data of the last V6118 (the one that does not have DO connected) must be loaded first and the data for the first V6118 (its DI is connected to the processor) loaded last (see Fig. 10). Note if an external voltage bias generation circuit is used as shown in Fig. 12 and 14, the LCD blank function (STR high) will not blank the LCD. When STR is high the LCD will be driven by the parallel combination of the external voltage bias generation circuit and part of the internal voltage bias generation circuit. The STR input, when high, synchronizes cascaded V6118s by forcing a new time frame to begin at the next falling edge of the FR input signal (see Fig.6). A time frame begins with row 1 and so the LCD picture is rebuilt from row 1 each time 10 R V6118 to one relationship between the display RAM and the LCD driver outputs. Each pixel (segment) driven by the V6118 on the LCD has a display RAM bit which corresponds to it. Setting the bit turns the segment "on" and clearing it turns it "off". cascaded V6118s are synchronized. When cascading devices, all STR lines must be tied together (see Fig. 10). FR input The FR signal controls the segment output frequency generation (see Fig. 7, 8 and 9). To avoid having DC on the display, the FR signal must have a 50% duty cycle. The frequency of the FR signal must be n times the desired display refresh rate, where n is the V6118 version no. (2,4 or 8). For example, if the desired refresh rate is 40 Hz, the FR signal frequency must be 320 Hz for the V6118 8. A selected row (on) is in phase with the FR signal (see Fig. 7, 8 and 9). It is recommended that data transfer to the V6118 should be synchronized to the FR signal to avoid a falling or rising edge on the FR signal while writing data to the V6118. The LCD pixels change polarity with the FR signal. On the edges of the FR signal current spikes will appear on the VSS and VLCD supply lines. If the supply lines have high impedance then voltage spikes will appear. These voltage spikes could interfere with data loading on the DI and CLK pins. COL Input The V6118 functions as a row and column driver while the COL input is inactive. When active the COL input configures the V6118 to function as a column driver only. The former row outputs function as column outputs. In cascaded applications one V6118 should be used in the row column configuration (COL inactive) and the rest as pure column drivers (COL active) (see Fig. 10). Note when cascading V6118s never cascade one version with another. If a V6118 8 is used to drive the rows then only V6118 8s can be cascaded with it. When COL is active the V6118 needs 48 bits of data in a load cycle. 40 bits are used for the column data and 8 bits to address the display RAM regardless of V6118 version (2, 4 or 8) (see Fig. 4, 5 and 10). Power Up On power up the data is shift registers, the display RAM and the 40 bit display latch are undefined. The STR input should be taken high on power up to blank the display, and then the display data written to the display RAM (see Fig. 11). When finished the initial write to the display RAM, take the STR input low to display the display RAM contents (see also section "STR Input"). Driver output S1 to S40 There are 40 LCD driver outputs on the V6118. When COL is inactive the outputs S1 to Sn function as row drivers and the outputs S(n + 1) to S40 function as column drivers, where n is the V6118 version no. (2,4 or 8). When COL is active, all 40 outputs function as column drivers (see table 6). There is a one 11 R V6118 Applications Two V6118 8s Cascaded LCD size = 8 * (32+40) = 576 pixels 8 row outputs 40 column outputs 32 column outputs V6118 8 V6118 8 V3 V2 V1 VLCD FR DI DO CLK STR VDD COL VSS V3 V2 V1 VLCD FR DI DO CLK STR VDD COL VSS VLCD FR DI CLK STR VDD VSS CLK DI Col40,Col39 Col1,addr.8 Addr.2,addr.1, Col32,Col31Col1,addr.8 addr.2,addr.1, STR By connecting the V1, V2 and V3 bias inputs as shown, the pixel load is averaged across all the drivers. The effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6118 are cascaded as above, then the maximum bias level impedance becomes 12. 5 k . Fig. 10 Microprocessor Interface and LCD Blanking DI RXD (Mode 0) TXD CLK VDD 8051 V6118 1) STR P2.x FR RESET 1) When the microprocessor is reset, the port pin will be configured as an input and so the STR line would Oscillator float. The pullup resistor will ensure that the LCD is blank while the system reset line is active and after 50% duty cycle. until the port pin is setup by software. Writing Data to the Display RAM while Keeping the LCD Blank CLK DI Col32 Col31 Col 1, addr.8 STR addr.2 addr.1 Fig. 11 12 R V6118 V 6118 with External Resistor Divider Bias Generation 52 column outputs 8 row outputs Rx VDisp VLCD C C R Temperature compensation / contrast adjustment V1 C R V6118 8 V2 R C V3 C R VSS VSS Example set values: R = 3.3 - 10 k C = 2.2 - 47 nF Rx is given by the formula: Rx = 4R((VDISP/VLCD)-1) = 10 - 30 k Fig. 12 Bias Configuration for a Large LCD Enhanced Switching from the V 6118 VDISP Temperature compensation/ contrast adjustment Rx VLCD C R V1 C V6118 8 + V1 + V2 R V2 C V6118 4 R V3 VSS C VSS VLCD VDISP C VSS VSS Large LCD example: 2 VOP= 5 V, average pixel active area up to 10'000 mm , display refresh = 64 Hz C= 1 mF Rx is given by the formula: Rx = 4 (20 k ) ((VDISP/VLCD) - 1) For single V6118 4 driving such an LCD the voltage follower buffer (opamp) requirements is: peak current 1.8 mA, steady state current typically 100 mA Fig. 13 13 Fig.14 R V6118 Package and Ordering Information Dimensions of TAB Package 0.30 (5x) 1.80 0.12 (19x) 0.10 0.30 (8x) 0.30 (2x) 0.30 (6x) S28 DO CLK STR VDD COL VSS S40 S27 0.15 ILB Window S14 0.15 S13 0.12 (19x) S1 FR VLCD V1 V2 V3 DI 0.90 0.30 (7x) 0.10 1.20 0.30 (6x) 0.30 (4x) 0.30 (7x) All dimensions in mm Fig. 15 Dimensions of QFP Package 14.25 max 0 - 10 9.9 max 14.25 max 0.4 max 9.9 max 0.65 1.3 max 2.2 max Detail 0.5 max All dimensions in mm Fig. 16 14 R V6118 Package and Ordering Informatiion S1 X 215, Y=2412 S2 X =407 S3 X=599 S4 X=791 S5 X =983 S6 X=1175 S7 X=1367 S8 X=1559 S9 X=1751 S10 X=1943 S11 X=2135 S12 X=2327 S13 X=2519 S14 X=2711 S15 X=2903 Dimensions of Chip Form X = -271 Y = -242 V6118 R S16 X=3149,Y=2166 S17 Y=1974 S18 Y=1782 S19 Y=1590 S20 Y=1398 S21 Y=1206 S22 Y=1014 S23 Y=822 S24 Y=630 S25 Y=438 S26 Y=246 VSS X=215 S40 X=407 S39 X=599 S38 X=791 S37 X=983 S36 X=1175 S35 X=1367 S34 X=1559 S33 X=1751 S32 X=1943 S31 X=2135 S30 X=2327 S29 X=2519 S28 X=2711 S27 X=2903,Y= 0 V3 X=0,Y=2168 V2 X=2, Y=1974 V1 Y=1782 VLCD Y=1590 FR Y=1398 DI Y=1206 DO Y=1014 CLK Y=822 STR Y=630 VDD Y=438 COL Y=246 Thickness (typ.) = 11 mils. Chip size is X = 3657 by Y = 2895 microns or X = 144 by Y = 114 mils. Note: The origin (0,0) is the lower left coordinate of center pads. The lower left corner of the chip shows distances to origin. Fig. 17 Dimensioms in microns 15 R V6118 Ordering Information When ordering, please specify the complete Part Number. Part Number V6118V2WP11 V6118V2QF52D V6118V2TBD V6118V4WP11 V6118V4QF52D V6118V4TBD V6118V8WP11 V6118V8QF52D V6118V8TBD Version 2 4 8 Package / Die Form Delivery Form / Bumping Die in waffle pack, 11 mils thickness No bumps QFP52, pin plastic package Tray TAB (Tape Automated Bonding), film D Die in waffle pack, 11 mils thickness No bumps QFP52, pin plastic package Tray TAB (Tape Automated Bonding), film D Die in waffle pack, 11 mils thickness No bumps QFP52, pin plastic package Tray TAB (Tape Automated Bonding), film D - Package Marking N/A V6118V252F N/A N/A V6118V452F N/A N/A V6118V852F N/A EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin product. EM Microelectronic-Marin reserves the right to change circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. O 2002 EM Microelectronic-Marin SA, 03/029, Rev. L/434 EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. +41 - (0)32 75 55 111, Fax +41 - (0)32 75 55 403