Typical Size 6,4 mm X 6,6 mm TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 3-A OUTPUT TRACKING/TERMINATION SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FETs (SWIFT) FEATURES D Qualified for Automotive Applications D Tracks Externally Applied Reference Voltage D 60-m MOSFET Switches for High Efficiency D D D D at 3-A Continuous Output Source or Sink Current 6% to 90% VI Output Tracking Range Wide PWM Frequency: Fixed 350 kHz or Adjustable 280 kHz to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost APPLICATIONS D DDR Memory Termination Voltage D Active Termination of GTL and SSTL D D High-Speed Logic Families DAC Controlled High Current Output Stage Precision Point of Load Power Supply DESCRIPTION As a member of the SWIFT family of dc/dc regulators, the TPS54372 low-input voltage high-output current synchronous-buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance under transient conditions and flexibility in choosing the output filter L and C components; an under-voltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally and externally set slow-start circuit to limit in-rush currents; and a status output to indicate valid operating conditions. The TPS54372 is available in a thermally enhanced 20-pin TSSOP (PWP) PowerPAD package, which eliminates bulky heatsinks. Texas Instruments provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. SIMPLIFIED SCHEMATIC SIMPLIFIED SCHEMATIC VIN PH TPS54372 BOOT PGND REFIN VTTQ COMP VBIAS AGND VSENSE VI = 5 V, VO = 1.25 V 0 A to 2.25 A Compensation Network I O - Output Current - 1 A/div VDDQ VO - Output Voltage - 50 mV/div TRANSIENT RESPONSE Input t - Time - 25 ms/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2008, Texas Instruments Incorporated TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION{ TJ REFIN VOLTAGE PACKAGE} PART NUMBER -40C to 125C 0.2 V to 1.75 V Plastic HTSSOP (PWP) TPS54372QPWPRQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. The PWP package is available taped and reeled as indicated by the R suffix to the device type (i.e., TPS54372QPWPRQ1). See the application section of the data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS54372 VI Input voltage range VO Output voltage range IO Source current IS Sink current VIN, ENA -0.3 V to 7 V RT -0.3 V to 6 V VSENSE, REFIN -0.3 V to 4 V BOOT -0.3 V to 17 V VBIAS, COMP, STATUS -0.3 V to 7 V PH -0.6 V to 6 V PH Internally limited COMP, VBIAS 6 mA PH Voltage differential 6A COMP 6 mA ENA, STATUS 10 mA 0.3 V AGND to PGND TJ Operating virtual junction temperature range -40C to 150C Tstg Storage temperature -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VI Input voltage TJ Operating junction temperature MAX UNIT 3 NOM 6 V -40 125 C DISSIPATION RATINGS(1)(2) (1) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25C POWER RATING TA = 70C POWER RATING TA = 85C POWER RATING 20 Pin PWP with solder 26.0C/W 3.85 W(3) 20 Pin PWP without solder 57.5C/W 2.11 W 1.54 W 1.73 W 0.96 W 0.69 W For more information on the PWP package, see the Texas Instruments technical brief (SLMA002). Test board conditions: 1. 3" x 3", four layers, thickness: 0.062" 2. 1.5 oz. copper traces located on the top of the PCB 3. 1.5 oz. copper ground plane on the bottom of the PCB 4. Ten thermal vias (see Recommended Land Pattern in the Applications Section of this data sheet) (3) Maximum power dissipation may be limited by overcurrent protection. (2) 2 TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 ELECTRICAL CHARACTERISTICS TJ = -40C to 125C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX fs = 350 kHz, RT open, PH pin open 6.2 9.6 fs = 386 kHz, RT = 160 k, PH pin open 8.4 12.8 1 1.4 2.95 3 UNIT SUPPLY VOLTAGE, VIN VIN I(Q) Input voltage range 3 Quiescent current Shutdown, ENA = 0 V 6 V mA UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO Stop threshold voltage, UVLO 2.7 V 2.8 V Hysteresis voltage, UVLO 115 mV Rising and falling edge deglitch, UVLO(1) 2.5 s BIAS VOLTAGE Output voltage, VBIAS I(VBIAS) = 0 2.7 2.8 Output current, VBIAS (2) 2.95 V 100 A REGULATION Line regulation(1)(3) IL = 1.5 A, fs = 350 kHz, TJ = 125C 0.07 %/V Load regulation(1)(3) IL = 0 A to 3 A, fs = 350 kHz, TJ = 125C 0.03 %/A kHz OSCILLATOR Internally set free running frequency Externally set free running frequency range RT open 265 350 440 RT = 180 k (1% resistor to AGND)(1) 252 280 308 RT = 160 k (1% resistor to AGND) 290 312 350 RT = 68 k (1% resistor to AGND)(1) 663 700 762 Ramp valley(1) 0.75 Ramp amplitude (peak-to-peak)(1) V 1 Minimum controllable on time(1) V 200 Maximum duty cycle(1) kHz ns 90% ERROR AMPLIFIER Error amplifier open loop voltage gain 1 k COMP to AGND(1) 90 110 Error amplifier unity gain bandwidth Parallel 10 k, 160 pF COMP to AGND(1) 3 5 Error amplifier common mode input voltage range Powered by internal LDO(1) 0 Input bias current, VSENSE VSENSE = Vref Output voltage slew rate (symmetric), COMP(1) 60 1 dB MHz VBIAS V 250 nA 1.4 V/s PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding deadtime) 10-mV overdrive(1) 70 85 ns 1.2 1.4 V SLOW-START/ENABLE Enable threshold voltage, ENA 0.82 Enable hysteresis voltage, ENA(1) Falling edge deglitch, 0.03 ENA(1) V s 2.5 Internal slow-start time(1) 2.6 3.35 4.1 0.18 0.3 ms STATUS Output saturation voltage, STATUS Isink = 2.5 mA Leakage current, STATUS VI = 3.6 V 1 V A (1) Specified by design Static resistive loads only (3) Specified by the circuit used in Figure 8. (2) 3 TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 ELECTRICAL CHARACTERISTICS (continued) TJ = -40C to 125C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VI = 3 V 4 6.5 VI = 6 V 4.5 7.5 MAX UNIT CURRENT LIMIT Current limit Current limit leading edge blanking time(1) Current limit total response time(1) A 100 ns 200 ns THERMAL SHUTDOWN Thermal shutdown trip point(1) 135 Thermal shutdown hysteresis(1) 150 165 C C 10 OUTPUT POWER MOSFETS rDS(on) Power MOSFET switches VI = 6 V(4) 59 88 VI = 3 V(4) 85 136 m (1) Specified by design Static resistive loads only (3) Specified by the circuit used in Figure 8. (4) Matched MOSFETs low-side r DS(on) production tested, high-side rDS(on) production tested. (2) HTSSOP PowerPAD (TOP VIEW) AGND VSENSE COMP STATUS BOOT PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT ENA REFIN VBIAS VIN VIN VIN PGND PGND PGND TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor and RT resistor. Connect the PowerPAD connection to AGND. BOOT 5 Bootstrap output. 0.022-F to 0.1-F low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect the frequency compensation network from COMP to VSENSE. ENA 19 Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and places device in a low quiescent current state. PGND 11-13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6-10 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. REFIN 18 External reference input. High impedance input to slow-start and error amplifier circuits. STATUS 4 Open drain output. Asserted low when VIN < UVLO, VBIAS and internal reference are not settled or the internal shutdown signal is active. Otherwise, STATUS is high. VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low-ESR 0.1-F to 1.0-F ceramic capacitor. VIN VSENSE 4 14-16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high-quality, low-ESR 10-F ceramic capacitor. 2 Error amplifier inverting input. Connect to output voltage compensation network/output divider. TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 INTERNAL BLOCK DIAGRAM VBIAS AGND Enable Comparator Falling Edge Deglitch ENA 1.2 V Hysteresis: 0.03 V 2.5 s VIN UVLO Comparator 2.95 V VDDQ Hysteresis: 0.16 V VIN ILIM Comparator Thermal Shutdown 150C VIN Leading Edge Blanking Falling and Rising Edge Deglitch VIN REG VBIAS SHUTDOWN 100 ns BOOT Sense FET 30 m 2.5 s SS_DIS SHUTDOWN PH REFIN Slow-start (0.25 V/ms minimum) + - R Q Error Amplifier S PWM Comparator LOUT CO Adaptive Dead-Time and Control Logic 25 ns Adaptive Dead Time Vtt VIN 30 m PGND OSC TPS54372 STATUS SS_DIS VSENSE COMP RT 5 TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 TYPICAL CHARACTERISTICS 90 120 VIN = 3.3 V IO = 3 A 80 60 40 20 0 -40 0 25 85 TJ - Junction Temperature - C VIN = 5 V IO = 3 A 80 70 60 50 40 30 20 10 0 -40 125 0 85 125 RT = Open 350 250 -40 0 Device Power Losses - W 700 RT = 68 k 600 500 RT = 100 k 400 1.75 1.5 VI = 3.3 V 1.25 1 VI = 5 V 0.75 0.5 0 1 2 3 IL - Load Current - A Figure 4 3.50 3.35 3.20 3.05 2.90 -40 4 0 RL = 10 k, CL = 160 pF, TA = 25C 100 -20 -40 -60 Phase -80 -100 60 -120 40 Gain 20 -140 -160 0 -180 -20 1 10 100 1k 10 k 100 k 1 M f - Frequency - Hz Figure 7 -200 10 M Phase - Degrees 140 80 25 Figure 6 ERROR AMPLIFIER OPEN LOOP RESPONSE 120 0 85 TJ - Junction Temperature - C Figure 5 Gain - dB 3.65 2.75 0 125 125 3.80 0.25 85 85 INTERNAL SLOW-START TIME vs JUNCTION TEMPERATURE 300 RT = 180 k 25 Figure 3 TJ - 125C fs = 700 kHz 2 TJ - Junction Temperature - C 6 450 TJ - Junction Temperature - C 2.25 25 550 DEVICE POWER LOSSES vs LOAD CURRENT 800 0 650 Figure 2 EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 200 -40 750 TJ - Junction Temperature - C Figure 1 f - Externally Set Oscillator Frequency - kHz 25 Internal Slow-Start Time - ms 100 INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE f - Internally Set Oscillator Frequency - kHz DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE Drain Source On-State Reststance - m Drain Source On-State Reststance - m DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 125 TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 APPLICATION INFORMATION Figure 8 shows the schematic diagram for a typical TPS54372 application. The TPS54372 (U1) can provide up to 3 A of output current at a nominal output voltage of one half of VDDQ (typically 1.25 V). For proper operation, the PowerPAD underneath the integrated circuit TPS54372 is soldered directly to the printed-circuit board. TP2 VI J1 2 1 GND TP1 TP9 TP3 C4 10 F 1 2 3 R2 36.5 k 4 C2 470 pF 5 6 C6 0.047 pF C1 12 pF R1 10 k 7 AGND RT VSENSE COMP ENA REFIN STATUS VBIAS BOOT VIN PH VIN J2 VDDQ 2 20 R6 10 k 19 18 GND C13 0.1 F 17 R7 10 k 16 15 C9 1 F 14 VIN 13 PGND 9 12 PH PGND 10 11 PGND PH PwrPAD 8 PH C12 0.1 F R5 71.5 k PH TP8 C8 10 F 21 R3 1.21 k C3 1500 pF 1 U1 TPS54372PWP TP4 TP5 1 2 L1 1 H R4 2.4 1 2 + C7 150 F + C5 3300 pF C10 150 F C11 1 F J2 VTTQ GND TP7 TP6 Figure 8. Application Circuit COMPONENT SELECTION FEEDBACK CIRCUIT The values for the components used in this design example were selected for good transient response and small PCB area. Special polymer capacitors are utilized in the output filter circuit. A small size, small value output inductor is also used. Compensation network components are chosen to maximize closed loop bandwidth and provide good transient response characteristics. Additional design information is available at www.ti.com. The values for these components are selected to provide fast transient response times. Components R1 R2, R3, C1, C2, and C3 forms the loop compensation network for the circuit. For this design, a Type 3 topology is used. The transfer function of the feedback network is chosen to provide maximum closed loop gain available with open loop characteristics of the internal error amplifier. Closed loop crossover frequency is typically between 80 kHz and 125 kHz for input from 3 V to 6 V. INPUT VOLTAGE The input voltage is a nominal 3.3 or 5 VDC. The input filter (C4) is a 10-F ceramic capacitor (Taiyo Yuden). Capacitor C8, a 10-F ceramic capacitor (Taiyo Yuden) that provides high frequency decoupling of the TPS54372 from the input supply, must be located as close as possible to the device. Ripple current is carried in both C4 and C8, and the return path to PGND should avoid the current circulating in the output capacitors C7, C10, and C11. OPERATING FREQUENCY In the application circuit, RT is grounded through a 71.5 k resistor to select the operating frequency of 700 kHz. To set a different frequency, place a 68-k to 180-k resistor between RT (pin 20) and analog ground or leave RT floating to select the default of 350 kHz. The resistance can be approximated using the following equation: R+ 500 kHz Switching Frequency 100 [kW] (1) 7 TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 OUTPUT FILTER The output filter is composed of a 1-H inductor and two 150-F capacitors. The inductor is a low dc resistance (0.010 ) type, Vishay IHLP-2525CZ-01 1-H, 8.5-A rated dc output. The capacitors used are 150 F, 6.3-V special polymer types. GROUNDING AND PowerPAD LAYOUT The TPS54372 has two internal grounds (analog and power). Inside the TPS54372, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD must be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54372, particularly at higher output currents. However, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground areas are recommended. The analog ground area should be tied to the power ground area directly at the IC to reduce noise between the two grounds. The only components that should tie directly to the power ground area are the input capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54372. The power ground areas as well as the powerpad mounting area should be tied to any internal ground planes using multiple vias. The layout of the TPS54372 evaluation module is representative of a 6 PL 0.0130 4 PL 0.0180 Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance recommended layout for a 2-layer board with the bottom layer representing the system ground plane. Documentation for the TPS54372 evaluation module can be found on the Texas Instruments web site under the TPS54372 product folder. LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal performance should be included in areas not under the device package. Minimum Recommended Thermal Vias: 6 x .013 dia. Inside PowerPAD Area 4 x .018 dia. Under Device as Shown. Additional .018 dia. Vias May be Used if Top Side Analog Ground Area is Extended. 0.0150 0.06 0.0227 0.0600 0.0400 0.2560 0.2454 0.1010 0.0400 0.0600 0.0256 Minimum Recommended Top Side Analog Ground Area 0.1700 0.1340 0.0620 0.0400 Minimum Recommended Exposed Copper Area For PowerPAD. 5mm Stencils may Require 10 Percent Larger Area Figure 9. Recommended Land Pattern for 20-Pin PWP PowerPAD 8 TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 PERFORMANCE GRAPHS LOAD REGULATION vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 1.255 100 1.253 fs = 700 kHz, TA = 25C, VI = 5 V, VO = 1.25 V 95 Load Regulation 85 80 75 70 65 fs = 700 kHz, VI = 5 V, VO = 1.25 V 1.249 1.247 50 2 3 1 Figure 10 fs = 700 kHz, TA = 25C, VO = 1.25 V 2 3 4 3 4 5 VI - Input Voltage - V Figure 11 VO - Output Voltage - 50 mV/div fs = 700 kHz, IO = 3 A, VI = 5 V, VO = 1.25 V SLOW-START TIMING VI = 5 V, VO = 1.25 V 0 A to 2.25 A t - Time - 25 ms/div t - Time - 1 s/div Figure 13 6 Figure 12 TRANSIENT RESPONSE OUTPUT RIPPLE VOLTAGE VI = 5 V, VO = 1.25 V t -Time - 2.5 ms/div Figure 15 Figure 14 AMBIENT TEMPERATURE vs LOAD CURRENT SOURCE-SINK TRANSIENT RESPONSE 125 VI = 5 V, VO = 1.25 V -1.5 A to 1.5 A T A - Ambient Temperature - C 115 I O - Output Current - 1 A/div VO - Output Voltage - 50 mV/div 1.249 IO - Output Current - A IO - Output Current - A Output Ripple Voltage - 10 mV/div IO = 3 A 1.247 0 4 I O - Output Current - 1 A/div 1 1.25 1.248 1.245 0 IO = 1.5 A 1.251 VO - Output Voltage - 500 mV/div 55 1.251 VI - Input Voltage - 2 V/div 60 IO = 0 A 1.252 Line Regulation 1.253 90 Efficiency - % LINE REGULATION vs INPUT VOLTAGE 95 85 VI = 3.3 V 75 Safe Operating Area(1) 65 55 45 TA = 25C, VO = 1.25 V 35 25 0 t - Time - 100 s/div Figure 16 VI = 5 V 105 (1) 1 2 3 IL - Load Current - A 4 Safe operating area is applicable to the test board conditions listed in the dissipation rating table section of this data sheet. Figure 17 9 TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 DETAILED DESCRIPTION UNDERVOLTAGE LOCK OUT (UVLO) The TPS54372 incorporates an undervoltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-s rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be a useful as a reference voltage for external circuits. VOLTAGE REFERENCE The REFIN pin provides an input for a user supplied tracking voltage. Typically this input is one half of VDDQ. The input range for this external reference is 0.2 V to 1.75 V. Above this level, the internal bandgap reference overrides the externally supplied reference voltage. ENABLE (ENA) The enable pin, ENA, provides a digital control to enable or disable (shutdown) the TPS54372. An input voltage of 1.4 V or greater ensures the TPS54372 is enabled. An input of 0.82 V or less ensures the device operation is disabled. These are not standard logic thresholds, even though they are compatible with TTL outputs. When ENA is low, the oscillator, slow-start, PWM control and MOSFET drivers are disabled and held in an initial state ready for device start-up. On an ENA transition from low to high, device start-up begins with the output starting from 0 V. SLOW-START The slow-start circuit provides start-up slope control of the output voltage to limit in-rush currents. The nominal internal slow-start rate is 0.25 V/ms with the minimum rate being 0.35 V/ms. When the voltage on REFIN rises faster than the internal slope or is present when device operation is enabled, the output rises at the internal rate. If the reference voltage on REFIN rises more slowly, then the output rises at approximately the same rate as REFIN. VBIAS REGULATOR (VBIAS) The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V and external loads on 10 OSCILLATOR AND PWM RAMP The oscillator frequency can be set to an internally fixed value of 350 kHz by leaving the RT pin unconnected (floating). If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a resistor to the RT pin to ground. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: Switching Frequency + 100 kW R 500 [kHz] (2) The following table summarizes the frequency selection configurations: SWITCHING FREQUENCY RT PIN 350 kHz, internally set Float Externally set 280 kHz to 700 kHz R = 180 k to 68 k ERROR AMPLIFIER The high performance, wide bandwidth, voltage error amplifier sets the TPS54372 apart from most dc/dc converters. The user has a wide range of output L and C filter components to suit the particular application needs. Type 2 or type 3 compensation can be employed using external compensation components. TPS54372-Q1 www.ti.com SGLS267E - OCTOBER 2004 - REVISED JUNE 2008 PWM CONTROL Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54372 is capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator is tripped. DEAD-TIME CONTROL AND MOSFET DRIVERS Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver does not turn on until the gate drive voltage to the low-side FET is below 2 V, while the low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V. The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-. bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. OVERCURRENT PROTECTION The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100 ns leading edge blanking circuit prevents false tripping of the current limit when the high-side switch is turning on. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. THERMAL SHUTDOWN The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150C. The device is released from shutdown automatically when the junction temperature decreases to 10C below the thermal shutdown trip point, and starts up under control of the slow-start circuit. Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the fault condition, and then shutting down upon reaching the thermal limit trip point. This sequence repeats until the fault condition is removed. STATUS The status pin is an open drain output that indicates when internal conditions are sufficient for proper operation. STATUS can be coupled back to a system controller or monitor circuit to indicate that the termination or tracking regulator is ready for start-up. STATUS is high impedance when the TPS54372 is operating or ready to be enabled. STATUS is active low if any of the following occur: D D D VIN < UVLO threshold VBIAS or internal reference have not settled. Thermal shutdown is active. 11 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPS54372QPWPRQ1 ACTIVE HTSSOP PWP Pins Package Eco Plan (2) Qty 20 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS54372-Q1 : * Catalog: TPS54372 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP(R) Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IF and ZigBee(R) Solutions www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2011, Texas Instruments Incorporated