¬
¬
¬
¬
¬
Security Cameras
Action Cameras
High Resolution Consumer Cameras
Digital Still Cameras (DSC)
Digital Video Camcorders (DVC)
Applications
¬
¬
¬
¬
¬
2 µm x 2 µm pixel
optical size of 1/1.8"
programmable controls for:
- frame rate
- mirror and flip
- cropping
- windowing
supports output formats:
- 12-/10-bit RGB RAW
supports image sizes:
- 4K2K (3840x2160)
- 2560 x 1440
- 1080p (1920x1080)
- 720p (1280x720)
supports 2x2 binning
standard serial SCCB interface
12-bit ADC
up to 4-lane MIPI/LVDS serial output
interface (supports maximum speed
up to 1500 Mbps/lane)
2-exposure staggered HDR support
programmable I/O drive capability
light sensing mode (LSM)
PLL with SCC support
support for FSIN
¬
¬
¬
¬
¬
¬
¬
¬
¬
Product Features
¬OS08A10-H92A-1B
(color, lead-free) 92-pin CSP
Ordering Information
¬
¬
¬
¬
¬
¬
¬
active array size: 3840 x 2160
power supply:
- core: 1.2V
- analog: 2.8V
- I/O: 1.8V
power requirements:
- active: 240 mA
- XSHUTDOWN: <10 µA
temperature range:
- operating: -30°C to +85°C junction
temperature
- stable image: 0°C to +60°C junction
temperature
output formats: 10/12-bit RGB RAW
lens size: 1/1.8"
input clock frequency: 6 ~ 27 MHz
¬
¬
¬
¬
¬
¬
¬
¬
¬
¬
lens chief ray angle: 11° linear
max S/N ratio: 39 dB
dynamic range: 74 dB @ 16x gain
maximum image transfer rate:
- 4K2K: 60 fps
- 2560 x 1440: 60 fps
- 1080p: 120 fps
sensitivity: 13,000 e-/Lux-sec
scan mode: progressive
maximum exposure interval: VTS-8
pixel size: 2.0 µm x 2.0 µm
image area: 7736.256 µm x 4379.616 µm
package dimensions:
- CSP: 8929.2 µm x 6330 µm
Product Specifications
Version 1.4, October, 2018
OmniVision reserves the right to make changes to their products or to discontinue any product
or service without further notice. OmniVision, the OmniVision logo, and PureCel are registered
trademarks of OmniVision Technologies, Inc. All other trademarks are the property of their
respective owners.
4275 Burton Drive
Santa Clara, CA 95054
USA
Tel: + 1 408 567 3000
Fax: + 1 408 567 3001
www.ovt.com
OS08A10
Functional Block Diagram
OS08A10
image sensor core image
sensor
processor
image
interface
column
sample/hold
row select
PLL PLL
control register bank
SCCB interface
timing generator and system control logic
gain
control
XVCLK
TM
XSHUTDOWN
XSHUTDOWN2
PWDNB
VSYNC
HREF
STROBE
GPIO[3:0]
SID
SCL
SDA
MCP/N
MDP/N[3:0]
image
array AMP
ISP
12-bit
ADC
FIFO
MIPI/LVDS TX