M48ST59W 64 Kbit (8 Kbit x 8) SUPERVISORY TIMEKEEPER SRAM PRELIMINARY DATA FEATURES SUMMARY 2.7V to 3.6V OPERATING VOLTAGE INTEGRATED ULTRA-LOW POWER SRAM, REAL TIME CLOCK (RTC), POWER-FAIL CONTROL CIRCUIT, CRYSTAL, and BATTERY 1.25V REFERENCE (for PFI/PFO) AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES VPFD (Power-fail Deselect Voltage): M48ST59W: 2.50V VPFD 2.70V MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) Figure 1. Package PROGRAMMABLE ALARM and INTERRUPT FUNCTION (valid even during battery back-up mode). BYTEWIDE , RAM-LIKE CLOCK ACCESS BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS FREQUENCY TEST OUTPUT FOR RTC CALIBRATION BATTERY LOW FLAG PROGRAMMABLE TREC PACKAGING INCLUDES a 44-LEAD SOIC and SNAPHAT TOP (to be ordered separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL SNAPHAT (SH) Battery & Crystal 44 1 SO44 (MH) January 2001 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/29 M48ST59W TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SOIC Pin Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating Modes (Table 2.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Register Map (Table 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode AC Waveforms (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode AC Characteristics (Table 4.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Mode AC Waveforms (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable Controlled, Write Mode AC Waveforms (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Mode AC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Programmable Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interrupt Reset Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Crystal Accuracy Across Temperature (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock Calibration (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Setting Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Alarm Repeat Mode (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Back-up Mode Alarm Waveform (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Fail Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Adding Hysteresis (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Hysteresis on Rising VIN (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 tREC Definitions POWER-ON (Table 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Initial Power-On Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Default Values (Table 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/29 M48ST59W POWER SUPPLY DECOUPLING AND UNDERSHOOT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . 18 Supply Voltage Protection (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Absolute Maximum Ratings (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC and AC Measurement Conditions (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Testing Load Circuit (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Capacitance (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC Characteristics (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power Down/Up Mode AC Waveforms (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power Down/Up Trip Points DC Characteristics (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power Down/Up AC Characteristics (Table 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3/29 M48ST59W SUMMARY DESCRIPTION The M48ST59W SUPERVISORY TIMEKEEPER RAM is an 8Kbit x 8 non-volatile static RAM and real time clock. The monolithic chip is available in a surface mount package to provide a highly integrated battery backed-up memory and real time clock solution. The 44-pin, 330mil SOIC package provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be attached after the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/ crystal packages are shipped separately in plastic, anti-static tubes or in Tape & Reel form (see Table 18, page 27) for the part numbering scheme.) The battery/crystal package (e.g., SNAPHAT) part number is "M4T28-BR12SH" or "M4T32BR12SH". Caution: Do not place the SNAPHAT battery/crystal package "M4TXX-BR12SH" in conductive foam, as this will drain the lithium button-cell battery. Figure 2. Logic Diagram Figure 3. SOIC Pin Connections VCC 13 8 A0-A12 DQ0-DQ7 W M48ST59W E IRQ/FT G PFO PFI RST VSS AI04600 Table 1. Signal Names A0-A12 DQ0-DQ7 IRQ/FT RST 4/29 Address inputs Data Inputs/Outputs Interrupt/Frequency Test Output (Open Drain) Reset Output (Open Drain) E Chip Enable G Output Enable Input W Write Enable Input PFO Power Fail Output PFI Power Fail Input VCC Supply Voltage Input VSS Ground NC PFO A12 A7 A6 A5 A4 A3 NC NC NC NC NC NC A2 A1 A0 RST DQ0 DQ1 DQ2 VSS 1 44 2 43 3 42 4 41 5 40 6 39 7 38 37 8 9 36 10 35 M48ST59W 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 23 22 VCC W PFI NC IRQ/FT A8 A9 A11 NC NC G NC NC A10 E NC DQ7 DQ6 DQ5 DQ4 DQ3 NC AI04601 M48ST59W Figure 4. Block Diagram IRQ/FT OSCILLATOR AND CLOCK CHAIN 16 x 8 TIMEKEEPER REGISTERS 32,768 Hz CRYSTAL A0-A12 POWER DQ0-DQ7 8,176 x 8 SRAM ARRAY LITHIUM CELL E W VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD G PFO 1.25V VCC RST PFI VSS AI04602 5/29 M48ST59W OPERATING MODES The static memory array and the quartz-controlled clock oscillator of the M48ST59W are integrated on one silicon chip (see Figure 4, page 5). The memory locations used to provide user accessible BYTEWIDE clock information are in the bytes with addresses 1FFFh-1FF9h (see Table 3, page 7). These clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour, BCD format. Corrections for 28, 29 (leap year - compliant until the year 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT read/write memory cells. The M48ST59W includes a clock control circuit which updates the clock bytes with current information approximately once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48ST59W also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit writes protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below VSO, the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2. Operating Modes Symbol VCC E G W DQ7 - DQ0 Power VIH X X High Z Standby VIL X V IL D IN Active Read VIL VIL VIH DOUT Active Read VIL VIH VIH High Z Active Deselect Write 2.7 to 3.6V Deselect VSO to VPFD (min)(2) X X X High Z CMOS Standby Deselect VSO X X X High Z Battery Back-up Mode Note: X = VIH or VIL; VSO = Battery Back-up Swit chover Voltage. 1. See Table 13 on page 22. 6/29 M48ST59W Table 3. Register Map Data Address D7 D6 1FFFh D5 D4 D3 D2 D1 10 Years 0 10 M D0 Function/Range BCD Format Year Year 00-99 Month Month 01-12 Date Date 01-31 Century/ Day 00-01/ 01-07 Hours Hour 00-23 1FFEh 0 0 1FFDh 0 0 1FFCh TR FT 1FFBh 0 0 1FFAh 0 10 Minutes Minutes Minutes 00-59 1FF9h ST 10 Seconds Seconds Seconds 00-59 1FF8h W R S 1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog 1FF6h AFE Y ABE Y Y Y Y Y Interrupts 1FF5h RPT4 Y Al. 10 Date Alarm Date Alarm Date 01-31 1FF4h RPT3 Y Al. 10 Hours Alarm Hours Alarm Hours 00-23 1FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Minutes 00-59 1FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm Seconds 00-59 1FF1h Y Y Y Y Y Y Y Y Unused 1FF0h WDF AF Z BL Z Z Z Z Flags 10 Date CB CEB 0 Day 10 Hours Keys: S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to zero Y = '1' or '0 Z = '0' and are Read only AF = Alarm Flag BL = Battery Low Calibration Control WDS = Watchdog Steering Bit BMB0-BMB4 = Watchdog Multiplier Bits RB0-RB1 = Watchdog Resolution Bits AFE = Alarm Flag Enable ABE = Alarm in Battery Back-up Mode Enable RPT1-RPT4 = Alarm Repeat Mode Bits WDF = Watchdog Flag CEB = Century Enable Bit CB = Century Bit TR = TREC Bit 7/29 M48ST59W Read Mode The M48ST59W is in the Read Mode whenever Write Enable (W) is high and Chip Enable (E) is low. The unique address specified by the 13 Address Inputs defines which one of the 8,176 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access Time (tAVQV) after the last address input signal is stable, providing that the E and Output Enable (G) access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access Time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold Time (tAXQX) but will be indeterminate until the next Address Access. Figure 5. Read Mode AC Waveforms tAVAV A0-A12 VALID tAVQV tAXQX tEHQX tELQV E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI04606 Table 4. Read Mode AC Characteristics M48ST59W Symbol Parameter -70 Min tAVAV tAVQV(1) Read Cycle Time Unit Max 70 ns Address Valid to Output Valid 70 ns Chip Enable Low to Output Valid 70 ns tGLQV(1) Output Enable Low to Output Valid 35 ns tELQX(2) Chip Enable Low to Output Transition 5 ns tGLQX(2) Output Enable Low to Output Transition 5 ns tEHQZ(2) Chip Enable High to Output Hi-Z 25 ns tGHQZ(2) Output Enable High to Output Hi-Z 25 ns tAXQX(1) Address Transition to Output Transition tELQV (1) Note: 1. CL = 50 pF (see Figure 15, page 20). 2. CL = 5 pF (see Figure 15, page 20). 8/29 10 ns M48ST59W Write Mode The M48ST59W is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write En- able prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for t WHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. Figure 6. Write Mode AC Waveforms tAVAV A0-A12 VALID tAVWH tAVEL tWHAX E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI04607 Figure 7. Chip Enable Controlled, Write Mode AC Waveforms tAVAV A0-A12 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI04608 9/29 M48ST59W Table 5. Write Mode AC Characteristics M48ST59W Symbol Parameter -70 Min Unit Max tAVAV Write Cycle Time 70 ns tAVWL Address Valid to Write Enable Low 0 ns tAVEL Address Valid to Chip Enable Low 0 ns tWLWH Write Enable Pulse Width 50 ns tELEH Chip Enable Low to Chip Enable High 55 ns tWHAX Write Enable High to Address Transition 0 ns tEHAX Chip Enable High to Address Transition 0 ns tDVWH Input Valid to Write Enable High 30 ns tDVEH Input Valid to Chip Enable High 30 ns tWHDX Write Enable High to Input Transition 5 ns tEHDX Chip Enable High to Input Transition 5 ns tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 ns tAVWH Address Valid to Write Enable High 60 ns tAVE1H Address Valid to Chip Enable High 60 ns Write Enable High to Output Transition 5 ns tWHQX (1, 2) Note: 1. CL = 5pF (see Figure 15, page 20). 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 10/29 M48ST59W Data Retention Mode With valid VCC applied, the M48ST59W operates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the Vcc fall time is not less than tF. The M48ST59W may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48ST59W for an accumulated period of tDR (at room temperature when VCC is less than VSO; see Table 13, page 22). As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external V CC. Normal RAM operation can resume tREC after VCC reaches VPFD(max). For more information on Data Retention Storage Life refer to the Application Note AN1012. Power-On Reset The M48ST59W continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for 40ms to 200ms after VCC passes VPFD. RST is valid for all VCC conditions. The RST pin is an open drain output and an appropriate resistor to VCC should be chosen to control rise time. Programmable Interrupts The M48ST59W provides two programmable interrupts; an alarm and a watchdog. When an interrupt condition occurs, the M48ST59W sets the appropriate flag bit in the flag register 1FF0h. The interrupt enable bits (AFE and ABE) in 1FF6h and the Watchdog Steering bit (WDS) in 1FF7h allow the interrupt to activate the IRQ/FT pin. The interrupt flags and the IRQ/FT output are cleared by a read to the flags register. An interrupt condition reset will not occur unless the addresses are stable at the flag location for at least 15ns while the device is in the read mode (see Figure 8, page 11). The IRQ/FT pin is an open drain output and requires a pull-up resistor (10k recommended) to VCC. The pin remains in the high impedance state unless an interrupt occurs or the frequency test mode is enabled. Figure 8. Interrupt Reset Waveforms 15 ns Min A0-A12 ADDRESS 1FF0h ACTIVE FLAG BIT IRQ/FT HIGH-Z AI04609 11/29 M48ST59W CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the Control register (1FF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs within a second after the bit is reset to a '0'. Setting the Clock Bit D7 of the Control register (1FF8h) is the WRITE bit. Setting the WRITE bit to a '1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 3, page 7). Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur within approximately one second. Note: Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset to `0'. Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. When reset to a '0', the M48ST59W oscillator starts within one second. Note: It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT), the STOP bit (ST) or the CENTURY ENABLE bit (CEB). 12/29 Calibrating the Clock The M48ST59W is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48ST59W improves to better than +1/-2 ppm at 25C. The oscillation rate of any crystal changes with temperature (see Figure 9, page 13). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M48ST59W design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage (see Figure 10, page 13). The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration byte occupies the five lower order bits (D4-D0) in the Control register (1FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles; for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48ST59W may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration byte. M48ST59W The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512Hz when the Stop bit (D7 of 1FF9h) is '0', the FT bit (D6 of 1FFCh) is '1', the AFE bit (D7 of 1FF6h) is '0', and the Watchdog Steering bit (D7 of 1FF7h) is '1' or the Watchdog Register is reset (1FF7h = 0). Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. Note: For more information on calibration, see the Application Note AN934, "TIMEKEEPER Calibration." Figure 9. Crystal Accuracy Across Temperature Frequency (ppm) 20 0 -20 -40 -60 -80 -100 F = -0.038 ppm (T - T )2 10% 0 F C2 -120 T0 = 25 C -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature C AI00999 Figure 10. Clock Calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 13/29 M48ST59W Setting Alarm Clock Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific day of the month or repeat every month, day, hour, minute, or second. It can also be programmed to go off while the M48ST59W is in the battery back-up mode of operation to serve as a system wake-up call. RPT1-RPT4 put the alarm in the repeat mode of operation. Possible configurations are shown in Table 6. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. Note: The user must transition address (or toggle chip enable) to see the Flag bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT1-RPT4, AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. To disable alarm, write `0' to the Alarm Date register and RPT1-4. The alarm flag and the IRQ/FT output are cleared by a read to the Flags register. The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48ST59W was in the deselect mode during power-up. Figure 11 illustrates the back-up mode alarm timing. Table 6. Alarm Repeat Mode RPT4 RPT3 RPT2 RPT1 Alarm Activated 1 1 1 1 Once per Second 1 1 1 0 Once per Minute 1 1 0 0 Once per Hour 1 0 0 0 Once per Day 0 0 0 0 Once per Month Figure 11. Back-up Mode Alarm Waveform tREC VCC VPFD (max) VPFD (min) VSO ABE, AFE bit in Interrupt Register AF bit in Flags Register IRQ/FT HIGH-Z HIGH-Z AI04610 14/29 M48ST59W Watchdog Timer The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the eight bit Watchdog Register (Address 1FF7h). The five bits (BMB4-BMB0) store a binary multiplier and the two lower order bits (RB1RB0) select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3 x 1 or 3 seconds). Note: Accuracy of timer is a function of the selected resolution. If the processor does not reset the timer within the specified period, the M48ST59W sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. The WDF is reset by reading the Flags Register (Address 1FF0h). The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to a '0', the watchdog will activate the IRQ/FT pin when timedout. When WDS is set to a '1', the watchdog will output a negative pulse on the RST pin for a duration of 40ms to 200ms. The Watchdog register and the FT bit will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1'. The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register. The time-out period then starts over. Should the watchdog timer time-out, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A read of the Flags Register will reset the Watchdog Flag (D7, Register 1FF0h). The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/ FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. Battery Low Flag The M48ST59W automatically performs periodic battery voltage monitoring upon power-up and at factory-programmed time intervals of 24 hours (at day rollover) as long as the device is powered and the oscillator is running. The Battery Low flag (BL), Bit D4 of the Flags Register 1FF0h, will be asserted high if the SNAPHAT battery is found to be less than approximately 2.5V. The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5V (approximately), which may be insufficient to maintain data integrity. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data has not been compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, it is recommended that the battery be replaced. The SNAPHAT top may be replaced while VCC is applied to the device. Note: Battery monitoring is a useful technique only when performed periodically. The M48ST59W only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. Power-Fail Comparator The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from the VPFD comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the M48ST59W or the microprocessor drops below the minimum operating voltage. During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low. This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of V PFI for the write protect time (tREC), which is the time from VPFD (max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. 15/29 M48ST59W Hysteresis may be added to PFI for additional noise margin if desired (see Figure 12, page 16). The ratio of R1 and R2 should be selected such that PFI sees VPFI when VIN falls to its trip point (VTRIP). Connecting R3 between PFI and PFO provides the hysteresis and should typically be more than ten (10) times the value of R1 or R2. The hysteresis window will extend both above (VH) and below (VL) the original trip point (Vt). Connecting an ordinary signal diode in series with R3 causes the lower trip point (VL) to coincide with the trip point without hysteresis, so the entire hysteresis window occurs above VTRIP (see Figure 13). This method provides additional noise margin without compromising the accuracy of the powerfail threshold when the monitored voltage is falling. The current through R1 and R2 should be at least 1uA to ensure that the 25nA PFI input current does not shift the trip point. R3 should be larger than 82K Ohms to avoid loading down the PFO pin. The capacitor C1 is added for noise rejection, but is optional. Figure 12. Adding Hysteresis VIN PFO R1 0V PFI R2 0V VCC VL VTRIP VH VIN VTRIP = VPFI ( R1 + R2) R2 R3 VH = ( VPFI + VPFH ) ( R1) ( 1 + 1 + 1 ) R1 R2 R3 V VL = R1 [ VPFI ( 1 + )1 + 1 - CC] R1 R2 R3 R3 C1 PFO GND where VPFI = 1.25V VPFH = 10mV TO CONTROLLER AI04611 Figure 13. Hysteresis on Rising VIN VIN PFO R1 0V PFI R2 VCC VTRIP VH VIN VTRIP = VPFI ( R1 + R2) R2 R3 C1 VD 1 + 1 + 1 VH = R1[ ( VPFI + VPFH ) ( R1 R2 R3 ) - R3 ] PFO GND TO CONTROLLER 0V where VPFI = 1.25V VPFH = 10mV VD = Diode Forward Voltage Drop AI04612 16/29 M48ST59W Century Bit Bits D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a "1" will cause CB to toggle, either from a "0" to "1" or from "1" to "0" at the turn of the century (depending upon its initial state). If CEB is set to a "0", CB will not toggle. Note: The WRITE Bit must be set in order to write to the CENTURY Bit. TREC Bit Bit D7 of Clock Register 1FFCh contains the TREC Bit (TR). TREC refers to the automatic continuation of the deselect time after VCC reaches VPFD (max). This allows for a voltage settling time before writes may again be performed to the device after a power-down condition. The TREC Bit will allow the user to set the length of this deselect time as defined by Table 7. Table 7. tREC Definitions POWER-ON TREC Bit (TR) tREC Time(1) 0 40 ms to 200 ms 1 2 ms (max) Note: 1. Initial default is undefined. Power-on Reset The M48ST59W continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for tREC (see Table 7) after VCC passes VPFD. The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time. Initial Power-On Defaults Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT (see Table 8): Table 8. Default Values W R FT AFE ABE WATCHDOG(1) Register Initial Power-up (Battery Attach for SNAPHAT)(2) 0 0 0 0 0 0 Subsequent Power-up / RESET(3) 0 0 0 0 0 0 Power-down(4) 0 0 0 1 1 0 Conditi on Note: 1. 2. 3. 4. WDS, BMB0-BMB4, RBO, RB1. State of other control bits undefined. State of other control bits remains unchanged. Assuming these bits set to '1' prior to power-down. 17/29 M48ST59W POWER SUPPLY DECOUPLING AND UNDERSHOOT PROTECTION Figure 14. Supply Voltage Protection ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy VCC stored in the bypass capacitors will be released as low going spikes are generated or energy will be VCC absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (see Figure 14) is recommended in order to provide the needed filtering. 0.1 mF DEVICE In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values VSS below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from AI04603 these voltage spikes, it is recommended to connect a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. 18/29 M48ST59W MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 9. Absolute Maximum Ratings Symbol TA Parameter Operating Temperature Value Unit Grade 1 0 to 70 C Grade 6 -40 to 85 C SNAPHAT -40 to 85 C SOIC -55 to 125 C 260 C TSTG(2) Storage Temperature (VCC, Oscillator Off) TSLD Lead Solder Temperature for 10 seconds VCC Supply Voltage (on any pin relative to Ground) -0.3 to 4.6 V VIO Input or Output Voltages -0.3 to 4.6 V IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). CAUTION! Negative undershoo ts below -0.3V are not allowed on any pin while in the Battery Back-up Mode. CAUTION! Do NOT wave-solder the SOIC to avoid damaging the SNAPHAT sockets. 19/29 M48ST59W DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 10. DC and AC Measurement Conditions Parameter M48ST59W VCC Supply Voltage 2.7 to 3.6V Ambient Operating Temperature -40 to 85C Load Capacitance (CL) 50pF Input Rise and Fall Times 5ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V Figure 15. AC Testing Load Circuit 645 DEVICE UNDER TEST C L= 50 pF or 5 pF 1.75V CL includes JIG capacitance AI04604 Table 11. Capacitance Symbol CIN C IO(1) Parameter Input Capacitance Input / Output Capacitance Test Condition Min Max Unit V IN = 0V 10 pF VOUT = 0V 10 pF Note: Effective capacitance measured with power supply at 3.6V. Sampled only, not 100% tested. 1. Outputs were deselected. 20/29 M48ST59W Table 12. DC Characteristics M48ST59W Symbol Parameter Test Condition Unit Min ILI (1) Input Leakage Current 0V VIN VCC Input Leakage Current (PFI) 0V VIN VCC ILO(1) Output Leakage Current ICC1 Supply Current ICC2 Supply Current (Standby) TTL ICC3 Supply Current (Standby) CMOS VIL(2) Input Low Voltage VIH Input High Voltage VOL VOH Typ Max 1 -25 2 A 25 0V VOUT VCC 1 A Outputs open 30 mA E = VIH 2 mA E = VCC - 0.2V 1 mA -0.2 0.8 V 2 VCC + 0.2 V Output Low Voltage IOL = 2.1mA 0.4 V Output Low Voltage (IRQ/FT and RST)(3) IOL = 10mA 0.4 V Output High Voltage IOH = -1mA 2.4 V Note: 1. Outputs deselected. 2. Negative spikes of -1V allowed for up to 10ns once per cycle. 3. The IRQ/FT and RST pins are Open Drain. 21/29 M48ST59W Figure 16. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tF tR tFB tPD PFO tRB tDR tREC VALID INPUTS VALID RECOGNIZED DON'T CARE RECOGNIZED RST HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI04605 Table 13. Power Down/Up Trip Points DC Characteristics Symbol Parameter VPFD Power-fail Deselect Voltage V SO Battery Back-up Switchover Voltage VPFI PFI Input Threshold tDR(3) Expected Data Retention Time (at 25 C) Min Typ Max Unit 2.5 2.6 2.7 V VPFD -100mV 1.225 1.250 mV 1.275 Grade 1 7 Years Grade 6(2) 10 Years Note: 1. All voltages referenced to VSS. 2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device). 3. At 25C 22/29 V M48ST59W Table 14. Power Down/Up AC Characteristics Symbol Parameter Min Typ Max Unit 0 s VPFD (max) to VPFD (min) VCC Fall Time 300 s VPFD (min) to VSS VCC Fall Time 10 s tR VPFD (min) to VPFD (max) VCC Rise Time 10 s tRB VSS to VPFD (min) VCC Rise Time 1 s tPFD PFI to PFO Propagation Delay tPD E or W at VIH before Power Down tF(1) tFB(2) tREC(3) VPFD (max) to RST High 15 Note 3 25 s ms Note: 1. VPFD (max) to VPFD (min) Fall Time of less than tF may result in deselection/write protection not occurring until 200 s after V CC passes V PFD (min). 2. VPFD (min) to VSS Fall Time of less than tFB may cause corruption of RAM data. 3. tREC is undefined at initial power-up. Refer to Table 7 on page 17. 23/29 M48ST59W PACKAGE MECHANICAL Figure 17. SO44 - 44-lead Plastic Small Outline, Package Outline A2 A C B eB e CP D N E H A1 L 1 SOH-A Note: Drawing is not to scale. Table 15. SOH44 - 44-lead Plastic Small Outline, Package Mechanical Data mm inches Symb Typ Min A Typ Min Max 3.05 0 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.46 0.014 0.018 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 - - - - eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 a 0 8 0 8 N 44 e CP 24/29 Max 0.81 0.032 44 0.10 0.004 M48ST59W Figure 18. SH - 4-pin SNAPHAT Housing for 48 mAh Battery and Crystal, Package Outline A1 A2 A A3 eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 16. SH - 4-pin SNAPHAT Housing for 48 mAh Battery and Crystal, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min Max 9.78 0 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 0.38 0 0.015 A3 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 eA 25/29 M48ST59W Figure 19. SH - 4-pin SNAPHAT Housing for 120 mAh Battery and Crystal, Package Outline A1 A2 A A3 eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 17. SH - 4-pin SNAPHAT Housing for 120 mAh Battery and Crystal, Package Mechanical Data mm inches Symb Typ Min A Typ Min Max 10.54 0 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 0.38 0 0.015 A3 26/29 Max B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M48ST59W PART NUMBERING Table 18. Ordering Information Scheme Example: M48ST 59W -70 MH 1 TR Device Type M48ST Supply Voltage and Write Protect Voltage 59W = VCC = 2.7 to 3.6V; VPFD = 2.5 to 2.7V Speed -70 = 70ns -100 = 100ns Package MH (1) = SOH44 Temperature Range 1 = 0 to 70C 6 = -40 to 85C Shipping Method for SOIC blank = Tubes TR = Tape & Reel Note: The SOIC package (SOH44) requires the battery crystal package (SNAPHAT ) which is ordered separately under part number "M4TXXBR12SHX" in plastic tube or "M4TXX-B R12SHXTR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery/crystal package "M4Txx-BR12SHx" in conductive foam since this will drain the lithium button-cell battery. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 19. SNAPHAT Battery Table Part Number Description Package M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH 27/29 M48ST59W REVISION HISTORY Table 20. Document Revision History Date September 2000 28/29 Revision Details First cut 10/10/00 First markups entered, text added, graphics changed 12/18/00 Reformatted, TOC added, and PFI ILI added (Table 12) M48ST59W Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . www.st.com 29/29