SM8513 NIPPON PRECISION CIRCUITS INC. Synchronous/Asynchronous Converter LSI mw OVERVIEW The SM8513 is an asynchronus/synchronous (ASYNC/SYNC) converter LSI fabricated using NPC's original molybdenum-gate CMOS technology and complies with ITU-T Recommendation v.14. At various modem data communication speeds ranging from 600 bps to 19.2 Kbps, etc., the LSI converts a synchronous signal to asynchronous signal, and vice versa. The SM8513 allows mutual conversion between synchronous and asynchronous signals according to the 8, 9, 10 and 11-bit asyn- chronous signal character format. It also supports the basic signal speed range complying with ITU-T Recommendation V.14, optional extended signal speed range and halt signal automatic extension. m FEATURES O Compliance with ITU-T Recommendation V.14 + Conversion from SYNC signal to ASYNC signal, and vice versa + Compatible with communication speeds ranging from 600 bps to 19.2 Kbps - Bypass mode for signals at speeds below 300 bps (SYNC/ASYNC signal conversion is not performed in the bypass mode.) * &-bit to 11-bit ASYNC signal character format + Supports both basic signal speed range and extended signal speed range. + Supports automatic extension of halt signal. O A crystal or an external clock may be used as the system clock. O Single +5 V power supply O Available in two package types: * 16-pin plastic DIP (SM8513P) * 16-pin plastic SOP (SM8513S) m APPLICATION Conversion of SYNC signal to ASYNC signal, and vice versa, between the modem and the terminal (compatible with 600, 1200, 2400, 4800, 7200, 9600, 14400, 19200 bps) Protocol converters Personal computers Synchronous terminals m PINOUT TOP VIEW - 16-pin DIP - 16-pin SOP BYPASS|| 1 6 [| VDD BYPASS|| 1 "6 [] vp EXTMD || 2 |] TXDOUT EXTMD | o !] TXDOUT cro 25 I] TXCIN cro] 2s ] TXCIN cri | > A I] RXDIN crf Va I] RXDIN xm oO | RXCIN xv [] ENS |] RXCIN xout[| 7% ES 1] TXDIN xovt[] ll rxDIN sl Cl lrxpour ts |] RKDOUT cnp|| 8 9 || WR cn] 8 9 | WR NIPPON PRECISION CIRCUITS 369m BLOCK DIAGRAM SM8513 TXDIN ASYNC TO SYNC XIN XOUT BYPASS EXTMD CFO CF1 TXDOUT TXCIN WR SYNC TO ASYNC RXDOUT RXDIN m PIN DESCRIPTION No. Name Description 1 BYPASS | Bypass mode specification (interface register). Bring this pin High when the speed is 300 bps or less (may be more than 300 bps). Lo: Normal mode Hi: Bypass mode (no SYNC/ASYNC conversion) 2 EXTMD | Specifies the allowable speed fluctuation range (interface register). Set the allowable range of speed fluctuations at the time of ASYNC signal reception. Lo: Basic signal speed range (+ 1.0% to -2.5%) Hi: Extended signal speed range (+2.3% to -2.5%) 3/4 CFO/CF1 | Character format selection (interface . : . register). Set the haracter format CEIV/CFO format (M) Start bit} Data bit| Stop Dit (M) of the ASYNC signal. Lo|{ Lo 8 1 6 1 *; Actual processing: | stop bit + 8 Lo Hi 9 ! 7 ! data bits + 2 stop bits Hi | Lo 10 ! 8 1 Hi Hi MW 1 9 1 * 5 XIN Oscillation input. Connect a 11.0592 MHz crystal between XIN and XOUT or connect an external clock to XIN. 6 XOUT__| Oscillation output 7 cs Chip select input <CPU in use> Bring CS Low to write data in interface registers at pins 1 to 4, Connect decoded addresses from the CPU in normal operation. <CPU not in use> Connect this pin to the ground. 8 GND Ground 9 WR Write enable <CPU in use> Data of pins | to 4 (interface registers) is input when the CS pin is active and the WR pin goes Low. The data is latched when WR goes from Low to High. <CPU not in use> Connect this pin to the ground. The states of pin 1 to 4 become valid at the moment a change is made. 10 RXDOUT | ASYNC signal output ll TXDIN _| ASYNC signal input 12 RXCIN | SYNC signal reception clock input 13 RXDIN__| SYNC signal input 14 TXCIN | SYNC signal transmission clock input 15 TXDOUT | SYNC signal output 16 VDD +5 V supply voltage 370 NIPPON PRECISION CIRCUITS$M8513 m ABSOLUTE MAXIMUM RATINGS (Vss = OV) Item Symbol Rating Unit Supply voltage Voo -0.3 to 7.0 Vv Input voltage Vin . ~0.3 to Vpp +0.3 Vv Power dissipation Pw 250 mW Operating temperature Ta 0 to +70 C Storage temperature Tstc -65 to +150 C Soldering temperature | Tsip 255 C Soldering time tsLD 10 Sec m = RECOMMENDED OPERATING CONDITIONS Item Symbol Rating Unit Supply voltage Vopp 4.5 to 5.5 Vv Operating temperature Ta 0 to +70 C Crystal frequency fxr 11.059240.01 % MHz m DC CHARACTERISTICS (Vpp = 5 V 10%, Ta = 0 to +70 C, fxr = 1 1.0592 MHz, Cx = 10 pF unless otherwise noted.) ITEM SYMBOL] MIN | TYP | MAX | UNIT CONDITION Ey Lo Vit 0.8 v All input pins other than XIN 3 Vix 0.3Vss Vv XIN only = Hi Vin 2.0 Vv All input pins other than XIN Vinx = | 0.7Vpp Vv XIN only Lo Vou 0.1 Vv All output pins other than XOUT Tor=20pA, Vin=Vui/ VL @ 0.4 Vv All output pins other than XOUT s Tor=40mA, Vin=Va Vai 2 Hi Vou = [Vopp-0.1 Vv | All output pins other than XOUT 6 Ton=20pA, Vin= Viv VHL 3.7 Vv All output pins other than XOUT loc=40mA, Vin= Vai VHL Output impedance Ro 500 Q XOUT pin only Input current In 10 HA Vin=OV or Vop All input pins other than XIN 6 pA | Vin=OV or Vp XIN pin only & | In operation Ino 2 5 mA | All output pins OPEN 5 = | All input pins LOW Bz Not in operation Ing 1 pA | All output pins 0 V S XIN=Vpp NIPPON PRECISION CIRCUITS 371SM8513 m AC CHARACTERISTICS (Von = 5 V +10%, Ta = 0 to +70 C, fat = 11.0592 MHz, Cx = 10 pF, TXCIN-RXCIN=1200bps, Ci=15pF*1 ITEM SYMBOL| MIN TYP MAX _| UNIT CONDITION Signal speed range fs: 600 7200 bps | #3 1200 9600 2400 14400 4800 19200 Allowable speed drssy | -0.01 0.01 % |SYNC signal side fluctuation range drsay -2.5 1.0 ASYNC signal side/EXTMD=0 -2.5 2.3 ASYNC signal side/EXTMD=1 Stop bit tstop =| 0.875ST EXTMD=0, T=1/fS 0.750T EXTMD=1, T=1/fS Data setup time ts 0 ns __| See Figure 1 CPU interface. Data hold time tH 20 ns__ | See Figure 1 CPU interface. WR pulse width tww 100 ns __ | See Figure 1 CPU interface. CS pulse width twe 140 ns__| See Figure 1 CPU interface. CS access time ta 20 ns _| See Figure 1 CPU interface. CS release time tr 20 ns__ | See Figure 1 CPU interface. TXDOUT delay time torx 1 jis _| See Figure 1 Normal mode. RXDIN setup time tsrx 1 ys _| See Figure 1 Normal mode. RXDIN hold time tHRx 1 ps | See Figure 1 Normal mode."* TXDOUT| Delay time tox 1 ys | Each data input. See Figure 1 Bypass mode.* RXDOUT] Delay time M bit |TXDIN to TXDOUT See Figure 7. length 2M"2 bit |RXDIN to RXDOUT See Figure 8. *1: CL is the load capacity of TXDOUT/RXDOUT. *2: M is the character format. *3: BYPASS =0 *4: BYPASS = 1 @ CPU interface BYPASS EXTMD 50% CFO~1 ts tww. tH WR 50% te t A+ t-_tR- twc cs 50% @ Normal mode (BYPASS = 0) TXCN \- 509% 50% tDTXx : i tDTx TXDOUT 50% a tSRX. tHRX RXDIN 7 50 % 372 : NIPPON PRECISION CIRCUITSSM8513 @ Bypass mode (BYPASS = 1) TXDIN':: RXDIN 50% tox tox TXDOUT N RXDOUT 50% Figure 1 Timing waveform NIPPON PRECISION CIRCUITS 373SM8513 mM OSCILLATOR CONNECTION CIRCUIT q t>4 XIN XOUT 5 5 6. 11.0592MHz cx = 11.0592MHz Cx clock Figure 2 qh Figure 3 System clock selection (1) Crystal Connect a crystal between XIN and XOUT as shown in Figure 2. Use 10 pF capacitors (Cx). (2) External clock signal Input an external clock to the XIN pin as shown in Figure 3. mM CHARACTER FORMAT 1. Asynchronous character format Transmission/reception of an ASYNC signal starts from the start bit (1-bit length) and ends at the stop bit (1 to 2-bit length), as shown in Figure 4. Therefore, the synchronizing clock is not necessary for data input or sending. Startbit(1 bit) 6 tg g bits Stop bit (1 to 2 bits) 6 to 9 bits 7 _-_-_---_* TXDIN Figure 4 Asynchronous signal character format 2. Synchronous character format Transmission/reception timing of synchronous data is synchronized by the transmission clock (EIA RS-232C, pin 15) and the reception clock (pin 17) supplied to TXCIN and RXCIN, respectively. Start bit (1 bit) Stop bit (1 to 2 bits) | 6 to 9 bits 6 to 9 bits Pid db PP dda ot td ieee UYU L~ UUW Figure 5 Synchronous signal character format 374 NIPPON PRECISION CIRCUITSMm TYPICAL APPLICATION SM8513 RS- Terminal} 232C l/F 1488 11.0592MHz XIN XOUT 1489 TXDOUT TXDIN TXCIN ASYNC side SM8513 RXDIN -; RXDOUT RXCIN Interface register SYNC side m INTERFACE REGISTER The SM8513 has four CPU interface registers--B YPASS, EXTMD, CFO and CF1--at pins 1,2,3 and 4, respectively. These registers can be controlled by the CPU with the WR pin and the CS pin. (1) CPU control Data at pins 1 to 4 is input when both WR and CS go Low. The data is latched in the registers when WR and CS go High. BA pe Figure 6 SM8513 application circuit example (See Figure 1 CPU interface for details of the timing.) (2) No CPU contro] Connect the WR and CS pins to the ground. Data becomes valid when pins | to 4 are changed. MODEM ke Communication line NIPPON PRECISION CIRCUITS 375SM8513 m ASYNC/SYNC CONVERSION @ Operation range In the ASYNC mode, data transmission/reception timing is not as strict as that of the SYNC mode (0.01%). Therefore, the speed varies in the ASYNC mode, which causes a difference in speed between the ASYNC and SYNC mode. To cope with speed fluctuations in the ASYNC system, the SM8513 is designed to absorb speed differences in the following ranges, as specified in ITU-T Recommendation V.14. (1) Speed fluctuations permissible in ASYNC signal reception Basic signal speed range +1.0 to -2.5% Extended signal speed range +2.3 to -2.5% (2) Speed fluctuations permissible in ASYNC signal transmission Basic signal speed range +1.0% Extended signal speed range +2.3% 376 NIPPON PRECISION CIRCUITSSM8513 @ Conversion from ASYNC signal to SYNC signal 1. Speed fluctuations of ASYNC signal input (1) Under speed (EXTMD = 0: 0 to -2.5%, EXTMD = 1: 0 to -2.5%) When the communication speed of the ASYNC signal input (TXDIN) is slower (under speed) than that of the SYNC signal output (TXDOUT), the speed difference is absorbed by adding a stop bit (1 bit or more) to the SYNC signal (TXDOUT) at the time of transmission. (2) Over speed (EXTMD = 0: +1.0 to 0%, EXTMD = 1: +2.3 to 0%) When the communication speed of the ASYNC signal input (TXDIN) is higher (over speed) than-that of the SYNC signal output (TXDOUT), the speed difference is absorbed by deleting a stop bit (maximum 1 bit) from the ASYNC signal as described below. Per 8 continuous characters in the basic signal speed range (EXTMD = 0) Per 4 continuous characters in the extended signal speed range (EXTMD = 1) 2. SYNC signal output delay A signal input to the ASYNC signal input pin (TXDIN) is output synchronized with the synchronizing clock (TXCIN). At this time, the signal transmitted from the SYNC signal output pin (TXDOUT) has a delay of about "M" bits. (See Figure 7.) ASYNC signal input Start bit Stop bit N bits N bits A | A. c ~ Aeis-LIN | bleis|-T S| TXDIN | SYNC signal output Stan bit Stop bit N bits | N bits ier - it LfelelLh | Ae Delay of about "M" bits | TXDOUT | T= Iffs, M: character format (M = N + 2) Figure 7 Conversion from ASYNC signal to SYNC signal NIPPON PRECISION CIRCUITS 377SM8513 @ Conversion from SYNC signal to ASYNC signal 1. Missing stop bit in SYNC signal input When a signal received at the SYNC signal input pin (RXDIN) is found to have its stop bit missing, a stop bit is inserted at the missing position when converted data is output from the ASYNC signal output pin (RXDOUT). The stop bit to be inserted is shorter than the regular stop bit by the following percentages: Basic signal speed range (EXTMD = 0): 12.5% Extended signal speed range (EXTMD = 1): 25.0% At the same time, the stop bit length is made identical to the length of the inserted stop bit for the following numbers of characters. The start bit length and the data bit length are not shortened. (See Figure 8.) Basic signal speed range (EXTMD = 0): 7 characters Extended signal speed range (EXTMD = 1): 3 characters 2. ASYNC signal output delay When a signal is input to the SYNC signal input pin (RXDIN), the signal output from the ASYNC signal output pin (RXDOUT) has a delay of about "2M" bits. (See Figure 8.) SYNC signal input Stop bit- Missing stop bit . N bits N bits ife[s)- c won LE Rs aT LeeLee | a Delay of about "2M" bits, ASYNC signal output i i i Stop bit N bits, N bits, Inserted stop bit ; op oe ee N bits N bits RXDOUT Liesl Lbebl-T es Pee 4 0.875T or 0.750T T = 1/fs, M: character format (M = N + 2) Figure 8 Conversion from SYNC signal to ASYNC signal 378 NIPPON PRECISION CIRCUITSSM8513 mM HALT SIGNAL @ Conversion from ASYNC signal to SYNC signal 1. When detecting a continuos start polarity of "M to 2M + 3" bits at the ASYNC signal input (TXDIN), the LSI outputs a start polarity of "2M + 3" bits from the SYNC signal output (TXDOUT). ASYNC signal input } Start polarity of TXDIN "M - 2M + 3" bits Delay of about "M bits | SYNC signal output TXDOUT Stan polarity of "2M + 3 bits T T = I/fs, M: character format (M = N + 2) Figure 9 Halt signal sending during ASYNC-to-SYNC signal conversion (1) 2. When the detected start polarity is input continuously for '2M + 3" bits or more, the LSI outputs the start polarity according to its duration. ASYNC signal input TXDIN Start polarity of "2M + 3 bits or longer Delay of about "M bits - 7 SYNC signal output TXDOUT Start polarity is output for the same duration. |} T T = 1/fs, M: character format (M = N + 2) Figure 10 Halt signal sending during ASYNC-to-SYNC signal conversion (2) NIPPON PRECISION CIRCUITS 379SM8513 @ Conversion from SYNC signal to ASYNC signal When detecting a continuos start polarity of ''2M + 3" bits or longer at the SYNC signal input (RXDIN), the LSI outputs a start polarity of the same duration from the ASYNC signal output (RXDOUT). o SYNC signal input Start polarity of "2M + 3" bits or longer __. |_ Delay of about "2M" bits T ASYNC signal input RXDOUT Lee Stan polarity of the same duration T = I/fs, M: character format (M = N + 2) Figure 11 Halt signal sending during SYNC-to-ASYNC signal conversion 380 NIPPON PRECISION CIRCUITSSM8513 mM PACKAGE DIMENSIONS * SM8513P (16-pin plastic DIP) 38 +o 19.4 + 0.3 oD | C41 mm ata ola S OC Hy} 41 + wo} eo 2 ole oO TOUTE Eee re ao + +i x iT H re 254| | o5+1 8 H oY 1) - SM8513S (16-pin SOP) 10.2 +03 0.15 +93 B8AABEA BH BEES = Enlarged view of the lead NIPPON PRECISION CIRCUITS 381