1
LT1956/LT1956-5
1956f
High Voltage, 1.5A,
500kHz Step-Down
Switching Regulators
■
Wide Input Range: 5.5V to 60V
■
1.5A Peak Switch Current
■
Small 16-Pin SSOP or Thermally Enhanced
TSSOP Package
■
Saturating Switch Design: 0.2Ω
■
Peak Switch Current Maintained Over
Full Duty Cycle Range
■
Constant 500kHz Switching Frequency
■
Effective Supply Current: 2.5mA
■
Shutdown Current: 25µA
■
1.2V Feedback Reference (LT1956)
■
5V Fixed Output (LT1956-5)
■
Easily Synchronizable
■
Cycle-by-Cycle Current Limiting
The LT
®
1956/LT1956-5 are 500kHz monolithic buck
switching regulators with an input voltage capability up to
60V. A high efficiency 1.5A, 0.2Ω switch is included on the
die along with all the necessary oscillator, control and logic
circuitry. A current mode architecture provides fast tran-
sient response and good loop stability.
Special design techniques and a new high voltage process
achieve high efficiency over a wide input range. Efficiency
is maintained over a wide output current range by using the
output to bias the circuitry and by utilizing a supply boost
capacitor to saturate the power switch. Patented circuitry
maintains peak switch current over the full duty cycle
range*. A shutdown pin reduces supply current to 25µA and
the device can be externally synchronized from 580kHz to
700kHz with a logic level input.
The LT1956
/LT1956-5
are available in fused-lead 16-pin
SSOP and thermally enhanced TSSOP packages.
■
High Voltage, Industrial and Automotive
■
Portable Computers
■
Battery-Powered Systems
■
Battery Chargers
■
Distributed Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
5V Buck Converter Efficiency vs Load Current
BOOST
V
IN
6
2
10
12
10MQ060N
V
OUT
5V
1A
4
15
14
11
220pF
4700pF
†
UNITED CHEMI-CON THCS50EZA225ZT
1, 8, 9, 16
LT1956-5
SHDN
SYNC
SW
BIAS
FB
V
C
GND
0.1µF
22µF
6.3V
CERAMIC
10µH
MMSD914TI
1956 TA01
2.2µF
†
100V
CERAMIC
V
IN
12V
(TRANSIENTS
TO 60V)
4.7k
LOAD CURRENT (A)
0
EFFICIENCY (%)
80
90
100
1.00
1956 TA02
70
60
50 0.25 0.50 0.75 1.25
V
OUT
= 5V
V
OUT
= 3.3V
V
IN
= 12V
L = 18µH
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
*U.S. PATENT NO. 6,498,466
2
LT1956/LT1956-5
1956f
Input Voltage (V
IN
) ................................................. 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, SENSE Voltage (LT1956-5) ........................... 7V
SHDN Voltage ........................................................... 6V
BIAS Pin Voltage .................................................... 30V
FB Pin Voltage/Current (LT1956)................... 3.5V/2mA
ORDER PART
NUMBER
LT1956EGN
LT1956IGN
LT1956EGN-5
LT1956IGN-5
GN PART MARKING
1956
1956I
19565
1956I5
T
JMAX
= 125°C, θ
JA
= 85°C/W, θ
JC
(PIN 8) = 25°C/W
FOUR CORNER PINS SOLDERED
TO GROUND PLANE
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
SW
NC
VIN
NC
BOOST
NC
GND
GND
SHDN
SYNC
NC
FB/SENSE
VC
BIAS
GND
Operating Junction Temperature Range
LT1956EFE/LT1956EFE-5/LT1956EGN/LT1956EGN-5
(Notes 8, 10) ..................................... –40°C to 125°C
LT1956IFE/LT1956IFE-5/LT1956IGN/LT1956IGN-5
(Notes 8, 10) ..................................... –40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
(Note 1)
ORDER PART
NUMBER
LT1956EFE
LT1956IFE
LT1956EFE-5
LT1956IFE-5
FE PART MARKING
T
JMAX
= 125°C, θ
JA
= 45°C/W, θ
JC
(PAD) = 10°C/W
EXPOSED BACKSIDE MUST BE SOLDERED
TO GROUND PLANE
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
SW
NC
V
IN
NC
BOOST
NC
GND
GND
SHDN
SYNC
NC
FB/SENSE
V
C
BIAS
GND
Consult LTC Marketing for parts specified with wider operating temperature ranges.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Voltage (LT1956) 5.5V ≤ V
IN
≤ 60V 1.204 1.219 1.234 V
V
OL
+ 0.2 ≤ V
C
≤ V
OH
– 0.2 ●1.195 1.243 V
SENSE Voltage (LT1956-5) 5.5V ≤ V
IN
≤ 60V 4.94 5 5.06 V
V
OL
+ 0.2 ≤ V
C
≤ V
OH
– 0.2 ●4.90 5.10 V
SENSE Pin Resistance (LT1956-5) 9.5 13.8 19 kΩ
FB Input Bias Current (LT1956) ●0.5 1.5 µA
Error Amp Voltage Gain (Notes 2, 9) 200 400 V/V
Error Amp g
m
dl (V
C
) = ±10µA (Note 9) 1500 2000 3000 µMho
●1000 3200 µMho
V
C
to Switch g
m
1.7 A/V
EA Source Current FB = 1V or V
SENSE
= 4.1V ●125 225 400 µA
EA Sink Current FB = 1.4V or V
SENSE
= 5.7V ●100 225 450 µA
V
C
Switching Threshold Duty Cycle = 0 0.9 V
V
C
High Clamp SHDN = 1V 2.1 V
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
1956EFE
1956IFE
1956EFE-5
1956IFE-5
3
LT1956/LT1956-5
1956f
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switch Current Limit V
C
Open, Boost = V
IN
+ 5V, FB = 1V or V
SENSE
= 4.1V ●1.5 2 3 A
Switch On Resistance I
SW
= 1.5A, Boost = V
IN
+ 5V (Note 7) 0.2 0.3 Ω
●0.4 Ω
Maximum Switch Duty Cycle FB = 1V or V
SENSE
= 4.1V 82 90 %
●75 90 %
Switch Frequency V
C
Set to Give DC = 50% 460 500 540 kHz
●430 570 kHz
f
SW
Line Regulation 5.5V ≤ V
IN
≤ 60V ●0.05 0.15 %/V
f
SW
Shifting Threshold Df = 10kHz 0.8 V
Minimum Input Voltage (Note 3) ●4.6 5.5 V
Minimum Boost Voltage (Note 4) I
SW
≤ 1.5A ●23 V
Boost Current (Note 5) Boost = V
IN
+ 5V, I
SW
= 0.5A ●12 25 mA
Boost = V
IN
+ 5V, I
SW
= 1.5A ●42 70 mA
Input Supply Current (I
VIN
) (Note 6) V
BIAS
= 5V 1.4 2.2 mA
Output Supply Current (I
BIAS
) (Note 6) V
BIAS
= 5V 2.9 4.2 mA
Shutdown Supply Current SHDN = 0V, V
IN
≤ 60V, SW = 0V, V
C
Open 25 75 µA
●200 µA
Lockout Threshold V
C
Open ●2.30 2.42 2.53 V
Shutdown Thresholds V
C
Open, Shutting Down ●0.15 0.37 0.6 V
V
C
Open, Starting Up ●0.25 0.45 0.6 V
Minimum SYNC Amplitude ●1.5 2.2 V
SYNC Frequency Range 580 700 kHz
SYNC Input Resistance 20 kΩ
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Gain is measured with a V
C
swing equal to 200mV above the low
clamp level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defined as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator remain constant.
Actual minimum input voltage to maintain a regulated output will depend
upon output voltage and load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 5: Boost current is the current flowing into the BOOST pin with the
pin held 5V above input voltage. It flows only during switch on time.
Note 6: Input supply current is the quiescent current drawn by the input
pin when the BIAS pin is held at 5V with switching disabled. Bias supply
current is the current drawn by the BIAS pin when the BIAS pin is held at
5V. Total input referred supply current is calculated by summing input
supply current (I
VIN
) with a fraction of supply current (I
BIAS
):
I
TOTAL
= I
VIN
+ (I
BIAS
)(V
OUT
/V
IN
)
with V
IN
= 15V, V
OUT
= 5V, I
VIN
= 1.4mA, I
BIAS
= 2.9mA, I
TOTAL
= 2.4mA.
Note 7: Switch on resistance is calculated by dividing V
IN
to SW voltage by
the forced current (1.5A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 8: The LT1956EFE/LT1956EFE-5/LT1956EGN/LT1956EGN-5 are
guaranteed to meet performance specifications from 0°C to 125°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LT1956IFE/LT1956IFE-5/
LT1956IGN/LT1956IGN-5 are guaranteed over the full –40°C to 125°C
operating junction temperature range.
Note 9: Transconductance and voltage gain refer to the internal amplifier
exclusive of the voltage divider. To calculate gain and transconductance,
refer to the SENSE pin on fixed voltage parts. Divide values shown by the
ratio V
OUT
/1.219.
Note 10: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
4
LT1956/LT1956-5
1956f
Switch Peak Current Limit SHDN Pin Bias Current
Shutdown Supply Current
Lockout and Shutdown
Thresholds Shutdown Supply Current
Error Amplifier Transconductance
FB Pin Voltage and Current
Error Amplifier Transconductance Frequency Foldback
TYPICAL PERFOR A CE CHARACTERISTICS
UW
DUTY CYCLE (%)
1.0
SWITCH PEAK CURRENT (A)
1.5
2.0
2.5
20 40
TYPICAL
60 80
1956 G01
1000
GUARANTEED MINIMUM
JUNCTION TEMPERATURE (°C)
–50
FEEDBACK VOLTAGE (V)
CURRENT (µA)
1.224
1.229
1.234
25 75
1956 G02
1.219
1.214
–25 0 50 100 125
1.209
1.204
1.5
2.0
1.0
0.5
0
VOLTAGE
CURRENT
JUNCTION TEMPERATURE (°C)
–50
250
200
150
100
12
6
025 75
1956 G03
–25 0 50 100 125
CURRENT (µA)
CURRENT REQUIRED TO FORCE SHUTDOWN
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW µA
AT 2.38V STANDBY THRESHOLD
(CURRENT FLOWS OUT OF PIN)
JUNCTION TEMPERATURE (°C)
–50
SHDN PIN VOLTAGE (V)
50 100
1956 G04
025 75
2.4
2.0
1.6
1.2
0.8
0.4
0–25 125
LOCKOUT
START-UP
SHUTDOWN
INPUT VOLTAGE (V)
0
INPUT SUPPLY CURRENT (µA)
1956 G05
10 20 30 40 50 60
40
35
30
25
20
15
10
5
0
V
SHDN
= 0V
SHUTDOWN VOLTAGE (V)
0
0
INPUT SUPPLY CURRENT (µA)
50
100
150
200
250
300
0.1 0.2 0.3 0.4
1956 G06
0.5
V
IN
= 60V
V
IN
= 15V
JUNCTION TEMPERATURE
TRANSCONDUCTANCE (µmho)
1956 G07
2500
2000
1500
1000
500
0
–50 50 100
025 75–25 125
FREQUENCY (Hz)
GAIN (µMho)
PHASE (DEG)
3000
2500
2000
1500
1000
500
200
150
100
50
0
–50
100 10k 100k 10M
1956 G08
1k 1M
GAIN
PHASE
ERROR AMPLIFIER EQUIVALENT CIRCUIT
R
OUT
200k
C
OUT
12pF
V
C
R
LOAD
= 50Ω
V
FB
2 • 10–3
)(
V
FB
(V)
0 0.2
SWITICHING FREQUENCY (kHz)
OR FB CURRENT (µA)
375
500
625
1.0
1956 G09
250
125
00.4 0.6 0.8 1.2
SWITCHING
FREQUENCY
FB PIN
CURRENT
5
LT1956/LT1956-5
1956f
Switching Frequency BOOST Pin Current
VC Pin Shutdown Threshold
Minimum Input Voltage with 5V
Output
Switch Voltage Drop
TYPICAL PERFOR A CE CHARACTERISTICS
UW
JUNCTION TEMPERATURE (°C)
–50
FREQUENCY (kHz)
50 100
1956 G10
025 75
575
550
525
500
475
450
425 –25 125
LOAD CURRENT (A)
0
INPUT VOLTAGE (V)
1956 G11
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
7.5
7.0
6.5
6.0
5.5
5.0
MINIMUM INPUT
VOLTAGE TO START
MINIMUM INPUT
VOLTAGE TO RUN
V
OUT
= 5V
L = 18µH
SWITCH CURRENT (A)
0 0.5 1 1.5
BOOST PIN CURRENT (mA)
1956 G12
45
40
35
30
25
20
15
10
5
0
JUNCTION TEMPERATURE (°C)
–50
1.5
1.7
2.1
25 75
1956 G13
1.3
1.1
–25 0 50 100 125
0.9
0.7
1.9
THRESHOLD VOLTAGE (V)
SWITCH CURRENT (A)
0 0.5 1 1.5
SWITCH VOLTAGE (mV)
1766 G14
450
400
350
300
250
200
150
100
50
0
T
J
= 125°C
T
J
= 25°C
T
J
= –40°C
JUNCTION TEMPERATURE (°C)
–50
SWITCH MINIMUM ON TIME (ns)
50 100
1956 G15
025 75
600
500
400
300
200
100
0–25 125
Switch Minimum ON Time
vs Temperature
6
LT1956/LT1956-5
1956f
V
C
(Pin 11) The V
C
pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. V
C
sits
at about 1V for light loads and 2V at maximum load. It can
be driven to ground to shut off the regulator, but if driven
high, current must be limited to 4mA.
FB/SENSE (Pin 12): The feedback pin is used to set the
output voltage using an external voltage divider that gen-
erates 1.22V at the pin for the desired output voltage. The
5V fixed output voltage parts have the divider included on
the chip and the FB pin is used as a SENSE pin, connected
directly to the 5V output. Three additional functions are
performed by the FB pin. When the pin voltage drops
below 0.6V, switch current limit is reduced and the exter-
nal SYNC function is disabled. Below 0.8V, switching
frequency is also reduced. See Feedback Pin Functions in
Applications Information for details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
10% and 90% duty cycle. The synchronizing range is
equal to initial operating frequency up to 700kHz. See
Synchronizing in Applications Information for details. If
unused, this pin should be tied to ground.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to a few microam-
peres. This pin has two thresholds: one at 2.38V to disable
switching and a second at 0.4V to force complete mi-
cropower shutdown. The 2.38V threshold functions as an
accurate undervoltage lockout (UVLO); sometimes used
to prevent the regulator from delivering power until the
input voltage has reached a predetermined level.
If the SHDN pin functions are not required, the pin can
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.
GND (Pins 1, 8, 9, 16): The GND pin connections act as
the reference for the regulated output, so load regulation
will suffer if the “ground” end of the load is not at the same
voltage as the GND pins of the IC. This condition will occur
when load current or other currents flow through metal
paths between the GND pins and the load ground. Keep the
paths between the GND pins and the load ground short
and use a ground plane when possible. For the FE package,
the exposed pad should be soldered to the copper GND
plane underneath the device. (See Applications Informa-
tion—Layout Considerations.)
SW (Pin 2): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
switch pin negative during switch off time. Negative volt-
age is clamped with the external catch diode. Maximum
negative switch voltage allowed is –0.8V.
NC (Pins 3, 5, 7, 13): No Connection.
V
IN
(Pin 4): This is the collector of the on-chip power NPN
switch. V
IN
powers the internal control circuitry when a
voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V
IN
pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V
CE
voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and voltage loss approximates that of a 0.2Ω FET struc-
ture, but with much smaller die area.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output volt-
age forces most of the internal circuitry to draw its oper-
ating current from the output voltage rather than the input
supply. This architecture increases efficiency especially
when the input voltage is much higher than the output.
Minimum output voltage setting for this mode of operation
is 3V.
UU
U
PI FU CTIO S
7
LT1956/LT1956-5
1956f
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
Most of the circuitry of the LT1956 operates from an
internal 2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage higher than 3V, bias
power will be drawn from the external source (typically the
regulated output voltage). This will improve efficiency if
the BIAS pin voltage is lower than regulator input voltage.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capaci-
tor and diode. Two comparators are connected to the
shutdown pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
The LT1956 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla-
tor pulse which sets the R
S
flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
BLOCK DIAGRA
W
Figure 1. LT1956 Block Diagram
–
+
–+
–
+
–
+
Σ
VIN
2.9V BIAS
REGULATOR
500kHz
OSCILLATOR
FREQUENCY
FOLDBACK
SW
FB
GND
1, 8, 9, 16
1956 F01
SLOPE COMP
ANTISLOPE COMP
BIAS INTERNAL
VCC
SYNC
0.4V
5.5µA
CURRENT
COMPARATOR
RLIMIT RSENSE
ERROR
AMPLIFIER
gm = 2000µMho
Q2
FOLDBACK
CURRENT
LIMIT
CLAMP
BOOST
RS
FLIP-FLOP DRIVER
CIRCUITRY
S
R
Q1
POWER
SWITCH
1.22V
4
10
14
SHDN 15
6
2
12
11
VC
LOCKOUT
COMPARATOR
SHUTDOWN
COMPARATOR
2.38V
×1
Q3
VC(MAX)
CLAMP
8
LT1956/LT1956-5
1956f
current through the diode and inductor is equal to the
short-circuit current limit of the switch (typically 2A for
the LT1956, folding back to less than 1A). Minimum
switch on time limitations would prevent the switcher
from attaining a sufficiently low duty cycle if switching
frequency were maintained at 500kHz, so frequency is
reduced by about 5:1 when the feedback pin voltage drops
below 0.8V (see Frequency Foldback graph). This does
not affect operation with normal load conditions; one
simply sees a shift in switching frequency during start-up
as the output voltage rises.
In addition to lower switching frequency, the LT1956 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs this
function by clamping the V
C
pin to a voltage less than its
normal 2.1V upper clamp level. This
foldback current limit
greatly reduces power dissipation in the IC, diode and in-
ductor during short-circuit conditions. External synchro-
nization is also disabled to prevent interference with fold-
back operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
affected are current source loads which maintain full load
current with output voltage less than 50% of final value. In
these rare situations the feedback pin can be clamped above
0.6V with an external diode to defeat foldback current limit.
Caution:
clamping the feedback pin means that frequency
shifting will also be defeated, so a combination of high in-
put voltage and dead shorted output may cause the LT1956
to lose control of current limit.
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 3.5kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 115µA out of the FB pin with 0.44V on the pin (R
DIV
≤ 3.8k).
The net result is that reductions in frequency and
current limit are affected by output voltage divider imped-
ance. Although divider impedance is not critical, caution
should be used if resistors are increased beyond the
suggested values and short-circuit conditions will occur
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1956 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The 5V fixed output voltage part (LT1956-5) has
internal divider resistors and the FB pin is renamed SENSE,
connected directly to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following section if divider resistors are
increased above the suggested values.
RRV
OUT
12122
122
=−
()
.
.
Table 1
OUTPUT R1 % ERROR AT OUTPUT
VOLTAGE R2 (NEAREST 1%) DUE TO DISCRETE 1%
(V) (k
Ω
)(k
Ω
) RESISTOR STEPS
3 4.99 7.32 +0.32
3.3 4.99 8.45 –0.43
5 4.99 15.4 –0.30
6 4.75 18.7 +0.38
8 4.47 24.9 +0.20
10 4.32 30.9 –0.54
12 4.12 36.5 +0.24
15 4.12 46.4 –0.27
More Than Just Voltage Feedback
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC
and in the external diode and inductor during short-circuit
conditions. A shorted output requires the switching regu-
lator to operate at very low duty cycles, and the average
APPLICATIO S I FOR ATIO
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9
LT1956/LT1956-5
1956f
Figure 2. Frequency and Current Limit Foldback
with high input voltage.
High frequency pickup will in-
crease and the protection accorded by frequency and
current foldback will decrease.
CHOOSING THE INDUCTOR
For most applications, the output inductor will fall into the
range of 5µH to 30µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT1956 switch, which has a 1.5A limit. Higher values
also reduce output ripple voltage.
When choosing an inductor you will need to consider
output ripple voltage, maximum load current, peak induc-
tor current and fault current in the inductor. In addition,
other factors such as core and copper losses, allowable
component height, EMI, saturation and cost should also
be considered. The following procedure is suggested as a
way of handling these somewhat complicated and con-
flicting requirements.
Output Ripple Voltage
Figure 3 shows a comparison of output ripple voltage for
the LT1956 using either a tantalum or ceramic output
capacitor. It can be seen from Figure 3 that output ripple
voltage can be significantly reduced by using the ceramic
output capacitor; the significant decrease in output ripple
voltage is due to the very low ESR of ceramic capacitors.
–
+
1.2V
BUFFER
V
SW
L1
V
C
GND
TO SYNC CIRCUIT
1956 F02
TO FREQUENCY
SHIFTING
R3
1k
R4
2k
R1
C1
R2
OUTPUT
5V
ERROR
AMPLIFIER
FB
1.4V Q1
LT1956
Q2
+
APPLICATIO S I FOR ATIO
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Output ripple voltage is determined by ripple current
(I
LP-P
) through the inductor and the high frequency
impedance of the output capacitor. At high frequencies,
the impedance of the tantalum capacitor is dominated by
its effective series resistance (ESR).
Tantalum Output Capacitor
The typical method for reducing output ripple voltage
when using a tantalum output capacitor is to increase the
inductor value (to reduce the ripple current in the induc-
tor). The following equations will help in choosing the
required inductor value to achieve a desirable output ripple
voltage level. If output ripple voltage is of less importance,
the subsequent suggestions in Peak Inductor and Fault
Current and EMI will additionally help in the
selection of
the inductor value.
Figure 3. LT1956 Output Ripple Voltage Waveforms.
Ceramic vs Tantalum Output Capacitors
1µs/DIV
10mV/DIV
V
OUT
USING
22µF CERAMIC
OUTPUT
CAPACITOR
V
OUT
USING
100µF, 0.08Ω
TANTALUM
OUTPUT
CAPACITOR
10mV/DIV
V
IN
= 12V
V
OUT
= 5V
L = 15µH
1956 F03
10
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1956f
APPLICATIO S I FOR ATIO
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Peak-to-peak output ripple voltage is the sum of a triwave
(created by peak-to-peak ripple current (I
LP-P
) times ESR)
and a square wave (created by parasitic inductance (ESL)
and ripple current slew rate). Capacitive reactance is
assumed to be small compared to ESR or ESL.
V I ESR ESL dI
dt
RIPPLE LP P
=
()()
+
()
-
Σ
where:
ESR = equivalent series resistance of the output
capacitor
ESL = equivalent series inductance of the output
capacitor
dI/dt = slew rate of inductor ripple current = V
IN
/L
Peak-to-peak ripple current (I
LP-P
) through the inductor
and into the output capacitor is typically chosen to be
between 20% and 40% of the maximum load current. It is
approximated by:
IVVV
VfL
LP P OUT IN OUT
IN
-
=
()( )
()()()
–
Example: with V
IN
= 12V, V
OUT
= 5V, L = 15µH, ESR =
0.080Ω and ESL = 10nH, output ripple voltage can be
approximated as follows:
IA
dI
dt
V
mV
RIPPLE
LP-P
P-P
=
()
−
()
()
()( )
=
==
=
()()
+
()()
()
=+=
−
−
512 5
12 15 10 500 10 0 389
12
15 10 10 0 8
0 389 0 08 10 10 10 0 8
0 031 0 008 39
66
66
96
••
.
••.
.. • .
..
––
Σ
To reduce output ripple voltage further requires an in-
crease in the inductor value with the trade-off being a
physically larger inductor with the possibility of increased
component height and cost.
Ceramic Output Capacitor
An alternative way to further reduce output ripple voltage
is to reduce the ESR of the output capacitor by using a
ceramic capacitor. Although this reduction of ESR re-
moves a useful zero in the overall loop response, this zero
can be replaced by inserting a resistor (R
C
) in series with
the V
C
pin and the compensation capacitor C
C
. (See
Ceramic Capacitors in Applications Information.)
Peak Inductor Current and Fault Current
To ensure that the inductor will not saturate, the peak in-
ductor current should be calculated knowing the maximum
load current. An appropriate inductor should then be cho-
sen. In addition, a decision should be made whether or not
the inductor must withstand continuous fault conditions.
If maximum load current is 0.5A, for instance, a 0.5A
inductor may not survive a continuous 2A overload condi-
tion. Dead shorts will actually be more gentle on the
inductor because the LT1956 has frequency and current
limit foldback.
Peak inductor and switch current can be significantly
higher than output current, especially with smaller induc-
tors and lighter loads, so don’t omit this step. Powdered
Table 2
VENDOR/ VALUE I
DC(MAX)
DCR HEIGHT
PART NO. (
µ
H) (Amps) (Ohms) (mm)
Coiltronics
UP1B-100 10 1.9 0.111 5.0
UP1B-220 22 1.2 0.254 5.0
UP2B-220 22 2.0 0.062 6.0
UP2B-330 33 1.7 0.092 6.0
UP1B-150 15 1.5 0.175 5.0
Coilcraft
D01813P-153HC 15 1.5 0.170 5.0
D01813P-103HC 10 1.9 0.111 5.0
D53316P-223 22 1.6 0.207 5.1
D53316P-333 33 1.4 0.334 5.1
LP025060B-682 6.8 1.3 0.165 1.65
Sumida
CDRH4D28-4R7 4.7 1.32 0.072 3.0
CDRH5D28-100 10 1.30 0.065 3.0
CDRH6D28-150 15 1.40 0.084 3.0
CDRH6D28-180 18 1.32 0.095 3.0
CDRH6D28-220 22 1.20 0.128 3.0
CDRH6D38-220 22 1.30 0.096 4.0
11
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APPLICATIO S I FOR ATIO
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iron cores are forgiving because they saturate softly,
whereas ferrite cores saturate abruptly. Other core mate-
rials fall somewhere in between. The following formula
assumes continuous mode of operation, but errs only
slightly on the high side for discontinuous mode, so it can
be used for all conditions.
II
IIVVV
VfL
PEAK OUT LP P OUT OUT IN OUT
IN
=+ =+
()
-
22
–
•••
EMI
Decide if the design can tolerate an “open” core geometry
like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid to
prevent EMI problems. This is a tough decision because
the rods or barrels are temptingly cheap and small and
there are no helpful guidelines to calculate when the
magnetic field radiation will be a problem.
Additional Considerations
After making an initial choice, consider additional factors
such as core losses and second sourcing, etc. Use the
experts in Linear Technology’s Applications department if
you feel uncertain about the final choice. They have
experience with a wide range of inductor types and can tell
you about the latest developments in low profile, surface
mounting, etc.
MAXIMUM OUTPUT LOAD CURRENT
Maximum load current for a buck converter is limited by
the maximum switch current rating (I
P
). The current rating
for the LT1956 is 1.5A. Unlike most current mode convert-
ers, the LT1956 maximum switch current limit does not
fall off at high duty cycles. Most current mode converters
suffer a drop off of peak switch current for duty cycles
above 50%. This is due to the effects of slope compensa-
tion required to prevent subharmonic oscillations in cur-
rent mode converters. (For detailed analysis, see Applica-
tion Note 19.)
The LT1956 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry to
cancel the effects of slope compensation on peak switch
current without affecting the frequency compensation it
provides.
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one half of peak-to-peak inductor current (I
LP-P
). The
following formula assumes continuous mode operation,
implying that the term on the right is less than one half
of␣ I
P
.
I Continuous Mode
IIIVVVVV
VfL
OUT MAX
PLP P POUT F IN OUT F
IN
()
–– ––
== +
()( )
()( )()()
-
22
For V
OUT
= 5V, V
IN(MAX)
= 8V, V
F(DI)
= 0.63V, f = 500kHz
and L = 10µH:
I
A
OUT MAX() –
.– .––.
••
.–. .
=+
()( )
()()
()()
==
15 5 0 63 8 5 0 63
2 8 500 10 10 10
15 017 133
36
Note that there is less load current available at the higher
input voltage because inductor ripple current increases. At
V
IN
= 15V and using the same set of conditions:
I
A
OUT MAX() –
.– .––.
••
.–. .
=+
()( )
()( )
()()
==
15 5 0 63 15 5 0 63
2 15 500 10 10 10
15 035 115
36
To calculate peak switch current with a given set of
conditions, use:
II
I
IVVVVV
VfL
SW PEAK OUT LP P
OUT OUT F IN OUT F
IN
()
––
=+
=+ +
()( )
()( )()()
-
2
2
Reduced Inductor Value and Discontinuous Mode
If the smallest inductor value is of the most importance to
a converter design, in order to reduce inductor size/cost,
discontinuous mode may yield the smallest inductor
12
LT1956/LT1956-5
1956f
APPLICATIO S I FOR ATIO
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load current is required, the inductor value must be
increased. If I
OUT(MAX)
no longer meets the discontinuous
mode criteria, use the I
OUT(MAX)
equation for continuous
mode; the LT1956 is designed to operate well in both
modes of operation, allowing a large range of inductor
values to be used.
SHORT-CIRCUIT CONSIDERATIONS
For a ground short-circuit fault on the regulated output,
the maximum input voltage for the LT1956 is typically
limited to 25V. If a greater input voltage is required,
increasing the resistance in series with the inductor may
suffice (see short-circuit calculations at the end of this
section). Alternatively, the 1.5A LT1766 can be used since
it is identical to the LT1956 but runs at a lower frequency
of 200kHz, allowing higher sustained input voltage capa-
bility during output short circuit.
The LT1956 is a current mode controller. It uses the V
C
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
peak switch current is reached. The internal clamp on the
V
C
node, nominally 2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit.
A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, V
C
, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
the value indicated by V
C
. However, there is finite response
time involved in both the current comparator and turnoff
of the output switch. These result in a minimum on time
t
ON(MIN)
. When combined with the large ratio of V
IN
to
(V
F
+ I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:
ft VIR
V
ON F
IN
••
≤+
solu
tion. The maximum output load current in discontinu-
ous mode, however, must be calculated and is defined
later in this section.
Discontinuous mode is entered when the output load
current is less than one-half of the inductor ripple current
(I
LP-P
). In this mode, inductor current falls to zero before
the next switch turn-on (see Figure 8). Buck converters
will be in discontinuous mode for output load current
given by:
I Discontinous Mode
VVVVV
VfL
OUT
OUT F IN OUT F
IN
<+()(––)
()( )()()2
The inductor value in a buck converter is usually chosen
large enough to keep inductor ripple current (I
LP-P
) low;
this is done to minimize output ripple voltage and maxi-
mize output load current. In the case of large inductor
values, as seen in the equation above, discontinuous
mode will be associated with “light loads.”
When choosing small inductor values, however, discon-
tinuous mode will occur at much higher output load
currents. The limit to the smallest inductor value that can
be chosen is set by the LT1956 peak switch current (I
P
)
and the maximum output load current required given by:
I
OUT(MAX)
LP-P
DiscontinuousMode
I
I
IfLV
VVVVV
PPIN
OUT F IN OUT F
==+−
22
22()
()()( )
()(– )
Example: For V
IN
= 15V, V
OUT
= 5V, V
F
= 0.63V, f = 500kHz
and L = 4µH
I Discontinuous Mode
OUT MAX()
. ( • )( • )( )
(.)(––.)
=+
−
1 5 500 10 4 10 15
25063155063
236
I
OUT(MAX)
Discontinuous Mode = 0.639A
What has been shown here is that if high inductor ripple
current and discontinuous mode operation can be toler-
ated, small inductor values can be used. If a higher output
13
LT1956/LT1956-5
1956f
APPLICATIO S I FOR ATIO
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where:
f = switching frequency
t
ON
= switch minimum on time
V
F
= diode forward voltage
V
IN
= input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at I
PK
, but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1956 clock frequency
of 500KHz, a V
IN
of 12V and a (V
F
+ I • R) of say 0.7V, the
maximum t
ON
to maintain control would be approximately
116ns, an unacceptably short time.
The solution to this dilemma is to slow down the oscillator
when the FB pin voltage is abnormally low thereby indicat-
ing some sort of short-circuit condition. Oscillator fre-
quency is unaffected until FB voltage drops to about 2/3 of
its normal value. Below this point the oscillator frequency
decreases roughly linearly down to a limit of about 100kHz.
This lower oscillator frequency during short-circuit condi-
tions can then maintain control with the effective mini-
mum on time. Even with frequency foldback, however, the
LT1956 will not survive a permanent output short at the
absolute maximum voltage rating of V
IN
= 60V; this is
defined solely by internal semiconductor junction break-
down effects.
For the maximum input voltage allowed during an output
short to ground, the previous equation defining minimum
on-time can be used. Assuming V
F
(D1 catch diode) =
0.63V at 1A (short-circuit current is folded back to typical
switch current limit • 0.5), I (inductor) • DCR = 1A • 0.128
= 0.128V (L␣ =␣ CDRH6D28-22), typical f = 100kHz (folded
back) and typical minimum on-time = 300ns, the maxi-
mum allowable input voltage during an output short to
ground is typically:
V
IN
= (0.63V + 0.128V)/(100kHz • 300ns)
V
IN(MAX)
= 25V
Increasing the DCR of the inductor will increase the maxi-
mum V
IN
allowed during an output short to ground but will
also drop overall efficiency during normal operation.
Every time the converter wakes up from shutdown or
undervoltage lockout to begin switching, the output
capacitor may potentially be starting from 0V. This re-
quires that the part obey the overall duty cycle demanded
by the loop, related to VIN and VOUT, as the output voltage
rises to its target value. It is recommended that for [VIN/
(VOUT + VF)] ratios > 4, a soft-start circuit should be used
to control the output capacitor charge rate during start-up
or during recovery from an output short circuit, thereby
adding additional control over peak inductor current. See
Buck Converter with Adjustable Soft-Start later in this
data sheet.
OUTPUT CAPACITOR
The LT1956 will operate with either ceramic or tantalum
output capacitors. The output capacitor is normally cho-
sen by its effective series resistance (ESR), because this
is what determines output ripple voltage. The ESR range
for typical LT1956 applications using a tantalum output
capacitor is 0.05Ω to 0.2Ω. A typical output capacitor is an
AVX type TPS, 100µF at 10V, with a guaranteed ESR less
than 0.1Ω. This is a “D” size surface mount solid tantalum
capacitor. TPS capacitors are specially constructed and
tested for low ESR, so they give the lowest ESR for a given
volume. The value in microfarads is not particularly criti-
cal, and values from 22µF to greater than 500µF work well,
but you cannot cheat mother nature on ESR. If you find a
tiny 22µF solid tantalum capacitor, it will have high ESR,
and output ripple voltage will be terrible. Table 3 shows
some typical solid tantalum surface mount capacitors.
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E CASE SIZE ESR (MAX,
Ω
) RIPPLE CURRENT (A)
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
D CASE SIZE
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
C CASE SIZE
AVX TPS 0.2 (typ) 0.5 (typ)
Unlike the input capacitor, RMS ripple current in the
output capacitor is normally low enough that ripple cur-
rent rating is not an issue. The current waveform is
triangular with a typical value of 125mA
RMS
. The formula
to calculate this is:
14
LT1956/LT1956-5
1956f
Output capacitor ripple current (RMS):
IVVV
LfV
RIPPLE RMS OUT IN OUT
IN
() .–
=
()( )
()()( )
029
Ceramic Capacitors
Ceramic capacitors are generally chosen for their good
high frequency operation, small size and very low ESR
(effective series resistance). Their low ESR reduces
output ripple voltage but also removes a useful zero in the
loop frequency response, common to tantalum capaci-
tors. To compensate for this, a resistor R
C
can be placed
in series with the V
C
compensation capacitor C
C
. Care
must be taken however, since this resistor sets the high
frequency gain of the error amplifier, including the gain
at the switching frequency. If the gain of the error
amplifier is high enough at the switching frequency,
output ripple voltage (although smaller for a ceramic
output capacitor) may still affect the proper operation of
the regulator. A filter capacitor C
F
in parallel with the
R
C
/C
C
network is suggested to control possible ripple at
the V
C
pin. The LT1956 can be stabilized for V
OUT
= 5V at
1A using a 22µF ceramic output capacitor and V
C
com-
ponent values of C
C
= 4700pF, R
C
␣ =␣ 4.7k and C
F
= 220pF.
INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT1956 and force the
switching current into a tight local loop, thereby minimiz-
ing EMI. The RMS ripple current can be calculated from:
ICI
VVV
V
RIPPLE RMS IN OUT OUT IN OUT
IN
()
–
=
()
2
Ceramic capacitors are ideal for input bypassing. At 500kHz
switching frequency, the energy storage requirement of
the input capacitor suggests that values in the range of
2.2µF to 10µF are suitable for most applications. If opera-
tion is required close to the minimum input required by the
output of the LT1956, a larger value may be required. This
is to prevent excessive ripple causing dips below the mini-
mum operating voltage resulting in erratic operation.
Depending on how the LT1956 circuit is powered up you
may need to check for input voltage transients.
The input voltage transients may be caused by input
voltage steps or by connecting the LT1956 converter to an
already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
cause the input voltage to swing above the DC level of input
power source and it may exceed the maximum voltage
rating of input capacitor and LT1956.
The easiest way to suppress input voltage transients is to
add a small aluminum electrolytic capacitor in parallel with
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR in order to critically
dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance will
fall in the range of 5µF to 50µF.
If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
taken to ensure the ripple and surge ratings are not
exceeded. The AVX TPS and Kemet T495 series are surge
rated. AVX recommends derating capacitor operating
voltage by 2 for high surge applications.
CATCH DIODE
Highest efficiency operation requires the use of a Schottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a significant reverse recovery time. Schottky
diodes are generally available with reverse voltage ratings
of up to 60V and even 100V, and are price competitive with
other types.
The use of so-called “ultrafast” recovery diodes is gener-
ally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
APPLICATIO S I FOR ATIO
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15
LT1956/LT1956-5
1956f
internal switch will ramp up V
IN
current into the diode in an
attempt to get it to recover. Then, when the diode has
finally turned off, some tens of nanoseconds later, the V
SW
node voltage ramps up at an extremely high dV/dt, per-
haps 5 to even 10V/ns! With real world lead inductances,
the V
SW
node can easily overshoot the V
IN
rail. This can
result in poor RFI behavior and if the overshoot is severe
enough, damage the IC itself.
The suggested catch diode (D1) is an International Recti-
fier 10MQ060N Schottky. It is rated at 1.5A average
forward current and 60V reverse voltage. Typical forward
voltage is 0.63V at 1A. The diode conducts current only
during switch off time. Peak reverse voltage is equal to
regulator input voltage. Average forward current in normal
operation can be calculated from:
I
D(AVG)
= I
OUT
(1 – DC)
This formula will not yield values higher than 1.5A with
maximum load current of 1.5A. The only reason to
consider a larger diode is the worst-case condition of a
high input voltage and shorted output. With a shorted
condition, diode current will increase to a typical value of
2A, determined by peak switch current limit. This is safe
for short periods of time, but it would be prudent to check
with the diode manufacturer if continuous operation
under these conditions must be tolerated.
BOOST␣ PIN␣
For most applications, the boost components are a 0.1µF
capacitor and an MMSD914TI diode. The anode is typi-
cally connected to the regulated output voltage to generate
a voltage approximately V
OUT
above V
IN
to drive the output
stage. However, the output stage discharges the boost
capacitor during the on time of the switch. The output
driver requires at least 3V of headroom throughout this
period to keep the switch fully saturated. If the output
voltage is less than 3V, it is recommended that an alternate
boost supply is used. The boost diode can be connected to
the input, although, care must be taken to prevent the 2×
V
IN
boost voltage from exceeding the BOOST pin absolute
maximum rating. The additional voltage across the switch
driver also increases power loss, reducing efficiency. If
available, an independent supply can be used with a local
bypass capacitor.
A 0.1µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitable, but the ESR should be <1Ω to ensure it can be
fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
1800ns on time, 42mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve
circuit operation or efficiency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1956. Typically, UVLO is used in situations where
the input supply is
current limited
, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
Threshold voltage for lockout is about 2.38V. A 5.5µA bias
current flows
out
of the pin at this threshold. The internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shut-
down current is not an issue, the error due to this current
can be minimized by making R
LO
10k or less. If shutdown
current is an issue, R
LO
can be raised to 100k, but the error
due to initial bias current and changes with temperature
should be considered.
Rk
RRV V
VR A
LO
HI LO IN
LO
=
()
=−
()
−
()
10
238
238 55
to 100k 25k suggested
.
..µ
V
IN
= minimum input voltage
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci-
tance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
APPLICATIO S I FOR ATIO
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16
LT1956/LT1956-5
1956f
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired in
the undervoltage lockout point, a resistor RFB can be
added to the output node. Resistor values can be calcu-
lated from:
RRV VV V
RA
RRV V
HI LO IN OUT
LO
FB HI OUT
=−+
()
+
[]
−
()
=
()
()
238 1
238 55
./
..
/
∆∆
∆
µ
25k suggested for R
LO
V
IN
= Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless
input rises back to 13.5V. ∆V is therefore 1.5V and
V
IN
␣ =␣ 12V. Let R
LO
= 25k.
Rk
kA
kk
Rk k
HI
FB
=−+
()
+
[]
µ
()
=
()
=
=
()
=
25 12 2 38 1 5 5 1 1 5
238 25 55
25 10 41
224 116
116 5 1 5 387
../ .
.– .
.
.
/.
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to
initial
operating frequency up to 700kHz. This means
that
minimum
practical sync frequency is equal to the
worst-case
high
self-oscillating frequency (570kHz), not
the typical operating frequency of 500kHz. Caution should
be used when synchronizing above 662kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
At power-up, when V
C
is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows the
frequency foldback to operate in the shorted output con-
dition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.8V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
APPLICATIO S I FOR ATIO
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–
+
–
+
2.38V
0.4V
GND
VSW
LT1956
INPUT
RFB
L1
RHI
1956 F04
OUTPUT
C1
SHDN
STANDBY
IN
TOTAL
SHUTDOWN
5.5µA
RLO
C2
+
Figure 4. Undervoltage Lockout
17
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LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implemented in the suggested layout of Figure 6. Shorten-
ing this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1956
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate volt-
ages across the LT1956 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1956
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Figure 6. Suggested Layout
GND GND SHDN
SYNC
GND
BOOST
V
IN
SW
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
LT1956
C3
C1
D1 C2
D2
R2
R1
1956 F06
C
FB
C
F
R
C
C
C
L1
MINIMIZE LT1956
C3-D1 LOOP
GND
GND
BIAS
FB
V
C
CONNECT TO
GROUND PLANE
KELVIN SENSE
V
OUT
KEEP FB AND V
C
COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
GND
V
OUT
V
IN
FOR THE FE PACKAGE,
SOLDER THE EXPOSED
PAD TO THE COPPER
GROUND PLANE
UNDERNEATH THE DEVICE
1956 F05
5V
L1
V
IN
LT1956
D1 C1C3
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
Figure 5. High Speed Switching Path
18
LT1956/LT1956-5
1956f
Board layout also has a significant effect on thermal resis-
tance. For the GN package, Pins 1, 8, 9 and 16, GND, are
a continuous copper plate that runs under the LT1956 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pins 1, 8, 9 and 16
onto the board will reduce die temperature and increase
the power capability of the LT1956. This is achieved by
providing as much copper area as possible around these
pins. Adding multiple solder filled feedthroughs under and
around these four corner pins to the ground plane will also
help. Similar treatment to the catch diode and coil termi-
nations will reduce any additional heating effects. For the
FE package, the exposed pad should be soldered to the
copper ground plane underneath the device.
PARASITIC RESONANCE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schot-
tky diodes have very high “Q” junction capacitance that
can ring for many cycles when excited at high frequency.
If total lead length for the input capacitor, diode and switch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
currents this spike can be in the order of 10V to 20V or
higher with a poor layout, potentially exceeding the abso-
lute max switch voltage. The path around switch, catch
diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
APPLICATIO S I FOR ATIO
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a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT1956 has special circuitry inside which
mitigates this problem, but negative voltages over 0.8V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance resonate
with the inductor to form damped ringing at 1MHz to 10
MHz. This ringing is not harmful to the regulator and it has
not been shown to contribute significantly to EMI. Any
attempt to damp it with a resistive snubber will degrade
efficiency.
THERMAL CALCULATIONS
Power dissipation in the LT1956 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
PRI V
VtIVf
SW SW OUT OUT
IN EFF OUT IN
=
()( )
+
()()()
2
12(/ )
Figure 7. Switch Node Resonance
50ns/DIV
1956 F07
2V/DIV
SW RISE SW FALL
SWITCH NODE
VOLTAGE
INDUCTOR
CURRENT AT
I
OUT
= 0.1A
V
IN
= 25V 500ns/DIV 1956 F08
V
OUT
= 5V
L = 15µH
Figure 8. Discontinuous Mode Ringing
10V/DIV
0.2A/DIV
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Boost current loss:
PVI
V
BOOST OUT OUT
IN
=
()
2
36/
Quiescent current loss:
PV V
Q IN OUT
=
()
+
()
0 0015 0 003..
R
SW
= switch resistance (≈0.3) hot
t
EFF
= effective switch current/voltage overlap time
= (t
r
+ t
f
+ t
Ir
+ t
If
)
t
r
= (V
IN
/1.2)ns
t
f
= (V
IN
/1.7)ns
t
Ir
= t
If
= (I
OUT
/0.05)ns
f = switch frequency
Example: with V
IN
= 12V, V
OUT
= 5V and I
OUT
= 1A:
P
W
PW
PW
SW
BOOST
Q
=
()()()
+
()
()
()( )
()
=+=
=
()
()
=
=
()
+
()
=
−
03 1 5
12 57 10 1 2 1 12 500 10
0 125 0 171 0 296
5136
12 0 058
12 0 0015 5 0 003 0 033
293
2
.•/ •
...
/.
...
Total power dissipation in the IC is given by:
P
TOT
= P
SW
+ P
BOOST
+ P
Q
= 0.296W + 0.058W + 0.033W = 0.39W
Thermal resistance for the LT1956 packages is influenced
by the presence of internal or backside planes.
SSOP (GN16) Package: With a full plane under the GN16
package, thermal resistance will be about 85°C/W.
TSSOP (Exposed Pad) Package: With a full plane under the
TSSOP package, thermal resistance (θ
JA
) will be about
45°C/W.
To calculate die temperature, use the proper thermal
resistance (θ
JA
) number for the desired package an add in
worst-case ambient temperature:
T
J
= T
A
+ (θ
JA
• P
TOT
)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power.
PVV V I
V
DIODE F IN OUT LOAD
IN
=( )( – )( )
V
F
= Forward voltage of diode (assume 0.63V at 1A)
PW
DIODE
==
(. )( – )() .
063 12 5 1
12 037
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
low V
F
diode can improve efficiency by several percent.
P
INDUCTOR
= (I
LOAD
)(L
DCR
)
L
DCR
= inductor DC resistance (assume 0.1Ω)
P
INDUCTOR
= (1)(0.1) = 0.1W
Typical thermal resistance of the board is 10°C/W. Taking
the catch diode and inductor power dissipation into ac-
count and using the example calculations for LT1956 dis-
sipation, the LT1956 die temperature will be estimated as:
T
J
= T
A
+ (θ
JA
• P
TOT
) + (10 • [P
DIODE
+ P
INDUCTOR
])
With the GN16 package (θ
JA
= 85°C/W), at an ambient
temperature of 70°C:
T
J
= 70 + (85 • 0.39) + (10 • 0.47) = 108°C
With the TSSOP package (θ
JA
= 45°C/W) at an ambient
temperature of 70°C:
T
J
= 70 + (45 • 0.37) + (10 • 0.47) = 91°C
Die temperature can peak for certain combinations of
V
IN
, V
OUT
and load current. While higher V
IN
gives greater
switch AC losses, quiescent and catch diode losses, a
lower V
IN
may generate greater losses due to switch DC
losses. In general, the maximum and minimum V
IN
levels
should be checked with maximum typical load current for
calculation of the LT1956 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin
current over temperature in a oven. This should be done
with minimal device power (low V
IN
and no switching
[V
C
= 0V]) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
20
LT1956/LT1956-5
1956f
APPLICATIO S I FOR ATIO
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Note: Some of the internal power dissipation in the IC, due
to BOOST pin voltage, can be transferred outside of the IC
to reduce junction temperature by increasing the voltage
drop in the path of the boost diode D2 (see Figure 9). This
reduction of junction temperature inside the IC will allow
higher ambient temperature operation for a given set of
conditions. BOOST pin circuitry dissipates power given by:
PVI V
V
DISS OUT SW C
IN
(BOOST Pin)=
()
•/•36
2
Typically, V
C2
(the boost voltage across the capacitor C2)
equals V
OUT
. This is because diodes D1 and D2 can be
considered almost equal, where:
V
C2
= V
OUT
– V
F
(D2) – [–V
F
(D1)] = V
OUT
.
Hence, the equation for boost circuitry power dissipation
given in the previous Thermal Calculations section, is
stated as:
PVI V
V
DISS BOOST OUT SW OUT
IN
()
•/•
=
()
36
Here it can be seen that boost power dissipation increases
as the square of V
OUT
. It is possible, however, to reduce
V
C2
below V
OUT
to save power dissipation by increasing
the voltage drop in the path of D2. Care should be taken
that V
C2
does not fall below the minimum 3.3V boost
voltage required for full saturation of the internal power
switch. For output voltages of 5V, V
C2
is approximately 5V.
During switch turn on, V
C2
will fall as the boost capacitor
C2 is discharged by the BOOST pin. In the previous BOOST
Pin section, the value of C2 was designed for a 0.7V droop
in V
C2
(= V
DROOP
). Hence, an output voltage as low as 4V
would still allow the minimum 3.3V for the boost function
using the C2 capacitor calculated.
If a target output voltage of 12V is required, however, an
excess of 8V is placed across the boost capacitor which is
not required for the boost function but still dissipates
additional power.
What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2.
A zener, D4, placed in series with D2 (see Figure 9), drops
voltage to C2.
Example:
The BOOST pin power dissipation for a 20V input to 12V
output conversion at 1A is given by:
PW
BOOST
=
()
=
12 1 36 12
20 02
•/ • .
If a 7V zener is placed in series with D2, then power
dissipation becomes:
PW
BOOST
=
()
=
12 1 36 5
20 0 084
•/ • .
For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be:
T (ambient) savings = 0.116W • 45°C/W = 5°C
For a GN package with thermal resistance of 85°C/W,
ambient temperature savings would be:
T (ambient) savings = 0.116W • 85°C/W = 10°C
The 7V zener should be sized for excess of 0.116W
operation. The tolerances of the zener should be consid-
ered to ensure minimum V
BOOST
exceeds 3.3V + V
DROOP
.
BOOST
V
IN
D1
R1
V
OUT
C
F
C
C
LT1956
SHDN
SYNC
SW
BIAS
FB
V
C
GND
C2
C1
L1
D2
R
C
R2
1956 F09
C3
V
IN
D2 D4
+
Figure 9. BOOST Pin, Diode Selection
21
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Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT1956
is specified at 60V. This is based on internal semiconduc-
tor junction breakdown effects. The practical maximum
input supply voltage for the LT1956 may be less than 60V
due to internal power dissipation or switch minimum on
time considerations.
For the extreme case of an output short-circuit fault to
ground, see the section Short-Circuit Considerations.
A detailed theoretical basis for estimating internal power
dissipation is given in the Thermal Calculations section.
This will allow a first pass check of whether an application’s
maximum input voltage requirement is suitable for the
LT1956. Be aware that these calculations are for DC input
voltages and that input voltage transients as high as 60V
are possible if the resulting increase in internal power
dissipation is of insufficient time duration to raise die
temperature significantly. For the FE package, this means
high voltage transients on the order of hundreds of milli-
seconds are possible. If LT1956 (FE package) thermal
calculations show power dissipation is not suitable for the
given application, the LT1766 (FE package) is a recom-
mended alternative since it is identical to the LT1956 but
runs cooler at 200kHz.
Switch minimum on time is the other factor that may limit
the maximum operational input voltage for the LT1956 if
pulse-skipping behavior is not allowed. For the LT1956,
pulse-skipping may occur for V
IN
/(V
OUT
+ V
F
) ratios > 4.
(V
F
= Schottky diode D1 forward voltage drop, Figure 5.)
If the LT1766 is used, the ratio increases to 10. Pulse-
skipping is the regulator’s way of missing switch pulses to
maintain output voltage regulation. Although an increase
in output ripple voltage can occur during pulse-skipping,
a ceramic output capacitor can be used to keep ripple
voltage to a minimum (see output ripple voltage compari-
son for tantalum vs ceramic output capacitors, Figure 3).
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the V
C
compensation to a
ground track carrying significant switch current. In addi-
tion, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
The LT1956 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT1956 can be considered as two g
m
blocks, the error
amplifier and the power stage.
Figure 11 shows the overall loop response. At the V
C
pin,
the frequency compensation components used are:
R
C
= 2.2k, C
C
= 0.022µF and C
F
= 220pF. The output
capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100mΩ.
The ESR of the tantalum output capacitor provides a useful
zero in the loop frequency response for maintaining stabil-
ity. This ESR, however, contributes significantly to the
ripple voltage at the output (see Output Ripple Voltage in
the Applications Information section). It is possible to
reduce capacitor size and output ripple voltage by replac-
ing the tantalum output capacitor with a ceramic output
capacitor because of its very low ESR. The zero provided
by the tantalum output capacitor must now be reinserted
back into the loop. Alternatively, there may be cases
where, even with the tantalum output capacitor, an addi-
tional zero is required in the loop to increase phase margin
for improved transient response.
A zero can be added into the loop by placing a resistor (R
C
)
at the V
C
pin in series with the compensation capacitor, C
C
,
or by placing a capacitor (C
FB
) between the output and the
FB pin.
When using R
C
, the maximum value has two limitations.
First, the combination of output capacitor ESR and R
C
may
stop the loop rolling off altogether. Second, if the loop gain
is not rolled off sufficiently at the switching frequency,
output ripple will perturb the V
C
pin enough to cause
unstable duty cycle switching similar to subharmonic
22
LT1956/LT1956-5
1956f
APPLICATIO S I FOR ATIO
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oscillations. If needed, an additional capacitor (C
F
) can be
added across the R
C
/C
C
network from the V
C
pin to ground
to further suppress V
C
ripple voltage.
With a tantalum output capacitor, the LT1956 already
includes a resistor (R
C
) and filter capacitor (C
F
) at the V
C
pin (see Figures 10 and 11) to compensate the loop over
the entire V
IN
range (to allow for stable pulse skipping for
high V
IN
-to-V
OUT
ratios ≥ 4). A ceramic output capacitor
can still be used with a simple adjustment to the resistor
R
C
for stable operation (see Ceramic Capacitors section
for stabilizing LT1956). If additional phase margin is
required, a capacitor (C
FB
) can be inserted between the
output and FB pin but care must be taken for high output
voltage applications. Sudden shorts to the output can
create unacceptably large negative transients on the FB
pin.
For V
IN
-to-V
OUT
ratios < 4, higher loop bandwidths are
possible by readjusting the frequency compensation com-
ponents at the V
C
pin.
When checking loop stability, the circuit should be oper-
ated over the application’s full voltage, current and tem-
perature range. Proper loop compensation may be obtained
by empirical methods as described in Application Notes 19
and 76.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for ex-
ample, a battery powered device with a wall adapter input,
the output of the LT1956 can be held up by the backup
supply with the LT1956 input disconnected. In this condi-
tion, the SW pin will source current into the V
IN
pin. If the
SHDN pin is held at ground, only the shut down current of
25µA will be pulled via the SW pin from the second supply.
With the SHDN pin floating, the LT1956 will consume its
quiescent operating current of 1.5mA. The V
IN
pin will also
source current to any other components connected to the
input line. If this load is greater than 10mA or the input
could be shorted to ground, a series Schottky diode must
be added, as shown in Figure 12. With these safeguards,
the output can be held at voltages up to the V
IN
absolute
maximum rating.
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, C
SS
and Q1.
As the output starts to rise, Q1 turns on, regulating switch
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
–20
–40
PHASE (DEG)
180
150
120
90
60
30
0
1956 F11
GAIN
PHASE
10
VIN = 12V
VOUT = 5V
ILOAD = 500mA
COUT = 100µF, 10V, 0.1Ω
1k 10k 1M100 100k
RC = 2.2k
CC = 22nF
CF = 220pF
–
+
1.22V
SW
V
C
LT1956
GND
1956 F10
R1
OUTPUT
ESR
C
F
C
C
R
C
R
O
200k
ERROR
AMPLIFIER
FB
R2
C1
R
LOAD
CURRENT MODE
POWER STAGE
g
m
= 2mho
g
m
=
2000µmho
+
TANTALUM
ESL
C1
CERAMIC
C
FB
Figure 10. Model for Loop Response Figure 11. Overall Loop Response
23
LT1956/LT1956-5
1956f
APPLICATIO S I FOR ATIO
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current via the V
C
pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current
through C
SS
defined by R4 and Q1’s V
BE
. Once the output
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.
RiseTime RC V
V
SS OUT
BE
=
()( )( )
4
Using the values shown in Figure 10,
Rise Time ms=
()( )
()
=
47 10 15 10 5
07 5
39
••
.
–
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can be
used for sequencing multiple regulator outputs.
DUAL POLARITY OUTPUT CONVERTER
The circuit in Figure 14a generates both positive and
negative 5V outputs with all components under 3mm
height. The topology for the 5V output is a standard buck
converter. The –5V output uses a second inductor L2,
diode D3 and output capacitor C6. The capacitor C4
5V, 1A
REMOVABLE
INPUT
C2
0.1µF
C
F
220pF
R
C
2.2k
R3
54k
D1
10MQ060N
1956 F12
C3
2.2µF
D3
10MQ060N
MMSD914TI
L1
18µH
C
C
0.022µF
C1
100µF
10V
ALTERNATE
SUPPLY
R4
25k
R1
15.4k
R2
4.99k
BOOST
V
IN
LT1956
SHDN
SYNC
SW
BIAS
FB
V
C
GND
+
Figure 12. Dual Source Supply with 25µA Reverse Leakage
OUTPUT
5V
1A
INPUT
12V
1766 F13
C2
0.1µF
C1
100µF
C
SS
15nF
D1
C3
2.2µF
CERAMIC
D2
MMSD914TI
L1
18µH
R1
15.4k
R3
2k
R2
4.99k
R4
47k
Q1
R
C
2.2k
C
F
220pF
C
C
0.022µF
BOOST BIAS
V
IN
LT1956
SHDN
SYNC
SW
FB
V
C
GND
+
Figure 13. Buck Converter with Adjustable Soft-Start
24
LT1956/LT1956-5
1956f
couples energy to L2 and ensures equal voltages across
L2 and L1 during steady state. Instead of using a trans-
former for L1 and L2, uncoupled inductors were used
because they require less height than a single transformer,
can be placed separately in the circuit layout for optimized
space savings and reduce overall cost. This is true even
when the uncoupled inductors are sized (twice the value of
inductance of the transformer) in order to keep ripple
current comparable to the transformer solution. If a single
transformer becomes available to provide a better height/
cost solution, refer to the dual output SEPIC circuit de-
scription in Design Note 100 for correct transformer
connection.
During switch on-time, in steady state, the voltage across
both L1 and L2 is positive and equal; with energy (and
current) ramping up in each inductor. The current in L2 is
provided by the coupling capacitor C4. During switch off-
time, current ramps downward in each inductor. The
APPLICATIO S I FOR ATIO
WUUU
V
OUT1
**
5V
V
OUT2
**
†
–5V
*SUMIDA CDRH4D28-150
**SEE FIGURE 14c FOR V
OUT1
, V
OUT2
LOAD CURRENT RELATIONSHIP
†
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 500Ω CAN BE
USED TO IMPROVE REGULATION
V
IN
9V TO 12V
(TRANSIENTS
TO 36V)
GND
1956 F14a
C2
0.1µF
C
F
220pF
R
C
2.2k
D1
B0540W
C5
10µF
6.3V
CER
C6
10µF
6.3V CER
C3
2.2µF
50V
CERAMIC
C4
10µF
6.3V
CER
D2
MMSD914TI
D3
B0540W
L1*
15µH
L2*
C
C
3300pF
R1
15.4k
R2
4.99k
+
+
+
BOOST
V
IN
LT1956
SHDN
SYNC
SW
FB
V
C
GND
Figure 14a. Dual Polarity Output Converter
V
OUT1
LOAD CURRENT (mA)
0
0
V
OUT2
MAXIMUM LOAD CURRENT (mA)
50
150
200
250
500
350
200 400
1956 F15b
100
400
450
300
600 800
Figure 14b. VOUT2 (–5V) Maximum
Allowable Load Current vs VOUT1
(5V) Load Current
VOUT2 LOAD CURRENT (mA)
0
4.75
|VOUT2| (V)
4.85
4.95
5.05
5.15
100 200 300 400
1956 F14c
500 600
5.25
4.80
4.90
5.00
5.10
5.20
5.30
VOUT1 LOAD CURRENT
750mA
VOUT1 LOAD CURRENT
250mA
VOUT1 LOAD CURRENT
500mA
V
OUT2
LOAD CURRENT (mA)
0
EFFICIENCY (%)
60
80
100
400
1956 F14d
40
20
50
70
90
30
10
0100 200 300 500
V
OUT1
LOAD CURRENT
750mA
V
OUT1
LOAD CURRENT
250mA
Figure 14c. VOUT2 (–5V) Output
Voltage vs Load Current Figure 14d. Dual Polarity Output
Converter Efficiency
25
LT1956/LT1956-5
1956f
current in L2 and C4 flows via the catch diode D3, charging
the negative output capacitor C6. If the negative output is
not loaded enough, it can go severely unregulated (be-
come more negative). Figure 14b shows the maximum
allowable –5V output load current (vs load current on the
5V output) that will maintain the –5V output within 3%
tolerance. Figure 14c shows the –5V output voltage regu-
lation vs its own load current when plotted for three
separate load currents on the 5V output. The efficiency of
the dual output converter circuit shown in Figure 14a is
given in Figure 14d.
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback signal
because the LT1956 accepts only positive feedback sig-
nals. The ground pin must be tied to the regulated negative
output. A resistor divider to the FB pin, then provides the
proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
APPLICATIO S I FOR ATIO
WUUU
I
IVV
VVfL
VV
VV VV
MAX
PIN OUT
OUT IN OUT IN
OUT IN OUT F
=+
++
–()( )
()()()
()(–.)
(–.)()
203
03
I
P
= maximum rated switch current
V
IN
= minimum input voltage
V
OUT
= output voltage
V
F
= catch diode forward voltage
0.3 = switch voltage drop at 1.5A
Example: with V
IN(MIN)
= 5.5V, V
OUT
= 12V, L = 15µH,
V
F
= 0.63V, I
P
= 1.5A: I
MAX
= 0.36A.
INDUCTOR VALUE
The criteria for choosing the inductor is typically based on
ensuring that peak switch current rating is not exceeded.
This gives the lowest value of inductance that can be used,
but in some cases (lower output load currents) it may give
a value that creates unnecessarily high output ripple
voltage.
The difficulty in calculating the minimum inductor size
needed is that you must first decide whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current reaches 1.5A. The first step is
to use the following formula to calculate the load current
above which the switcher must use continuous mode. If
your load current is less than this, use the discontinuous
mode formula to calculate minimum inductor needed. If
load current is higher, use the continuous mode formula.
Output current where continuous mode is needed:
IVI
VV VV V
CONT IN P
IN OUT IN OUT F
>+++
()()
()( )
22
4
Minimum inductor discontinuous mode:
LVI
fI
MIN OUT OUT
P
=2
2
()()
()( )
OUTPUT**
–12V, 0.25A
VIN
12V
1956 F15
C2
0.1µF
CC
RC
D1
10MQO60N
R1
36.5k
C1
100µF
20V TANT
C3
2.2µF
25V
D2
MMSD914TI
L1*
7µH
CF
BOOST
LT1956
VIN SW
FB
GND VC
R2
4.12k
* INCREASE L1 TO 10µH OR 18µH FOR HIGHER CURRENT APPLICATIONS.
SEE APPLICATIONS INFORMATION
** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION
+
Figure 15. Positive-to-Negative Converter
26
LT1956/LT1956-5
1956f
U
PACKAGE DESCRIPTIO
Minimum inductor continuous mode:
LVV
fV V I I VV
V
MIN IN OUT
IN OUT P OUT OUT F
IN
=++
+
()( )
()( ) – ()
21
For a 12V to –12V converter using the LT1956 with peak
switch current of 1.5A and a catch diode of 0.63V:
IA
CONT
>+++
=
()(.)
()( .)
.
12 1 5
412121212063 0 370
22
For a load current of 0.25A, this says that discontinuous
mode can be used and the minimum inductor needed is
found from:
LH
MIN
==µ
212 025
500 10 1 5 53
32
()(.)
(•)(.) .
In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of
7µH for this application.
Ripple Current in the Input and Output Capacitors
Positive-to-negative converters have high ripple current
in the input capacitor. For long capacitor lifetime, the
RMS value of this current must be less than the high
frequency ripple current rating of the capacitor. The
following formula will give an
approximate
value for RMS
ripple current.
This formula assumes continuous mode
and large inductor value
. Small inductors will give some-
what higher ripple current, especially in discontinuous
mode. The exact formulas are very complex and appear
in Application Note 44, pages 29 and 30. For our pur-
poses here I have simply added a fudge factor (ff). The
value for ff is about 1.2 for higher load currents and L
≥15µH. It increases to about 2.0 for smaller inductors at
lower load currents.
Capacitor I ff I V
V
RMS OUT OUT
IN
=()( )
ff = 1.2 to 2.0
The output capacitor ripple current for the positive-to-
negative converter is similar to that for a typical buck
regulator—it is a triangular waveform with peak-to-peak
value equal to the peak-to-peak triangular waveform of the
inductor. The low output ripple design in Figure 14 places
the input capacitor between V
IN
and the regulated negative
output. This placement of the input capacitor significantly
reduces the size required for the output capacitor (versus
placing the input capacitor between V
IN
and ground).
The peak-to-peak ripple current in both the inductor and
output capacitor (assuming continuous mode) is:
I
P-P
P-P
=
==
+
++
=
DC V
fL
DC Duty Cycle VV
VVV
I RMS I
IN
OUT F
OUT IN F
COUT
•
•
()
12
The output ripple voltage for this configuration is as low as
the typical buck regulator based predominantly on the
inductor’s triangular peak-to-peak ripple current and the
ESR of the chosen capacitor (see Output Ripple Voltage in
Applications Information).
Diode Current
Average
diode current is equal to load current.
Peak
diode
current will be considerably higher.
Peak diode current:
ContinuousMode
IVV
V
VV
LfV V
DiscontinuousMode IV
Lf
OUT IN OUT
IN
IN OUT
IN OUT
OUT OUT
=
+++
=
()()()
()()( )
()( )
()()
2
2
Keep in mind that during start-up and output overloads,
average diode current may be much higher than with
normal loads. Care should be used if diodes rated less than
1A are used, especially if continuous overload conditions
must be tolerated.
27
LT1956/LT1956-5
1956f
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
FE16 (BB) TSSOP 0203
0.09 – 0.20
(.0036 – .0079)
0° – 8°
0.45 – 0.75
(.018 – .030)
4.30 – 4.50*
(.169 – .177)
6.40
BSC
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.94
(.116)
0.195 – 0.30
(.0077 – .0118)
2
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.94
(.116)
3.58
(.141)
3.58
(.141)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
28
LT1956/LT1956-5
1956f
LT/TP 0303 2K • PRINTED IN USA
LINEAR TECHNO LOGY CORPORATION 2001
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LT1076HV
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IN
, 100kHz Operation, 700mA Internal Switch, S8
LT1765 Monolithic 3A, 1.25MHz Step-Down Regulator V
IN
: 3V to 25V; V
REF
= 1.2V; S8, TSSOP-16E
Exposed Pad
LT1766 Wide Input Range, High Efficiency, Step-Down Switching Regulator 5.5V to 60V Input, 200kHz Operation, 1.5A Internal Switch,
TSSOP-16E
LT1767 Monolithic 1.5A, 1.25MHz Step-Down Regulator V
IN
: 3V to 25V; V
REF
= 1.2V; MS8
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TSSOP-16E
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and Current Slew Rates, S16
ThinSOT is a trademark of Linear Technology Corporation.
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0502
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
.008 – .012
(0.203 – 0.305)
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 TYP.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
U
PACKAGE DESCRIPTIO
