ARM-based Embedded MPU SAMA5D3 Series DATASHEET Description The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM(R) Cortex(R)-A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of connectivity in the industrial and consumer markets. Its lowpower consumption levels make the SAMA5D3 particularly suited for battery-powered devices. There are five SAMA5D3 devices in this series. Table 1-1 "SAMA5D3 Device Differences" shows the differences in the embedded features. All other features are available on all derivatives; this includes the three USB ports as well as the encryption engine and secure boot features. 11121C-ATARM-15-Oct-13 1. Features Core ARM(R) Cortex(R)-A5 Processor with ARM v7-A Thumb2(R) Instruction Set 32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA) Fully Integrated MMU and Floating Point Unit (VFPv4) CPU Frequency up to 536 MHz Memories One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on 8-bit NAND Flash, SDCard, eMMC, serial DataFlash(R), selectable Order One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed High Bandwidth 32-bit Multi-port Dynamic RAM Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 with datapath scrambling Independent Static Memory Controller with datapath scrambling and SLC/MLC NAND Support with up to 24-bit Error Correcting Code (PMECC) System running up to 166 MHz Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock Boot Mode Select Option, Remap Command Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed 39 DMA Channels including two 8-channel 64-bit Central DMA Controllers 64-bit Advanced Interrupt Controller Three Programmable External Clock Signals Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer Low Power Management Shut Down Controller Battery Backup Registers Clock Generator and Power Management Controller Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Peripherals LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion ITU-R BT. 601/656 Image Sensor Interface Three HS/FS/LS USB Ports with On-Chip Transceivers One Device Controller One Host Controller with Integrated Root Hub (3 Downstream Ports) One 10/100/1000 Mbps Gigabit Ethernet MAC Controller (GMAC) with IEEE1588 support One 10/100 Mbps Ethernet MAC Controller (EMAC) Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B Softmodem Interface Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0) Two Master/Slave Serial Peripheral Interfaces Two Synchronous Serial Controllers Three Two-wire Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS Four USARTs, two UARTs, one DBGU Two Three-channel 32-bit Timer/Counters One 4-channel 16-bit PWM Controller SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 2 Safety Power-on Reset Cells Independent Watchdog Main Crystal Clock Failure Detection Write Protection Registers SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512) Memory Management Unit Security TRNG: True Random Number Generator Encryption Engine One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications Atmel(R) Secure Boot Solution I/O Five 32-bit Parallel Input/Output Controllers 160 I/Os Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering Slew Rate Control on High Speed I/Os Impedance Control on DDR I/Os Package 324-ball LFBGA, 15 x 15 x 1.4 mm, pitch 0.8 mm 324-ball TFBGA, 12 x 12 x 1.2 mm, pitch 0.5 mm Table 1-1. SAMA5D3 Device Differences Peripherals SAMA5D31 SAMA5D33 SAMA5D34 SAMA5D35 SAMA5D36 CAN0, CAN1 -- -- X X X EMAC X -- -- X X GMAC -- X X X X HSMCI2 X -- X X X LCDC X X X -- X TC1 -- -- -- X X UART0, UART1 X -- -- X X SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 3 2. Block Diagram SysC FIQ IRQ HS Trans HS Trans In-Circuit Emulator Cortex-A5 ICache 32 KB PLLA PLLUTMI Osc12 MHz VFP WDT DCache 32 KB MMU BIU PMC HS EHCI USB HOST HS USB Device DMA DMA EMAC 10/100 DDR_DQM[3..0] DDR_DQS[3..0] DDR_DQSN[3..0] DDR_CS DDR_CLK,DDR_CLKN DDR_CKE DDR_RAS, DDR_CAS DDR_WE DDR_BA[2..0] LCD ISI DMA DMA DMA DMA DDR2 LPDDR2 512 MB EBI PIT 4 GPBR RC OSC 32K VDDBU GMAC 10/100/1000 I/D 12 MHZ RC Osc XIN32 XOUT32 SHDN WKUP DDR_VREF DDR_A0-DDR_A13 DDR_D0-DDR_D31 PIO PA PC PB DBGU PCK0-PCK2 XIN XOUT HS Trans AIC PIO DRXD DTXD JTAG / SWD DH S DH DP SD /HH M/ SD HH PA G1 SD 25 MA GT CK -G X GT CK 12 5 X GC EN GRX CKO -G C GRRS, TX K X G E GR ER CO R - L GT X0- GRX X GR D GM 0-G X7 V D TX7 ER C, G M ET EFC DI O X K EC EN R ER SD V, X E T 0- E E R X R X EM 0-ET X1 ER DC X1 ,E LC MD LCD-D D_ AT0 IO LC V -L D_ SY CD LC PC NC _ D_ K , L DA DE , LC CD T23 N, D_ _H LC D S IS I_D D_ ISP YN C PW IS OI_P IS M I _ C IS I_H K D11 SY NC , IS I_V SY NC DD R_ CA LP DD R_ CA LN BMS HH S HH DPC SD H H MC HH SDP SD B MB VB G TST NT RS T TD I TD O TM TC S/SW K/S D WC IO LK JTA GS EL Figure 2-1. SAMA5D3 Block Diagram NAND Flash Controller MCL/SLC ECC (4 KB SRAM) Multi-Layer Matrix SHDC RTC POR RSTC NRST POR TRNG PIOB PIOD SRAM0 64 KB ROM 160 KB SRAM1 64 KB 8-CH DMA0 8-CH DMA1 Peripheral (1) Bridges SHA AES TDES Reduced Static Memory Controller DMA PIO PIOA PIOC D0-D15 A21/NANDALE A22/NANDCLE NRD/NANDOE NWE/NWR0/NANDWE NCS3/NANDCS NANDRDY A0/NBS0 A1-A20 A23-A25 NWR1/NBS1 NCS0,NCS1,NCS2 NWAIT PIOE DMA CAN0 CAN1 TWI0 TWI1 TWI2 DMA USART0 USART1 USART2 USART3 DMA UART0 UART1 DMA SPI0 SPI1 DMA DMA SSC0 SSC1 MCI0/MCI1/MCI2 SD/SDIO eMMC DMA TC0, TC1 TC2, TC3 TC4, TC5 4-CH PWM Real-time Events DMA 12-CH 12-bit ADC TouchScreen SMD P DIB DI N CA RX NT 0-C X0 A -C NR A X TW NT 1 TW D0 X1 CK -TW 0TW D2 CK CT 2 S RT 03 SCS03 RDK03 X TX 0-3 UR D0 DX -3 0 U NP TX -U CS D0 RD X 1, NP -UT 1 XD CS 1 2, NP C NP S3 CS SP 0 C M K O M SI TK ISO 0 TF -TK TD 0-T 1 F 0 RD -T 1 0 D RF -RD1 0 1 RK -RF 0 1 M -RK CI 1 M 0_C CI D M 1_ A CI C D 2 M _C A C D M I0_ A CI C M MC 1_CK CI I K M 0_D 2_C CI A K M 1_D [7..0 CI A ] 2 [ TI _D 3..0 O A ] TI A0 [3.. O -T 0] B TC 0 IO -T A PW LK0 IOB5 M -TC 5 LK PW H0 5 PW ML PW M 0-P MH FI W 3 0- M PW L3 M TS FI AD 3 TR AD IG 0U AD L 1 AD UR 2 AD LL GP 3 AD A LR 5- D4 G P TS PAD I AD 11 VR EF BN PIO CA SPI0_, SPI1_ Note: 1. Peripheral Bridge 0 (APB0) connects HSMCI0, SPI0, USART0, USART1, TWI0, TWI1, UART0, SSC0, SMD. Peripheral Bridge 1 (APB1) connects HSMCI1, HSMCI2, ADC, SSC1, UART1, USART2, USART3, TWI2, DBGU, SPI1, SHA, AES, TDES. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 4 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Input -- Output -- Input -- Clocks, Oscillators and PLLs XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output Output -- VBG Bias Voltage Reference for USB Analog -- PCK0-PCK2 Programmable Clock Output Output -- Output -- Input -- Shutdown, Wake-up Logic SHDN Shut-Down Control WKUP Wake-Up Input ICE and JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input -- TDI Test Data In Input -- TDO Test Data Out Output -- TMS/SWDIO Test Mode Select/Serial Wire Input/Output I/O -- JTAGSEL JTAG Selection Input -- I/O Low Reset/Test NRST Microcontroller Reset TST Test Mode Select Input -- NTRST Test Reset Signal Input -- BMS Boot Mode Select Input -- Debug Unit - DBGU DRXD Debug Receive Data Input -- DTXD Debug Transmit Data Output -- Advanced Interrupt Controller - AIC IRQ External Interrupt Input Input -- FIQ Fast Interrupt Input Input -- PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0-PAxx Parallel IO Controller A I/O -- PB0-PBxx Parallel IO Controller B I/O -- PC0-PCxx Parallel IO Controller C I/O -- PD0-PDxx Parallel IO Controller D I/O -- PE0-PExx Parallel IO Controller E I/O -- External Bus Interface - EBI SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 5 Table 3-1. Signal Description List (Continued) Signal Name Function D0-D15 Data Bus A0-A25 Address Bus NWAIT External Wait Signal Type Active Level I/O -- Output -- Input Low Static Memory Controller - HSMC NCS0-NCS3 Chip Select Lines Output Low NWR0-NWR1 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0-NBS1 Byte Mask Signal Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low DDR2/LPDDR Controller DDR_VREF Reference Voltage Input -- DDR_CALP Positive Calibration Reference Input -- DDR_CALN Negative Calibration Reference Input -- DDR_CK, DDR_CKN DDR2 differential clock Output -- DDR_CKE DDR2 Clock Enable Output High DDR_CS DDR2 Controller Chip Select Output Low DDR_BA[2..0] Bank Select Output Low DDR_WE DDR2 Write Enable Output Low DDR_RAS, DDR_CAS Row and Column Signal Output Low DDR_A[13..0] DDR2 Address Bus Output -- DDR_D[31..0] DDR2 Data Bus I/O -- DQS[3..0] Differential Data Strobe I/O -- DQSN[3..0] DQSN must be connected to DDR_VREF for DDR2 memories I/O -- DQM[3..0] Write Data Mask Output -- High Speed Multimedia Card Interface - HSMCI0-2 MCI0_CK, MCI1_CK, MCI2_CK Multimedia Card Clock I/O -- MCI0_CDA, MCI1_CDA, MCI2_CDA Multimedia Card Command I/O -- MCI0_DA[7..0] Multimedia Card 0 Data I/O -- MCI1_DA[3..0] Multimedia Card 1 Data I/O -- MCI2_DA[3..0) Multimedia Card 2 Data I/O -- SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 6 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level I/O -- Universal Synchronous Asynchronous Receiver Transmitter - USART0-3 SCKx USARTx Serial Clock TXDx USARTx Transmit Data Output -- RXDx USARTx Receive Data Input -- RTSx USARTx Request To Send Output -- CTSx USARTx Clear To Send Input -- Universal Asynchronous Receiver Transmitter - UARTx [1..0] UTXDx UARTx Transmit Data Output -- URXDx UARTx Receive Data Input -- Synchronous Serial Controller - SSCx [1..0] TDx SSC Transmit Data Output -- RDx SSC Receive Data Input -- TKx SSC Transmit Clock I/O -- RKx SSC Receive Clock I/O -- TFx SSC Transmit Frame Sync I/O -- RFx SSC Receive Frame Sync I/O -- Input -- Timer/Counter - TCx [5..0] TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A I/O -- TIOBx TC Channel x I/O Line B I/O -- Serial Peripheral Interface - SPIx [1..0] SPIx_MISO Master In Slave Out I/O -- SPIx_MOSI Master Out Slave In I/O -- SPIx_SPCK SPI Serial Clock I/O -- SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS[3..1] SPI Peripheral Chip Select Output Low Two-Wire Interface - TWIx [2..0] TWDx Two-wire Serial Data I/O -- TWCKx Two-wire Serial Clock I/O -- Input -- Output -- CAN controller - CANx CANRXx CAN input CANTXx CAN output Soft Modem - SMD DIBN Soft Modem Signal I/O -- DIBP Soft Modem Signal I/O -- Output -- Pulse Width Modulation Controller - PWMC PWMH[3..0] PWM Waveform Output High SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 7 Table 3-1. Signal Description List (Continued) Signal Name Function PWML[3..0] PWM Waveform Output Low PWMFIx PWM Fault Input Type Active Level Output -- Input -- USB Host High Speed Port - UHPHS HHSDPA USB Host Port A High Speed Data + Analog -- HHSDMA USB Host Port A High Speed Data - Analog -- HHSDPB USB Host Port B High Speed Data + Analog -- HHSDMB USB Host Port B High Speed Data - Analog -- HHSDPC USB Host Port C High Speed Data + Analog -- HHSDMC USB Host Port C High Speed Data - Analog -- USB Device High Speed Port - UDPHS DHSDP USB Device High Speed Data + Analog -- DHSDM USB Device High Speed Data - Analog -- GIgabit Ethernet 10/100/1000 - GMAC GTXCK Transmit Clock or Reference Clock Input -- G125CK 125 MHz input Clock Input -- G125CKO 125 MHz output Clock Output -- GTXEN Transmit Enable Output -- GTX[7..0] Transmit Data Output -- GTXER Transmit Coding Error Output -- GRXCK Receive Clock Input -- GRXDV Receive Data Valid Input -- GRX[7..0] Receive Data Input -- GRXER Receive Error Input -- GCRS Carrier Sense and Data Valid Input -- GCOL Collision Detect Input -- GMDC Management Data Clock Output -- GMDIO Management Data Input/Output I/O -- Input -- RMII Ethernet 10/100 - EMAC EREFCK Transmit Clock or Reference Clock ETXEN Transmit Enable Output -- ETX[1..0] Transmit Data Output -- ECRSDV Carrier Sense/Data Valid Input -- ERX[1..0] Receive Data Input -- ERXER Receive Error Input -- EMDC Management Data Clock Output -- EMDIO Management Data Input/Output I/O -- LCD Controller - LCDC SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 8 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level LCDDAT[23..0] LCD Data Bus Output -- LCDVSYNC LCD Vertical Synchronization Output -- LCDHSYNC LCD Horizontal Synchronization Output -- LCDPCK LCD pixel Clock Output -- LCDDEN LCD Data Enable Output -- LCDPWM LCDPWM for Contrast Control Output -- LCDDISP LCD Display ON/OFF Output -- Image Sensor Interface - ISI ISI_D[11..0] Image Sensor Data Input -- ISI_HSYNC Image Sensor Horizontal Synchro input -- ISI_VSYNC Image Sensor Vertical Synchro input -- ISI_PCK Image Sensor Data clock input -- Touch Screen Analog-to-Digital Converter - ADC AD0UL Upper Left Touch Panel Analog -- AD1UR Upper Right Touch Panel Analog -- AD2LL Lower Left Touch Panel Analog -- AD3LR Lower Right Touch Panel Analog -- AD4PI Panel Input Analog -- AD5-AD11 7 Analog Inputs Analog -- ADTRG ADC Trigger Input -- ADVREF ADC Reference Analog -- SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 9 4. Package and Pinout The SAMA5D3 product is available in two packages: 4.1 324-ball LFBGA (15 x 15 x 1.4 mm, pitch 0.8 mm) 324-ball TFBGA (12 x 12 x 1.2 mm, pitch 0.5 mm) 324-ball LFBGA Package (15 x 15 x 1.4 mm, pitch 0.8 mm) Figure 4-1 shows the ball map of the 324-ball LFBGA package. Figure 4-1. 324-ball LFBGA Ball Map Bottom VIEW V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 10 4.2 324-ball LFBGA Package Pinout Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST E3 VDDIOP0 GPIO PA0 I/O -- -- LCDDAT0 O -- -- -- -- PIO, I, PU, ST F5 VDDIOP0 GPIO PA1 I/O -- -- LCDDAT1 O -- -- -- -- PIO, I, PU, ST D2 VDDIOP0 GPIO PA2 I/O -- -- LCDDAT2 O -- -- -- -- PIO, I, PU, ST Pin F4 VDDIOP0 GPIO PA3 I/O -- -- LCDDAT3 O -- -- -- -- PIO, I, PU, ST D1 VDDIOP0 GPIO PA4 I/O -- -- LCDDAT4 O -- -- -- -- PIO, I, PU, ST J10 VDDIOP0 GPIO PA5 I/O -- -- LCDDAT5 O -- -- -- -- PIO, I, PU, ST G4 VDDIOP0 GPIO PA6 I/O -- -- LCDDAT6 O -- -- -- -- PIO, I, PU, ST J9 VDDIOP0 GPIO PA7 I/O -- -- LCDDAT7 O -- -- -- -- PIO, I, PU, ST F3 VDDIOP0 GPIO PA8 I/O -- -- LCDDAT8 O -- -- -- -- PIO, I, PU, ST J8 VDDIOP0 GPIO PA9 I/O -- -- LCDDAT9 O -- -- -- -- PIO, I, PU, ST E2 VDDIOP0 GPIO PA10 I/O -- -- LCDDAT10 O -- -- -- -- PIO, I, PU, ST K8 VDDIOP0 GPIO PA11 I/O -- -- LCDDAT11 O -- -- -- -- PIO, I, PU, ST F2 VDDIOP0 GPIO PA12 I/O -- -- LCDDAT12 O -- -- -- -- PIO, I, PU, ST G6 VDDIOP0 GPIO PA13 I/O -- -- LCDDAT13 O -- -- -- -- PIO, I, PU, ST PIO, I, PU, ST E1 VDDIOP0 GPIO PA14 I/O -- -- LCDDAT14 O -- -- -- -- H5 VDDIOP0 GPIO PA15 I/O -- -- LCDDAT15 O -- -- -- -- PIO, I, PU, ST H3 VDDIOP0 GPIO PA16 I/O -- -- LCDDAT16 O -- -- ISI_D0 I PIO, I, PU, ST H6 VDDIOP0 GPIO PA17 I/O -- -- LCDDAT17 O -- -- ISI_D1 I PIO, I, PU, ST H4 VDDIOP0 GPIO PA18 I/O -- -- LCDDAT18 O TWD2 I/O ISI_D2 I PIO, I, PU, ST H7 VDDIOP0 GPIO PA19 I/O -- -- LCDDAT19 O TWCK2 O ISI_D3 I PIO, I, PU, ST H2 VDDIOP0 GPIO PA20 I/O -- -- LCDDAT20 O PWMH0 O ISI_D4 I PIO, I, PU, ST J6 VDDIOP0 GPIO PA21 I/O -- -- LCDDAT21 O PWML0 O ISI_D5 I PIO, I, PU, ST G2 VDDIOP0 GPIO PA22 I/O -- -- LCDDAT22 O PWMH1 O ISI_D6 I PIO, I, PU, ST J5 VDDIOP0 GPIO PA23 I/O -- -- LCDDAT23 O PWML1 O ISI_D7 I PIO, I, PU, ST F1 VDDIOP0 GPIO PA24 I/O -- -- LCDPWM O -- -- -- -- PIO, I, PU, ST J4 VDDIOP0 GPIO PA25 I/O -- -- LCDDISP O -- -- -- -- PIO, I, PU, ST G3 VDDIOP0 GPIO PA26 I/O -- -- LCDVSYNC O -- -- -- -- PIO, I, PU, ST J3 VDDIOP0 GPIO PA27 I/O -- -- LCDHSYNC O -- -- -- -- PIO, I, PU, ST G1 VDDIOP0 GPIO_CLK2 PA28 I/O -- -- LCDPCK O -- -- -- -- PIO, I, PU, ST K4 VDDIOP0 GPIO PA29 I/O -- -- LCDDEN O -- -- -- -- PIO, I, PU, ST H1 VDDIOP0 GPIO PA30 I/O -- -- TWD0 I/O URXD1 I ISI_VSYNC I PIO, I, PU, ST K3 VDDIOP0 GPIO PA31 I/O -- -- TWCK0 O UTXD1 O ISI_HSYNC I PIO, I, PU, ST T2 VDDIOP1 GMAC PB0 I/O -- -- GTX0 O PWMH0 O -- -- PIO, I, PU, ST N7 VDDIOP1 GMAC PB1 I/O -- -- GTX1 O PWML0 O -- -- PIO, I, PU, ST T3 VDDIOP1 GMAC PB2 I/O -- -- GTX2 O TK1 I/O -- -- PIO, I, PU, ST N6 VDDIOP1 GMAC PB3 I/O -- -- GTX3 O TF1 I/O -- -- PIO, I, PU, ST P5 VDDIOP1 GMAC PB4 I/O -- -- GRX0 I PWMH1 O -- -- PIO, I, PU, ST T4 VDDIOP1 GMAC PB5 I/O -- -- GRX1 I PWML1 O -- -- PIO, I, PU, ST R4 VDDIOP1 GMAC PB6 I/O -- -- GRX2 I TD1 O -- -- PIO, I, PU, ST U1 VDDIOP1 GMAC PB7 I/O -- -- GRX3 I RK1 I -- -- PIO, I, PU, ST R5 VDDIOP1 GMAC PB8 I/O -- -- GTXCK I PWMH2 O -- -- PIO, I, PU, ST P3 VDDIOP1 GMAC PB9 I/O -- -- GTXEN O PWML2 O -- -- PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 11 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Alternate Pin Power Rail I/O Type Signal Dir Signal R6 VDDIOP1 GMAC PB10 I/O -- V3 VDDIOP1 GMAC PB11 I/O -- P6 VDDIOP1 GMAC PB12 I/O -- V1 VDDIOP1 GMAC PB13 I/O R7 VDDIOP1 GMAC PB14 I/O Dir PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST O RF1 I/O -- -- PIO, I, PU, ST I RD1 I -- -- PIO, I, PU, ST I PWMH3 O -- -- PIO, I, PU, ST I PWML3 O -- -- PIO, I, PU, ST I CANRX1 I -- -- PIO, I, PU, ST Signal Dir -- GTXER -- GRXCK -- GRXDV -- -- GRXER -- -- GCRS U3 VDDIOP1 GMAC PB15 I/O -- -- GCOL I CANTX1 O -- -- PIO, I, PU, ST P7 VDDIOP1 GMAC PB16 I/O -- -- GMDC O -- -- -- -- PIO, I, PU, ST V2 VDDIOP1 GMAC PB17 I/O -- -- GMDIO I/O -- -- -- -- PIO, I, PU, ST V5 VDDIOP1 GMAC PB18 I/O -- -- G125CK I -- -- -- -- PIO, I, PU, ST T6 VDDIOP1 GMAC PB19 I/O -- -- MCI1_CDA I/O GTX4 O -- -- PIO, I, PU, ST N8 VDDIOP1 GMAC PB20 I/O -- -- MCI1_DA0 I/O GTX5 O -- -- PIO, I, PU, ST U4 VDDIOP1 GMAC PB21 I/O -- -- MCI1_DA1 I/O GTX6 O -- -- PIO, I, PU, ST M7 VDDIOP1 GMAC PB22 I/O -- -- MCI1_DA2 I/O GTX7 O -- -- PIO, I, PU, ST U5 VDDIOP1 GMAC PB23 I/O -- -- MCI1_DA3 I/O GRX4 I -- -- PIO, I, PU, ST M8 VDDIOP1 GMAC PB24 I/O -- -- MCI1_CK I/O GRX5 I -- -- PIO, I, PU, ST T5 VDDIOP1 GMAC PB25 I/O -- -- SCK1 I/O GRX6 I -- -- PIO, I, PU, ST N9 VDDIOP1 GMAC PB26 I/O -- -- CTS1 I GRX7 I -- -- PIO, I, PU, ST V4 VDDIOP1 GPIO PB27 I/O -- -- RTS1 O G125CKO O -- -- PIO, I, PU, ST M9 VDDIOP1 GPIO PB28 I/O -- -- RXD1 I -- -- -- -- PIO, I, PU, ST P8 VDDIOP1 GPIO PB29 I/O -- -- TXD1 O -- -- -- -- PIO, I, PU, ST M10 VDDIOP0 GPIO PB30 I/O -- -- DRXD I -- -- -- -- PIO, I, PU, ST R9 VDDIOP0 GPIO PB31 I/O -- -- DTXD O -- -- -- -- PIO, I, PU, ST D8 VDDIOP0 GPIO PC0 I/O -- -- ETX0 O TIOA3 I/O -- -- PIO, I, PU, ST A4 VDDIOP0 GPIO PC1 I/O -- -- ETX1 O TIOB3 I/O -- -- PIO, I, PU, ST E8 VDDIOP0 GPIO PC2 I/O -- -- ERX0 I TCLK3 I -- -- PIO, I, PU, ST A3 VDDIOP0 GPIO PC3 I/O -- -- ERX1 I TIOA4 I/O -- -- PIO, I, PU, ST PIO, I, PU, ST A2 VDDIOP0 GPIO PC4 I/O -- -- ETXEN O TIOB4 I/O -- -- F8 VDDIOP0 GPIO PC5 I/O -- -- ECRSDV I TCLK4 I -- -- PIO, I, PU, ST B3 VDDIOP0 GPIO PC6 I/O -- -- ERXER I TIOA5 I/O -- -- PIO, I, PU, ST G8 VDDIOP0 GPIO PC7 I/O -- -- EREFCK I TIOB5 I/O -- -- PIO, I, PU, ST B4 VDDIOP0 GPIO PC8 I/O -- -- EMDC O TCLK5 I -- -- PIO, I, PU, ST F7 VDDIOP0 GPIO PC9 I/O -- -- EMDIO I/O -- -- -- -- PIO, I, PU, ST A1 VDDIOP0 GPIO PC10 I/O -- -- MCI2_CDA I/O -- -- LCDDAT20 O PIO, I, PU, ST D7 VDDIOP0 GPIO PC11 I/O -- -- MCI2_DA0 I/O -- -- LCDDAT19 O PIO, I, PU, ST C6 VDDIOP0 GPIO PC12 I/O -- -- MCI2_DA1 I/O TIOA1 I/O LCDDAT18 O PIO, I, PU, ST E7 VDDIOP0 GPIO PC13 I/O -- -- MCI2_DA2 I/O TIOB1 I/O LCDDAT17 O PIO, I, PU, ST B2 VDDIOP0 GPIO PC14 I/O -- -- MCI2_DA3 I/O TCLK1 I LCDDAT16 O PIO, I, PU, ST F6 VDDIOP0 MCI_CLK PC15 I/O -- -- MCI2_CK I/O PCK2 O LCDDAT21 O PIO, I, PU, ST B1 VDDIOP0 GPIO PC16 I/O -- -- TK0 I/O -- -- -- -- PIO, I, PU, ST E6 VDDIOP0 GPIO PC17 I/O -- -- TF0 I/O -- -- -- -- PIO, I, PU, ST PIO, I, PU, ST C3 VDDIOP0 GPIO PC18 I/O -- -- TD0 O -- -- -- -- D6 VDDIOP0 GPIO PC19 I/O -- -- RK0 I/O -- -- -- -- PIO, I, PU, ST C4 VDDIOP0 GPIO PC20 I/O -- -- RF0 I/O -- -- -- -- PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 12 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST D5 VDDIOP0 GPIO PC21 I/O -- -- RD0 I -- -- -- -- PIO, I, PU, ST C2 VDDIOP0 GPIO PC22 I/O -- -- SPI1_MISO I/O -- -- -- -- PIO, I, PU, ST G9 VDDIOP0 GPIO PC23 I/O -- -- SPI1_MOSI I/O -- -- -- -- PIO, I, PU, ST C1 VDDIOP0 GPIO_CLK PC24 I/O -- -- SPI1_SPCK I/O -- -- -- -- PIO, I, PU, ST H10 VDDIOP0 GPIO PC25 I/O -- -- SPI1_NPCS0 I/O -- -- -- -- PIO, I, PU, ST H9 VDDIOP0 GPIO PC26 I/O -- -- SPI1_NPCS1 O TWD1 I/O ISI_D11 I PIO, I, PU, ST D4 VDDIOP0 GPIO PC27 I/O -- -- SPI1_NPCS2 O TWCK1 O ISI_D10 I PIO, I, PU, ST PIO, I, PU, ST H8 VDDIOP0 GPIO PC28 I/O -- -- SPI1_NPCS3 O PWMFI0 I ISI_D9 I G5 VDDIOP0 GPIO PC29 I/O -- -- URXD0 I PWMFI2 I ISI_D8 I PIO, I, PU, ST D3 VDDIOP0 GPIO PC30 I/O -- -- UTXD0 O -- -- ISI_PCK O PIO, I, PU, ST E4 VDDIOP0 GPIO PC31 I/O -- -- FIQ I PWMFI1 I -- -- PIO, I, PU, ST K5 VDDIOP1 GPIO PD0 I/O -- -- MCI0_CDA I/O -- -- -- -- PIO, I, PU, ST P1 VDDIOP1 GPIO PD1 I/O -- -- MCI0_DA0 I/O -- -- -- -- PIO, I, PU, ST K6 VDDIOP1 GPIO PD2 I/O -- -- MCI0_DA1 I/O -- -- -- -- PIO, I, PU, ST R1 VDDIOP1 GPIO PD3 I/O -- -- MCI0_DA2 I/O -- -- -- -- PIO, I, PU, ST L7 VDDIOP1 GPIO PD4 I/O -- -- MCI0_DA3 I/O -- -- -- -- PIO, I, PU, ST P2 VDDIOP1 GPIO PD5 I/O -- -- MCI0_DA4 I/O TIOA0 I/O PWMH2 O PIO, I, PU, ST L8 VDDIOP1 GPIO PD6 I/O -- -- MCI0_DA5 I/O TIOB0 I/O PWML2 O PIO, I, PU, ST R2 VDDIOP1 GPIO PD7 I/O -- -- MCI0_DA6 I/O TCLK0 I PWMH3 O PIO, I, PU, ST PIO, I, PU, ST K7 VDDIOP1 GPIO PD8 I/O -- -- MCI0_DA7 I/O -- -- PWML3 O U2 VDDIOP1 MCI_CLK PD9 I/O -- -- MCI0_CK I/O -- -- -- -- PIO, I, PU, ST K9 VDDIOP1 GPIO PD10 I/O -- -- SPI0_MISO I/O -- -- -- -- PIO, I, PU, ST M5 VDDIOP1 GPIO PD11 I/O -- -- SPI0_MOSI I/O -- -- -- -- PIO, I, PU, ST K10 VDDIOP1 GPIO_CLK PD12 I/O -- -- SPI0_SPCK I/O -- -- -- -- PIO, I, PU, ST N4 VDDIOP1 GPIO PD13 I/O -- -- SPI0_NPCS0 I/O -- -- -- -- PIO, I, PU, ST L9 VDDIOP1 GPIO PD14 I/O -- -- SCK0 I/O SPI0_NPCS1 O CANRX0 I PIO, I, PU, ST N3 VDDIOP1 GPIO PD15 I/O -- -- CTS0 I SPI0_NPCS2 O CANTX0 O PIO, I, PU, ST L10 VDDIOP1 GPIO PD16 I/O -- -- RTS0 O SPI0_NPCS3 O PWMFI3 I PIO, I, PU, ST N5 VDDIOP1 GPIO PD17 I/O -- -- RXD0 I -- -- -- -- PIO, I, PU, ST M6 VDDIOP1 GPIO PD18 I/O -- -- TXD0 O -- -- -- -- PIO, I, PU, ST T1 VDDIOP1 GPIO PD19 I/O -- -- ADTRG I -- -- -- -- PIO, I, PU, ST N2 VDDANA GPIO_ANA PD20 I/O -- -- AD0 I -- -- -- -- PIO, I, PU, ST M3 VDDANA GPIO_ANA PD21 I/O -- -- AD1 I -- -- -- -- PIO, I, PU, ST M2 VDDANA GPIO_ANA PD22 I/O -- -- AD2 I -- -- -- -- PIO, I, PU, ST L3 VDDANA GPIO_ANA PD23 I/O -- -- AD3 I -- -- -- -- PIO, I, PU, ST M1 VDDANA GPIO_ANA PD24 I/O -- -- AD4 I -- -- -- -- PIO, I, PU, ST N1 VDDANA GPIO_ANA PD25 I/O -- -- AD5 I -- -- -- -- PIO, I, PU, ST L1 VDDANA GPIO_ANA PD26 I/O -- -- AD6 I -- -- -- -- PIO, I, PU, ST L2 VDDANA GPIO_ANA PD27 I/O -- -- AD7 I -- -- -- -- PIO, I, PU, ST K1 VDDANA GPIO_ANA PD28 I/O -- -- AD8 I -- -- -- -- PIO, I, PU, ST K2 VDDANA GPIO_ANA PD29 I/O -- -- AD9 I -- -- -- -- PIO, I, PU, ST J1 VDDANA GPIO_ANA PD30 I/O -- -- AD10 I PCK0 O -- -- PIO, I, PU, ST J2 VDDANA GPIO_ANA PD31 I/O -- -- AD11 I PCK1 O -- -- PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 13 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Pin Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST A,I, PD, ST P13 VDDIOM EBI PE0 I/O -- -- A0/NBS0 O -- -- -- -- R14 VDDIOM EBI PE1 I/O -- -- A1 O -- -- -- -- A,I, PD, ST R13 VDDIOM EBI PE2 I/O -- -- A2 O -- -- -- -- A,I, PD, ST V18 VDDIOM EBI PE3 I/O -- -- A3 O -- -- -- -- A,I, PD, ST P14 VDDIOM EBI PE4 I/O -- -- A4 O -- -- -- -- A,I, PD, ST U18 VDDIOM EBI PE5 I/O -- -- A5 O -- -- -- -- A,I, PD, ST T18 VDDIOM EBI PE6 I/O -- -- A6 O -- -- -- -- A,I, PD, ST R15 VDDIOM EBI PE7 I/O -- -- A7 O -- -- -- -- A,I, PD, ST P17 VDDIOM EBI PE8 I/O -- -- A8 O -- -- -- -- A,I, PD, ST P15 VDDIOM EBI PE9 I/O -- -- A9 O -- -- -- -- A,I, PD, ST P18 VDDIOM EBI PE10 I/O -- -- A10 O -- -- -- -- A,I, PD, ST R16 VDDIOM EBI PE11 I/O -- -- A11 O -- -- -- -- A,I, PD, ST N16 VDDIOM EBI PE12 I/O -- -- A12 O -- -- -- -- A,I, PD, ST R17 VDDIOM EBI PE13 I/O -- -- A13 O -- -- -- -- A,I, PD, ST A,I, PD, ST N17 VDDIOM EBI PE14 I/O -- -- A14 O -- -- -- -- R18 VDDIOM EBI PE15 I/O -- -- A15 O SCK3 I/O -- -- A,I, PD, ST N18 VDDIOM EBI PE16 I/O -- -- A16 O CTS3 I -- -- A,I, PD, ST P16 VDDIOM EBI PE17 I/O -- -- A17 O RTS3 O -- -- A,I, PD, ST M18 VDDIOM EBI PE18 I/O -- -- A18 O RXD3 I -- -- A,I, PD, ST N15 VDDIOM EBI PE19 I/O -- -- A19 O TXD3 O -- -- A,I, PD, ST M15 VDDIOM EBI PE20 I/O -- -- A20 O SCK2 I/O -- -- A,I, PD, ST N14 VDDIOM EBI PE21 I/O -- -- A21/NANDALE O -- -- -- -- A,I, PD, ST M17 VDDIOM EBI PE22 I/O -- -- A22/NANDCLE O -- -- -- -- A,I, PD, ST M13 VDDIOM EBI PE23 I/O -- -- A23 O CTS2 I -- -- A,I, PD, ST M16 VDDIOM EBI PE24 I/O -- -- A24 O RTS2 O -- -- A,I, PD, ST N12 VDDIOM EBI PE25 I/O -- -- A25 O RXD2 I -- -- A,I, PD, ST M14 VDDIOM EBI PE26 I/O -- -- NCS0 O TXD2 O -- -- A,I, PD, ST M12 VDDIOM EBI PE27 I/O -- -- NCS1 O TIOA2 I/O LCDDAT22 O PIO,I, PD, ST L13 VDDIOM EBI PE28 I/O -- -- NCS2 O TIOB2 I/O LCDDAT23 O PIO, I, PD, ST L15 VDDIOM EBI PE29 I/O -- -- NWR1/NBS1 O TCLK2 I -- -- PIO, I, PD, ST L14 VDDIOM EBI PE30 I/O -- -- NWAIT I -- -- -- -- PIO, I, PD, ST L16 VDDIOM EBI PE31 I/O -- -- IRQ I PWML1 O -- -- PIO,I, PD, ST U15 VDDBU SYSC TST I -- -- -- -- -- -- -- -- I, PD, U9 VDDIOP0 SYSC BMS I -- -- -- -- -- -- -- -- I U8 VDDIOP0 CLOCK XIN I -- -- -- -- -- -- -- -- I V8 VDDIOP0 CLOCK XOUT O -- -- -- -- -- -- -- -- O U16 VDDBU CLOCK XIN32 I -- -- -- -- -- -- -- -- I V16 VDDBU CLOCK XOUT32 O -- -- -- -- -- -- -- -- O T12 VDDBU SYSC SHDN O -- -- -- -- -- -- -- -- O T10 VDDBU SYSC WKUP I -- -- -- -- -- -- -- -- I, ST V9 VDDIOP0 RSTJTAG NRST I/O -- -- -- -- -- -- -- -- I, PU, ST P11 VDDIOP0 RSTJTAG NTRST I -- -- -- -- -- -- -- -- I, PU, ST R8 VDDIOP0 RSTJTAG TDI I -- -- -- -- -- -- -- -- I, ST SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 14 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Alternate Pin Power Rail I/O Type Signal Dir Signal M11 VDDIOP0 RSTJTAG TDO O N10 VDDIOP0 RSTJTAG TMS I P9 VDDIOP0 RSTJTAG TCK I SWCLK PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST Dir Signal Dir Signal Dir Signal Dir -- -- -- -- -- -- -- -- O SWDIO I/O -- -- -- -- -- -- I, ST I -- -- -- -- -- -- I, ST T9 VDDBU SYSC JTAGSEL I -- -- -- -- -- -- -- -- I, PD V6 VDDIOP0 DIB DIBP O -- -- -- -- -- -- -- -- O, PU U6 VDDIOP0 DIB DIBN O -- -- -- -- -- -- -- -- O, PU K12 VDDIOM EBI D0 I/O -- -- -- -- -- -- -- -- I, PD I, PD K15 VDDIOM EBI D1 I/O -- -- -- -- -- -- -- -- K14 VDDIOM EBI D2 I/O -- -- -- -- -- -- -- -- I, PD K16 VDDIOM EBI D3 I/O -- -- -- -- -- -- -- -- I, PD K13 VDDIOM EBI D4 I/O -- -- -- -- -- -- -- -- I, PD K17 VDDIOM EBI D5 I/O -- -- -- -- -- -- -- -- I, PD J12 VDDIOM EBI D6 I/O -- -- -- -- -- -- -- -- I, PD K18 VDDIOM EBI D7 I/O -- -- -- -- -- -- -- -- I, PD J14 VDDIOM EBI D8 I/O -- -- -- -- -- -- -- -- I, PD J16 VDDIOM EBI D9 I/O -- -- -- -- -- -- -- -- I, PD J13 VDDIOM EBI D10 I/O -- -- -- -- -- -- -- -- I, PD J17 VDDIOM EBI D11 I/O -- -- -- -- -- -- -- -- I, PD J15 VDDIOM EBI D12 I/O -- -- -- -- -- -- -- -- I, PD I, PD J18 VDDIOM EBI D13 I/O -- -- -- -- -- -- -- -- H16 VDDIOM EBI D14 I/O -- -- -- -- -- -- -- -- I, PD H18 VDDIOM EBI D15 I/O -- -- -- -- -- -- -- -- I, PD L12 VDDIOM EBI NCS3/NANDCS O -- -- -- -- -- -- -- -- O, PU L18 VDDIOM EBI NANDRDY I -- -- -- -- -- -- -- -- I, PU L17 VDDIOM EBI NRD/NANDOE O -- -- -- -- -- -- -- -- O, PU K11 VDDIOM EBI NWE/NANDWE O -- -- -- -- -- -- -- -- O, PU C13 VDDIODDR Reference voltage DDR_VREF I -- -- -- -- -- -- -- -- I B10 VDDIODDR DDR_IO DDR_A0 O -- -- -- -- -- -- -- -- O C11 VDDIODDR DDR_IO DDR_A1 O -- -- -- -- -- -- -- -- O A9 VDDIODDR DDR_IO DDR_A2 O -- -- -- -- -- -- -- -- O D11 VDDIODDR DDR_IO DDR_A3 O -- -- -- -- -- -- -- -- O B9 VDDIODDR DDR_IO DDR_A4 O -- -- -- -- -- -- -- -- O E10 VDDIODDR DDR_IO DDR_A5 O -- -- -- -- -- -- -- -- O D10 VDDIODDR DDR_IO DDR_A6 O -- -- -- -- -- -- -- -- O A8 VDDIODDR DDR_IO DDR_A7 O -- -- -- -- -- -- -- -- O C10 VDDIODDR DDR_IO DDR_A8 O -- -- -- -- -- -- -- -- O O B8 VDDIODDR DDR_IO DDR_A9 O -- -- -- -- -- -- -- -- F11 VDDIODDR DDR_IO DDR_A10 O -- -- -- -- -- -- -- -- O A7 VDDIODDR DDR_IO DDR_A11 O -- -- -- -- -- -- -- -- O D9 VDDIODDR DDR_IO DDR_A12 O -- -- -- -- -- -- -- -- O A6 VDDIODDR DDR_IO DDR_A13 O -- -- -- -- -- -- -- -- O H12 VDDIODDR DDR_IO DDR_D0 I/O -- -- -- -- -- -- -- -- HiZ H17 VDDIODDR DDR_IO DDR_D1 I/O -- -- -- -- -- -- -- -- HiZ SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 15 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST H13 VDDIODDR DDR_IO DDR_D2 I/O -- -- -- -- -- -- -- -- HiZ G17 VDDIODDR DDR_IO DDR_D3 I/O -- -- -- -- -- -- -- -- HiZ G16 VDDIODDR DDR_IO DDR_D4 I/O -- -- -- -- -- -- -- -- HiZ H15 VDDIODDR DDR_IO DDR_D5 I/O -- -- -- -- -- -- -- -- HiZ F17 VDDIODDR DDR_IO DDR_D6 I/O -- -- -- -- -- -- -- -- HiZ G15 VDDIODDR DDR_IO DDR_D7 I/O -- -- -- -- -- -- -- -- HiZ F16 VDDIODDR DDR_IO DDR_D8 I/O -- -- -- -- -- -- -- -- HiZ E17 VDDIODDR DDR_IO DDR_D9 I/O -- -- -- -- -- -- -- -- HiZ G14 VDDIODDR DDR_IO DDR_D10 I/O -- -- -- -- -- -- -- -- HiZ E16 VDDIODDR DDR_IO DDR_D11 I/O -- -- -- -- -- -- -- -- HiZ D17 VDDIODDR DDR_IO DDR_D12 I/O -- -- -- -- -- -- -- -- HiZ C18 VDDIODDR DDR_IO DDR_D13 I/O -- -- -- -- -- -- -- -- HiZ D16 VDDIODDR DDR_IO DDR_D14 I/O -- -- -- -- -- -- -- -- HiZ C17 VDDIODDR DDR_IO DDR_D15 I/O -- -- -- -- -- -- -- -- HiZ B16 VDDIODDR DDR_IO DDR_D16 I/O -- -- -- -- -- -- -- -- HiZ B18 VDDIODDR DDR_IO DDR_D17 I/O -- -- -- -- -- -- -- -- HiZ C15 VDDIODDR DDR_IO DDR_D18 I/O -- -- -- -- -- -- -- -- HiZ A18 VDDIODDR DDR_IO DDR_D19 I/O -- -- -- -- -- -- -- -- HiZ C16 VDDIODDR DDR_IO DDR_D20 I/O -- -- -- -- -- -- -- -- HiZ C14 VDDIODDR DDR_IO DDR_D21 I/O -- -- -- -- -- -- -- -- HiZ D15 VDDIODDR DDR_IO DDR_D22 I/O -- -- -- -- -- -- -- -- HiZ B14 VDDIODDR DDR_IO DDR_D23 I/O -- -- -- -- -- -- -- -- HiZ A15 VDDIODDR DDR_IO DDR_D24 I/O -- -- -- -- -- -- -- -- HiZ A14 VDDIODDR DDR_IO DDR_D25 I/O -- -- -- -- -- -- -- -- HiZ E12 VDDIODDR DDR_IO DDR_D26 I/O -- -- -- -- -- -- -- -- HiZ A11 VDDIODDR DDR_IO DDR_D27 I/O -- -- -- -- -- -- -- -- HiZ B11 VDDIODDR DDR_IO DDR_D28 I/O -- -- -- -- -- -- -- -- HiZ F12 VDDIODDR DDR_IO DDR_D29 I/O -- -- -- -- -- -- -- -- HiZ A10 VDDIODDR DDR_IO DDR_D30 I/O -- -- -- -- -- -- -- -- HiZ E11 VDDIODDR DDR_IO DDR_D31 I/O -- -- -- -- -- -- -- -- HiZ G12 VDDIODDR DDR_IO DDR_DQM0 O -- -- -- -- -- -- -- -- O E15 VDDIODDR DDR_IO DDR_DQM1 O -- -- -- -- -- -- -- -- O B15 VDDIODDR DDR_IO DDR_DQM2 O -- -- -- -- -- -- -- -- O D12 VDDIODDR DDR_IO DDR_DQM3 O -- -- -- -- -- -- -- -- O E18 VDDIODDR DDR_IO DDR_DQS0 I/O -- -- -- -- -- -- -- -- I, PD G18 VDDIODDR DDR_IO DDR_DQS1 I/O -- -- -- -- -- -- -- -- I, PD B17 VDDIODDR DDR_IO DDR_DQS2 I/O -- -- -- -- -- -- -- -- I, PD B13 VDDIODDR DDR_IO DDR_DQS3 I/O -- -- -- -- -- -- -- -- I, PD D18 VDDIODDR DDR_IO DDR_DQSN0 I/O -- -- -- -- -- -- -- -- I, PU F18 VDDIODDR DDR_IO DDR_DQSN1 I/O -- -- -- -- -- -- -- -- I, PU A17 VDDIODDR DDR_IO DDR_DQSN2 I/O -- -- -- -- -- -- -- -- I, PU A13 VDDIODDR DDR_IO DDR_DQSN3 I/O -- -- -- -- -- -- -- -- I, PU C8 VDDIODDR DDR_IO DDR_CS O -- -- -- -- -- -- -- -- O SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 16 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Pin Power Rail I/O Type B12 VDDIODDR A12 VDDIODDR B7 VDDIODDR C12 E13 Alternate PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST Signal Dir Signal Dir DDR_IO DDR_CLK O -- -- -- -- -- -- -- -- O DDR_IO DDR_CLKN O -- -- -- -- -- -- -- -- O DDR_IO DDR_CKE O -- -- -- -- -- -- -- -- O VDDIODDR DDR_IO DDR_CALN I -- -- -- -- -- -- -- -- O VDDIODDR DDR_IO DDR_CALP I -- -- -- -- -- -- -- -- O G11 VDDIODDR DDR_IO DDR_RAS O -- -- -- -- -- -- -- -- O A5 VDDIODDR DDR_IO DDR_CAS O -- -- -- -- -- -- -- -- O B5 VDDIODDR DDR_IO DDR_WE O -- -- -- -- -- -- -- -- O E9 VDDIODDR DDR_IO DDR_BA0 O -- -- -- -- -- -- -- -- O B6 VDDIODDR DDR_IO DDR_BA1 O -- -- -- -- -- -- -- -- O F9 VDDIODDR DDR_IO DDR_BA2 O -- -- -- -- -- -- -- -- O R11 VBG VBG VBG I -- -- -- -- -- -- -- -- I U14 VDDUTMII USBHS HHSDPC I/O -- -- -- -- -- -- -- -- O, PD V14 VDDUTMII USBHS HHSDMC I/O -- -- -- -- -- -- -- -- O, PD U12 VDDUTMII USBHS HHSDPB I/O -- -- -- -- -- -- -- -- O, PD V12 VDDUTMII USBHS HHSDMB I/O -- -- -- -- -- -- -- -- O, PD U10 VDDUTMII USBHS HHSDPA I/O DHSDP -- -- -- -- -- -- -- O, PD V10 VDDUTMII USBHS HHSDMA I/O DHSDM -- -- -- -- -- -- -- O, PD V15 VDDBU power supply VDDBU I -- -- -- -- -- -- -- -- I T13 GNDBU ground GNDBU I -- -- -- -- -- -- -- -- I C5, C7, D14, T15, T7, U17, V7 VDDCORE power supply VDDCORE I -- -- -- -- -- -- -- -- I A16, C9, N13, T14, T8, V17 GNDCORE ground GNDCORE I -- -- -- -- -- -- -- -- I D13, F14, G10, G13, H11 VDDIODDR power supply VDDIODDR I -- -- -- -- -- -- -- -- I E14, F10, F13, F15, H14 GNDIODDR ground GNDIODDR I -- -- -- -- -- -- -- -- I P12, T16 VDDIOM power supply VDDIOM I -- -- -- -- -- -- -- -- I J11, T17 GNDIOM ground GNDIOM I -- -- -- -- -- -- -- -- I G7, V11 VDDIOP0 power supply VDDIOP0 I -- -- -- -- -- -- -- -- I L11, M4 VDDIOP1 power supply VDDIOP1 I -- -- -- -- -- -- -- -- I E5, J7, N11, U7 GNDIOP Ground GNDIOP I -- -- -- -- -- -- -- -- I V13 VDDUTMIC Power supply VDDUTMIC I -- -- -- -- -- -- -- -- I SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 17 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Pin Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST U13 VDDUTMII Power supply VDDUTMII I -- -- -- -- -- -- -- -- I R12 GNDUTMI Ground GNDUTMI I -- -- -- -- -- -- -- -- I R10 VDDPLLA Power supply VDDPLLA I -- -- -- -- -- -- -- -- I P10 GNDPLL Ground GNDPLL I -- -- -- -- -- -- -- -- I U11 VDDOSC Power supply VDDOSC I -- -- -- -- -- -- -- -- I T11 GNDOSC Ground GNDOSC I -- -- -- -- -- -- -- -- I L6 VDDANA Power supply VDDANA I -- -- -- -- -- -- -- -- I L4 GNDANA Ground GNDANA I -- -- -- -- -- -- -- -- I L5 VDDANA Power supply ADVREF I -- -- -- -- -- -- -- -- I R3 VDDFUSE Power supply VDDFUSE I -- -- -- -- -- -- -- -- I P4 GNDFUSE Ground GNDFUSE I -- -- -- -- -- -- -- -- I SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 18 4.3 324-ball TFBGA Package (12 x 12 x 1.2 mm, pitch 0.5 mm) Figure 4-2 shows the ball map of the 324-ball TFBGA package. Figure 4-2. 324-ball TFBGA Ball Map SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 19 4.4 324-ball TFBGA Package Pinout Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package Primary Pin Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST PIO, I, PU, ST D2 VDDIOP0 GPIO PA0 I/O -- -- LCDDAT0 O -- -- -- -- G4 VDDIOP0 GPIO PA1 I/O -- -- LCDDAT1 O -- -- -- -- PIO, I, PU, ST C2 VDDIOP0 GPIO PA2 I/O -- -- LCDDAT2 O -- -- -- -- PIO, I, PU, ST F3 VDDIOP0 GPIO PA3 I/O -- -- LCDDAT3 O -- -- -- -- PIO, I, PU, ST F2 VDDIOP0 GPIO PA4 I/O -- -- LCDDAT4 O -- -- -- -- PIO, I, PU, ST G3 VDDIOP0 GPIO PA5 I/O -- -- LCDDAT5 O -- -- -- -- PIO, I, PU, ST B1 VDDIOP0 GPIO PA6 I/O -- -- LCDDAT6 O -- -- -- -- PIO, I, PU, ST G2 VDDIOP0 GPIO PA7 I/O -- -- LCDDAT7 O -- -- -- -- PIO, I, PU, ST C1 VDDIOP0 GPIO PA8 I/O -- -- LCDDAT8 O -- -- -- -- PIO, I, PU, ST H3 VDDIOP0 GPIO PA9 I/O -- -- LCDDAT9 O -- -- -- -- PIO, I, PU, ST D1 VDDIOP0 GPIO PA10 I/O -- -- LCDDAT10 O -- -- -- -- PIO, I, PU, ST H4 VDDIOP0 GPIO PA11 I/O -- -- LCDDAT11 O -- -- -- -- PIO, I, PU, ST E2 VDDIOP0 GPIO PA12 I/O -- -- LCDDAT12 O -- -- -- -- PIO, I, PU, ST K9 VDDIOP0 GPIO PA13 I/O -- -- LCDDAT13 O -- -- -- -- PIO, I, PU, ST H2 VDDIOP0 GPIO PA14 I/O -- -- LCDDAT14 O -- -- -- -- PIO, I, PU, ST K4 VDDIOP0 GPIO PA15 I/O -- -- LCDDAT15 O -- -- -- -- PIO, I, PU, ST G1 VDDIOP0 GPIO PA16 I/O -- -- LCDDAT16 O -- -- ISI_D0 I PIO, I, PU, ST K10 VDDIOP0 GPIO PA17 I/O -- -- LCDDAT17 O -- -- ISI_D1 I PIO, I, PU, ST F1 VDDIOP0 GPIO PA18 I/O -- -- LCDDAT18 O TWD2 I/O ISI_D2 I PIO, I, PU, ST J4 VDDIOP0 GPIO PA19 I/O -- -- LCDDAT19 O TWCK2 O ISI_D3 I PIO, I, PU, ST J3 VDDIOP0 GPIO PA20 I/O -- -- LCDDAT20 O PWMH0 O ISI_D4 I PIO, I, PU, ST K2 VDDIOP0 GPIO PA21 I/O -- -- LCDDAT21 O PWML0 O ISI_D5 I PIO, I, PU, ST J2 VDDIOP0 GPIO PA22 I/O -- -- LCDDAT22 O PWMH1 O ISI_D6 I PIO, I, PU, ST L9 VDDIOP0 GPIO PA23 I/O -- -- LCDDAT23 O PWML1 O ISI_D7 I PIO, I, PU, ST H1 VDDIOP0 GPIO PA24 I/O -- -- LCDPWM O -- -- -- -- PIO, I, PU, ST K3 VDDIOP0 GPIO PA25 I/O -- -- LCDDISP O -- -- -- -- PIO, I, PU, ST PIO, I, PU, ST J1 VDDIOP0 GPIO PA26 I/O -- -- LCDVSYNC O -- -- -- -- L10 VDDIOP0 GPIO PA27 I/O -- -- LCDHSYNC O -- -- -- -- PIO, I, PU, ST K1 VDDIOP0 GPIO_CLK2 PA28 I/O -- -- LCDPCK O -- -- -- -- PIO, I, PU, ST L3 VDDIOP0 GPIO PA29 I/O -- -- LCDDEN O -- -- -- -- PIO, I, PU, ST L2 VDDIOP0 GPIO PA30 I/O -- -- TWD0 I/O URXD1 I ISI_VSYNC I PIO, I, PU, ST L4 VDDIOP0 GPIO PA31 I/O -- -- TWCK0 O UTXD1 O ISI_HSYNC I PIO, I, PU, ST AA1 VDDIOP1 GMAC PB0 I/O -- -- GTX0 O PWMH0 O -- -- PIO, I, PU, ST W3 VDDIOP1 GMAC PB1 I/O -- -- GTX1 O PWML0 O -- -- PIO, I, PU, ST Y2 VDDIOP1 GMAC PB2 I/O -- -- GTX2 O TK1 I/O -- -- PIO, I, PU, ST Y3 VDDIOP1 GMAC PB3 I/O -- -- GTX3 O TF1 I/O -- -- PIO, I, PU, ST AA2 VDDIOP1 GMAC PB4 I/O -- -- GRX0 I PWMH1 O -- -- PIO, I, PU, ST W5 VDDIOP1 GMAC PB5 I/O -- -- GRX1 I PWML1 O -- -- PIO, I, PU, ST W7 VDDIOP1 GMAC PB6 I/O -- -- GRX2 I TD1 O -- -- PIO, I, PU, ST AB2 VDDIOP1 GMAC PB7 I/O -- -- GRX3 I RK1 I -- -- PIO, I, PU, ST AB1 VDDIOP1 GMAC PB8 I/O -- -- GTXCK I PWMH2 O -- -- PIO, I, PU, ST AA3 VDDIOP1 GMAC PB9 I/O -- -- GTXEN O PWML2 O -- -- PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 20 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST W6 VDDIOP1 GMAC PB10 I/O -- -- GTXER O RF1 I/O -- -- PIO, I, PU, ST AB3 VDDIOP1 GMAC PB11 I/O -- -- GRXCK I RD1 I -- -- PIO, I, PU, ST Y5 VDDIOP1 GMAC PB12 I/O -- -- GRXDV I PWMH3 O -- -- PIO, I, PU, ST Y4 VDDIOP1 GMAC PB13 I/O -- -- GRXER I PWML3 O -- -- PIO, I, PU, ST W8 VDDIOP1 GMAC PB14 I/O -- -- GCRS I CANRX1 I -- -- PIO, I, PU, ST AA5 VDDIOP1 GMAC PB15 I/O -- -- GCOL I CANTX1 O -- -- PIO, I, PU, ST AA4 VDDIOP1 GMAC PB16 I/O -- -- GMDC O -- -- -- -- PIO, I, PU, ST Y7 VDDIOP1 GMAC PB17 I/O -- -- GMDIO I/O -- -- -- -- PIO, I, PU, ST AB4 VDDIOP1 GMAC PB18 I/O -- -- G125CK I -- -- -- -- PIO, I, PU, ST Y6 VDDIOP1 GMAC PB19 I/O -- -- MCI1_CDA I/O GTX4 O -- -- PIO, I, PU, ST Y8 VDDIOP1 GMAC PB20 I/O -- -- MCI1_DA0 I/O GTX5 O -- -- PIO, I, PU, ST AA6 VDDIOP1 GMAC PB21 I/O -- -- MCI1_DA1 I/O GTX6 O -- -- PIO, I, PU, ST W9 VDDIOP1 GMAC PB22 I/O -- -- MCI1_DA2 I/O GTX7 O -- -- PIO, I, PU, ST AB6 VDDIOP1 GMAC PB23 I/O -- -- MCI1_DA3 I/O GRX4 I -- -- PIO, I, PU, ST AB5 VDDIOP1 GMAC PB24 I/O -- -- MCI1_CK I/O GRX5 I -- -- PIO, I, PU, ST AB7 VDDIOP1 GMAC PB25 I/O -- -- SCK1 I/O GRX6 I -- -- PIO, I, PU, ST AA7 VDDIOP1 GMAC PB26 I/O -- -- CTS1 I GRX7 I -- -- PIO, I, PU, ST AB8 VDDIOP1 GPIO PB27 I/O -- -- RTS1 O G125CKO O -- -- PIO, I, PU, ST AA8 VDDIOP1 GPIO PB28 I/O -- -- RXD1 I -- -- -- -- PIO, I, PU, ST Y9 VDDIOP1 GPIO PB29 I/O -- -- TXD1 O -- -- -- -- PIO, I, PU, ST W10 VDDIOP0 GPIO PB30 I/O -- -- DRXD I -- -- -- -- PIO, I, PU, ST Y12 VDDIOP0 GPIO PB31 I/O -- -- DTXD O -- -- -- -- PIO, I, PU, ST D10 VDDIOP0 GPIO PC0 I/O -- -- ETX0 O TIOA3 I/O -- -- PIO, I, PU, ST B8 VDDIOP0 GPIO PC1 I/O -- -- ETX1 O TIOB3 I/O -- -- PIO, I, PU, ST D9 VDDIOP0 GPIO PC2 I/O -- -- ERX0 I TCLK3 I -- -- PIO, I, PU, ST C8 VDDIOP0 GPIO PC3 I/O -- -- ERX1 I TIOA4 I/O -- -- PIO, I, PU, ST PIO, I, PU, ST B7 VDDIOP0 GPIO PC4 I/O -- -- ETXEN O TIOB4 I/O -- -- D8 VDDIOP0 GPIO PC5 I/O -- -- ECRSDV I TCLK4 I -- -- PIO, I, PU, ST A6 VDDIOP0 GPIO PC6 I/O -- -- ERXER I TIOA5 I/O -- -- PIO, I, PU, ST A7 VDDIOP0 GPIO PC7 I/O -- -- EREFCK I TIOB5 I/O -- -- PIO, I, PU, ST B6 VDDIOP0 GPIO PC8 I/O -- -- EMDC O TCLK5 I -- -- PIO, I, PU, ST D7 VDDIOP0 GPIO PC9 I/O -- -- EMDIO I/O -- -- -- -- PIO, I, PU, ST A5 VDDIOP0 GPIO PC10 I/O -- -- MCI2_CDA I/O -- -- LCDDAT20 O PIO, I, PU, ST C7 VDDIOP0 GPIO PC11 I/O -- -- MCI2_DA0 I/O -- -- LCDDAT19 O PIO, I, PU, ST B5 VDDIOP0 GPIO PC12 I/O -- -- MCI2_DA1 I/O TIOA1 I/O LCDDAT18 O PIO, I, PU, ST C6 VDDIOP0 GPIO PC13 I/O -- -- MCI2_DA2 I/O TIOB1 I/O LCDDAT17 O PIO, I, PU, ST B4 VDDIOP0 GPIO PC14 I/O -- -- MCI2_DA3 I/O TCLK1 I LCDDAT16 O PIO, I, PU, ST A4 VDDIOP0 MCI_CLK PC15 I/O -- -- MCI2_CK I/O PCK2 O LCDDAT21 O PIO, I, PU, ST A3 VDDIOP0 GPIO PC16 I/O -- -- TK0 I/O -- -- -- -- PIO, I, PU, ST C5 VDDIOP0 GPIO PC17 I/O -- -- TF0 I/O -- -- -- -- PIO, I, PU, ST PIO, I, PU, ST C4 VDDIOP0 GPIO PC18 I/O -- -- TD0 O -- -- -- -- D6 VDDIOP0 GPIO PC19 I/O -- -- RK0 I/O -- -- -- -- PIO, I, PU, ST B3 VDDIOP0 GPIO PC20 I/O -- -- RF0 I/O -- -- -- -- PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 21 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST D5 VDDIOP0 GPIO PC21 I/O -- -- RD0 I -- -- -- -- PIO, I, PU, ST C3 VDDIOP0 GPIO PC22 I/O -- -- SPI1_MISO I/O -- -- -- -- PIO, I, PU, ST B2 VDDIOP0 GPIO PC23 I/O -- -- SPI1_MOSI I/O -- -- -- -- PIO, I, PU, ST A2 VDDIOP0 GPIO_CLK PC24 I/O -- -- SPI1_SPCK I/O -- -- -- -- PIO, I, PU, ST A1 VDDIOP0 GPIO PC25 I/O -- -- SPI1_NPCS0 I/O -- -- -- -- PIO, I, PU, ST D3 VDDIOP0 GPIO PC26 I/O -- -- SPI1_NPCS1 O TWD1 I/O ISI_D11 I PIO, I, PU, ST D4 VDDIOP0 GPIO PC27 I/O -- -- SPI1_NPCS2 O TWCK1 O ISI_D10 I PIO, I, PU, ST E4 VDDIOP0 GPIO PC28 I/O -- -- SPI1_NPCS3 O PWMFI0 I ISI_D9 I PIO, I, PU, ST E3 VDDIOP0 GPIO PC29 I/O -- -- URXD0 I PWMFI2 I ISI_D8 I PIO, I, PU, ST E1 VDDIOP0 GPIO PC30 I/O -- -- UTXD0 O -- -- ISI_PCK O PIO, I, PU, ST F4 VDDIOP0 GPIO PC31 I/O -- -- FIQ I PWMFI1 I -- -- PIO, I, PU, ST M10 VDDIOP1 GPIO PD0 I/O -- -- MCI0_CDA I/O -- -- -- -- PIO, I, PU, ST T1 VDDIOP1 GPIO PD1 I/O -- -- MCI0_DA0 I/O -- -- -- -- PIO, I, PU, ST R4 VDDIOP1 GPIO PD2 I/O -- -- MCI0_DA1 I/O -- -- -- -- PIO, I, PU, ST U1 VDDIOP1 GPIO PD3 I/O -- -- MCI0_DA2 I/O -- -- -- -- PIO, I, PU, ST M9 VDDIOP1 GPIO PD4 I/O -- -- MCI0_DA3 I/O -- -- -- -- PIO, I, PU, ST V1 VDDIOP1 GPIO PD5 I/O -- -- MCI0_DA4 I/O TIOA0 I/O PWMH2 O PIO, I, PU, ST N10 VDDIOP1 GPIO PD6 I/O -- -- MCI0_DA5 I/O TIOB0 I/O PWML2 O PIO, I, PU, ST W1 VDDIOP1 GPIO PD7 I/O -- -- MCI0_DA6 I/O TCLK0 I PWMH3 O PIO, I, PU, ST PIO, I, PU, ST R3 VDDIOP1 GPIO PD8 I/O -- -- MCI0_DA7 I/O -- -- PWML3 O Y1 VDDIOP1 MCI_CLK PD9 I/O -- -- MCI0_CK I/O -- -- -- -- PIO, I, PU, ST T3 VDDIOP1 GPIO PD10 I/O -- -- SPI0_MISO I/O -- -- -- -- PIO, I, PU, ST T2 VDDIOP1 GPIO PD11 I/O -- -- SPI0_MOSI I/O -- -- -- -- PIO, I, PU, ST N9 VDDIOP1 GPIO_CLK PD12 I/O -- -- SPI0_SPCK I/O -- -- -- -- PIO, I, PU, ST U2 VDDIOP1 GPIO PD13 I/O -- -- SPI0_NPCS0 I/O -- -- -- -- PIO, I, PU, ST T4 VDDIOP1 GPIO PD14 I/O -- -- SCK0 I/O SPI0_NPCS1 O CANRX0 I PIO, I, PU, ST V2 VDDIOP1 GPIO PD15 I/O -- -- CTS0 I SPI0_NPCS2 O CANTX0 O PIO, I, PU, ST U3 VDDIOP1 GPIO PD16 I/O -- -- RTS0 O SPI0_NPCS3 O PWMFI3 I PIO, I, PU, ST V3 VDDIOP1 GPIO PD17 I/O -- -- RXD0 I -- -- -- -- PIO, I, PU, ST U4 VDDIOP1 GPIO PD18 I/O -- -- TXD0 O -- -- -- -- PIO, I, PU, ST W2 VDDIOP1 GPIO PD19 I/O -- -- ADTRG I -- -- -- -- PIO, I, PU, ST P3 VDDANA GPIO_ANA PD20 I/O -- -- AD0 I -- -- -- -- PIO, I, PU, ST R2 VDDANA GPIO_ANA PD21 I/O -- -- AD1 I -- -- -- -- PIO, I, PU, ST PIO, I, PU, ST P2 VDDANA GPIO_ANA PD22 I/O -- -- AD2 I -- -- -- -- R1 VDDANA GPIO_ANA PD23 I/O -- -- AD3 I -- -- -- -- PIO, I, PU, ST P1 VDDANA GPIO_ANA PD24 I/O -- -- AD4 I -- -- -- -- PIO, I, PU, ST N3 VDDANA GPIO_ANA PD25 I/O -- -- AD5 I -- -- -- -- PIO, I, PU, ST N1 VDDANA GPIO_ANA PD26 I/O -- -- AD6 I -- -- -- -- PIO, I, PU, ST N2 VDDANA GPIO_ANA PD27 I/O -- -- AD7 I -- -- -- -- PIO, I, PU, ST M2 VDDANA GPIO_ANA PD28 I/O -- -- AD8 I -- -- -- -- PIO, I, PU, ST M1 VDDANA GPIO_ANA PD29 I/O -- -- AD9 I -- -- -- -- PIO, I, PU, ST M3 VDDANA GPIO_ANA PD30 I/O -- -- AD10 I PCK0 O -- -- PIO, I, PU, ST L1 VDDANA GPIO_ANA PD31 I/O -- -- AD11 I PCK1 O -- -- PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 22 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST W17 VDDIOM EBI PE0 I/O -- -- A0/NBS0 O -- -- -- -- A,I, PD, ST Y18 VDDIOM EBI PE1 I/O -- -- A1 O -- -- -- -- A,I, PD, ST W18 VDDIOM EBI PE2 I/O -- -- A2 O -- -- -- -- A,I, PD, ST AA21 VDDIOM EBI PE3 I/O -- -- A3 O -- -- -- -- A,I, PD, ST Y16 VDDIOM EBI PE4 I/O -- -- A4 O -- -- -- -- A,I, PD, ST Pin Y20 VDDIOM EBI PE5 I/O -- -- A5 O -- -- -- -- A,I, PD, ST W19 VDDIOM EBI PE6 I/O -- -- A6 O -- -- -- -- A,I, PD, ST Y22 VDDIOM EBI PE7 I/O -- -- A7 O -- -- -- -- A,I, PD, ST Y21 VDDIOM EBI PE8 I/O -- -- A8 O -- -- -- -- A,I, PD, ST W22 VDDIOM EBI PE9 I/O -- -- A9 O -- -- -- -- A,I, PD, ST V19 VDDIOM EBI PE10 I/O -- -- A10 O -- -- -- -- A,I, PD, ST W20 VDDIOM EBI PE11 I/O -- -- A11 O -- -- -- -- A,I, PD, ST W21 VDDIOM EBI PE12 I/O -- -- A12 O -- -- -- -- A,I, PD, ST T19 VDDIOM EBI PE13 I/O -- -- A13 O -- -- -- -- A,I, PD, ST A,I, PD, ST V22 VDDIOM EBI PE14 I/O -- -- A14 O -- -- -- -- V20 VDDIOM EBI PE15 I/O -- -- A15 O SCK3 I/O -- -- A,I, PD, ST V21 VDDIOM EBI PE16 I/O -- -- A16 O CTS3 I -- -- A,I, PD, ST T20 VDDIOM EBI PE17 I/O -- -- A17 O RTS3 O -- -- A,I, PD, ST U20 VDDIOM EBI PE18 I/O -- -- A18 O RXD3 I -- -- A,I, PD, ST U21 VDDIOM EBI PE19 I/O -- -- A19 O TXD3 O -- -- A,I, PD, ST U22 VDDIOM EBI PE20 I/O -- -- A20 O SCK2 I/O -- -- A,I, PD, ST R19 VDDIOM EBI PE21 I/O -- -- A21/NANDALE O -- -- -- -- A,I, PD, ST R20 VDDIOM EBI PE22 I/O -- -- A22/NANDCLE O -- -- -- -- A,I, PD, ST T21 VDDIOM EBI PE23 I/O -- -- A23 O CTS2 I -- -- A,I, PD, ST T22 VDDIOM EBI PE24 I/O -- -- A24 O RTS2 O -- -- A,I, PD, ST P19 VDDIOM EBI PE25 I/O -- -- A25 O RXD2 I -- -- A,I, PD, ST R22 VDDIOM EBI PE26 I/O -- -- NCS0 O TXD2 O -- -- A,I, PD, ST R21 VDDIOM EBI PE27 I/O -- -- NCS1 O TIOA2 I/O LCDDAT22 O PIO,I, PD, ST P20 VDDIOM EBI PE28 I/O -- -- NCS2 O TIOB2 I/O LCDDAT23 O PIO, I, PD, ST P21 VDDIOM EBI PE29 I/O -- -- NWR1/NBS1 O TCLK2 I -- -- PIO, I, PD, ST N19 VDDIOM EBI PE30 I/O -- -- NWAIT I -- -- -- -- PIO, I, PD, ST N21 VDDIOM EBI PE31 I/O -- -- IRQ I PWML1 O -- -- PIO,I, PD, ST Y15 VDDBU SYSC TST I -- -- -- -- -- -- -- -- I, PD, -- -- -- -- I -- -- -- -- -- -- I -- -- -- -- O AB14 VDDIOP0 SYSC BMS I -- -- AB11 VDDIOP0 CLOCK XIN I -- -- AA11 VDDIOP0 CLOCK XOUT O -- -- AB19 VDDBU CLOCK XIN32 I -- -- AA19 VDDBU CLOCK XOUT32 O -- -- W16 VDDBU SYSC SHDN O -- -- AB16 VDDBU SYSC WKUP I -- -- -- -- -- -- -- -- -- -- I -- -- -- -- O -- -- -- -- O -- -- -- -- I, ST Y13 VDDIOP0 RSTJTAG NRST I/O -- -- -- -- -- -- -- -- I, PU, ST AA14 VDDIOP0 RSTJTAG NTRST I -- -- -- -- -- -- -- -- I, PU, ST W13 VDDIOP0 RSTJTAG TDI I -- -- -- -- -- -- -- -- I, ST SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 23 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Alternate Power Rail I/O Type Signal Dir Signal PIO Peripheral A PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Dir Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST W11 VDDIOP0 RSTJTAG TDO O -- -- -- -- -- -- -- -- O W12 VDDIOP0 RSTJTAG TMS I SWDIO I/O -- -- -- -- -- -- I, ST Y14 VDDIOP0 RSTJTAG TCK I SWCLK I -- -- -- -- -- -- I, ST AA16 VDDBU SYSC JTAGSEL I -- -- -- -- -- -- -- -- I, PD AA9 VDDIOP0 DIB DIBP O -- -- -- -- -- -- -- -- O, PU AB9 VDDIOP0 DIB DIBN O -- -- -- -- -- -- -- -- O, PU M19 VDDIOM EBI D0 I/O -- -- -- -- -- -- -- -- I, PD I, PD M22 VDDIOM EBI D1 I/O -- -- -- -- -- -- -- -- M20 VDDIOM EBI D2 I/O -- -- -- -- -- -- -- -- I, PD L22 VDDIOM EBI D3 I/O -- -- -- -- -- -- -- -- I, PD L20 VDDIOM EBI D4 I/O -- -- -- -- -- -- -- -- I, PD L21 VDDIOM EBI D5 I/O -- -- -- -- -- -- -- -- I, PD K21 VDDIOM EBI D6 I/O -- -- -- -- -- -- -- -- I, PD H22 VDDIOM EBI D7 I/O -- -- -- -- -- -- -- -- I, PD L19 VDDIOM EBI D8 I/O -- -- -- -- -- -- -- -- I, PD J22 VDDIOM EBI D9 I/O -- -- -- -- -- -- -- -- I, PD K19 VDDIOM EBI D10 I/O -- -- -- -- -- -- -- -- I, PD J21 VDDIOM EBI D11 I/O -- -- -- -- -- -- -- -- I, PD K22 VDDIOM EBI D12 I/O -- -- -- -- -- -- -- -- I, PD H20 VDDIOM EBI D13 I/O -- -- -- -- -- -- -- -- I, PD K20 VDDIOM EBI D14 I/O -- -- -- -- -- -- -- -- I, PD J20 VDDIOM EBI D15 I/O -- -- -- -- -- -- -- -- I, PD N20 VDDIOM EBI NCS3/NANDCS O -- -- -- -- -- -- -- -- O, PU M21 VDDIOM EBI NANDRDY I -- -- -- -- -- -- -- -- I, PU N22 VDDIOM EBI NRD/NANDOE O -- -- -- -- -- -- -- -- O, PU P22 VDDIOM EBI NWE/NANDWE O -- -- -- -- -- -- -- -- O, PU J13, J14 VDDIODDR Reference voltage DDR_VREF I -- -- -- -- -- -- -- -- I B13 VDDIODDR DDR_IO DDR_A0 O -- -- -- -- -- -- -- -- O C14 VDDIODDR DDR_IO DDR_A1 O -- -- -- -- -- -- -- -- O B16 VDDIODDR DDR_IO DDR_A2 O -- -- -- -- -- -- -- -- O C13 VDDIODDR DDR_IO DDR_A3 O -- -- -- -- -- -- -- -- O A14 VDDIODDR DDR_IO DDR_A4 O -- -- -- -- -- -- -- -- O D13 VDDIODDR DDR_IO DDR_A5 O -- -- -- -- -- -- -- -- O C12 VDDIODDR DDR_IO DDR_A6 O -- -- -- -- -- -- -- -- O B12 VDDIODDR DDR_IO DDR_A7 O -- -- -- -- -- -- -- -- O D12 VDDIODDR DDR_IO DDR_A8 O -- -- -- -- -- -- -- -- O A13 VDDIODDR DDR_IO DDR_A9 O -- -- -- -- -- -- -- -- O C11 VDDIODDR DDR_IO DDR_A10 O -- -- -- -- -- -- -- -- O B11 VDDIODDR DDR_IO DDR_A11 O -- -- -- -- -- -- -- -- O A12 VDDIODDR DDR_IO DDR_A12 O -- -- -- -- -- -- -- -- O A11 VDDIODDR DDR_IO DDR_A13 O -- -- -- -- -- -- -- -- O J19 VDDIODDR DDR_IO DDR_D0 I/O -- -- -- -- -- -- -- -- HiZ H21 VDDIODDR DDR_IO DDR_D1 I/O -- -- -- -- -- -- -- -- HiZ SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 24 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST F20 VDDIODDR DDR_IO DDR_D2 I/O -- -- -- -- -- -- -- -- HiZ G20 VDDIODDR DDR_IO DDR_D3 I/O -- -- -- -- -- -- -- -- HiZ F21 VDDIODDR DDR_IO DDR_D4 I/O -- -- -- -- -- -- -- -- HiZ H19 VDDIODDR DDR_IO DDR_D5 I/O -- -- -- -- -- -- -- -- HiZ G21 VDDIODDR DDR_IO DDR_D6 I/O -- -- -- -- -- -- -- -- HiZ D21 VDDIODDR DDR_IO DDR_D7 I/O -- -- -- -- -- -- -- -- HiZ G19 VDDIODDR DDR_IO DDR_D8 I/O -- -- -- -- -- -- -- -- HiZ D20 VDDIODDR DDR_IO DDR_D9 I/O -- -- -- -- -- -- -- -- HiZ C22 VDDIODDR DDR_IO DDR_D10 I/O -- -- -- -- -- -- -- -- HiZ C20 VDDIODDR DDR_IO DDR_D11 I/O -- -- -- -- -- -- -- -- HiZ B21 VDDIODDR DDR_IO DDR_D12 I/O -- -- -- -- -- -- -- -- HiZ C21 VDDIODDR DDR_IO DDR_D13 I/O -- -- -- -- -- -- -- -- HiZ D19 VDDIODDR DDR_IO DDR_D14 I/O -- -- -- -- -- -- -- -- HiZ F19 VDDIODDR DDR_IO DDR_D15 I/O -- -- -- -- -- -- -- -- HiZ B20 VDDIODDR DDR_IO DDR_D16 I/O -- -- -- -- -- -- -- -- HiZ E21 VDDIODDR DDR_IO DDR_D17 I/O -- -- -- -- -- -- -- -- HiZ E19 VDDIODDR DDR_IO DDR_D18 I/O -- -- -- -- -- -- -- -- HiZ C17 VDDIODDR DDR_IO DDR_D19 I/O -- -- -- -- -- -- -- -- HiZ D18 VDDIODDR DDR_IO DDR_D20 I/O -- -- -- -- -- -- -- -- HiZ HiZ A18 VDDIODDR DDR_IO DDR_D21 I/O -- -- -- -- -- -- -- -- C19 VDDIODDR DDR_IO DDR_D22 I/O -- -- -- -- -- -- -- -- HiZ C18 VDDIODDR DDR_IO DDR_D23 I/O -- -- -- -- -- -- -- -- HiZ C16 VDDIODDR DDR_IO DDR_D24 I/O -- -- -- -- -- -- -- -- HiZ A21 VDDIODDR DDR_IO DDR_D25 I/O -- -- -- -- -- -- -- -- HiZ D15 VDDIODDR DDR_IO DDR_D26 I/O -- -- -- -- -- -- -- -- HiZ A20 VDDIODDR DDR_IO DDR_D27 I/O -- -- -- -- -- -- -- -- HiZ B14 VDDIODDR DDR_IO DDR_D28 I/O -- -- -- -- -- -- -- -- HiZ A22 VDDIODDR DDR_IO DDR_D29 I/O -- -- -- -- -- -- -- -- HiZ A16 VDDIODDR DDR_IO DDR_D30 I/O -- -- -- -- -- -- -- -- HiZ D14 VDDIODDR DDR_IO DDR_D31 I/O -- -- -- -- -- -- -- -- HiZ E20 VDDIODDR DDR_IO DDR_DQM0 O -- -- -- -- -- -- -- -- O B22 VDDIODDR DDR_IO DDR_DQM1 O -- -- -- -- -- -- -- -- O B18 VDDIODDR DDR_IO DDR_DQM2 O -- -- -- -- -- -- -- -- O C15 VDDIODDR DDR_IO DDR_DQM3 O -- -- -- -- -- -- -- -- O G22 VDDIODDR DDR_IO DDR_DQS0 I/O -- -- -- -- -- -- -- -- I, PD E22 VDDIODDR DDR_IO DDR_DQS1 I/O -- -- -- -- -- -- -- -- I, PD A19 VDDIODDR DDR_IO DDR_DQS2 I/O -- -- -- -- -- -- -- -- I, PD B17 VDDIODDR DDR_IO DDR_DQS3 I/O -- -- -- -- -- -- -- -- I, PD F22 VDDIODDR DDR_IO DDR_DQSN0 I/O -- -- -- -- -- -- -- -- I, PU D22 VDDIODDR DDR_IO DDR_DQSN1 I/O -- -- -- -- -- -- -- -- I, PU B19 VDDIODDR DDR_IO DDR_DQSN2 I/O -- -- -- -- -- -- -- -- I, PU A17 VDDIODDR DDR_IO DDR_DQSN3 I/O -- -- -- -- -- -- -- -- I, PU C9 VDDIODDR DDR_IO DDR_CS O -- -- -- -- -- -- -- -- O SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 25 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Signal Alternate Power Rail I/O Type Dir Signal D17 VDDIODDR DDR_IO DDR_CLK O D16 VDDIODDR DDR_IO DDR_CLKN O A9 VDDIODDR DDR_IO DDR_CKE O -- PIO Peripheral A PIO Peripheral B PIO Peripheral C Dir Reset State Signal, Dir, PU, PD, HiZ, ST Dir Signal Dir Signal Dir Signal -- -- -- -- -- -- -- -- O -- -- -- -- -- -- -- -- O -- -- -- -- -- -- -- O A15 VDDIODDR DDR_IO DDR_CALN I -- -- -- -- -- -- -- -- O B15 VDDIODDR DDR_IO DDR_CALP I -- -- -- -- -- -- -- -- O B10 VDDIODDR DDR_IO DDR_RAS O -- -- -- -- -- -- -- -- O B9 VDDIODDR DDR_IO DDR_CAS O -- -- -- -- -- -- -- -- O A8 VDDIODDR DDR_IO DDR_WE O -- -- -- -- -- -- -- -- O D11 VDDIODDR DDR_IO DDR_BA0 O -- -- -- -- -- -- -- -- O A10 VDDIODDR DDR_IO DDR_BA1 O -- -- -- -- -- -- -- -- O C10 VDDIODDR DDR_IO DDR_BA2 O -- -- -- -- -- -- -- -- O P12 VBG VBG VBG I -- -- -- -- -- -- -- -- I AA17 VDDUTMII USBHS HHSDPC I/O -- -- -- -- -- -- -- -- O, PD AB17 VDDUTMII USBHS HHSDMC I/O -- -- -- -- -- -- -- -- O, PD O, PD AA15 VDDUTMII USBHS HHSDPB I/O -- -- -- -- -- -- -- -- AB15 VDDUTMII USBHS HHSDMB I/O -- -- -- -- -- -- -- -- O, PD AA13 VDDUTMII USBHS HHSDPA I/O DHSDP -- -- -- -- -- -- -- O, PD AB13 VDDUTMII USBHS HHSDMA I/O DHSDM -- -- -- -- -- -- -- O, PD N13 VDDBU Power supply VDDBU I -- -- -- -- -- -- -- -- I N12 GNDBU Ground GNDBU I -- -- -- -- -- -- -- -- I Y17, Y19, AA20, AA22, AB20, AB22 VDDCORE Power supply VDDCORE I -- -- -- -- -- -- -- -- I Y10, Y11, AA10, AA12, AB10, AB12 GNDCORE Ground GNDCORE I -- -- -- -- -- -- -- -- I J12, K12, K13, K14, L12 VDDIODDR Power supply VDDIODDR I -- -- -- -- -- -- -- -- I L13, L14, M12, M13, N11 GNDIODDR Ground GNDIODDR I -- -- -- -- -- -- -- -- I M14, U19 VDDIOM Power supply VDDIOM I -- -- -- -- -- -- -- -- I N14, P14 GNDIOM Ground GNDIOM I -- -- -- -- -- -- -- -- I J9, J10 VDDIOP0 Power supply VDDIOP0 I -- -- -- -- -- -- -- -- I P9, P10 VDDIOP1 Power supply VDDIOP1 I -- -- -- -- -- -- -- -- I J11, K11, L11, M11 GNDIOP Ground GNDIOP I -- -- -- -- -- -- -- -- I AB18 VDDUTMIC Power supply VDDUTMIC I -- -- -- -- -- -- -- -- I AA18 VDDUTMII Power supply VDDUTMII I -- -- -- -- -- -- -- -- I SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 26 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST P13 GNDUTMI Ground GNDUTMI I -- -- -- -- -- -- -- -- I W14 VDDPLLA Power supply VDDPLLA I -- -- -- -- -- -- -- -- I W15 GNDPLL Ground GNDPLL I -- -- -- -- -- -- -- -- I AB21 VDDOSC Power supply VDDOSC I -- -- -- -- -- -- -- -- I P11 GNDOSC Ground GNDOSC I -- -- -- -- -- -- -- -- I M4 VDDANA Power supply VDDANA I -- -- -- -- -- -- -- -- I P4 GNDANA Ground GNDANA I -- -- -- -- -- -- -- -- I I N4 VDDANA Power supply ADVREF I -- -- -- -- -- -- -- -- W4 VDDFUSE Power supply VDDFUSE I -- -- -- -- -- -- -- -- I V4 GNDFUSE Ground GNDFUSE I -- -- -- -- -- -- -- -- I SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 27 4.5 Input/Output Description Table 4-3. SAMA5 I/O Types Description I/O Type Voltage Range Analog Pull-up Pull-up Typ. Value (Ohm) Pull-down Pull-down Typ. Value (Ohm) Schmitt Trigger GPIO 1.65-3.6V -- Switchable 100K Switchable 100K Switchable GPIO_CLK 1.65-3.6V -- Switchable 100K Switchable 100K Switchable GPIO_CLK2 1.65-3.6V -- Switchable 100K Switchable 100K Switchable GPIO_ANA 3.0-3.6V I Switchable 100K -- -- Switchable EBI 1.65-1.95V, 3.0-3.6V -- Switchable 100K Switchable 100K -- RSTJTAG 3.0-3.6V -- Reset State 100K Reset State 100K Reset State SYSC 1.65-3.6V -- -- -- Reset State 15K Reset State USBHS 3.0-3.6V I/O -- -- -- -- -- CLOCK 1.65-3.6V I/O -- -- -- -- -- DIB 3.0-3.6V I/O -- -- -- -- -- When "Reset State" is indicated, the configuration is defined by the "Reset State" column of the Pin Description table (see Table 4-1 on page 11). Table 4-4. SAMA5 I/O Type Assignation and Frequency I/O Type Max I/O Frequency (MHz) Load (pF) Fan-out Drive Control Signal Name GPIO 33 40 -- High/Medium/Low All PIO lines except the lines indicated further on in this table MCI_CLK 52 20 -- High/Medium/Low MCI0CK, MCI1CK, MCI2CK GPIO_CLK 66 20 -- High/Medium/Low SPI0CK, SPI1CK, ETXCLK, ERXCLK GPIO_CLK2 75 20 -- High/Medium/Low LCDDOTCK GPIO_ANA 25 20 Fixed to Medium ADx EBI 66 50 -- DDR_IO 166 20 -- High/Medium/Low All DDR signals RST 3 10 -- Fixed to Low NRST, NTRST, BMS JTAG 10 10 -- Fixed to Medium TCK, TDI, TMS, TDO SYSC 0.25 10 -- No WKUP, SHDN, JTAGSEL, TST, SHDN VBG 0.25 10 -- No VBG USBHS 480 20 -- No HHSDPC, HHSDPB, HHSDPA/DHSDP, HHSDMC, HHSDMB, HHSDMA/DHSDM CLOCK 50 50 -- No XIN, XOUT, XIN32, XOUT32 GMAC 125 15 -- High/Medium/Low Gigabit Ethernet I/Os 16 mA, 40 mA (peak) High/Medium/Low 1.8V/3.3V All EBI signals SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 28 5. Power Considerations 5.1 Power Supplies Table 5-1 defines the power supply rails and the estimated power consumption at typical voltage. Table 5-1. SAMA5D3 Power supplies Name Voltage Range, Nominal Associated Ground Powers VDDCORE 1.1-1.32V, 1.2V The core, including the processor, the embedded memories and the peripherals VDDIODDR VDDIOM 1.7-1.9V, 1.8V 1.14-1.30, 1.2V 1.65-1.95V, 1.8V 3.0-3.6V, 3.3V GNDCORE GNDIODDR LPDDR/DDR2 Interface I/O lines LPDDR2 Interface I/O lines GNDIOM NAND and HSMC Interface I/O lines VDDIOP0 1.65-3.6V GNDIOP Peripheral I/O lines VDDIOP1 1.65-3.6V GNDIOP Peripheral I/O lines VDDBU 1.65-3.6V GNDBU The Slow Clock Oscillator, the internal 32 kHz RC Oscillator and a part of the System Controller The USB device and host UTMI+ core VDDUTMIC 1.1-1.32V, 1.2V GNDUTMI VDDUTMII 3.0-3.6V, 3.3V GNDUTMI The USB device and host UTMI+ interface VDDPLLA 1.1-1.32V, 1.2V GNDPLL The PLLA cell VDDOSC 1.65-3.6V GNDOSC Main Oscillator Cell and PLL UTMI. If PLL UTMI is used the range is to be 3.0V to 3.6V. VDDANA 3.0-3.6V, 3.3V GNDANA The Analog-to-Digital Converter VDDFUSE 2.25-2.75V, 2.5V GNDFUSE The UTMI PLL Fuse box for programming. 5.2 It can be tied to ground with a 100 resistor for fuse reading only. Power-up Consideration The user must first activate VDDIOP and VDDIOM, then VDDPLL and VDDCORE with the constraint that VDDPLL is established no later than 1 ms after VDDCORE. The VDDCORE and VDDBU power supplies rising time must be defined according to the Core and Backup Power-OnReset characteristics to ensure VDDCORE or VDDBU has reached VIH after the POR reset time. Please refer to the "Core Power Supply POR Characteristics" and "Backup Power Supply POR Characteristics" sections of the product datasheet for power-up constraints. 5.3 Power-down Consideration The user must remove VDDPLL first, then VDDCORE, and at last VDDIOP and VDDIOM, to ensure a reliable operation of the device. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 29 6. Memories Figure 6-1. Memory Mapping Internal Memory Mapping Addressl Memory Space 0x0000 0000 Notes: (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP 0x0000 0000 Internal Memories ROM 0x0020 0000 256 MBytes NFC SRAM 0x0FFF FFFF 0x1000 0000 0x0030 0000 EBI Chip Select 0 256 MBytes 0x1FFF FFFF 0x2000 0000 0xF000 4000 DDRCS Peripheral Mapping 0x0031 0000 HSMCI0 0x0040 0000 SPI0 0x0050 0000 SRAM0 0xF000 0000 0xF000 8000 SSC0 UDPH SRAM 0x0060 0000 UHP OHCI 0xF000 C000 512 MBytes SRAM1 SMD CAN0 0xF001 0000 0x0070 0000 UHP EHCI 0x0080 0000 TC0, TC1, TC2 TWI0 EBI Chip Select 1 0xF001 8000 256 MBytes DAP 0x00A0 0000 Undefined (Abort) TWI1 0xF001 C000 0x4FFF FFFF 0x5000 0000 AXI Matrix 0x0090 0000 0xF001 4000 0x3FFF FFFF 0x4000 0000 0x0FFF FFFF USART0 EBI Chip Select 2 0xF002 0000 USART1 256 MBytes 0xF002 4000 0x5FFF FFFF 0x6000 0000 UART0 EBI Chip Select 3 0xF002 8000 256 MBytes GMAC System Controller Mapping 0xF002 C000 PWMC 0x6FFF FFFF 0x7000 0000 0xFFFF C000 0xF003 0000 NFC Command Registers 256 MBytes LCDC 0xF003 4000 Reserved 0xF003 8000 SFR 0xF003 C000 0xFFFF E400 FUSE Reserved 0xFFFF E600 HSMCI1 0xFFFF E800 HSMCI2 0xFFFF EA00 SPI1 0xFFFF EC00 SSC1 0xFFFF EE00 CAN1 0xFFFF F000 TC3, TC4, TC5 0xFFFF F200 TSADC 0xFFFF F400 0xF800 0000 DMAC0 0xF800 4000 DMAC1 0xF800 8000 MPDDRC 0xF800 C000 0xF801 0000 0xF801 4000 0xF801 8000 Undefined (Abort) MATRIX DBGU AIC PIOA 0xF801 C000 PIOB TWI2 0xFFFF F600 USART2 0xFFFF F800 0xF802 0000 PIOC 0xF802 4000 PIOD USART3 0xFFFF FA00 0xF802 8000 UART1 0xF802 C000 EMAC 0xF803 0000 UDPHS 0xF803 8000 0xFFFF FE10 0xFFFF FE20 0xFFFF FE30 AES 256 MBytes PMC 0xFFFF FE00 SHDC SHA Internal Peripherals PIOE 0xFFFF FC00 RSTC 0xF803 4000 0xEFFF FFFF 0xF000 0000 0xF803 C000 Reserved PITC 0xFFFF FE40 WDT TDES 0xF804 0000 0xFFFF FE50 0xFFFF FE54 0xFFFF FE60 Reserved 0xFFFF FE70 0xFFFF FEB0 0xFFFF C000 SYSC SCKC_CR BSC TRNG 0xF804 4000 0xFFFF FFFF HSMC 0xFFFF D000 ISI 0x7FFF FFFF 0xFFFF FFFF (1) Boot Memory 0x0010 0000 GPBR Reserved RTCC 0xFFFF FEE0 0xFFFF FFFF Reserved SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 30 6.1 Embedded Memories 6.1.1 Internal SRAM The SAMA5D3 product embeds a total of 128 Kbytes high-speed SRAM0 and SRAM1. After Remap the SRAM is accessible at address 0 but also at address 0x00300000. Only the ARM core has access to the SRAM at address 0. The others masters (DMA, peripherals, etc.) always access the SRAM at address 0x00300000. SRAM0 and SRAM1 can be accessed in parallel to improve the overall bandwidth of the system. 6.1.2 Internal ROM The SAMA5D3 product embeds one 160-Kbyte internal ROM containing a standard and a secure bootloader. The secure bootloader is described in a separate document, under NDA. The standard bootloader supports booting from: 8-bit NAND Flash with ECC management SPI Serial Flash SDCARD EMMC TWI EEPROM The boot sequence can be selected using the boot order facility (Boot Select Control Register). The internal ROM embeds Galois field tables that are used to compute NandFlash ECC. Please refer to Figure 12-9 "Galois Field Table Mapping" in the "Boot Strategies" section of this datasheet. 6.1.3 Boot Strategies For standard boot strategies, please refer to the "Boot Strategies" section of this datasheet. For secure boot strategies, please refer to the Application Note "Secure Boot on SAMA5D3 Series" (NDA required). 6.2 External Memory The SAMA5D3 features interfaces to offer connexion to a wide range of external memories or to parallel peripherals. 6.2.1 6.2.2 DDR2/LPDDR/LPDDR2 Interface 32-bit external interface 512 Mbytes address space on CS1 Supports DDR2, LPDDR and LPDDR2 memories Drive level control I/O impedance control embedded Supports 4-banks and 8-banks and up to 512 Mbytes Multi-port Static Memories and NAND Flash The static memory controller is dedicated to interfacing external memory devices: The static memory controller is able to drive up to four chip selects. NCS3 is dedicated to the NAND Flash control. Asynchronous SRAM-like memories and parallel peripherals NAND Flash (8-bit MLC and SLC) The HSMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 31 In order to improve overall system performance the DATA phase of the transfer can be DMA assisted. The static memory embeds a NAND Flash Error Correcting Code controller with the features as follows: Algorithm based on BCH codes Supports also SLC 1-bit (BCH 2-bit), SLC 4-bit (BCH 4-bit) Programmable Error Correcting Capability: 2-bit, 4-bit, 8-bit and 16-bit errors for 512 bytes/sector (4 Kbyte page) 24-bit error for 1024 bytes/sector (8 Kbyte page) Programmable sector size: 512 bytes or 1024 bytes Programmable number of sector per page: 1, 2, 4 or 8 blocks of data per page Programmable spare area size Supports spare area ECC protection Supports 8 Kbyte page size using 1024 bytes/sector and 4 Kbyte page size using 512 bytes/sector Error detection is interrupt driven Provides hardware acceleration for error location Finds roots of error-locator polynomial Programmable number of roots SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 32 7. Real-time Event Management The events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processor intervention. Peripherals receiving events contain logic by which to select the one required. 7.1 Embedded Characteristics Peripherals generate event triggers which are directly routed to event managers such as ADC, for example, to start measurement/conversion without processor intervention. 7.2 Real-time Event Mapping List Table 7-1. Real-time Event Mapping List Event Generator Event Manager PMC Pulse Width Modulation (PWM) Analog-to-Digital Converter (ADC) PWM Function Safety / Puts the PWM Outputs in Safe Mode (Main Crystal Clock Failure Detection) Safety / Puts the PWM Outputs in Safe Mode (Overspeed, Overcurrent detection, etc.) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 33 8. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories. The System Controller's peripherals are all mapped within the highest 16 KB of address space, between addresses 0xFFFF D000 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of 4 KB. Figure 8-1 on page 35 shows the System Controller block diagram. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 34 Figure 8-1. SAMA5D3 System Controller Block Diagram VDDCORE Powered System Controller nirq irq_vect irq fiq periph_irq[2..42] pit_irq wdt_irq dbgu_irq nfiq fiq_vect Advanced Interrupt Controller Cortex-A5 pmc_irq por_ntrst ntrst proc_nreset rstc_irq PCK MCK periph_nreset Debug Unit dbgu_irq dbgu_txd dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset debug Periodic Interval Timer pit_irq Watchdog Timer wdt_irq jtag_nreset Boundary Scan TAP Controller MCK periph_nreset Bus Matrix wdt_fault WDRPROC NRST por_ntrst jtag_nreset VDDCORE POR Reset Controller periph_nreset proc_nreset backup_nreset VDDBU VDDBU POR VDDBU Powered UPLLCK UHP48M UHP12M SLCK SLCK backup_nreset Real-Time Clock rtc_irq periph_nreset rtc_alarm periph_irq[32] USB High Speed Host Port SLCK SHDN WKUP backup_nreset rtc_alarm UPLLCK Shut-Down Controller periph_nreset XIN32 XOUT32 SLOW CLOCK OSC 32 kHz RC OSC XIN USB High Speed Device Port periph_irq[33] SCKC_CR 12 MHz RC OSC XOUT 4 General-purpose Backup Registers SLCK int MAINCK 12 MHz MAIN OSC SMDCK UPLL UPLLCK PLLA PLLACK Power Management Controller periph_clk[2..49] pck[0-1] UHP48M UHP12M PCK MCK DDR sysclk LCD Pixel clock pmc_irq idle SMDCK = periph_clk[11] SMDCK periph_nreset SMD Software Modem periph_irq[11] periph_clk[2..49] periph_nreset periph_nreset periph_nreset periph_clk[5.9] dbgu_rxd PA0-PA31 PIO Controllers PB0-PB31 periph_irq[5..9] irq fiq dbgu_txd Embedded Peripherals periph_irq[2..49] in out enable PC0-PC31 PD0-PD31 PE0-PE31 Fuse Box SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 35 8.1 Chip Identification Chip ID: 0x8A5C07C2 Extended ID: Table 8-1. 8.2 Chip Identification of SAMA5D3 Devices Device Extended ID SAMA5D31 0x00444300 SAMA5D33 0x00414300 SAMA5D34 0x00414301 SAMA5D35 0x00584300 SAMA5D36 0x00004301 Boundary JTAG ID: 0x05B3103F Cortex-A5 JTAG IDCODE: 0x4BA00477 Cortex-A5 Serial Wire IDCODE: 0x2BA01477 Backup Section The SAMA5D3 features a Backup Section that embeds: RC Oscillator Slow Clock Oscillator SCKR register Real-time Clock (RTC) Shutdown Controller 4 Backup registers Part of the Reset Controller (RSTC) Boot Select Control Register This section is powered by the VDDBU rail. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 36 9. Peripherals 9.1 Peripheral Mapping As shown in Section 6. "Memories" the peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each user peripheral is allocated 16 Kbytes of address space. 9.2 Peripheral Identifiers Table 9-1. Peripheral Identifiers Instance Interrupt ID Name Description External Wired-OR Clock Type 0 AIC Advanced Interrupt Controller FIQ -- SYS_CLK 1 SYS System Controller Interrupt -- PMC, RSTC, RTC SYS_CLK 2 DBGU Debug Unit Interrupt -- -- PCLOCK 3 PIT Periodic Interval Timer Interrupt -- -- SYS_CLK 4 WDT Watchdog timer Interrupt -- -- SYS_CLK 5 HSMC Multi-bit ECC Interrupt -- -- HCLOCK 6 PIOA Parallel I/O Controller A -- -- PCLOCK 7 PIOB Parallel I/O Controller B -- -- PCLOCK 8 PIOC Parallel I/O Controller C -- -- PCLOCK 9 PIOD Parallel I/O Controller D -- -- PCLOCK 10 PIOE Parallel I/O Controller E -- -- PCLOCK 11 SMD SMD Soft Modem -- -- HCLOCK 12 USART0 USART 0 -- -- PCLOCK 13 USART1 USART 1 -- -- PCLOCK 14 USART2 USART 2 -- -- PCLOCK 15 USART3 USART 3 -- -- PCLOCK 16 UART0 UART 0 -- -- PCLOCK 17 UART1 UART 1 -- -- PCLOCK 18 TWI0 Two-Wire Interface 0 -- -- PCLOCK 19 TWI1 Two-Wire Interface 1 -- -- PCLOCK 20 TWI2 Two-Wire Interface 2 -- -- PCLOCK 21 HSMCI0 High Speed Multimedia Card Interface 0 -- -- PCLOCK 22 HSMCI1 High Speed Multimedia Card Interface 1 -- -- PCLOCK 23 HSMCI2 High Speed Multimedia Card Interface 2 -- -- PCLOCK 24 SPI0 Serial Peripheral Interface 0 -- -- PCLOCK 25 SPI1 Serial Peripheral Interface 1 -- -- PCLOCK 26 TC0 Timer Counter 0 (ch. 0, 1, 2) -- -- PCLOCK 27 TC1 Timer Counter 1 (ch. 3, 4, 5) -- -- PCLOCK SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 37 Table 9-1. Peripheral Identifiers (Continued) Instance Interrupt ID Name Description External Wired-OR Clock Type 28 PWM Pulse Width Modulation Controller -- -- PCLOCK 29 ADC Touch Screen ADC Controller -- -- PCLOCK 30 DMAC0 DMA Controller 0 -- -- HCLOCK 31 DMAC1 DMA Controller 1 -- -- HCLOCK 32 UHPHS USB Host High Speed -- -- HCLOCK 33 UDPHS USB Device High Speed -- -- HCLOCK 34 GMAC Gigabit Ethernet MAC -- -- HCLOCK + PCLOCK 35 EMAC Ethernet MAC -- -- HCLOCK + PCLOCK 36 LCDC LCD Controller -- -- HCLOCK 37 ISI Image Sensor Interface -- -- HCLOCK 38 SSC0 Synchronous Serial Controller 0 -- -- PCLOCK 39 SSC1 Synchronous Serial Controller 1 -- -- PCLOCK 40 CAN0 CAN Controller 0 -- -- PCLOCK 41 CAN1 CAN Controller 1 -- -- PCLOCK 42 SHA Secure Hash Algorithm -- -- PCLOCK 43 AES Advanced Encryption Standard -- -- PCLOCK 44 TDES Triple Data Encryption Standard -- -- PCLOCK 45 TRNG True Random Number Generator -- -- PCLOCK 46 ARM Performance Monitor Unit -- -- PROC_CLOCK 47 AIC Advanced Interrupt Controller IRQ -- SYS_CLK 48 FUSE Fuse Controller -- -- PCLOCK 49 MPDDRC MPDDR controller -- -- HCLOCK 50-63 Reserved -- -- -- -- SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 38 9.3 Peripheral Signal Multiplexing on I/O Lines The SAMA5D3 product features five PIO controllers (PIOA, PIOB, PIOC, PIOD and PIOE) which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines. Each line can be assigned to one of three peripheral functions: A, B or C. The multiplexing tables (Table 4-1 "SAMA5D3 Pinout for 324-ball LFBGA Package" and Table 4-2 "SAMA5D3 Pinout for 324ball TFBGA Package") define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO controllers. Note that some output-only peripheral functions might be duplicated within the tables. The column "Reset State" indicates whether the PIO line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the "Reset State" column, the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 9.4 Peripheral Clock Type The SAMA5D3 Series embeds peripherals with five different clock types: HCLOCK: AHB Clock, managed with the PMC_SCER, PMC_SCDR and PMC_SCSR registers of PMC System Clock PCLOCK: APB Clock, managed with the PMC_PCER, PMC_PCDR, PMC_PCSR and PMC_PCR registers of Peripheral Clock HCLOCK+PCLOCK: Both clock types coexist. The clock is managed with the PMC_PCER, PMC_PCDR, PMC_PCSR and PMC_PCR registers of Peripheral Clock SYS_CLOCK: This clock cannot be disabled. PROC_CLOCK: The clock related to Processor Clock (PCK) and managed with the PMC_SCDR and PMC_SCSR registers of PMC System Clock Please refer to Table 9-1 "Peripheral Identifiers" for details. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 39 10. ARM Cortex-A5 Processor 10.1 Description The ARM Cortex-A5 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A5 processor implements the ARMv7 architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit JavaTM byte codes in Jazelle(R) state. The Floating-Point Unit (FPU) supports the ARMv7 VFPv4-D16 architecture without Advanced SIMD extensions (NEON). It is tightly integrated to the Cortex-A5 processor pipeline. It provides trapless execution and is optimized for scalar operation. It can generate an Undefined instruction exception on vector instructions that enables the programmer to emulate vector capability in software. The design can include the FPU only, in which case the Media Processing Engine (MPE) is not included. See the Cortex-A5 Floating-Point Unit Technical Reference Manual. 10.1.1 Power Management The Cortex-A5 design supports the following main levels of power management: Run Mode Standby Mode 10.1.1.1 Run Mode Run mode is the normal mode of operation where all of the processor functionality is available. Everything, including core logic and embedded RAM arrays, is clocked and powered up. 10.1.1.2 Standby Mode Standby mode disables most of the clocks of the processor, while keeping it powered up. This reduces the power drawn to the static leakage current, plus a small clock power overhead required to enable the processor to wake up from Standby mode. The transition from Standby mode to Run mode is caused by one of the following: 10.2 the arrival of an interrupt, either masked or unmasked the arrival of an event, if standby mode was initiated by a Wait for Event (WFE) instruction a debug request, when either debug is enabled or disabled a reset. Embedded Characteristics In-order pipeline with dynamic branch prediction ARM, Thumb, and ThumbEE instruction set support Harvard level 1 memory system with a Memory Management Unit (MMU) 32 Kbytes Data Cache 32 Kbytes Instruction Cache 64-bit AXI master interface ARM v7 debug architecture VFPv4-D16 FPU with trapless execution Jazelle hardware acceleration SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 40 10.3 Block Diagram Figure 10-1. Cortex-A5 Processor Top-level Diagram '& & ' "#$% $ & # ! & # ! ! )% ! $(! 10.4 Programmer Model 10.4.1 Processor Operating Modes The following operation modes are present in all states: User mode (USR) is the usual ARM program execution state. It is used for executing most application programs. Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process. Interrupt (IRQ) mode is used for general-purpose interrupt handling. Supervisor mode (SVC) is a protected mode for the operating system. Abort mode (ABT) is entered after a data or instruction prefetch abort. System mode (SYS) is a privileged user mode for the operating system. Undefined mode (UND) is entered when an undefined instruction exception occurs. Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 10.4.2 Processor Operating States The processor has the following instruction set states controlled by the T bit and J bit in the CPSR. ARM state: The processor executes 32-bit, word-aligned ARM instructions. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 41 Thumb state: The processor executes 16-bit and 32-bit, halfword-aligned Thumb instructions. ThumbEE state: The processor executes a variant of the Thumb instruction set designed as a target for dynamically generated code. This is code compiled on the device either shortly before or during execution from a portable bytecode or other intermediate or native representation. Jazelle state: The processor executes variable length, byte-aligned Java bytecodes. The J bit and the T bit determine the instruction set used by the processor. Table 10-1 shows the encoding of these bits. Table 10-1. CPSR J and T Bit Encoding J T Instruction Set State 0 0 ARM 0 1 Thumb 1 0 Jazelle 1 1 ThumbEE Changing between ARM and Thumb states does not affect the processor mode or the register contents. See the ARM Architecture Reference Manual for information on entering and exiting ThumbEE state. 10.4.2.1 Switching State It is possible to change the instruction set state of the processor between: ARM state and Thumb state using the BX and BLX instructions. Thumb state and ThumbEE state using the ENTERX and LEAVEX instructions. ARM and Jazelle state using the BXJ instruction. Thumb and Jazelle state using the BXJ instruction. See the ARM Architecture Reference Manual for more information about changing instruction set state. 10.4.3 Cortex-A5 Registers This view provides 16 ARM core registers, R0 to R15, that include the Stack Pointer (SP), Link Register (LR), and Program Counter (PC). These registers are selected from a total set of either 31 or 33 registers, depending on whether or not the Security Extensions are implemented. The current execution mode determines the selected set of registers, as shown in Table 10-2. This shows that the arrangement of the registers provides duplicate copies of some registers, with the current register selected by the execution mode. This arrangement is described as banking of the registers, and the duplicated copies of registers are referred to as banked registers. Table 10-2. Cortex-A5 Modes and Registers Layout User and System Monitor Supervisor Abort Undefined Interrupt Fast Interrupt R0 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R6 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 42 Table 10-2. Cortex-A5 Modes and Registers Layout (Continued) User and System Monitor Supervisor Abort Undefined Interrupt Fast Interrupt R7 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10 R10_FIQ R11 R11 R11 R11 R11 R11 R11_FIQ R12 R12 R12 R12 R12 R12 R12_FIQ R13 R13_MON R13_SVC R13_ABT R13_UND R13_IRQ R13_FIQ R14 R14_MON R14_SVC R14_ABT R14_UND R14_IRQ R14_FIQ PC PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR CPSR SPSR_MON SPSR_SVC SPSR_ABT SPSR_UND SPSR_IRQ SPSR_FIQ Mode-specific banked registers The core contains one CPSR, and six SPSRs for exception handlers to use. The program status registers: hold information about the most recently performed ALU operation control the enabling and disabling of interrupts set the processor operation mode Figure 10-2. Status Register Format 31 30 29 28 27 N Z C V Q 24 23 20 19 IT J Reserved [1:0] 16 15 GE[3:0] 10 9 8 7 6 5 4 IT[7:2] E A I F T 0 Mode N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags Q: cumulative saturation flag IT: If-Then execution state bits for the Thumb IT (If-Then) instruction J: Jazelle bit, see the description of the T bit GE: Greater than or Equal flags, for SIMD instructions E: Endianness execution state bit. Controls the load and store endianness for data accesses. This bit is ignored by instruction fetches. E = 0: Little endian operation E = 1: Big endian operation A: Asynchronous abort disable bit. Used to mask asynchronous aborts. I: Interrupt disable bit. Used to mask IRQ interrupts. F: Fast interrupt disable bit. Used to mask FIQ interrupts. T: Thumb execution state bit. This bit and the J execution state bit, bit [24], determine the instruction set state of the processor, ARM, Thumb, Jazelle, or ThumbEE. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 43 Mode: five bits to encode the current processor mode. The effect of setting M[4:0] to a reserved value is UNPREDICTABLE. Table 10-3. Processor Mode vs. Mode Field Mode M[4:0] USR 10000 FIQ 10001 IRQ 10010 SVC 10011 ABT 10111 UND 11011 SYS 11111 Reserved Other 10.4.3.1 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: Cortex A5 Caches (ICache, DCache and write buffer) MMU Security Other system options To control these features, CP15 provides 16 additional registers. See Table 10-4. Table 10-4. CP15 Registers Register Name Read/Write (1) 0 ID Code Read/Unpredictable 0 Cache type(1) Read/Unpredictable 1 (1) Control Read/Write (1) Read/Write 1 Security 2 Translation Table Base Read/Write 3 Domain Access Control Read/Write 4 Reserved None (1) 5 Data fault Status Read/Write 5 Instruction fault status Read/Write 6 Fault Address Read/Write 7 Cache and MMU Operations 8 TLB operations (1) Read/Write Unpredictable/Write (1) 9 Cache lockdown 10 TLB lockdown Read/Write 11 Reserved None 12 Interrupts management Read/Write 13 (1) Read/Write FCSE PID Read/Write SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 44 Table 10-4. CP15 Registers (Continued) Register Note: Name Read/Write 13 Context ID(1) Read/Write 14 Reserved None 15 Test configuration Read/Write 1. This register provides access to more than one register. The register accessed depends on the value of the CRm field or Opcode_2 field. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 45 10.4.4 CP 15 Register Access CP15 registers can only be accessed in privileged mode by: * MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. * MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions such as CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR/MRC instructions bit pattern is shown below: 31 30 29 28 27 1 26 1 21 20 L 19 18 13 12 11 1 5 4 1 3 cond 23 22 opcode_1 15 14 Rd 7 6 opcode_2 25 1 24 0 17 16 10 1 9 1 8 1 2 1 0 CRn CRm * CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. * opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. * Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. * CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. * L: Instruction Bit 0: MCR instruction 1: MRC instruction * opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. * cond [31:28]: Condition SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 46 10.4.5 Addresses in the Cortex-A5 processor The Cortex-A5 processor operates using virtual addresses (VAs). The Memory Management Unit (MMU) translates these VAs into the physical addresses (PAs) used to access the memory system. Translation tables hold the mappings between VAs and PAs. See the ARM Architecture Reference Manual for more information. When the Cortex-A5 processor is executing in Non-secure state, the processor performs translation table look-ups using the Non-secure versions of the Translation Table Base Registers. In this situation, any VA can only translate into a Nonsecure PA. When it is in Secure state, the Cortex-A5 processor performs translation table look-ups using the Secure versions of the Translation Table Base Registers. In this situation, the security state of any VA is determined by the NS bit of the translation table descriptors for that address. Following is an example of the address manipulation that occurs when the Cortex-A5 processor requests an instruction: 1. The Cortex-A5 processor issues the VA of the instruction as Secure or Non-secure VA accesses according to the state the processor is in. 2. The instruction cache is indexed by the bits of the VA. The MMU performs the translation table look-up in parallel with the cache access. If the processor is in the Secure state it uses the Secure translation tables, otherwise it uses the Non-secure translation tables. 3. If the protection check carried out by the MMU on the VA does not abort and the PA tag is in the instruction cache, the instruction data is returned to the processor. 4. If there is a cache miss, the MMU passes the PA to the AXI bus interface to perform an external access. The external access is always Non-secure when the core is in the Non-secure state. In the Secure state, the external access is Secure or Non-secure according to the NS attribute value in the selected translation table entry. In Secure state, both L1 and L2 translation table walk accesses are marked as Secure, even if the first level descriptor is marked as NS. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 47 10.5 Memory Management Unit 10.5.1 About the MMU The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. It also controls accesses to and from external memory. The ARM v7 Virtual Memory System Architecture (VMSA) features include the following: Page table entries that support: 16-Mbyte supersections. The processor supports supersections that consist of 16-Mbyte blocks of memory. 1-Mbyte sections 64-Kbyte large pages 4-Kbyte small pages 16 access domains Global and application-specific identifiers to remove the requirement for context switch TLB flushes. Extended permissions checking capability. TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated with the core. This coprocessor provides a standard mechanism for configuring the L1 memory system. See the ARM Architecture Reference Manual for a full architectural description of the ARMv7 VMSA. 10.5.2 Memory Management System The Cortex-A5 processor supports the ARM v7 VMSA The translation of a Virtual Address (VA) used by the instruction set architecture to a Physical Address (PA) used in the memory system and the management of the associated attributes and permissions is carried out using a two-level MMU. The first level MMU uses a Harvard design with separate micro TLB structures in the PFU for instruction fetches (IuTLB) and in the DPU for data read and write requests (DuTLB). A miss in the micro TLB results in a request to the main unified TLB shared between the data and instruction sides of the memory system. The TLB consists of a 128-entry two-way set-associative RAM based structure. The TLB page-walk mechanism supports page descriptors held in the L1 data cache. The caching of page descriptors is configured globally for each translation table base register, TTBRx, in the system coprocessor, CP15. The TLB contains a hitmap cache of the page types which have already been stored in the TLB. 10.5.2.1 Memory types Although various different memory types can be specified in the page tables, the Cortex-A5 processor does not implement all possible combinations: Write-through caches are not supported. Any memory marked as write-through is treated as Non-cacheable. The outer shareable attribute is not supported. Anything marked as outer shareable is treated in the same way as inner shareable. Write-back no write-allocate is not supported. It is treated as write-back write-allocate. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 48 Table 10-5 shows the treatment of each different memory type in the Cortex-A5 processor in addition to the architectural requirements. Table 10-5. Treatment of Memory Attributes Memory Type Attribute Shareability Other attributes Notes -- -- -- Non-shareable -- -- Shareable -- -- Non-cacheable Does not access L1 caches Write-through cacheable Treated as non-cacheable Write-back cacheable, write allocate Can dynamically switch to no write allocate, if more than three full cache lines are written in succession Write-back cacheable, no write allocate Treated as non-shareable write-back cacheable, write allocate Non-cacheable -- Write-through cacheable Treated as inner shareable non-cacheable Write-back cacheable, write allocate Treated as inner shareable non-cacheable unless the SMP bit in the Auxiliary Control Register is set (ACTLR[6] = b1). If this bit is set the area is treated as write-back cacheable write allocate. Strongly Ordered Device Non-shareable Inner shareable Normal Write-back cacheable, no write allocate Non-cacheable Treated as inner shareable non-cacheable Write-through cacheable Outer shareable Write-back cacheable, write allocate Write-back cacheable, no write allocate Treated as inner shareable non-cacheable unless the SMP bit in the Auxiliary Control Register is set (ACTLR[6] = b1). If this bit is set the area is treated as write-back cacheable write allocate. 10.5.3 TLB Organization TLB Organization is described in the sections that follow: Micro TLB Main TLB 10.5.3.1 Micro TLB The first level of caching for the page table information is a micro TLB of 10 entries that is implemented on each of the instruction and data sides. These blocks provide a lookup of the virtual addresses in a single cycle. The micro TLB returns the physical address to the cache for the address comparison, and also checks the access permissions to signal either a Prefetch Abort or a Data Abort. All main TLB related maintenance operations affect both the instruction and data micro TLBs, causing them to be flushed. In the same way, any change of the following registers causes the micro TLBs to be flushed: Context ID Register (CONTEXTIDR) Domain Access Control Register (DACR) Primary Region Remap Register (PRRR) Normal Memory Remap Register (NMRR) Translation Table Base Registers (TTBR0 and TTBR1) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 49 10.5.3.2 Main TLB Misses from the instruction and data micro TLBs are handled by a unified main TLB. Accesses to the main TLB take a variable number of cycles, according to competing requests from each of the micro TLBs and other implementationdependent factors. The main TLB is 128-entry two-way set-associative. TLB match process Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory properties. Each is marked as being associated with a particular application space (ASID), or as global for all application spaces. The CONTEXTIDR determines the currently selected application space. A TLB entry matches when these conditions are true: its virtual address matches that of the requested address its Non-secure TLB ID (NSTID) matches the Secure or Non-secure state of the MMU request its ASID matches the current ASID in the CONTEXTIDR or is global The operating system must ensure that, at most, one TLB entry matches at any time. The TLB can store entries based on the following block sizes: Supersections Describe 16-Mbyte blocks of memory. Sections Describe 1-Mbyte blocks of memory. Large pages Describe 64-Kbyte blocks of memory. Small pages Describe 4-Kbyte blocks of memory Supersections, sections and large pages are supported to permit mapping of a large region of memory while using only a single entry in the TLB. If no mapping for an address is found within the TLB, then the translation table is automatically read by hardware and a mapping is placed in the TLB. 10.5.4 Memory Access Sequence When the processor generates a memory access, the MMU: 1. Performs a lookup for the requested virtual address and current ASID and security state in the relevant instruction or data micro TLB. 2. If there is a miss in the micro TLB, performs a lookup for the requested virtual address and current ASID and security state in the main TLB. 3. If there is a miss in main TLB, performs a hardware translation table walk. The MMU can be configured to perform hardware translation table walks in cacheable regions by setting the IRGN bits in Translation Table Base Register 0 and Translation Table Base Register 1. If the encoding of the IRGN bits is write-back, an L1 data cache lookup is performed and data is read from the data cache. If the encoding of the IRGN bits is writethrough or non-cacheable, an access to external memory is performed. For more information refer to: Cortex-A5 Technical Reference Manual. The MMU might not find a global mapping, or a mapping for the currently selected ASID, with a matching Non-secure TLB ID (NSTID) for the virtual address in the TLB. In this case, the hardware does a translation table walk if the translation table walk is enabled by the PD0 or PD1 bit in the Translation Table Base Control Register. If translation table walks are disabled, the processor returns a Section Translation fault. For more information refer to: Cortex-A5 Technical Reference Manual. If the TLB finds a matching entry, it uses the information in the entry as follows: 1. The access permission bits and the domain determine if the access is enabled. If the matching entry does not pass the permission checks, the MMU signals a memory abort. See the ARM Architecture Reference Manual for a SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 50 description of access permission bits, abort types and priorities, and for a description of the Instruction Fault Status Register (IFSR) and Data Fault Status Register (DFSR). 2. The memory region attributes specified in both the TLB entry and the CP15 c10 remap registers determine if the access is Secure or Non-secure Shared or not Normal memory, Device, or Strongly-ordered For more information refer to: Cortex-A5 Technical Reference Manual, Memory region remap. 3. The TLB translates the virtual address to a physical address for the memory access. 10.5.5 Interaction with Memory System The MMU can be enabled or disabled as described in the ARM Architecture Reference Manual. 10.5.6 External Aborts External memory errors are defined as those that occur in the memory system rather than those that are detected by the MMU. External memory errors are expected to be extremely rare. External aborts are caused by errors flagged by the AXI interfaces when the request goes external to the Cortex-A5 processor. External aborts can be configured to trap to Monitor mode by setting the EA bit in the Secure Configuration Register. For more information refer to: Cortex-A5 Technical Reference Manual. 10.5.6.1 External Aborts on Data Write Externally generated errors during a data write can be asynchronous. This means that the r14_abt on entry into the abort handler on such an abort might not hold the address of the instruction that caused the exception. The DFAR is Unpredictable when an asynchronous abort occurs. Externally generated errors during data read are always synchronous. The address captured in the DFAR matches the address which generated the external abort. 10.5.6.2 Synchronous and Asynchronous Aborts Chapter 4, System Control in the Cortex-A5 Technical Reference Manual describes synchronous and asynchronous aborts, their priorities, and the IFSR and DFSR. To determine a fault type, read the DFSR for a data abort or the IFSR for an instruction abort. The processor supports an Auxiliary Fault Status Register for software compatibility reasons only. The processor does not modify this register because of any generated abort. 10.5.7 MMU Software Accessible Registers The system control coprocessor registers, CP15, in conjunction with page table descriptors stored in memory, control the MMU. Access all the registers with instructions of the form: MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2> MCR p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2> CRn is the system control coprocessor register. Unless specified otherwise, CRm and Opcode_2 Should Be Zero. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 51 11. SAMA5D3 Series Debug and Test 11.1 Description The device features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. A 2-pin debug port Serial Wire Debug (SWD). SWD replaces the 5-pin JTAG port and provides an easy and risk free alternative to JTAG as the two signals SWDIO and SWCLK are overlaid on the TMS and TCK pins, allowing for bi-modal devices that provide the other JTAG signals. These extra JTAG pins can be switched to other uses when in SWD mode. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 11.2 Embedded Characteristics Cortex-A5 Real-time In-circuit Emulator Two real-time Watchpoint Units Two Independent Registers: Debug Control Register and Debug Status Register Test Access Port Accessible through JTAG Protocol Debug Communications Channel Serial Wire Debug Debug Unit Two-pin UART Debug Communication Channel Interrupt Handling Chip ID Register IEEE1149.1 JTAG Boundary-scan on All Digital Pins. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 52 Block Diagram Figure 11-1. Debug and Test Block Diagram TMS / SWDIO TCK / SWCLK TDI NTRST SWD/ICE/JTAG SELECT Boundary Port JTAGSEL TDO SWD DEBUG PORT ICE/JTAG DEBUG PORT POR Reset and Test TST Cortex-A5 DTXD DMA DBGU PIO 11.3 DRXD SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 53 11.4 Application Examples 11.4.1 Debug Environment Figure 11-2 on page 54 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 11-2. Application Debug and Trace Environment Example Host Debugger PC ICE/JTAG Interface ICE/JTAG Connector SAM device RS232 Connector Terminal SAM-based Application Board SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 54 11.4.2 Test Environment Figure 11-3 on page 55 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the "board in test" is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 11-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Chip n SAM device Chip 2 Chip 1 SAM-based Application Board In Test SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 55 11.5 Debug and Test Pin Description Table 11-1. Debug and Test Pin List Pin Name Function Type Active Level Input/Output Low Input High Low Reset/Test NRST Microcontroller Reset TST Test Mode Select ICE and JTAG NTRST Test Reset Signal Input TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select Input JTAGSEL JTAG Selection Input Output SWD SWCLK Serial Debug Clock SWDIO Serial Debug IO Input Input/Output Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 56 11.6 Functional Description 11.6.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 11.6.2 EmbeddedICE The Cortex-A5 EmbeddedICE-RTTM is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface.The internal state of the Cortex-A5 is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a storemultiple (STM) can be inserted into the instruction pipeline. This exports the contents of the Cortex-A5 registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the Cortex-A5 processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the ARM document: ARM IHI 0031A_ARM_debug_interface_v5.pdf 11.6.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel Cortex-A5-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. 11.6.4 Chip Access Using JTAG Connection In some cases, the JTAG connection is not allowed on this chip (JMem, SAM-BA, etc.) due to the Secure ROM Code implementation. By default, the SAMA5D3 devices boot in Standard mode and not in Secure mode. When the Secure ROM Code starts, it disables the JTAG access for the whole boot sequence. If the Secure ROM Code does not find any program in the external memory, it enables the USB connection and waits for a dedicated command to switch the chip into Secure mode. If any other character is received, the Secure ROM Code starts the Standard SAM-BA Monitor, locks access to the ROM memory, and enables the JTAG. Then you can access to the chip using the JTAG connection. If the Secure ROM Code finds a bootable program, it disables automatically ROM access and enables JTAG just before launching the program. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 57 The procedure to enable JTAG access is as follows: Connect your computer to the board with JTAG and USB (J20 USB-A) Power on the chip Open a terminal console (TeraTerm or HyperTerminal, etc.) on your computer and connect to the USB CDC Serial COM port related to the J20 connector on the board Send the '#' character. You will see then the prompt '>' character sent by the device (indicating that the Standard SAM-BA Monitor is running) Use the Standard SAM-BA Monitor to connect to the chip with JTAG Note that you don't need to follow this sequence in order to connect the Standard SAM-BA Monitor with USB. 11.6.5 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. For further details on the Debug Unit, see the Debug Unit section. 11.6.6 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 58 11.7 The Boundary JTAG ID Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 * VERSION[31:28]: Product Version Number Set to 0x0. * PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B31 * MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B3_103F. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 59 11.8 The Cortex-A5 DP Identification Code Register IDCODE The Identification Code Register is always present on all DP implementations. It provides identification information about the ARM Debug Interface. 11.8.1 JTAG Debug Port (JTAG-DP) It is accessed using its own scan chain, the JTAG-DP Device ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 9 8 PART NUMBER 15 14 13 12 11 10 PART NUMBER 7 6 DESIGNER 5 4 3 2 1 DESIGNER 0 1 * VERSION[31:28]: Product Version Number Set to 0x0. * PART NUMBER[27:12]: Product Part Number Product part Number is 0xBA00 * DESIGNER[11:1] Set to 0x23B. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. Cortex-A5 JTAG-DP IDCODE value is 0x0BA0_0477 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 60 11.8.2 Serial Wire Debug Port (SW-DP) It is at address 0x0 on read operations when the APnDP bit = 0. Access to the Identification Code Register is not affected by the value of the CTRLSEL bit in the Select Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 9 8 PART NUMBER 15 14 13 12 11 10 PART NUMBER 7 6 DESIGNER 5 4 3 2 1 DESIGNER 0 1 * VERSION[31:28]: Product Version Number Set to 0x0. * PART NUMBER[27:12]: Product Part Number Product part Number is 0xBA01 * DESIGNER[11:1] Set to 0x23B. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. Cortex-A5 SW-DP IDCODE is 0x0BA0_1477 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 61 12. Standard Boot Strategies The system always boots from the ROM memory at address 0x0. The ROM Code is a boot program contained in the embedded ROM. It is also called "First level bootloader". This microcontroller can be configured to run a Standard Boot Mode or a Secure Boot Mode. More information on how the Secure Boot Mode can be enabled, and how the chip operates in this mode, is provided in the application note "Secure Boot on SAMAD3 Series", literature number 11165A. Please refer to the Atmel web site at www.atmel.com. By default, the chip starts in Standard Boot Mode. Note: JTAG access is disabled during the execution of ROM Code Sequence. It is re-enabled when jumping into SRAM when a valid code has been found on an external NVM, in the same time the ROM memory is hidden. If no valid boot has been found on an external NVM, the ROM Code enables the USB connection and waits for a special command to set the chip in Secure mode. If any other character is received, the ROM Code starts the Standard SAM-BA Monitor, locks access to the ROM memory and re-enables the JTAG. The user can choose to boot from an external NOR Flash memory with the help of the BMS pin. The sampling of the BMS pin is done by hardware at reset, and the result is available in the BMS_EBI bit of the SFR_EBICFG register. The first steps of the ROM Code program is to check the state of this pin by reading this register. If BMS signal is tied to 0, BMS_BIT is read at 1 The ROM Code allows execution of the code contained into the memory connected to Chip Select 0 of the External Bus Interface. To achieve that, the following sequence is preformed by the ROM Code: The main clock is the on-chip 12 MHz RC oscillator The Static Memory Controller is configured with timing allowing code execution inCS0 external memory at 12 MHz AXI matrix is configured to remap EBI CS0 address at 0x0 0x0 is loaded in the Program Counter register The user software in the external memory must perform the next operation in order to complete the clocks and SMC timings configuration to run at a higher clock frequency: Enable the 32768 Hz oscillator if best accuracy is needed Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock Program the PMC (Main Oscillator Enable or Bypass mode) Program and Start the PLL Switch the system clock to the new value If BMS signal is tied to 1, BMS_BIT is read at 0 The ROM Code standard sequence is executed as follows: Basic chip initialization: crystal or external clock frequency detection Attempt to retrieve a valid code from external non-volatile memories (NVM) Execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 62 12.1 Flow Diagram The ROM Code implements the algorithm shown in Figure 12-1. Figure 12-1. ROM Code Algorithm Flow Diagram Chip Setup Valid boot code found in one NVM Yes Copy and run it in internal SRAM No SAM-BA Monitor 12.2 Chip Setup At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz fast RC oscillator. Initialization follows the steps described below: 1. Stack Setup for ARM supervisor mode 2. Main Oscillator Detection: The Main Clock is switched to the 32 kHz RC oscillator to allow external clock frequency to be measured. Then the Main Oscillator is enabled and set in the bypass mode. If the MOSCSELS bit rises, an external clock is connected, and the next step is Main Clock Selection (3). If not, the bypass mode is cleared to attempt external quartz detection. This detection is successful when the MOSCXTS and MOSCSELS bits rise, else the internal 12 MHz fast RC oscillator is used as the Main Clock. 3. Main Clock Selection: The Master Clock source is switched from the Slow Clock to the Main Oscillator without prescaler. The PMC Status Register is polled to wait for MCK Ready. PCK and MCK are now the Main Clock. 4. C Variable Initialization: Non zero-initialized data is initialized in the RAM (copy from ROM to RAM). Zero-initialized data is set to 0 in the RAM. 5. PLLA Initialization: PLLA is configured to get a PCK at 96 MHz and an MCK at 48 MHz. If an external clock or crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz fast RC oscillator, but USB will not be activated. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 63 12.3 NVM Boot 12.3.1 NVM Boot Sequence The boot sequence on external memory devices can be controlled using the Boot Sequence Configuration Register (BSC_CR). The user can then choose to bypass some steps shown in Figure 12-2 "NVM Bootloader Sequence Diagram" according to the BOOT value in the BSC_CR. Table 12-1. Values of the Boot Sequence Configuration Register BOOT Value SPI0 NPCS0 SD Card / eMMC (MCI0) SD Card / eMMC (MCI1) 8-bit NAND Flash SPI0 NPCS1 TWI EEPROM SAM-BA Monitor 0 Y Y Y Y Y Y Y 1 Y -- Y Y Y Y Y 2 Y -- -- Y Y Y Y 3 Y -- -- -- Y Y Y 4 Y -- -- -- Y Y Y 5 -- -- -- -- -- -- Y 6 -- -- -- -- -- -- Y 7 -- -- -- -- -- -- Y SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 64 Figure 12-2. NVM Bootloader Sequence Diagram Device Setup SPI0 CS0 Flash Boot Yes Copy from SPI Flash to SRAM Run SPI Flash Bootloader Yes Copy from SD Card to SRAM Run SD Card Bootloader Yes Copy from NAND Flash to SRAM Run NAND Flash Bootloader Yes Copy from SPI Flash to SRAM Run SPI Flash Bootloader Yes Copy from TWI EEPROM to SRAM Run TWI EEPROM Bootloader No SD Card Boot No NAND Flash Boot No SPI0 CS1 Flash Boot No TWI EEPROM Boot No SAM-BA Monitor SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 65 12.3.2 NVM Bootloader Program Description Figure 12-3. NVM Bootloader Program Diagram Start Initialize NVM Initialization OK ? No Restore the reset values for the peripherals and Jump to next boot solution Yes Valid code detection in NVM NVM contains valid code No Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. Perform the REMAP and set the PC to 0 to jump to the downloaded application End SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 66 The NVM bootloader program first initializes the PIOs related to the NVM device. Then it configures the right peripheral depending on the NVM and tries to access this memory. If the initialization fails, it restores the reset values for the PIO and the peripheral, and then tries to fulfill the same operations on the next NVM of the sequence. If the initialization is successful, the NVM bootloader program reads the beginning of the NVM and determines if the NVM contains a valid code. If the NVM does not contain a valid code, the NVM bootloader program restores the reset value for the peripherals and then tries to fulfill the same operations on the next NVM of the sequence. If a valid code is found, this code is loaded from the NVM into the internal SRAM and executed by branching at address 0x0000_0000 after remap. This code may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. Figure 12-4. Remap Action after Download Completion 0x0000_0000 0x0000_0000 REMAP Internal ROM Internal SRAM 0x0010_0000 0x0010_0000 Internal ROM Internal ROM 0x0030_0000 0x0030_0000 Internal SRAM Internal SRAM 12.3.3 Valid Code Detection There are two kinds of valid code detection. 12.3.3.1 ARM Exception Vectors Check The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM instructions for either branch or load PC with PC relative addressing. Figure 12-5. LDR Opcode 31 1 28 27 1 1 0 0 24 23 1 I P U 20 19 1 W 0 16 15 Rn 12 11 Rd 0 Offset Figure 12-6. B Opcode 31 1 28 27 1 1 0 1 24 23 0 1 0 0 Offset (24 bits) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 67 Unconditional instruction: 0xE for bits 31 to 28. Load PC with the PC relative addressing instruction: Rn = Rd = PC = 0xF I==0 (12-bit immediate value) P==1 (pre-indexed) U offset added (U==1) or subtracted (U==0) W==1 The sixth vector, at the offset 0x14, contains the size of the image to download. The user must replace this vector with the user's own vector. This procedure is described below. Figure 12-7. Structure of the ARM Vector 6 31 0 Size of the code to download in bytes The value has to be smaller than 64 Kbytes. Example An example of valid vectors: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B0x20 B0x04 B_main B0x0c B0x10 B0x14<- Code size = 4660 bytes B0x18 12.3.3.2 boot.bin File Check This method is the one used on FAT formatted SD Card and eMMC. The boot program must be a file named "boot.bin" written in the root directory of the file system. Its size must not exceed the maximum size allowed: 64 Kbytes (0x10000). 12.3.4 Detailed Memory Boot Procedures 12.3.4.1 NAND Flash Boot: NAND Flash Detection After the NAND Flash interface configuration, a reset command is sent to the memory. Hardware ECC detection and correction are provided by the PMECC peripheral. Please refer to the "PMECC Controller Functional Description" section of this datasheet for more details. The Boot Program is able to retrieve NAND Flash parameters and ECC requirements using two methods as follows: The detection of a specific header written at the beginning of the first page of the NAND Flash, or Note: Through the ONFI parameters for the ONFI compliant memories Booting on 16-bit NAND Flash is not possible; only 8-bit NAND Flash memories are supported. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 68 Figure 12-8. Boot NAND Flash Download Start Initialize NAND Flash interface Send Reset command No First page contains valid header Yes NAND Flash is ONFI Compliant No Yes Read NAND Flash and PMECC parameters from the header Read NAND Flash and PMECC parameters from the ONFI Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. Perform the REMAP and set the PC to 0 to jump to the downloaded application End Restore the reset values for the peripherals and Jump to next bootable memory SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 69 NAND Flash Specific Header Detection This is the first method used to determine NAND Flash parameters. After Initialization and Reset command, the Boot Program reads the first page without an ECC check, to determine if the NAND parameter header is present. The header is made of 52 times the same 32-bit word (for redundancy reasons) which must contain NAND and PMECC parameters used to correctly perform the read of the rest of the data in the NAND. This 32-bit word is described below: 31 30 29 28 23 22 27 26 - key 21 20 25 19 18 17 eccOffset 15 14 13 6 12 11 10 9 8 1 0 spareSize 5 4 spareSize Note: 16 sectorSize eccBitReq 7 24 eccOffset 3 2 nbSectorPerPage usePmecc Booting on 16-bit NAND Flash is not possible; only 8-bit NAND Flash memories are supported. * usePmecc: Use PMECC 0: Do not use PMECC to detect and correct the data 1: Use PMECC to detect and correct the data * nbSectorPerPage: Number of Sectors per Page * spareSize: Size of the Spare Zone in Bytes * eccBitReq: Number of ECC Bits Required 0: 2-bit ECC 1: 4-bit ECC 2: 8-bit ECC 3: 12-bit ECC 4: 24-bit ECC * sectorSize: Size of the ECC Sector 0: For 512 bytes 1: For 1024 bytes per sector Other value for future use. * eccOffset: Offset of the First ECC Byte in the Spare Zone A value below 2 is not allowed and will be considered as 2. * key: Value 0xC Must be Written here to Validate the Content of the Whole Word. If the header is valid, the Boot Program continues with the detection of a valid code. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 70 ONFI 2.2 Parameters In case no valid header is found, the Boot Program checks if the NAND Flash is ONFI compliant, sending a Read Id command (0x90) with 0x20 as parameter for the address. If the NAND Flash is ONFI compliant, the Boot Program retrieves the following parameters with the help of the Get Parameter Page command: Number of bytes per page (byte 80) Number of bytes in spare zone (byte 84) Number of ECC bit correction required (byte 112) ECC sector size: by default, set to 512 bytes; or to 1024 bytes if the ECC bit capability above is 0xFF By default, the ONFI NAND Flash detection will turn ON the usePmecc parameter, and the ECC correction algorithm is automatically activated. Once the Boot Program retrieves the parameter, using one of the two methods described above, it reads the first page again, with or without ECC, depending on the usePmecc parameter. Then it looks for a valid code programmed just after the header offset 0xD0. If the code is valid, the program is copied at the beginning of the internal SRAM. Note: Booting on 16-bit NAND Flash is not possible; only 8-bit NAND Flash memories are supported. 12.3.4.2 NAND Flash Boot: PMECC Error Detection and Correction NAND Flash boot procedure uses PMECC to detect and correct errors during NAND Flash read operations in two cases: When the usePmecc flag is set in a specific NAND header. If the flag is not set, no ECC correction is performed during the NAND Flash page read. When the NAND Flash has been detected using ONFI parameters. The ROM memory embeds the Galois field tables. The user does not need to embed them in his own software. The Galois field tables are mapped in the ROM just after the ROM code, as described in Figure 12-9. Figure 12-9. Galois Field Table Mapping 0x0010_0000 0x0010_0000 ROM Code Code ROM 0x0010_8000 0x0010_8000 0x0011_0000 0x0011_0000 Galois field field Galois tables for for tables 512-byte 512-byte sectors sectors correction correction Galois field field Galois tables for for tables 1024-byte 1024-byte sectors sectors correction correction For a full description and an example of how to use the PMECC detection and correction feature, refer to the software package dedicated to this device on Atmel's web site. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 71 12.3.4.3 SD Card / eMMC Boot The SD Card / eMMC bootloader looks for a "boot.bin" file in the root directory of a FAT12/16/32 file system. Supported SD Card Devices SD Card Boot supports all SD Card memories compliant with the SD Memory Card Specification V2.0. This includes SDHC cards. 12.3.4.4 SPI Flash Boot Two types of SPI Flash are supported: SPI Serial Flash and SPI DataFlash. The SPI Flash bootloader tries to boot on SPI0, first looking for SPI Serial Flash, and then for SPI DataFlash. It uses only one valid code detection: analysis of ARM exception vectors. The SPI Flash read is done by means of a Continuous Read command from the address 0x0. This command is 0xE8 for DataFlash and 0x0B for Serial Flash devices. Supported DataFlash Devices The SPI Flash Boot program supports all Atmel DataFlash devices. Table 12-2. DataFlash Device Device Density Page Size (bytes) Number of Pages AT45DB011 1 Mbit 264 512 AT45DB021 2 Mbits 264 1024 AT45DB041 4 Mbits 264 2048 AT45DB081 8 Mbits 264 4096 AT45DB161 16 Mbits 528 4096 AT45DB321 32 Mbits 528 8192 AT45DB642 64 Mbits 1056 8192 Supported Serial Flash Devices The SPI Flash Boot program supports all SPI Serial Flash devices responding correctly at both Get Status and Continuous Read commands. 12.3.4.5 TWI EEPROM Boot The TWI EEPROM Bootloader uses the TWI0. It uses only one valid code detection. It analyzes the ARM exception vectors. Supported TWI EEPROM Devices TWI EEPROM Boot supports all I2C-compatible TWI EEPROM memories using the 7-bit device address 0x50. 12.3.5 Hardware and Software Constraints The NVM drivers use several PIOs in peripheral mode to communicate with external memory devices. Care must be taken when these PIOs are used by the application. The connected devices could be unintentionally driven at boot time, and thus electrical conflicts between output pins used by the NVM drivers and the connected devices could occur. To assure the correct functionality, it is recommended to plug in critical devices to other pins, not used by the NVM. Table 12-3 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 72 Before performing the jump to the application in the internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 12-3. PIO Driven during Boot Program Execution NVM Bootloader Peripheral Pin PIO Line EBI CS3 SMC NANDOE -- EBI CS3 SMC NANDWE -- EBI CS3 SMC NANDCS -- EBI CS3 SMC NAND ALE -- EBI CS3 SMC NAND CLE -- EBI CS3 SMC Cmd/Addr/Data -- MCI0 MCI0_CK PIOD9 MCI0 MCI0_CDA PIOD0 MCI0 MCI0_D0 PIOD1 MCI0 MCI0_D1 PIOD2 MCI0 MCI0_D2 PIOD3 MCI0 MCI0_D3 PIOD4 MCI1 MCI1_CK PIOB24 MCI1 MCI1_CDA PIOB19 MCI1 MCI1_D0 PIOB20 MCI1 MCI1_D1 PIOB21 MCI1 MCI1_D2 PIOB22 MCI1 MCI1_D3 PIOB23 SPI0 MOSI PIOD11 SPI0 MISO PIOD10 SPI0 SPCK PIOD12 SPI0 NPCS0 PIOD13 SPI0 NPCS1 PIOD14 TWI0 TWD0 PIOA30 TWI0 TWCK0 PIOA31 DBGU DRXD PIOB30 DBGU DTXD PIOB31 NAND SD Card / eMMC SPI Flash TWI0 EEPROM SAM-BA Monitor SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 73 12.4 SAM-BA Monitor If no valid code is found in the NVM during the NVM bootloader sequence, the SAM-BA Monitor program is launched. The SAM-BA Monitor principle is to: Initialize DBGU and USB Check if USB Device enumeration occurred Check if characters are received on the DBGU Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in Table 12-4. Figure 12-10.SAM-BA Monitor Diagram No valid code in NVM Init DBGU and USB No USB Enumeration Successful ? No Character(s) received on DBGU ? Yes Yes Run monitor Wait for command on the DBGU link Run monitor Wait for command on the USB link 12.4.1 Command List Table 12-4. Commands Available through the SAM-BA Monitor Command Action Argument(s) Example N Set Normal Mode No argument N# T Set Terminal Mode No argument T# O Write a byte Address, Value# O200001,CA# o Read a byte Address,# o200001,# H Write a half word Address, Value# H200002,CAFE# h Read a half word Address,# h200002,# W Write a word Address, Value# W200000,CAFEDECA# w Read a word Address,# w200000,# S Send a file Address,# S200000,# R Receive a file Address, NbOfBytes# R200000,1234# G Go Address# G200200# V Display version No argument V# SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 74 Note: Mode commands: Normal mode configures SAM-BA Monitor to send / receive data in binary format, Terminal mode configures SAM-BA Monitor to send / receive data in ASCII format. Write commands: Write a byte (O), a halfword (H) or a word (W) to the target Address: Address in hexadecimal Value: Byte, halfword or word to write in hexadecimal Output: `>' Read commands: Read a byte (o), a halfword (h) or a word (w) from the target Address: Address in hexadecimal Output: The byte, halfword or word read in hexadecimal followed by `>' Send a file (S): Send a file to a specified address Address: Address in hexadecimal Output: `>' There is a time-out on this command which is reached when the prompt `>' appears before the end of the command execution. Receive a file (R): Receive data into a file from a specified address Address: Address in hexadecimal NbOfBytes: Number of bytes in hexadecimal to receive Output: `>' Go (G): Jump to a specified address and execute the code Address: Address to jump in hexadecimal Output: `>' once returned from the program execution. If the executed program does not handle the link register at its entry and does not return, the prompt will not be displayed Get Version (V): Return the Boot Program version Output: version, date and time of ROM code followed by `>' 12.4.2 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115,200 Baud, 8 bits of data, no parity, 1 stop bit. 12.4.2.1 Supported External Crystal/External Clocks The SAM-BA Monitor supports a frequency of 12, 16, 24 or 48 MHz to allow DBGU communication for both external crystal and external clock. 12.4.2.2 Xmodem Protocol The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory in order to work. The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC16 to guarantee detection of maximum bit errors. Xmodem protocol with CRC is supported by successful transmission reports provided both by a sender and by a receiver. Each transfer block is as follows: <SOH><blk #><255-blk #><--128 data bytes--><checksum> in which: <SOH> = 01 hex <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) <255-blk #> = 1's complement of the blk#. <checksum> = 2 bytes CRC16 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 75 Figure 12-11 shows a transmission using this protocol. Figure 12-11.Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 12.4.3 USB Device Port 12.4.3.1 Supported External Crystal / External Clocks The SAM-BA Monitor supports a frequency of 12, 16, 24 or 48 MHz to allow USB communication for both external crystal and external clock. 12.4.3.2 USB Class The device uses the USB Communication Device Class (CDC) drivers to take advantage of the installed PC Serial Communication software to talk over the USB. The CDC class is implemented in all releases of Windows(R), from Windows 98SE(R) to Windows 7(R). The CDC document, available at www.usb.org, describes how to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is the Atmel's vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, INF files contain the correspondence between vendor ID and product ID. 12.4.3.3 Enumeration Process The USB protocol is a master/slave protocol. The host starts the enumeration, sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 12-5. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value SET_ADDRESS Sets the device address for all future device access SET_CONFIGURATION Sets the device configuration GET_CONFIGURATION Returns the current device configuration value GET_STATUS Returns status for the specified recipient SET_FEATURE Used to set or enable a specific feature CLEAR_FEATURE Used to clear or disable a specific feature SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 76 The device also handles some class requests defined in the CDC class. Table 12-6. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits SET_CONTROL_LINE_STATE RS-232 signal used to indicate to the DCE device that the DTE device is now present Unhandled requests are STALLed. 12.4.3.4 Communication Endpoints Endpoint 0 is used for the enumeration process. Endpoint 1 (64-byte Bulk OUT) and endpoint 2 (64-byte Bulk IN) are used as communication endpoints. SAM-BA Boot commands are sent by the host through Endpoint 1. If required, the message is split into several data payloads by the host driver. If the command requires a response, the host sends IN transactions to pick up the response. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 77 13. Boot Sequence Controller (BSC) 13.1 Description The System Controller embeds a Boot Sequence Configuration Register (BSC_CR) to save timeout delays on boot. The boot sequence is programmable through the BSC_CR. The BSC_CR is powered by VDDBU. Any modification of the register value is stored and applied after the next reset. The register defaults to the factory value in case of battery removal. The BSC_CR is programmable with user programs or SAM-BA and is key-protected. 13.2 Embedded Characteristics 13.3 VDDBU powered register Product Dependencies Product-dependent order SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 78 13.4 Boot Sequence Controller (BSC) Registers User Interface Table 13-1. Register Mapping Offset 0x0 Register Name Boot Sequence Configuration Register BSC_CR Access Reset Read-write - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 79 13.4.1 Boot Sequence Configuration Register Name: BSC_CR Address: 0xFFFFFE54 Access: Read-write Factory Value: 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 - 10 - 9 - 8 - 3 2 1 0 WPKEY 23 22 21 20 WPKEY 15 - 14 - 13 - 12 - 7 6 5 4 BOOT * BOOT: Boot media sequence This value is defined in the product-dependent ROM code. It is only written if WPKEY carries the valid value. * WPKEY: Write Protect Key (Write-only) Value Name 0x6683 PASSWD Description Writing any other value in this field aborts the write operation of the BOOT field. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 80 14. AXI Bus Matrix (AXIMX) 14.1 Description The AXI Bus Matrix (AXIMX) comprises the embedded Advanced EXtensible Interface (AXI) bus protocol which supports separate address/control and data phases, unaligned data transfers using byte strobes, burst-based transactions with only start address issued, separate read and write data channels to enable low-cost DMA, ability to issue multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to provide timing closure. 14.2 Embedded Characteristics High Performance AXI Network Interconnect 1 AXI Slave Interface 1 AHB-Lite Slave Interface 3 AXI Master Interfaces 1 APB3 Slave Interface Single-cycle Arbitration Full Pipelining to prevent Master Stalls 2 Remap States SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 81 14.3 Operation 14.3.1 Remap There are two remap states using bits 0 and 1 in the Remap Register (AXIMX_REMAP) Bit 1 is used to remap EBI @ addr 0x00000000 for external boot. Bit 0 is used to remap RAM @ addr 0x00000000 Refer to Section 14.4 "AXI Matrix (AXIMX) User Interface" and Table 14-1, "Register Mapping". The number of remap states can be defined using eight bits of the remap register, and a bit in the remap register controls each remap state. Each remap state can be used to control the address decoding for one or more slave interfaces. If a slave interface is affected by two remap states that are both asserted, the remap state with the lowest remap bit number takes precedence. Each slave interface can be configured independently so that a remap state can perform different functions for different masters. A remap state can: Alias a memory region into two different address ranges Move an address region Remove an address region Because of the nature of the distributed register sub-system, the masters receive the updated remap bit states in sequence, and not simultaneously. A slave interface does not update to the latest remap bit setting until: The address completion handshake accepts any transaction that is pending Any current lock sequence completes The BRESP from a GPV after a remap update guarantees that the next transaction issued to each slave interface, or the first one after the completion of a locked sequence, uses the updated value. The AXI Matrix uses two remap bits. At powerup, ROM is seen at address 0 After powerup, ahbslave can be moved down to address 0 by means of the remap bits. Figure 14-1 shows the memory map when remap is set to 000, representing no remap, SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 82 Figure 14-1. No Remap 0x00000000 ROM 0x000FFFFF 0x00100000 0x001FFFFF 0x00200000 0x002FFFFF 0x00300000 0x0007FFFFF 0x00800000 0x008FFFFF 0x00900000 0x09FFFFF 0x0A00000 0x001FFFFF 0x01000000 0x01FFFFFF 0x20000000 0x3FFFFFFF 0x40000000 ROM ahbslave ahbslave gpv_0 dap [apb3bridge] reserved ahbslave MPDDR ahbslave 0x7FFFFFFF 0x80000000 0xEFFFFFFF 0xF0000000 reserved ahbslave 0xFFFFFFFF Figure 14-2 shows mapping when remap state is 01 or 11. This state is used for RAM boot. RAM is seen at address 0 through ahbslave. Figure 14-2. Remap state is 01 or 11 0x00000000 ahbslave (RAM) 0x000FFFFF 0x00100000 0x001FFFFF 0x00200000 0x002FFFFF 0x00300000 0x0007FFFFF 0x00800000 ROM ahbslave ahbslave gpv_0 0x008FFFFF 0x00900000 0x09FFFFF 0x0A00000 0x001FFFFF 0x01000000 0x01FFFFFF 0x20000000 0x3FFFFFFF 0x40000000 dap [apb3bridge] reserved ahbslave MPDDR ahbslave 0x7FFFFFFF 0x80000000 0xEFFFFFFF 0xF0000000 0xFFFFFFFF reserved ahbslave Figure 14-3 shows mapping when remap state is 10. This state is used for external boot. EBI is seen at address 0 through ahbslave. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 83 Figure 14-3. Remap State is 10 0x00000000 ahbslave (EBI) 0x000FFFFF 0x00100000 0x001FFFFF 0x00200000 0x002FFFFF 0x00300000 0x0007FFFFF 0x00800000 ROM ahbslave ahbslave gpv_0 0x008FFFFF 0x00900000 0x009FFFFF 0x00A00000 0x001FFFFF 0x01000000 0x01FFFFFF 0x20000000 0x3FFFFFFF 0x40000000 dap[apb3bridge] reserved ahbslave MPDDR ahbslave 0x7FFFFFFF 0x80000000 0xEFFFFFFF 0xF0000000 0xFFFFFFFF reserved ahbslave SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 84 14.4 AXI Matrix (AXIMX) User Interface Table 14-1. Register Mapping Offset Register Name 0x00 Remap Register AXIMX_REMAP 0x04 - 0x43108 Reserved - Access Reset Write-only 0x00000000 - 0x00000000 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 85 14.4.1 AXI Matrix Remap Register Name: AXIMX_REMAP Address: 0x00800000 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 - - 1 REMAP1 0 REMAP0 - 23 22 21 20 - 15 14 13 12 - 7 - 6 - 5 - 4 - REMAP0 has higher priority than REMAP1, i.e., if both REMAP0 & REMAP1 are asserted, the matrix is in remap state 0. * REMAP0: Remap State 0 SRAM is seen at address 0x00000000 (through AHB slave interface) instead of ROM. * REMAP1: Remap State 1 HEBI is seen at address 0x00000000 (through AHB slave interface) instead of ROM for external boot. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 86 15. Bus Matrix (MATRIX) 15.1 Description The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus. 15.1.1 Matrix Masters The Bus Matrix of the SAMA5D3 product manages 15 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. List of Bus Matrix Masters Master 0 Cortex A5 Master 1, 2, 3 DMA Controller 0 Master 4, 5, 6 DMA Controller 1 Master 7 GMAC DMA Master 8, 9 LCDC DMA Master 10 UHP EHCI DMA Master 11 UHP OHCI DMA Master 12 UDPHS DMA Master 13 EMAC DMA Master 14 ISI DMA 15.1.2 Matrix Slaves The Bus Matrix of the SAMA5 product manages 13 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 15-1. List of Bus Matrix Slaves Slave 0 Internal SRAM0 Slave 1 Internal SRAM1 Slave 2 NFC SRAM Slave 3 Internal ROM Slave 4 Soft Modem (SMD) USB Device High Speed Dual Port RAM (DPR) Slave 5 USB Host OHCI registers USB Host EHCI registers Slave 6 External Bus Interface/NFC Slave 7 DDR2 Port0 Slave 8 DDR2 Port1 Slave 9 DDR2 Port2 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 87 Table 15-1. List of Bus Matrix Slaves Slave 10 DDR2 Port3 Slave 11 Peripheral Bridge 0 Slave 12 Peripheral Bridge 1 15.1.3 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as "-" in the following table. Table 15-2. SAMA5 Master to Slave Access Masters Slaves 0 1 A5 2 3 DMAC0 4 5 6 7 GMAC DMA DMAC1 8 9 LCDC DMA 10 11 12 13 14 UHPHS EHCI DMA UHPHS OHCI DMA UDPHS DMA EMAC DMA ISI DMA 0 Internal SRAM0 X X X X X X X X 1 Internal SRAM1 X X X X X X X X 2 NFC SRAM X X 3 Internal ROM X X X X X 4 SMD X X X X X X X X X X UDPHS RAM 5 UHP OHCI Reg X UHP EHCI Reg EBI CS0..CS3 X NFC Command Register X 7 DDR2 Port 0 X 8 DDR2 port1 9 DDR2 port2 10 DDR2 port3 11 APB 0 X 12 APB 1 X 6 X X X X X X X X X X X X X X X X X SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 88 15.2 Embedded Characteristics AMBA Advanced High-performance Bus (AHB Lite) Compliant Interfaces 32-bit or 64-bit Data Bus APB Compliant User Interface Configurable Number of Masters (Up to sixteen) Configurable Number of Slaves (Up to sixteen) One Decoder for Each Master Several Possible Boot Memories for Each Master before Remap One Remap Function for Each Master Support for Long Bursts of 32, 64, 128 and Up to the 256-beat Word Burst AHB Limit Enhanced Programmable Mixed Arbitration for Each Slave Round-Robin Fixed Priority Programmable Default Master for Each Slave No Default Master Last Accessed Default Master Fixed Default Master Deterministic Maximum Access Latency for Masters Zero or One Cycle Arbitration Latency for the First Access of a Burst Bus Lock Forwarding to Slaves Master Number Forwarding to Slaves One Special Function Register for Each Slave (Not dedicated) Write Protection of User Interface Registers SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 89 15.3 Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. Each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR), that performs remap action for every master independently. The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap action for every master independently. 15.4 Special Bus Granting Mechanism The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from masters. This mechanism reduces latency at first access of a burst, or for a single transfer, as long as the slave is free from any other master access. It does not provide any benefit if the slave is continuously accessed by more than one master, since arbitration is pipelined and has no negative effect on the slave bandwidth or access latency. This bus granting mechanism sets a different default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: No default master Last access master Fixed default master To change from one type of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for every slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to Section 15.10.2 "Bus Matrix Slave Configuration Registers" on page 97. 15.5 No Default Master After the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without default master may be used for masters that perform significant bursts or several transfers with no Idle in between, or if the slave bus bandwidth is widely used by one or more masters. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever the number of requesting masters. 15.6 Last Access Master After the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 90 15.7 Fixed Default Master After the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike the last access master, the fixed default master does not change unless the user modifies it by software (FIXED_DEFMSTR field of the related MATRIX_SCFG). This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-privileged masters will get one latency cycle. This technique is useful for a master that mainly performs single accesses or short bursts with Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, regardless of the number of requesting masters. 15.8 Arbitration The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each slave specifically. The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or mixing them for each slave: 1. Round-robin Arbitration (default) 2. Fixed Priority Arbitration The resulting algorithm may be complemented by selecting a default master configuration for each slave. When re-arbitration must be done, specific conditions apply. See Section 15.8.1 "Arbitration Scheduling" on page 91. 15.8.1 Arbitration Scheduling Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: When a slave is currently doing a single access. 3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See "Undefined Length Burst Arbitration" on page 91 4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. See "Slot Cycle Limit Arbitration" on page 92 15.8.1.1 Undefined Length Burst Arbitration In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the following Undefined Length Burst Type (ULBT) possibilities: 1. Unlimited: no predetermined end of burst is generated. This value enables 1-kbyte burst lengths. 2. 1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer. 3. 4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer. 4. 8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer. 5. 16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR transfer. 6. 32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR transfer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 91 7. 64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR transfer. 8. 128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR transfer. The use of undefined length16-beat bursts, or less, is discouraged since this generally decreases significantly the overall bus bandwidth due to arbitration and slave latencies at each first access of a burst. If the master does not permanently and continuously request the same slave or has an intrinsically limited average throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kbyte address boundaries. Unless duly needed, the ULBT should be left at its default value of 0 for power saving. This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG). 15.8.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At each arbitration time, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access cycle. Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by some Atmel masters. In most cases, this feature is not needed and should be disabled for power saving. Warning: This feature cannot prevent any slave from locking its access indefinitely. 15.8.2 Arbitration Priority Scheme The bus Matrix arbitration scheme is organized in priority pools. Round-robin priority is used in the highest and lowest priority pools, whereas fixed level priority is used between priority pools and in the intermediate priority pools. For each slave, each master is assigned to one of the slave priority pools through the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating master requests, this programmed priority level always takes precedence. After reset, all the masters belong to the lowest priority pool (MxPR = 0) and are therefore granted bus access in a true round-robin order. The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight and deterministic maximum access latency from AHB bus requests. In the worst case, any currently occurring high-priority master request will be granted after the current bus master access has ended and other high priority pool master requests, if any, have been granted once each. The lowest priority pool shares the remaining bus bandwidth between AHB Masters. Intermediate priority pools allow fine priority tuning. Typically, a moderately latency-critical master or a bandwidth-only critical master will use such a priority level. The higher the priority level (MxPR value), the higher the master priority. All combinations of MxPR values are allowed for all masters and slaves. For example, some masters might be assigned the highest priority pool (round-robin), and remaining masters the lowest priority pool (round-robin), with no master for intermediate fix priority levels. If more than one master requests the slave bus, regardless of the respective masters priorities, no master will be granted the slave bus for two consecutive runs. A master can only get back-to-back grants so long as it is the only requesting master. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 92 15.8.2.1 Fixed Priority Arbitration Fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority pools). Fixed priority arbitration allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the MxPR field for each master in the Priority Registers, MATRIX_PRAS and MATRIX_PRBS. If two or more master requests are active at the same time, the master with the highest priority MxPR number is serviced first. In intermediate priority pools, if two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first. 15.8.2.2 Round-Robin Arbitration This algorithm is only used in the highest and lowest priority pools. It allows the Bus Matrix arbiters to properly dispatch requests from different masters to the same slave. If two or more master requests are active at the same time in the priority pool, they are serviced in a round-robin increasing master number order. 15.9 Write Protect Registers To prevent any single software error that may corrupt the Bus Matrix behavior, the entire Bus Matrix address space can be write-protected by setting the WPEN bit in the Bus Matrix Write Protect Mode Register (MATRIX_WPMR). If WPEN is at one and a write access in the Bus Matrix address space is detected, then the WPVS flag in the Bus Matrix Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the Bus Matrix Write Protect Mode Register (MATRIX_WPMR) with the appropriate access key WPKEY. The protected registers are: "Bus Matrix Master Configuration Registers" "Bus Matrix Slave Configuration Registers" "Bus Matrix Priority Registers A For Slaves" "Bus Matrix Priority Registers B For Slaves" "Bus Matrix Master Remap Control Register" SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 93 15.10 Bus Matrix (MATRIX) User Interface Table 15-3. Register Mapping Offset Register Name Access Reset 0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read-write 0x00000001 0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read-write 0x00000000 0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read-write 0x00000000 0x000C Master Configuration Register 3 MATRIX_MCFG3 Read-write 0x00000000 0x0010 Master Configuration Register 4 MATRIX_MCFG4 Read-write 0x00000000 0x0014 Master Configuration Register 5 MATRIX_MCFG5 Read-write 0x00000000 0x0018 Master Configuration Register 6 MATRIX_MCFG6 Read-write 0x00000000 0x001C Master Configuration Register 7 MATRIX_MCFG7 Read-write 0x00000000 0x0020 Master Configuration Register 8 MATRIX_MCFG8 Read-write 0x00000000 0x0024 Master Configuration Register 9 MATRIX_MCFG9 Read-write 0x00000000 0x0028 Master Configuration Register 10 MATRIX_MCFG10 Read-write 0x00000000 0x002C Master Configuration Register 11 MATRIX_MCFG11 Read-write 0x00000000 0x0030 Master Configuration Register 12 MATRIX_MCFG12 Read-write 0x00000000 0x0034 Master Configuration Register 13 MATRIX_MCFG13 Read-write 0x00000000 0x0038 Master Configuration Register 14 MATRIX_MCFG14 Read-write 0x00000000 0x003C Master Configuration Register 15 MATRIX_MCFG15 Read-write 0x00000000 0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read-write 0x000001FF 0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read-write 0x000001FF 0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read-write 0x000001FF 0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read-write 0x000001FF 0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read-write 0x000001FF 0x0054 Slave Configuration Register 5 MATRIX_SCFG5 Read-write 0x000001FF 0x0058 Slave Configuration Register 6 MATRIX_SCFG6 Read-write 0x000001FF 0x005C Slave Configuration Register 7 MATRIX_SCFG7 Read-write 0x000001FF 0x0060 Slave Configuration Register 8 MATRIX_SCFG8 Read-write 0x000001FF 0x0064 Slave Configuration Register 9 MATRIX_SCFG9 Read-write 0x000001FF 0x0068 Slave Configuration Register 10 MATRIX_SCFG10 Read-write 0x000001FF 0x006C Slave Configuration Register 11 MATRIX_SCFG11 Read-write 0x000001FF 0x0070 Slave Configuration Register 12 MATRIX_SCFG12 Read-write 0x000001FF 0x0074 Slave Configuration Register 13 MATRIX_SCFG13 Read-write 0x000001FF 0x0078 Slave Configuration Register 14 MATRIX_SCFG14 Read-write 0x000001FF 0x007C Slave Configuration Register 15 MATRIX_SCFG15 Read-write 0x000001FF 0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read-write 0x33333333(1) 0x0084 Priority Register B for Slave 0 MATRIX_PRBS0 Read-write 0x33333333(1) 0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read-write 0x33333333(1) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 94 Table 15-3. Register Mapping (Continued) Offset Register Name Access Reset 0x008C Priority Register B for Slave 1 MATRIX_PRBS1 Read-write 0x33333333(1) 0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read-write 0x33333333(1) 0x0094 Priority Register B for Slave 2 MATRIX_PRBS2 Read-write 0x33333333(1) 0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read-write 0x33333333(1) 0x009C Priority Register B for Slave 3 MATRIX_PRBS3 Read-write 0x33333333(1) 0x00A0 Priority Register A for Slave 4 MATRIX_PRAS4 Read-write 0x33333333(1) 0x00A4 Priority Register B for Slave 4 MATRIX_PRBS4 Read-write 0x33333333(1) 0x00A8 Priority Register A for Slave 5 MATRIX_PRAS5 Read-write 0x33333333(1) 0x00AC Priority Register B for Slave 5 MATRIX_PRBS5 Read-write 0x33333333(1) 0x00B0 Priority Register A for Slave 6 MATRIX_PRAS6 Read-write 0x33333333(1) 0x00B4 Priority Register B for Slave 6 MATRIX_PRBS6 Read-write 0x33333333(1) 0x00B8 Priority Register A for Slave 7 MATRIX_PRAS7 Read-write 0x33333333(1) 0x00BC Priority Register B for Slave 7 MATRIX_PRBS7 Read-write 0x33333333(1) 0x00C0 Priority Register A for Slave 8 MATRIX_PRAS8 Read-write 0x33333333(1) 0x00C4 Priority Register B for Slave 8 MATRIX_PRBS8 Read-write 0x33333333(1) 0x00C8 Priority Register A for Slave 9 MATRIX_PRAS9 Read-write 0x33333333(1) 0x00CC Priority Register B for Slave 9 MATRIX_PRBS9 Read-write 0x33333333(1) 0x00D0 Priority Register A for Slave 10 MATRIX_PRAS10 Read-write 0x33333333(1) 0x00D4 Priority Register B for Slave 10 MATRIX_PRBS10 Read-write 0x33333333(1) 0x00D8 Priority Register A for Slave 11 MATRIX_PRAS11 Read-write 0x33333333(1) 0x00DC Priority Register B for Slave 11 MATRIX_PRBS11 Read-write 0x33333333(1) 0x00E0 Priority Register A for Slave 12 MATRIX_PRAS12 Read-write 0x33333333(1) 0x00E4 Priority Register B for Slave 12 MATRIX_PRBS12 Read-write 0x33333333(1) 0x00E8 Priority Register A for Slave 13 MATRIX_PRAS13 Read-write 0x33333333(1) 0x00EC Priority Register B for Slave 13 MATRIX_PRBS13 Read-write 0x33333333(1) 0x00F0 Priority Register A for Slave 14 MATRIX_PRAS14 Read-write 0x33333333(1) 0x00F4 Priority Register B for Slave 14 MATRIX_PRBS14 Read-write 0x33333333(1) 0x00F8 Priority Register A for Slave 15 MATRIX_PRAS15 Read-write 0x33333333(1) 0x00FC Priority Register B for Slave 15 MATRIX_PRBS15 Read-write 0x33333333(1) 0x0100 Master Remap Control Register MATRIX_MRCR Read-write 0x00000000 0x0104 - 0x010C Reserved - - - 0x01A0 - 0x01E0 Reserved - - - 0x01E4 Write Protect Mode Register MATRIX_WPMR Read-write 0x00000000 0x01E8 Write Protect Status Register MATRIX_WPSR Read-only 0x00000000 Notes: 1. Values in the Bus Matrix Priority Registers are product dependent. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 95 15.10.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0...MATRIX_MCFG15 Address: 0xFFFFEC00 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - ULBT This register can only be written if the WPEN bit is cleared in the "Write Protect Mode Register" . * ULBT: Undefined Length Burst Type 0: Unlimited Length Burst No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts. This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 1: Single Access The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 2: 4-beat Burst The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 3: 8-beat Burst The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 4: 16-beat Burst The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 5: 32-beat Burst The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 6: 64-beat Burst The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 7: 128-beat Burst The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Unless duly needed, the ULBT should be left at its default 0 value for power saving. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 96 15.10.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...MATRIX_SCFG15 Address: 0xFFFFEC40 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - 15 14 13 12 11 10 9 8 - - - - - - - SLOT_CYCLE 7 6 5 4 3 2 1 0 FIXED_DEFMSTR DEFMSTR_TYPE SLOT_CYCLE This register can only be written if the WPEN bit is cleared in the "Write Protect Mode Register" . * SLOT_CYCLE: Maximum Bus Grant Duration for Masters When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place to let another master access this slave. If another master is requesting the slave bus, then the current master burst is broken. If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabled and bursts always complete unless broken according to the ULBT. This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access. This limit must not be too small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice. In most cases, this feature is not needed and should be disabled for power saving. See "Slot Cycle Limit Arbitration" on page 92 for details. * DEFMSTR_TYPE: Default Master Type 0: No Default Master At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 1: Last Default Master At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. This results in not having one clock cycle latency when the last master tries to access the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having one clock cycle latency when the fixed master tries to access the slave again. * FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 97 15.10.3 Bus Matrix Priority Registers A For Slaves Name: MATRIX_PRAS0...MATRIX_PRAS15 Address: 0xFFFFEC80 [0], 0xFFFFEC88 [1], 0xFFFFEC90 [2], 0xFFFFEC98 [3], 0xFFFFECA0 [4], 0xFFFFECA8 [5], 0xFFFFECB0 [6], 0xFFFFECB8 [7], 0xFFFFECC0 [8], 0xFFFFECC8 [9], 0xFFFFECD0 [10], 0xFFFFECD8 [11], 0xFFFFECE0 [12], 0xFFFFECE8 [13], 0xFFFFECF0 [14], 0xFFFFECF8 [15] Access: Read-write 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M7PR 21 20 M5PR 13 12 M3PR 5 4 M1PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M6PR 17 16 M4PR 9 8 M2PR 1 0 M0PR This register can only be written if the WPE bit is cleared in the "Write Protect Mode Register" . * MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2). See "Arbitration Priority Scheme" on page 92 for details. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 98 15.10.4 Bus Matrix Priority Registers B For Slaves Name: MATRIX_PRBS0...MATRIX_PRBS15 Address: 0xFFFFEC84 [0], 0xFFFFEC8C [1], 0xFFFFEC94 [2], 0xFFFFEC9C [3], 0xFFFFECA4 [4], 0xFFFFECAC [5], 0xFFFFECB4 [6], 0xFFFFECBC [7], 0xFFFFECC4 [8], 0xFFFFECCC [9], 0xFFFFECD4 [10], 0xFFFFECDC [11], 0xFFFFECE4 [12], 0xFFFFECEC [13], 0xFFFFECF4 [14], 0xFFFFECFC [15] Access: Read-write 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M15PR 21 20 M13PR 13 12 M11PR 5 4 M9PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M14PR 17 16 M12PR 9 8 M10PR 1 0 M8PR This register can only be written if the WPEN bit is cleared in the "Write Protect Mode Register" . * MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2). See "Arbitration Priority Scheme" on page 92 for details. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 99 15.10.5 Bus Matrix Master Remap Control Register Name: MATRIX_MRCR Address: 0xFFFFED00 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 RCB15 RCB14 RCB13 RCB12 RCB11 RCB10 RCB9 RCB8 7 6 5 4 3 2 1 0 RCB7 RCB6 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 This register can only be written if the WPEN bit is cleared in the "Write Protect Mode Register" . * RCB: Remap Command Bit for Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 100 15.10.6 Write Protect Mode Register Name: MATRIX_WPMR Address: 0xFFFFEDE4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 - - - - - - - WPEN For more details on MATRIX_WPMR, refer to Section 15.9 "Write Protect Registers" on page 93. The protected registers are: "Bus Matrix Master Configuration Registers" "Bus Matrix Slave Configuration Registers" "Bus Matrix Priority Registers A For Slaves" "Bus Matrix Priority Registers B For Slaves" "Bus Matrix Master Remap Control Register" * WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x4D4154 ("MAT" in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x4D4154 ("MAT" in ASCII). Protects the entire Bus Matrix address space from address offset 0x000 to 0x1FC. * WPKEY: Write Protect KEY (Write-only) Should be written at value 0x4D4154 ("MAT" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 101 15.10.7 Write Protect Status Register Name: MATRIX_WPSR Address: 0xFFFFEDE8 Access: Read-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 - - - - - - - WPVS For more details on MATRIX_WPSR, refer to Section 15.9 "Write Protect Registers" on page 93. * WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR. 1: At least one Write Protect Violation has occurred since the last write of the MATRIX_WPMR. * WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the register address offset in which a write access has been attempted. Otherwise it reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 102 16. Special Function Registers (SFR) 16.1 Description Special Function Registers (SFR) manage specific aspects of the integrated memory, bridge implementations, processor and other functionality not controlled elsewhere. 16.2 Embedded Characteristics 32-bit Special Function Registers control specific behavior of the product SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 103 16.3 Special Function Registers (SFR) User Interface Table 16-1. Register Mapping Offset Register 0x00-0x04 Reserved 0x08-0x0C Reserved Name Access Reset - - - - - - 0x10 OHCI Interrupt Configuration Register SFR_OHCIICR Read-write 0x0 0x14 OHCI Interrupt Status Register SFR_OHCIISR Read-only - 0x18 Reserved - - - 0x1C Reserved - - - 0x20-0x24 Reserved - - - Read-write 0x0 - - 0x28 Security Configuration Register SFR_SECURE 0x2C Reserved 0x30 UTMI Clock Trimming Register SFR_UTMICKTRIM Read-write 0x00010000 0x40 EBI Configuration Register SFR_EBICFG Read-write - 0x44 Reserved - - - 0x48 Reserved - - - 0x4C-0x50 Reserved - - - 0x54-0x3FFC Reserved - - - - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 104 16.3.1 OHCI Interrupt Configuration Register Name: SFR_OHCIICR Address: 0xF0038010 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 UDPPUDIS - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - APPSTART ARIE - RES2 RES1 RES0 * RESx: USB PORTx RESET 0: Resets USB PORT. 1: Usable USB PORT. * ARIE: OHCI Asynchronous Resume Interrupt Enable 0: Interrupt disabled. 1: Interrupt enabled. * APPSTART: Reserved 0: Must write 0. * UDPPUDIS: USB DEVICE PULL-UP DISABLE 0: USB device Pull-up connection is enabled. 1: USB device Pull-up connection is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 105 16.3.2 OHCI Interrupt Status Register Name: SFR_OHCIISR Address: 0xF0038014 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - RIS2 RIS1 RIS0 * RISx: OHCI Resume Interrupt Status Port x 0: OHCI Port resume not detected. 1: OHCI Port resume detected. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 106 16.3.3 APB Bridge Configuration Register Name: SFR_BRIDGE Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - AXI2AHBSEL 7 6 5 4 3 2 1 0 - - - - - - - APBTURBO * APBTURBO: AHB to APB Bridge Mode 0: AHB transaction optimization disabled. 1: AHB transaction optimization enabled. * AXI2AHBSEL: AXI to AHB Bridge for DDR Controller Selection 0 (SINGLE): Uses single port bridge. 1 (DUAL): Uses dual port bridge. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 107 16.3.4 Security Configuration Register Name: SFR_SECURE Address: 0xF0038028 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - FUSE 7 6 5 4 3 2 1 0 - - - - - - - ROM * ROM: Disable Access to ROM Code This bit is writable once only. When the ROM is secured, only reset signal can clear this bit. 0: ROM is enabled. 1: ROM is disabled. * FUSE: Disable Access to Fuse Controller This bit is writable once only. When the Fuse Controller is secured, only reset signal can clear this bit. 0: Fuse Controller is enabled. 1: Fuse Controller is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 108 16.3.5 UTMI Clock Trimming Register Name: SFR_UTMICKTRIM Address: 0xF0038030 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 1 7 6 5 4 3 2 - - - - - - 0 FREQ * FREQ: UTMI Reference Clock Frequency Value Name Description 0 12 12 MHz reference clock 1 16 16 MHz reference clock 2 24 24 MHz reference clock 3 48 48 MHz reference clock SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 109 16.3.6 EBI Configuration Register Name: SFR_EBICFG Address: 0xF0038040 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - BMS 15 14 13 12 11 10 9 - - - SCH1 7 6 5 4 - - - SCH0 PULL1 3 2 PULL0 8 DRIVE1 1 0 DRIVE0 This register controls EBI pins which are not multiplexed with PIO controller lines. DRIVE0, PULL0, SCH0 control EBI Data pins when applicable. DRIVE1, PULL1, SCH1 control other EBI pins when applicable. * DRIVEx: EBI Pins Drive Level Drive level should be programmed depending on target frequency and board characteristics. Refer to pad characteristics to set correct drive level. Value Name Description 0 LOW Low drive level 1 RESERVED Low drive level 2 MEDIUM Medium drive level 3 HIGH High drive level * PULLx: EBI Pins Pull Value Value Name Description 0 UP Pull-up 1 NONE No Pull 2 Reserved No Change (forbidden write value) 3 DOWN Pull-down * SCHx: EBI Pins Schmitt Trigger 0: Schmitt Trigger off. 1: Schmitt Trigger on. * BMS: BMS Sampled Value (Read Only) This bit examines whether boot is on EBI or ROM. 0 (ROM): Boot on ROM. 1 (EBI): Boot on EBI. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 110 17. Advanced Interrupt Controller (AIC) 17.1 Description The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to hundred and twenty-eight interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or high-level or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. 17.2 Embedded Characteristics Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM(R) Processor 128 Individually Maskable and Vectored Interrupt Sources Source 0 is Reserved for the Fast Interrupt Input (FIQ) Source 1 is Reserved for System Peripheral Interrupts Source 2 to Source 127, Control up to 126 Embedded Peripheral Interrupts or External Interrupts Programmable Edge-triggered or Level-sensitive Internal Sources Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources 8-level Priority Controller Drives the Normal Interrupt of the Processor Handles Priority of the Interrupt Sources 1 to 127 Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt Vectoring Optimizes Interrupt Service Routine Branch and Execution One 32-bit Vector Register for all Interrupt Sources Interrupt Vector Register Reads the Corresponding Current Interrupt Vector Protect Mode Easy Debugging by Preventing Automatic Operations when Protect Models are Enabled Fast Forcing Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the Processor General Interrupt Mask Write Protected Registers Provides Processor Synchronization on Events Without Triggering an Interrupt SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 111 17.3 Block Diagram Figure 17-1. Block Diagram FIQ AIC ARM Processor IRQ0-IRQn Up to 128 Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 17.4 Application Block Diagram Figure 17-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 17.5 AIC Detailed Block Diagram Figure 17-3. AIC Detailed Block Diagram Advanced Interrupt Controller FIQ PIO Controller Fast Interrupt Controller External Source Input Stage ARM Processor nFIQ nIRQ IRQ0-IRQn Embedded Peripherals Interrupt Priority Controller Fast Forcing PIOIRQ Internal Source Input Stage Processor Clock Power Management Controller User Interface Wake Up APB SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 112 17.6 I/O Line Description Table 17-1. I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0 - IRQn Interrupt 0 - Interrupt n Input 17.7 Product Dependencies 17.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. Table 17-2. I/O Lines Instance Signal I/O Line Peripheral AIC FIQ PC31 A AIC IRQ PE31 A 17.7.2 Power Management The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event. 17.7.3 Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature a FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 127 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 127. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID127. 17.8 Functional Description 17.8.1 Interrupt Source Control 17.8.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the AIC_SMR (Source Mode Register) selects the interrupt condition of the interrupt source selected by the INTSEL field of the "AIC Source Select Register". SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 113 Note: Configuration registers such as AIC_SMR, AIC_SSR, return the values corresponding to the interrupt source selected by INTSEL. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes. 17.8.1.2 Interrupt Source Enabling Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; "AIC Interrupt Enable Command Register" on page 139 and "AIC Interrupt Disable Command Register" on page 140. The interrupt mask of the selected interrupt source can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts. 17.8.1.3 Interrupt Clearing and Setting All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in levelsensitive mode has no effect. The clear operation is perfunctory, as the software must perform an action to reinitialize the "memorization" circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See "Priority Controller" on page 117.) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, see Section 17.8.4.5 "Fast Forcing"). The automatic clear of the interrupt source 0 is performed when AIC_FVR is read. 17.8.1.4 Interrupt Status AIC_IPR registers represent the state of the interrupt lines, whether they are masked or not. The AIC_IMR register permits to define the mask of the interrupt lines. The AIC_ISR register reads the number of the current interrupt (see "Priority Controller" on page 117) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. 17.8.1.5 Internal Interrupt Source Input Stage Figure 17-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear AIC_ISCR FF AIC_ICCR AIC_IDCR SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 114 17.8.1.6 External Interrupt Source Input Stage Figure 17-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg. Edge Detector Set AIC_ISCR FF Clear AIC_IDCR AIC_ICCR SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 115 17.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: The time the software masks the interrupts. Occurrence, either at the processor level or at the AIC level. The execution time of the instruction in progress when the interrupt occurs. The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 17.8.2.1 External Interrupt Edge Triggered Source Figure 17-6. External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles 17.8.2.2 External Interrupt Level Sensitive Source Figure 17-7. External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 116 17.8.2.3 Internal Interrupt Edge Triggered Source Figure 17-8. Internal Interrupt Edge Triggered Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles 17.8.2.4 Internal Interrupt Level Sensitive Source Figure 17-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 17.8.3 Normal Interrupt 17.8.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 127 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 117 indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 17.8.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is reasserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 17.8.3.3 Interrupt Vectoring The interrupt handler address corresponding to the interrupt source selected by the INTSEL field can be stored in the registers AIC_SVR (Source Vector Register). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining the AIC_SVR of the interrupt sources to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system's general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 17.8.3.4 Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits. It is assumed that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring LDR PC, [PC, # -&F20] When nIRQ is asserted, if the bit "I" of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 118 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. Automatically clears the interrupt, if it has been programmed to be edge-triggered. Pushes the current level and the current interrupt number on to the stack. Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the "I" bit in CPSR, allowing re-assertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. The "I" bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the "I" bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: The "I" bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked). 17.8.4 Fast Interrupt 17.8.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. 17.8.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR and INTSEL = 0, the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt when INTSEL = 0. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 119 17.8.4.3 Fast Interrupt Vectoring The fast interrupt handler address can be stored through the AIC_SVR (Source Vector Register). The value written into this register when INTSEL = 0 is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. 17.8.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt: 3. LDR PC, [PC, # -&F20] The user does not need nested fast interrupts. When nFIQ is asserted, if the bit "F" of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor.The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 4. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 5. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The "F" bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction. 17.8.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 120 Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages. When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR). The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edgetriggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the fast forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. Figure 17-10.Fast Forcing Source 0 _ FIQ AIC_IPR Input Stage Automatic Clear AIC_IMR nFIQ Read FVR if Fast Forcing is disabled on Sources 1 to 127. AIC_FFSR Source n AIC_IPR Input Stage Priority Manager Automatic Clear nIRQ AIC_IMR Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. 17.8.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences: If an enabled interrupt with a higher priority than the current one is pending, it is stacked. If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 121 This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. 17.8.6 Spurious Interrupt The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 17.8.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution. 17.8.8 Write Protected Registers To prevent any single software error that may corrupt AIC behavior, the registers listed below can be write-protected by setting the WPEN bit in the "AIC Write Protect Mode Register" (AIC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the "AIC Write Protect Status Register"(AIC_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the "AIC Write Protect Status Register". SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 122 List of the write-protected registers: "AIC Source Mode Register" "AIC Source Vector Register" "AIC Spurious Interrupt Vector Register" "AIC Debug Control Register" SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 123 17.9 Advanced Interrupt Controller (AIC) User Interface Table 17-3. Register Mapping Offset Register Name Access Reset 0x00 Source Select Register AIC_SSR Read-write 0x0 0x04 Source Mode Register AIC_SMR Read-write 0x0 0x08 Source Vector Register AIC_SVR Read-write 0x0 0x0C Reserved - - - 0x10 Interrupt Vector Register AIC_IVR Read-only 0x0 0x14 FIQ Interrupt Vector Register AIC_FVR Read-only 0x0 0x18 Interrupt Status Register AIC_ISR Read-only 0x0 0x1C Reserved - - - (2) AIC_IPR0 Read-only 0x0(1) 0x24 (2) Interrupt Pending Register 1 AIC_IPR1 Read-only 0x0(1) 0x28 Interrupt Pending Register 2(2) AIC_IPR2 Read-only 0x0(1) 0x2C Interrupt Pending Register 3(2) AIC_IPR3 Read-only 0x0(1) 0x30 Interrupt Mask Register AIC_IMR Read-only 0x0 0x34 Core Interrupt Status Register AIC_CISR Read-only 0x0 0x38 End of Interrupt Command Register AIC_EOICR Write-only - 0x3C Spurious Interrupt Vector Register AIC_SPU Read-write 0x0 0x40 Interrupt Enable Command Register AIC_IECR Write-only - 0x44 Interrupt Disable Command Register AIC_IDCR Write-only - 0x48 Interrupt Clear Command Register AIC_ICCR Write-only - 0x4C Interrupt Set Command Register AIC_ISCR Write-only - 0x20 Interrupt Pending Register 0 0x50 Fast Forcing Enable Register AIC_FFER Write-only - 0x54 Fast Forcing Disable Register AIC_FFDR Write-only - 0x58 Fast Forcing Status Register AIC_FFSR Read-only 0x0 0x5C Reserved - - - 0x6C Debug Control Register AIC_DCR Read-write 0x0 0xE4 Write Protect Mode Register AIC_WPMR Read-write 0x0 0xE8 Write Protect Status Register AIC_WPSR Read-only 0x0 0xEC - 0xFC Reserved Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID127 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 124 17.9.1 AIC Source Select Register Name: AIC_SSR Address: 0xFFFFF000 Access: Read-write Reset: 0x0 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 4 3 INTSEL 2 1 0 * INTSEL: Interrupt Line Selection 0-127 = Selects the interrupt line to handle. See Section 17.8.1.1 "Interrupt Source Mode". SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 125 17.9.2 AIC Source Mode Register Name: AIC_SMR Address: 0xFFFFF004 Access: Read-write Reset: 0x0 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 4 - 3 - 2 1 PRIOR 0 SRCTYPE * PRIOR: Priority Level Programs the priority level of the source selected by INTSEL in except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ. * SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt source selected by INTSEL. Value Name Description 0x0 INT_LEVEL_SENSITIVE 0x1 INT_EDGE_TRIGGERED 0x2 EXT_HIGH_LEVEL 0x3 EXT_POSITIVE_EDGE Value High level Sensitive for internal source Low level Sensitive for external source Positive edge triggered for internal source Negative edge triggered for external source High level Sensitive for internal source High level Sensitive for external source Positive edge triggered for internal source Positive edge triggered for external source Internal Interrupt External Interrupt 0 0 High level sensitive Low level sensitive 0 1 Positive edge triggered Negative edge triggered 1 0 High level sensitive High level sensitive 1 1 Positive edge triggered Positive edge triggered SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 126 17.9.3 AIC Source Vector Register Name: AIC_SVR Address: 0xFFFFF008 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR * VECTOR: Source Vector The user may store in this register the address of the corresponding handler for the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 127 17.9.4 AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF010 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV * IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 128 17.9.5 AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF014 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV * FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register when INTSEL = 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 129 17.9.6 AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF018 Access: Read-only Reset: 0x0 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 4 3 IRQID 2 1 0 * IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 130 17.9.7 AIC Interrupt Pending Register 0 Name: AIC_IPR0 Address: 0xFFFFF020 Access: Read-only Reset: 0x0 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 SYS 0 FIQ * FIQ, SYS, PIDx: Interrupt Pending 0 = The corresponding interrupt is not pending. 1 = The corresponding interrupt is pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 131 17.9.8 AIC Interrupt Pending Register 1 Name: AIC_IPR1 Address: 0xFFFFF024 Access: Read-only Reset: 0x0 31 PID63 30 PID62 29 PID61 28 PID60 27 PID59 26 PID58 25 PID57 24 PID56 23 PID55 22 PID54 21 PID53 20 PID52 19 PID51 18 PID50 17 PID49 16 PID48 15 PID47 14 PID46 13 PID45 12 PID44 11 PID43 10 PID42 9 PID41 8 PID40 7 PID39 6 PID38 5 PID37 4 PID36 3 PID35 2 PID34 1 PID33 0 PID32 * PIDx: Interrupt Pending 0 = The corresponding interrupt is not pending. 1 = The corresponding interrupt is pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 132 17.9.9 AIC Interrupt Pending Register 2 Name: AIC_IPR2 Address: 0xFFFFF028 Access: Read-only Reset: 0x0 31 PID95 30 PID94 29 PID93 28 PID92 27 PID91 26 PID90 25 PID89 24 PID88 23 PID87 22 PID86 21 PID85 20 PID84 19 PID83 18 PID82 17 PID81 16 PID80 15 PID79 14 PID78 13 PID77 12 PID76 11 PID75 10 PID74 9 PID73 8 PID72 7 PID71 6 PID70 5 PID69 4 PID68 3 PID67 2 PID66 1 PID65 0 PID64 * PIDx: Interrupt Pending 0 = The corresponding interrupt is not pending. 1 = The corresponding interrupt is pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 133 17.9.10 AIC Interrupt Pending Register 3 Name: AIC_IPR3 Address: 0xFFFFF02C Access: Read-only Reset: 0x0 31 PID127 30 PID126 29 PID125 28 PID124 27 PID123 26 PID122 25 PID121 24 PID120 23 PID119 22 PID118 21 PID117 20 PID116 19 PID115 18 PID114 17 PID113 16 PID112 15 PID111 14 PID110 13 PID109 12 PID108 11 PID107 10 PID106 9 PID105 8 PID104 7 PID103 6 PID102 5 PID101 4 PID100 3 PID99 2 PID98 1 PID97 0 PID96 * PIDx: Interrupt Pending 0 = The corresponding interrupt is not pending. 1 = The corresponding interrupt is pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 134 17.9.11 AIC Interrupt Mask Register Name: AIC_IMR Address: 0xFFFFF030 Access: Read-only Reset: 0x0 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 INTM * INTM: Interrupt Mask 0 = The interrupt source selected by INTSEL is disabled. 1 = The interrupt source selected by INTSEL is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 135 17.9.12 AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF034 Access: Read-only Reset: 0x0 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 NIRQ 0 NFIQ * NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. * NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 136 17.9.13 AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF038 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ENDIT * ENDIT: Interrupt Processing Complete Command The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 137 17.9.14 AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF03C Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR * SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 138 17.9.15 AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF040 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 INTEN * INTEN: Interrupt Enable 0 = No effect. 1 = Enables the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 139 17.9.16 AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF044 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 INTD * INTD: Interrupt Disable 0 = No effect. 1 = Disables the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 140 17.9.17 AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF048 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 INTCLR * INTCLR: Interrupt Clear Clears one the following depending on the setting of the INTSEL bit FIQ, SYS, PID2-PID127 0 = No effect. 1 = Clears the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 141 17.9.18 AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF04C Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 INTSET * INTSET: Interrupt Set 0 = No effect. 1 = Sets the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 142 17.9.19 AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF050 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 FFEN * FFEN: Fast Forcing Enable 0 = No effect. 1 = Enables the fast forcing feature on the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 143 17.9.20 AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF054 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 FFDIS * FFDIS: Fast Forcing Disable 0 = No effect. 1 = Disables the Fast Forcing feature on the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 144 17.9.21 AIC Fast Forcing Status Register Name: AIC_FFSR Address: 0xFFFFF058 Access: Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 FFS * FFS: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the interrupt source selected by INTSEL. 1 = The Fast Forcing feature is enabled on the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 145 17.9.22 AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF06C Access: Read-write Reset: 0x0 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 GMSK 0 PROT * PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled. * GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 146 17.9.23 AIC Write Protect Mode Register Name: AIC_WPMR Address: 0xFFFFF0E4 Access: Read-write Reset: See Table 17-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 - 2 - 1 - 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 - 6 - 5 - 4 - * WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII). Protects the registers: * "AIC Source Mode Register" * "AIC Source Vector Register" * "AIC Spurious Interrupt Vector Register" * "AIC Debug Control Register" * WPKEY: Write Protect KEY Value 0x414943 Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 147 17.9.24 AIC Write Protect Status Register Name: AIC_WPSR Address: 0xFFFFF0E8 Access: Read-only Reset: See Table 17-3 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 - 24 - 19 18 17 16 11 10 9 8 3 - 2 - 1 - 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 - 6 - 5 - 4 - * WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the AIC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the AIC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. * WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading AIC_WPSR automatically clears all fields. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 148 18. Watchdog Timer (WDT) 18.1 Description The Watchdog Timer (WDT) can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 18.2 Embedded Characteristics 12-bit key-protected programmable counter Watchdog Clock is independent from Processor Clock Provides reset or interrupt signals to the system Counter may be stopped while the processor is in debug state or in idle mode SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 149 18.3 Block Diagram Figure 18-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDV WDT_CR WDRSTT reload 1 0 12-bit Down Counter WDT_MR reload WDD Current Value 1/128 SLCK <= WDD WDT_MR WDRSTEN = 0 wdt_fault (to Reset Controller) set set read WDT_SR or reset WDERR reset WDUNF reset wdt_int WDFIEN WDT_MR SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 150 18.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz). After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. If the watchdog is restarted by writing into the WDT_CR register, the WDT_MR register must not be programmed during a period of time of 3 slow clock periods following the WDT_CR write access. In any case, programming a new value in the WDT_MR register automatically initiates a restart instruction. The Watchdog Mode Register (WDT_MR) can be written only once . Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the "wdt_fault" signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register WDT_MR. Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the "wdt_fault" signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal "wdt_fault" to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the "wdt_fault" signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 151 Figure 18-2. Watchdog Behavior Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF if WDRSTEN is 0 Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault WDT_CR = WDRSTT SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 152 18.5 Watchdog Timer (WDT) User Interface Table 18-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register WDT_CR Write-only - 0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 153 18.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0xFFFFFE40 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 WDRSTT * WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog if KEY is written to 0xA5. * KEY: Password. Value 0xA5 Name Description PASSWD Writing any other value in this field aborts the write operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 154 18.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0xFFFFFE44 Access: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 18 11 10 22 26 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV Note: The first write access prevents any further modification of the value of this register, read accesses remain possible. Note: The WDD and WDV values must not be modified within a period of time of 3 slow clock periods following a restart of the watchdog performed by means of a write access in the WDT_CR register, else the watchdog may trigger an end of period earlier than expected. * WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. * WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt. * WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset. * WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset. * WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error. * WDDBGHLT: Watchdog Debug Halt 0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. * WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 155 1: The Watchdog stops when the system is in idle state. * WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 156 18.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0xFFFFFE48 Access Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 WDERR 0 WDUNF * WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR. * WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 157 19. Reset Controller (RSTC) 19.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 19.2 Embedded Characteristics External Devices Through the NRST Pin Processor Reset Peripheral Set Reset Backed-up Peripheral Reset Based on 2 Embedded Power-on Reset Cells Reset Source Status 19.3 Manages All Resets of the System, Including Status of the Last Reset Either General Reset, Wake-up Reset, Software Reset, User Reset, Watchdog Reset External Reset Signal Shaping Block Diagram Figure 19-1. Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR rstc_irq Startup Counter Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager periph_nreset exter_nreset backup_neset WDRPROC wd_fault SLCK SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 158 19.4 Functional Description 19.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: proc_nreset: Processor reset line. It also resets the Watchdog Timer. backup_nreset: Affects all the peripherals powered by VDDBU. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product datasheet. The Reset Controller Mode Register (RSTC_MR), used to configure the reset controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 19.4.2 NRST Manager After power-up, NRST is an output during the ERSTL time defined in the RSTC. When ERSTL elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal. The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 19-2shows the block diagram of the NRST Manager. Figure 19-2. NRST Manager RSTC_SR URSTS NRSTL user_reset NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset NRST Signal The NRST Manager handles the NRST input line asynchronously. When the line is low, a User Reset is immediately reported to the Reset State Manager. When the NRST goes from low to high, the internal reset is synchronized with the Slow Clock to provide a safe internal de-assertion of reset. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in the Reset Controller Status Register (RSTC_SR). As soon as the pin NRST is asserted, the bit URSTS in the RSTC_SR is set. This bit clears only when RSTC_SR is read. 19.4.2.1 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the "nrst_out" signal is driven low by the NRST Manager for a time programmed by the field ERSTL in the RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 s and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 159 This feature allows the reset controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 19.4.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 19-3. BMS Sampling SLCK Core Supply POR output BMS Signal XXX H or L BMS sampling delay = 3 cycles proc_nreset 19.4.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the RSTC_SR. The update of the field RSTTYP is performed when the processor reset is released. 19.4.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in the RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises two cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the backup supply POR cell, all resets signals are immediately asserted, even if the main supply POR cell does not report a main supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (main supply POR output). Figure 19-4 shows how the General Reset affects the reset signals. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 160 Figure 19-4. General Reset State SLCK Any Freq. MCK Backup Supply POR output Startup Time Main Supply POR output backup_nreset Processor Startup proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles BMS Sampling 19.4.4.2 Wake-up Reset The wake-up reset occurs when the main supply is down. When the main supply POR output is active, all the reset signals are asserted except backup_nreset. When the main supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in the RSTC_SR is updated to report a wake-up reset. The "nrst_out" remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the main supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the main supply POR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 161 Figure 19-5. Wake-up Reset SLCK Any Freq. MCK Main Supply POR output backup_nreset Resynch. 2 cycles Processor Startup proc_nreset RSTTYP XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 19.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin. When a falling edge occurs on NRST (reset activation), internal reset lines are immediately asserted. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the RSTC_SR is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 162 Figure 19-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Processor Startup proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 19.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously.) EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the reset controller reports the software status in the field RSTTYP of the RSTC_SR. Other software resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the RSTC_SR. It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 163 Figure 19-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 to 2 cycles Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 19.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 164 Figure 19-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 19.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: Backup Reset Wake-up Reset User Reset Watchdog Reset Software Reset Particular cases are listed below: When in User Reset: A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated. When in Software Reset: A watchdog event has priority over the current state. The NRST has no effect. When in Watchdog Reset: The processor reset is active and so a Software Reset cannot be programmed. A User Reset cannot be entered. 19.4.6 Reset Controller Status Register The Reset Controller Status Register (RSTC_SR) provides several status fields: RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This bit indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. NRSTL bit: This bit gives the level of the NRST pin sampled on each MCK rising edge. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 165 URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 19-9). Reading the RSTC_SR resets the URSTS bit. Figure 19-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 166 19.5 Reset Controller (RSTC) User Interface Table 19-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 Note: Access Reset Back-up Reset RSTC_CR Write-only - - Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read-write - 0x0000_0000 1. The reset value of RSTC_SR either reports a general reset or a wake-up reset depending on last rising power supply. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 167 19.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFE00 Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 8 - 7 - 6 - 5 - 4 - 3 EXTRST 2 PERRST 1 - 0 PROCRST * PROCRST: Processor Reset 0: No effect 1: If KEY is correct, resets the processor * PERRST: Peripheral Reset 0: No effect 1: If KEY is correct, resets the peripherals * EXTRST: External Reset 0: No effect 1: If KEY is correct, asserts the NRST pin and resets the processor and the peripherals * KEY: Write Access Password Value Name 0xA5 PASSWD Description Writing any other value in this field aborts the write operation. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 168 19.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFE04 Access Type: Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 SRCMP 16 NRSTL 15 - 14 - 13 - 12 - 11 - 10 9 RSTTYP 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 URSTS * URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. * RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. Value Name Description 0 GENERAL_RST Both VDDCORE and VDDBU rising 1 WKUP_RST VDDCORE rising 2 WDT_RST Watchdog fault occurred 3 SOFT_RST Processor reset required by the software 4 USER_RST NRST pin detected low * NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). * SRCMP: Software Reset Command in Progress 0: No software command is being performed by the reset controller. The reset controller is ready for a software command. 1: A software reset command is being performed by the reset controller. The reset controller is busy. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 169 19.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFE08 Access Type: Read-write 31 30 29 28 27 26 25 24 17 - 16 - 9 8 1 - 0 - KEY 23 - 22 - 21 - 20 - 19 - 18 - 15 - 14 - 13 - 12 - 11 10 7 - 6 - 5 4 - 3 - ERSTL 2 - * ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows the assertion duration to be programmed between 60 s and 2 seconds. * KEY: Write Access Password Value Name 0xA5 PASSWD Description Writing any other value in this field aborts the write operation. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 170 20. Shutdown Controller (SHDWC) 20.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 20.2 Embedded Characteristics 20.3 Shutdown and Wake-up Logic Software Assertion of the SHDW Output Pin Programmable De-assertion from the WKUP Input Pins Block Diagram Figure 20-1. Shutdown Controller Block Diagram SLCK Shutdown Controller SHDW_MR read SHDW_SR CPTWK0 reset WAKEUP0 SHDW_SR WKMODE0 set WKUP0 read SHDW_SR Wake-up reset RTCWKEN SHDW_MR RTC Alarm RTCWK SHDW_SR set SHDW_CR SHDW 20.4 Shutdown Output Controller SHDN Shutdown I/O Lines Description Table 20-1. I/O Lines Description Name Description Type WKUP0 Wake-up 0 input Input SHDN Shutdown output Output SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 171 20.5 Product Dependencies 20.5.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller. 20.6 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any pushbuttons or signal that wake up the system. The software is able to control the pin SHDN by writing the Shutdown Control Register (SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is passwordprotected and so the value written should contain the correct key for the command to be taken into account. As a result, the system should be powered down. A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register (SHDW_MR). The transition detector can be programmed to detect either a positive or negative transition or any level change on WKUP0. The detection can also be disabled. Programming is performed by defining WKMODE0. Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the SHDW_MR register. If the programmed level change is detected on a pin, a counter starts. When the counter reaches the value programmed in the corresponding field, CPTWK0, the SHDN pin is released. If a new input change is detected before the counter reaches the corresponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register (SHDW_SR) reports the detection of the programmed events on WKUP0 with a reset after the read of SHDW_SR. The Shutdown Controller can be programmed so as to activate the wake-up using the RTC alarm (the detection of the rising edge of the RTC alarm is synchronized with SLCK). This is done by writing the SHDW_MR register using the RTCWKEN field. When enabled, the detection of RTC alarm is reported in the RTCWK bit of the SHDW_SR Status register. They are reset after the read of SHDW_SR. When using the RTC alarm to wake up the system, the user must ensure that RTC alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flags may be detected and the wake-up will fail. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 172 20.7 Shutdown Controller (SHDWC) User Interface Table 20-2. Register Mapping Offset Register Name Access Reset 0x00 Shutdown Control Register SHDW_CR Write-only - 0x04 Shutdown Mode Register SHDW_MR Read-write 0x0000_0003 0x08 Shutdown Status Register SHDW_SR Read-only 0x0000_0000 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 173 20.7.1 Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFE10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SHDW * SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. * KEY: Password. Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 174 20.7.2 Shutdown Mode Register Name: SHDW_MR Address: 0xFFFFFE14 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 RTCWKEN 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 - 2 - 1 0 CPTWK0 WKMODE0 * WKMODE0: Wake-up Mode 0 Value Name Description 0 NO_DETECTION No detection is performed on the wake-up input 1 RISING_EDGE Low to high transition triggers the detection process 2 FALLING_EDGE High to low level transition triggers the detection process 3 ANY_EDGE Any edge on the wake-up input triggers the detection process * CPTWK0: Debounce Counter on Wake-up 0 Defines the minimum duration of the WKUP1 pin after the occurrence of the selected triggering edge (WKMODE0). The SHDN pin is released if the WKUP0 holds the selected level for (CPTWK * 16 + 1) consecutive Slow Clock cycles after the occurrence of the selected triggering edge on WKUP0. * RTCWKEN: Real-time Clock Wake-up Enable 0 = The RTC Alarm signal has no effect on the Shutdown Controller. 1 = The RTC Alarm signal forces the de-assertion of the SHDN pin. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 175 20.7.3 Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFE18 Access: Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 RTCWK 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 WAKEUP0 * WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on WKUP0 input since the last read of SHDW_SR. 1 = At least one wake-up event occurred on WKUP0 input since the last read of SHDW_SR. * RTCWK: Real-time Clock Wake-up 0 = No wake-up alarm from the RTC occurred since the last read of SHDW_SR. 1 = At least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 176 21. General-Purpose Backup Registers (GPBR) 21.1 Description The System Controller embeds 4 General-purpose Backup registers. 21.2 Embedded Characteristics 4 32-bit General Purpose Backup Registers SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 177 21.3 General Purpose Backup Registers (GPBR) User Interface Table 21-1. Register Mapping Offset 0x0 ... 0x6C Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 3 SYS_GPBR3 Access Reset Read-write - ... ... Read-write - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 178 21.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0xFFFFFE60 Access: Read-write 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 GPBR_VALUE 23 22 21 20 19 GPBR_VALUE 15 14 13 12 11 GPBR_VALUE 7 6 5 4 3 GPBR_VALUE * GPBR_VALUE: Value of GPBR x SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 179 22. Periodic Interval Timer (PIT) 22.1 Description The Periodic Interval Timer (PIT) provides the operating system's scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 22.2 Embedded Characteristics 20-bit Programmable Counter plus 12-bit Interval Counter Reset-on-read Feature Both Counters Work on Master Clock/16 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 180 22.3 Block Diagram Figure 22-1. Periodic Interval Timer PIT_MR PIV = PIT_MR PITIEN set 0 PIT_SR PITS pit_irq reset 0 MCK Prescaler 0 0 1 12-bit Adder 1 read PIT_PIVR 20-bit Counter MCK/16 CPIV PIT_PIVR CPIV PIT_PIIR PICNT PICNT SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 181 22.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 22-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 22-2. Enabling/Disabling PIT with PITEN APB cycle APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN CPIV PICNT 0 1 PIV - 1 0 PIV 1 0 1 0 PITS (PIT_SR) APB Interface read PIT_PIVR SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 182 22.5 Periodic Interval Timer (PIT) User Interface Table 22-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read-write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 183 22.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFE30 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 23 - 22 - 21 - 20 - 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV * PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). * PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. * PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 184 22.5.2 Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFE34 Access: Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PITS * PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 185 22.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFE38 Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. * CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 186 22.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFE3C Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV * CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 187 23. Real-time Clock (RTC) 23.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. 23.2 Embedded Characteristics Ultra Low Power Consumption Full Asynchronous Design Gregorian Calendar up to 2099 Programmable Periodic Interrupt Safety/security features: Valid Time and Date Programmation Check SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 188 23.3 Block Diagram Figure 23-1. RTC Block Diagram Slow Clock: SLCK 32768 Divider Date Entry Control Interrupt Control Bus Interface Bus Interface 23.4 Time RTC Interrup Product Dependencies 23.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 23.4.2 Interrupt Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. When a System Controller interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading each status register of the System Controller peripherals successively. Table 23-1. Peripheral IDs 23.5 Instance ID RTC 1 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099. 23.5.1 Reference Clock The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 189 23.5.2 Timing The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 23.5.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition: If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. If only the "seconds" field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC, MIN, HOUR fields. Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_TIMALR or RTC_CALALR registers. The first access clears the enable corresponding to the field to change (SECEN,MINEN,HOUREn,DATEEN,MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by writing 1 in SECEN,MINEN,HOUREn,DATEEN,MTHEN fields. 23.5.4 Error Checking when Programming Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 1. Century (check if it is in range 19 - 20 ) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding "date") 5. Day (check range 1 - 7) 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8. Second (check BCD and range 00 - 59) Note: If the 12-hour mode is selected by means of the RTC_MR register, a 12-hour value can be programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIMR register) to determine the range to be checked. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 190 23.5.5 Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropriate Time and Calendar register. Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control When entering programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 191 Figure 23-2. Update Sequence Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD =1? No Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 192 23.6 Real-time Clock (RTC) User Interface Table 23-2. Register Mapping Offset Register Name Access Reset 0x00 Control Register RTC_CR Read-write 0x0 0x04 Mode Register RTC_MR Read-write 0x0 0x08 Time Register RTC_TIMR Read-write 0x0 0x0C Calendar Register RTC_CALR Read-write 0x01810720 0x10 Time Alarm Register RTC_TIMALR Read-write 0x0 0x14 Calendar Alarm Register RTC_CALALR Read-write 0x01010000 0x18 Status Register RTC_SR Read-only 0x0 0x1C Status Clear Command Register RTC_SCCR Write-only - 0x20 Interrupt Enable Register RTC_IER Write-only - 0x24 Interrupt Disable Register RTC_IDR Write-only - 0x28 Interrupt Mask Register RTC_IMR Read-only 0x0 0x2C Valid Entry Register RTC_VER Read-only 0x0 0x30-0xC4 Reserved Register - - - 0xC8-0xF8 Reserved Register - - - 0xFC Reserved Register - - - Note: If an offset is not listed in the table it must be considered as reserved. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 193 23.6.1 RTC Control Register Name: RTC_CR Address: 0xFFFFFEB0 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 - - - - - - 15 14 13 12 11 10 - - - - - - 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 - - - - - - UPDCAL UPDTIM * UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register. * UPDCAL: Update Request Calendar Register 0 = No effect. 1 = Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set. * TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL. Value Name Description 0 MINUTE Minute change 1 HOUR Hour change 2 MIDNIGHT Every day at midnight 3 NOON Every day at noon * CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 194 23.6.2 RTC Mode Register Name: RTC_MR Address: 0xFFFFFEB4 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - HRMOD * HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 195 23.6.3 RTC Time Register Name: RTC_TIMR Address: 0xFFFFFEB8 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 - 7 11 MIN 6 5 - 4 3 SEC * SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. * MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. * HOUR: Current Hour The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode. * AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0 = AM. 1 = PM. All non-significant bits read zero. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 196 23.6.4 RTC Calendar Register Name: RTC_CALR Address: 0xFFFFFEBC Access: Read-write 31 30 - - 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 - 4 CENT * CENT: Current Century The range that can be set is 19 - 20 (gregorian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. * YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. * MONTH: Current Month The range that can be set is 01 - 12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. * DAY: Current Day in Current Week The range that can be set is 1 - 7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. * DATE: Current Day in Current Month The range that can be set is 01 - 31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 197 23.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0xFFFFFEC0 Access: Read-write 31 30 29 28 27 26 25 24 - - - - - - - - 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 6 5 SECEN Note: 11 MIN 4 3 SEC To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_TIMALR register. The first access clears the enable corresponding to the field to change (SECEN,MINEN,HOUREN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREN fields. * SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. * SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled. * MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. * MINEN: Minute Alarm Enable 0 = The minute-matching alarm is disabled. 1 = The minute-matching alarm is enabled. * HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. * AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. * HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled. 1 = The hour-matching alarm is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 198 23.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0xFFFFFEC4 Access: Read-write 31 30 DATEEN - 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN - - 15 14 13 12 11 10 9 8 - - - - - - - - Note: 20 19 MONTH 7 6 5 4 3 2 1 0 - - - - - - - - To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_CALALR register. The first access clears the enable corresponding to the field to change (DATEEN,MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (DATE,MONTH). The third access is required to re-enable the field by writing 1 in DATEEN, MTHEN fields. * MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. * MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled. * DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. * DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled. 1 = The date-matching alarm is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 199 23.6.7 RTC Status Register Name: RTC_SR Address: 0xFFFFFEC8 Access: Read-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - CALEV TIMEV SEC ALARM ACKUPD * ACKUPD: Acknowledge for Update 0 (FREERUN) = Time and calendar registers cannot be updated. 1 (UPDATE) = Time and calendar registers can be updated. * ALARM: Alarm Flag 0 (NO_ALARMEVENT) = No alarm matching condition occurred. 1 (ALARMEVENT) = An alarm matching condition has occurred. * SEC: Second Event 0 (NO_SECEVENT) = No second event has occurred since the last clear. 1 (SECEVENT) = At least one second event has occurred since the last clear. * TIMEV: Time Event 0 (NO_TIMEVENT) = No time event has occurred since the last clear. 1 (TIMEVENT) = At least one time event has occurred since the last clear. The time event is selected in the TIMEVSEL field in RTC_CR (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). * CALEV: Calendar Event 0 (NO_CALEVENT) = No calendar event has occurred since the last clear. 1 (CALEVENT) = At least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 200 23.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0xFFFFFECC Access: Write-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - CALCLR TIMCLR SECCLR ALRCLR ACKCLR * ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). * ALRCLR: Alarm Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). * SECCLR: Second Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). * TIMCLR: Time Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). * CALCLR: Calendar Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 201 23.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0xFFFFFED0 Access: Write-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - CALEN TIMEN SECEN ALREN ACKEN * ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. * ALREN: Alarm Interrupt Enable 0 = No effect. 1 = The alarm interrupt is enabled. * SECEN: Second Event Interrupt Enable 0 = No effect. 1 = The second periodic interrupt is enabled. * TIMEN: Time Event Interrupt Enable 0 = No effect. 1 = The selected time event interrupt is enabled. * CALEN: Calendar Event Interrupt Enable 0 = No effect. 1 = The selected calendar event interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 202 23.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0xFFFFFED4 Access: Write-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - CALDIS TIMDIS SECDIS ALRDIS ACKDIS * ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. * ALRDIS: Alarm Interrupt Disable 0 = No effect. 1 = The alarm interrupt is disabled. * SECDIS: Second Event Interrupt Disable 0 = No effect. 1 = The second periodic interrupt is disabled. * TIMDIS: Time Event Interrupt Disable 0 = No effect. 1 = The selected time event interrupt is disabled. * CALDIS: Calendar Event Interrupt Disable 0 = No effect. 1 = The selected calendar event interrupt is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 203 23.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0xFFFFFED8 Access: Read-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - CAL TIM SEC ALR ACK * ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled. * ALR: Alarm Interrupt Mask 0 = The alarm interrupt is disabled. 1 = The alarm interrupt is enabled. * SEC: Second Event Interrupt Mask 0 = The second periodic interrupt is disabled. 1 = The second periodic interrupt is enabled. * TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled. 1 = The selected time event interrupt is enabled. * CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled. 1 = The selected calendar event interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 204 23.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0xFFFFFEDC Access: Read-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - NVCALALR NVTIMALR NVCAL NVTIM * NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed. * NVCAL: Non-valid Calendar 0 = No invalid data has been detected in RTC_CALR (Calendar Register). 1 = RTC_CALR has contained invalid data since it was last programmed. * NVTIMALR: Non-valid Time Alarm 0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1 = RTC_TIMALR has contained invalid data since it was last programmed. * NVCALALR: Non-valid Calendar Alarm 0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1 = RTC_CALALR has contained invalid data since it was last programmed. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 205 24. Slow Clock Controller (SCKC) 24.1 Description The System Controller embeds a Slow Clock Controller. The slow clock can be generated either by an external 32768 Hz crystal oscillator or by the on-chip 32 kHz RC oscillator. The 32768 Hz crystal oscillator can be bypassed by setting the OSC32BYP bit to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1, respectively, the RCEN and OSC32EN bits in the System Controller user interface. The OSCSEL command selects the slow clock source. 24.2 Embedded Characteristics 32 kHz RC Oscillator or 32768 Hz Crystal Oscillator Selector VDDBU Powered SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 206 24.3 Block Diagram Figure 24-1. Block Diagram RCEN On Chip RC OSC Slow Clock SLCK XIN32 XOUT32 Slow Clock Oscillator OSCSEL OSC32EN OSC32BYP RCEN, OSC32EN, OSCSEL and OSC32BYP bits are located in the Slow Clock Controller Configuration Register (SCKC_CR) located at the address 0xFFFFFE50 in the backed-up part of the System Controller and, thus, they are preserved while VDDBU is present. After the VDDBU power-on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0, allowing the system to start on the internal 32 kHz RC oscillator. The programmer controls the slow clock switching by software and so must take precautions during the switching phase. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 207 24.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator To switch from the internal 32 kHz RC oscillator to the 32768 Hz crystal oscillator, the programmer must execute the following sequence: Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller. Enable the 32768 Hz oscillator by writing a 1 to the OSC32EN bit. Wait 32768 Hz startup time for clock stabilization (software loop). Switch from internal 32 kHz RC oscillator to 32768 Hz oscillator by writing a 1 to the OSCSEL bit. Wait 5 slow clock cycles for internal resynchronization. Disable the 32 kHz RC oscillator by writing a 0 to the RCEN bit. 24.3.2 Bypass the 32768 Hz Oscillator The following steps must be added to bypass the 32768 Hz oscillator: An external clock must be connected on XIN32. Enable the bypass path by writing a 1 to the OSC32BYP bit. Disable the 32768 Hz oscillator by writing a 0 to the OSC32EN bit. 24.3.3 Switch from 32768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator The same procedure must be followed to switch from the 32768 Hz crystal oscillator to the internal 32 kHz RC oscillator: Switch the master clock to a source different from slow clock (PLL or Main Oscillator). Enable the internal 32 kHz RC oscillator for low power by writing a 1 to the RCEN bit. Wait internal 32 kHz RC startup time for clock stabilization (software loop). Switch from 32768 Hz oscillator to internal RC by writing a 0 to the OSCSEL bit. Wait 5 slow clock cycles for internal resynchronization. Disable the 32768 Hz oscillator by writing a 0 to the OSC32EN bit. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 208 24.4 Slow Clock Controller (SCKC) User Interface Table 24-1. Register Mapping Offset 0x0 Register Name Slow Clock Controller Configuration Register SCKC_CR Access Reset Read/Write 0x0000_0001 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 209 24.4.1 Slow Clock Controller Configuration Register Name: SCKC_CR Address: 0xFFFFFE50 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 OSCSEL 2 OSC32BYP 1 OSC32EN 0 RCEN * RCEN: Internal 32 kHz RC Oscillator 0: 32 kHz RC oscillator is disabled. 1: 32 kHz RC oscillator is enabled. * OSC32EN: 32768 Hz Oscillator 0: 32768 Hz oscillator is disabled. 1: 32768 Hz oscillator is enabled. * OSC32BYP: 32768Hz Oscillator Bypass 0: 32768 Hz oscillator is not bypassed. 1: 32768 Hz oscillator is bypassed, accept an external slow clock on XIN32. * OSCSEL: Slow Clock Selector 0 (RC): Slow clock is internal 32 kHz RC oscillator. 1 (XTAL): Slow clock is 32768 Hz oscillator. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 210 25. Fuse Controller (FUSE) 25.1 Description The Fuse Controller (FUSE) supports software fuse programming through a 32-bit register. Only fuses set to level `1' are programmed. The fast (main) RC oscillator must be enabled at startup to access the fuse matrix. It reads the fuse states on startup and stores them into 32-bit registers. The first 8 Fuse Status registers (FUSE_SRx) can be masked and will read as a value of `0' regardless of the fuse state when masked. 25.2 Embedded Characteristics Software Fuse Programming User Write Access for Fuse Part of Fuse can be Masked After Read 256 FUSE bits: 192 bits are dedicated to Users 3 bits are dedicated to Special Functions The Fuse Controller can be hidden thanks to a SFR write-once bit. Please refer to the "Special Function Registers (SFR)" section of the SAMA5D3 series datasheet for details. 25.2.1 FUSE Bit Mapping To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" FUSE bits. Table 25-1. FUSE Bit Mapping 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 DO NOT USE (DNU) 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 USER_DATA 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 DO NOT USE (DNU) B J W 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 USER_DATA 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 USER_DATA 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 45 44 43 42 41 40 39 38 37 36 35 34 33 32 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USER_DATA 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 USER_DATA 16 15 14 USER_DATA SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 211 25.2.2 Special Functions The user is allowed to set special bits as described in the following table. Table 25-2. Special Bits Bit Number Bit Name Function 162 B BMS_SAMPLING_DISABLED - BMS sampling is disabled if set 161 J JTAG_DISABLED - JTAG is disabled if set 160 W FUSE_WRITE_DISABLED - FUSE bit writing is disabled if set SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 212 25.3 Block Diagram Figure 25-1. Fuse Controller Block Diagram Fuse States Fuse States Fuse Cell Fuse Controller Controls Controls SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 213 25.4 Functional Description 25.4.1 Fuse Reading The fuse states are automatically read on CORE startup and are available for reading in the 8 Fuse Status (FUSE_SRx) registers. The fuse states of bits 31 to 0 will be available at FUSE_SR0, the fuse states of bits 63 to 32 will be available at FUSE_SR1 and so on. FUSE_SRx registers can be updated manually by using the RRQ bit of the Fuse Control register (FUSE_CR). RS and WS bits of the Fuse Index register (FUSE_IR) must be at level one before issuing the read request. Figure 25-2. Fuse Read Clock FUSE_SRx outdated up to date RRQ WS RS 25.4.2 Fuse Programming All the fuses, except Atmel reserved fuses, can be written by software. To program fuses, strictly follow the order of the sequence instructions as provided below: 1. Select the word to write, using the WSEL field of the Fuse Index register (FUSE_IR). 2. Write the word to program in the Fuse Data register (FUSE_DR). 3. Check that RS and WS bits of the FUSE_IR are at level one (no read and no write pending). 4. Write the WRQ bit of the Fuse Control register (FUSE_CR) to begin the fuse programming. The KEY field must be written at the same time with a value 0xFB to make the write request valid. Writing the WRQ bit will clear the WS bit. 5. Check the WS bit of FUSE_IR. When WS has a value of `1' the fuse write process is over. Only fuses to be set to level `1' are written. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 214 Figure 25-3. Fuse Write Clock WSEL DATA XX 00 XX 01 Fuse[31:0] Fuse[63:32] WRQ WS RS 25.4.3 Fuse Masking It is possible to mask the first 8 FUSE_SRx registers so that they will be read at a value of `0', regardless of the fuse state. To activate fuse masking on the first 8 FUSE_SRx registers, the MSK bit of the Fuse Mode register (FUSE_MR) must be written to level `1'. The MSK bit is write-only. Only a general reset can disable fuse masking. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 215 25.5 Fuse Controller (FUSE) User Interface Table 25-3. Register Mapping Offset Register Name Access Reset 0x00 Fuse Control Register FUSE_CR Write-only - 0x04 Fuse Mode Register FUSE_MR Write-only - 0x08 Fuse Index Register FUSE_IR Read-write 0x00000000 0x0C Fuse Data Register FUSE_DR Read-write - 0x10 Fuse Status Register 0 FUSE_SR0 Read-only 0x00000000 0x14 Fuse Status Register 1 FUSE_SR1 Read-only 0x00000000 ... ... ... FUSE_SR7 Read-only 0x00000000 ... 0x2C ... Fuse Status Register 7 0x30-0xDC Reserved - - - 0xE0-0xFC Reserved - - - Note: 1. Values in the Version Register vary with the version of the IP block implementation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 216 25.5.1 Fuse Control Register Name: FUSE_CR Address: 0xFFFFE400 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 11 10 9 8 3 - 2 - 1 RRQ 0 WRQ KEY 7 - 6 - 5 - 4 - * WRQ: Write Request 0: No effect. 1: Requests the word DATA to be programmed if KEY field value is 0xFB. * RRQ: Read Request 0: No effect. 1: Requests the fuses to be read and FUSE_SRx registers to be updated if KEY field value is 0xFB. * KEY: Key code Value Name 0xFB VALID Description Writing any other value in this field aborts the write operation of the WRQ and RRQ bits. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 217 25.5.2 Fuse Mode Register Name: FUSE_MR Address: 0xFFFFE404 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 MSK * MSK: Mask Fuse Status Registers 0: No effect. 1: Masks the first 8 FUSE_SRx registers. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 218 25.5.3 Fuse Index Register Name: FUSE_IR Address: 0xFFFFE408 Access: Read-write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 10 9 8 7 - 6 - 5 - 4 - 3 - 1 RS 0 WS WSEL 2 - * WS: Write Status 0: Write is pending or no write has been requested since general reset. 1: Write of fuses is done. * RS: Read Status 0: Read is pending or no read has been requested since general reset. 1: Read of fuses is done. * WSEL: Word Selection 0-15: Selects the word to write. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 219 25.5.4 Fuse Data Register Name: FUSE_DR Address: 0xFFFFE40C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA * DATA: Data to Program Data to program. Only bits with a value of `1' will be programmed. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 220 25.5.5 Fuse Status Register Name: FUSE_SRx [x=0..7] Address: 0xFFFFE410 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FUSE 23 22 21 20 FUSE 15 14 13 12 FUSE 7 6 5 4 FUSE * FUSE: Fuse Status Indicates the status of corresponding fuses: 0: Unprogrammed. 1: Programmed. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 221 26. Power Management Controller (PMC) 26.1 Clock Generator 26.1.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 26.2.15 "Power Management Controller (PMC) User Interface". However, the Clock Generator registers are named CKGR_. 26.1.2 Embedded Characteristics The Clock Generator is made up of: Low-power 32768 Hz Slow Clock Oscillator with bypass mode Low-power 32 kHz RC Oscillator 8 to 48 MHz Crystal Oscillator or a 24/48 MHz XRCGB Crystal Resonator, which can be bypassed (12 MHz, 24 MHz (preferred) or 48 MHz must be used in case of USB operations) Fast RC Oscillator, at 12 MHz 480 MHz UTMI PLL providing a clock for the USB High Speed Device Controller 400 to 1000 MHz programmable PLL (input from 8 to 50 MHz), capable of providing the clock MCK to the processor and to the peripherals It provides the following clocks: SLCK, the Slow Clock, which is the only permanent clock within the system MAINCK is the output of the Main Clock Oscillator selection: either 8 to 48 MHz Crystal Oscillator or 12 MHz Fast RC Oscillator PLLACK is the output of the Divider and 400 to 1000 programmable PLL (PLLA) UPLLCK is the output of the 480 MHz UTMI PLL (UPLL) SMDCK is the Software Modem Clock The Power Management Controller also provides the following operations on clocks: Main crystal oscillator clock failure detector Frequency counter on main clock and an on-the-fly adjustable main RC oscillator frequency SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 222 26.1.3 Block Diagram Figure 26-1. Clock Generator Block Diagram Clock Generator RCEN On Chip 32K RC OSC XIN32 XOUT32 Slow Clock SLCK Slow Clock Oscillator OSCSEL OSC32EN OSC32BYP MOSCRCEN MOSCSEL On Chip 12M RC OSC XIN XOUT 8 to 48 MHz Main Oscillator UPLL UPLLCK PLLA and Divider Status Main Clock MAINCK PLLA Clock PLLACK Control Power Management Controller 26.1.4 Main Clock Selection The main clock can be generated either by an external 8 to 48 MHz crystal, an XRCGB crystal resonator or by the onchip12 MHz Fast RC Oscillator. This allows the processor to start or restart in a few microseconds when 12 MHz Fast RC Oscillator is selected. The 8 to 48 MHz crystal oscillator can be bypassed by setting the MOSCXTBY bit to accept an external main clock on XIN. Figure 26-2. Main Clock Selection MOSCRCEN On Chip 12 MHz RC Oscillator Main Clock XIN XOUT Main Clock Oscillator MOSCSEL SMDCK MOSCXTEN MOSCXTBY SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 223 MOSCRCEN, MOSCXTEN, MOSCSEL and MOSCXTBY bits are located in the PMC Clock Generator Main Oscillator Register (CKGR_MOR). After a VDDBU power on reset, the default configuration is MOSCRCEN = 1, MOSCXTEN = 0 and MOSCSEL = 0, the 12 MHz RC is started as Main clock. 26.1.4.1 Fast Wake-up To speed up the wake-up phase, the user can switch the system clock from 32 kHz RC (SLCK) to 12 MHz RC (Main Clock). This enables the user to perform system configuration (PLL, DDR, etc.) at 12 MHz instead of 32 kHz during the12 MHz Oscillator startup. Figure 26-3. PMC Startup 12 MHz RC External Main clock Main Supply 12 MHz RC Startup Time POR output Crystal Startup Time System starts on 32 kHz RC Wait MOSCRCS = 1 RCEN = 1 User switch on Main Clock OSC32EN = 0 to speed-up the boot OSCSEL = 0 PMC_MCKR =1 MOSCRCEN = 1 System is running at 12 MHz MOSCXTEN = 0 MOSCSEL = 0 External oscillator PMC_MCKR = 0 is started for better accuracy MOSCXTEN = 1 MOSCSEL = 0 Wait MOSCXTS = 1 User switches on external oscillator MOSCSEL = 1 Wait while MOSCSELS = 1 System is runnning on 12 MHz Crystal PLL can be used 26.1.4.2 Switch from Internal 12 MHz Fast RC Oscillator to the 8 to 48 MHz Crystal The programmer controls the main clock switching by software and must take precautions during the switching phase. To switch from internal 12 MHz Fast RC Oscillator to the 8 to 48 MHz crystal, the programmer must execute the following sequence: Enable the 8 to 48 MHz oscillator by writing a 1 to bit MOSCXTEN. Wait for 8 to 48 MHz oscillator status MAINRDY is 1. Switch from internal 12 MHz RC to the 8 to 48 MHz oscillator by writing a 1 to bit MOSCSEL. If not, the PMC writes a 0 to bit MOSCSEL. Disable the 12 MHz RC oscillator by writing a 0 to bit MOSCRCEN. 26.1.4.3 Bypass the 8 to 48 MHz Crystal Oscillator The following step must be added to bypass the 8 to 48 MHz crystal oscillator. An external clock must be connected on XIN. Enable the bypass path MOSCXTBY bit set to 1. Disable the 8 to 48 MHz oscillator by writing a 0 to bit MOSCXTEN. 26.1.4.4 Switch from the 8 to 48 MHz Crystal Oscillator to internal 12 MHz Fast RC Oscillator The same procedure must be followed to switch from a 8 to 48 MHz crystal oscillator to the internal 12 MHz Fast RC Oscillator. Enable the internal 12 MHz RC oscillator for low power by writing a 1 to bit MOSCRCEN. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 224 Wait internal 12 MHz RC startup time for clock stabilization (software loop). Switch from 8 to 48 MHz oscillator to the internal 12 MHz Fast RC Oscillator by writing a 0 to bit MOSCSEL. Disable the 8 to 48 MHz oscillator by writing a 0 to bit MOSCXTEN. 26.1.5 Main Clock Figure 26-4. Main Clock Block Diagram MOSCRCEN MOSCRCF MOSCRCS On Chip 12 MHz RC Oscillator MOSCSEL MOSCSELS 1 MAINCK Main Clock MOSCXTEN 0 XIN XOUT 8 to 48 MHz Crystal Oscillator MOSCXTCNT SLCK Slow Clock 8 to 48 MHz Crystal Oscillator Counter MOSCXTS MOSCRCEN MOSCXTEN MOSCSEL Main Clock Frequency Counter MAINF MAINRDY The Main Clock has two sources: 12 MHz Fast RC Oscillator which starts very quickly and is used at startup 8 to 48 MHz Crystal Oscillator, which can be bypassed 26.1.5.1 12 MHz Fast RC Oscillator After reset, the 12 MHz Fast RC Oscillator is enabled and it is selected as the source of MCK. MCK is the default clock selected to start up the system. Please refer to the "DC Characteristics" section of the product electrical characteristics. The software can disable or enable the 12 MHz Fast RC Oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator Register (CKGR_MOR). When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared, indicating the Main Clock is off. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 225 26.1.5.2 12 MHz Fast RC Oscillator Clock Frequency Adjustment It is possible for the user to adjust the main RC oscillator frequency through PMC_OCR. By default, SEL is low, so the RC oscillator is driven with fuse calibration bits which are programmed during the chip production. The user can adjust the trimming of the 12 MHz Fast RC oscillator through the PMC_OCR in order to obtain more accurate frequency (to compensate derating factors such as temperature and voltage). In order to calibrate the 12 MHz oscillator frequency, SEL must be set to 1 and a correct frequency value must be configured in CAL. It is possible to restart, at anytime, a measurement of the main frequency by means of the RCMEAS bit in Main Clock Frequency Register (CKGR_MCFR). Thus, when MAINFRDY flag reads 1, another read access on CKGR_MCFR provides an image of the frequency of the main clock on MAINF field. The software can calculate the error with an expected frequency and correct the CAL field accordingly. This may be used to compensate frequency drift due to derating factors such as temperature and/or voltage. 26.1.5.3 8 to 48 MHz Crystal Oscillator After reset, the 8 to 48 MHz Crystal Oscillator is disabled and it is not selected as the source of MAINCK. The user can select the 8 to 48 MHz crystal oscillator to be the source of MAINCK, as it provides a more accurate frequency. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCXTEN bit in the Main Oscillator Register (CKGR_MOR). When disabling the main oscillator by clearing the MOSCXTEN bit in CKGR_MOR, the MOSCXTS bit in PMC_SR is automatically cleared, indicating the Main Clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the oscillator. When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to enable the main oscillator, the MOSCXTS bit in the PMC_SR is cleared and the counter starts counting down on the slow clock divided by 8 from the MOSCXTCNT value. Since the MOSCXTCNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor. 26.1.5.4 Main Clock Oscillator Selection The user can select either the 12 MHz Fast RC Oscillator or the Crystal Oscillator to be the source of Main Clock. The selection is made by writing the MOSCSEL bit in the CKGR_MOR. The switch of the Main Clock source is glitch free, so there is no need to run out of SLCK or PLLACK in order to change the selection. The MOSCSELS bit of the PMC_SR indicates when the switch sequence is done. Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor. 26.1.5.5 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator Both sources must be enabled during the switch operation. Only after completion can the unused oscillator be disabled. If switching to Fast Crystal Oscillator, the clock presence must first be checked according to what is described in Section 26.1.5.6 "Software Sequence to Detect the Presence of Fast Crystal" because the source may not be reliable (crystal failure or bypass on a non-existent clock). 26.1.5.6 Software Sequence to Detect the Presence of Fast Crystal The frequency meter carried on the CKGR_MCFR is operating on the selected main clock and not on the fast crystal clock nor on the fast RC Oscillator clock. Therefore, to check for the presence of the fast crystal clock, it is necessary to switch the main clock on the fast crystal clock. The following software sequence must be followed (during this sequence the Main RC oscillator must be kept enabled (MOSCRCEN = 1)): SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 226 1. MCK must select the slow clock (CSS = 0 in PMC_MCKR). 2. Wait for the MCKRDY flag in the PMC_SR to be 1. 3. The fast crystal must be enabled by programming 1 in the MOSCXTEN field in the CKGR_MOR, with the MOSCXTST field being programmed to the appropriate value (see the electrical characteristics section). 4. Wait for the MOSCXTS flag to be 1 in the PMC_SR to allow the start-up period of the fast crystal oscillator to end. 5. MOSCSEL must be programmed to 1 in the CKGR_MOR to select the fast main crystal oscillator for the main clock. 6. MOSCSEL must be read until its value equals 1. 7. The MOSCSELS status flag must be checked in the PMC_SR. At this point, two cases may occur: either MOSCSELS = 0 or MOSCSELS = 1. MOSCSELS = 1: There is a valid crystal connected and its frequency can be determined by initiating a frequency measure by programming RCMEAS in the CKGR_MCFR. MOSCSELS = 0: There is no fast crystal clock (either no crystal connected or a crystal clock out of specification). A frequency measure can reinforce this status by initiating a frequency measure by programming RCMEAS in the CKGR_MCFR. The selection of the main clock must be programmed back to the main RC oscillator by writing MOSCSEL to 0 prior to disabling the fast crystal oscillator. The crystal oscillator can be disabled (MOSCXTEN = 0 in CKGR_MOR). 26.1.5.7 Main Clock Frequency Counter The device features a Main Clock frequency counter that provides the frequency of the Main Clock. The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock in the following cases: When the 12 MHz Fast RC Oscillator clock is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCRCS bit is set) When the Crystal Oscillator is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set) When the Main Clock Oscillator selection is modified Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the CKGR_MCFR is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the 12 MHz Fast RC Oscillator or the Crystal Oscillator can be determined. 26.1.6 Divider and PLLA Block The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLLA minimum input frequency when programming the divider. Figure 26-5 shows the block diagram of the divider and PLLA block. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 227 Figure 26-5. Divider and PLLA Block Diagram DIVA MAINCK MULA Divider OUTA PLLA PLLACK PLLACOUNT SLCK PLLA Counter LOCKA 26.1.6.1 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLLA allows multiplication of the divider's outputs. The PLLA clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIVA and MULA. The factor applied to the source signal frequency is (MULA + 1)/DIVA. When MULA is written to 0, the PLLA is disabled and its power consumption is saved. Re-enabling the PLLA can be performed by writing a value higher than 0 in the MUL field. Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in PMC_SR is automatically cleared. The values written in the PLLACOUNT field in CKGR_PLLAR are loaded in the PLLA counter. The PLLA counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLLA transient time into the PLLACOUNT field. The PLLA clock must be divided by 2 by writing the PLLADIV2 bit in the PMC_MCKR. 26.1.7 UTMI Phase Lock Loop Programming The source clock of the UTMI PLL is the Main OSC output. When the 12 MHz Fast RC Oscillator is selected as the source of the MAINCK, the 12 MHz frequency must also be selected because the UTMI PLL multiplier contains a built-in multiplier of x 40 to obtain the USB High Speed 480 MHz. A 12, 16, 24 or 48 MHz crystal is needed to use the USB. Please refer to the SFR_UTMICKTRIM register to set the value. Figure 26-6. UTMI PLL Block Diagram UPLLEN MAINCK UTMI PLL UPLLCK UPLLCOUNT SLCK UTMI PLL Counter LOCKU Whenever the UTMI PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter. The UTMI PLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At this time, the LOCKU bit is set SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 228 in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 229 26.2 Power Management Controller (PMC) 26.2.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core. 26.2.2 Embedded Characteristics The Power Management Controller provides the following clocks: MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently. Processor Clock (PCK), must be switched off when entering the processor in Sleep Mode. The USB Device HS Clock (UDPCK) The Software Modem Clock (SMDCK) Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, HSMCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet. Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 230 26.2.3 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a Master Clock divider which allows the processor clock to be faster than the Master Clock. The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 6. The PRES field in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. Figure 26-7. Master Clock Controller PMC_MCKR CSS PMC_MCKR PRES SLCK MAINCK PLLACK Master Clock Prescaler MCK UPLLCK To the Processor Clock Controller (PCK) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 231 26.2.4 Block Diagram Figure 26-8. General Clock Block Diagram PLLACK /2 PLLADIV2 1 0 USBS UHP48M USBDIV+1 USB OHCI UHP12M /4 USB EHCI PCK Processor Clock Controller UPLLCK Any Peripheral Interrupt Master Clock Controller (PMC_MCKR) MAINCK SLCK CSS Prescaler /1,/2,/3,/4,...,/64 Divider /1, /2, /3, /4 PRES MDIV MCK PMC_PCR Peripherals Clock Controller ON/OFF Divider EN DIV Periph_clk[..] Programmable Clock Controller (PMC_PCKx) SLCK MAINCK ON/OFF Prescaler /1, /2, /4,... /64 UPLLCK MCK CSS pck[..] PRES 26.2.5 Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 232 The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 26.2.6 USB Device and Host Clocks The USB Device and Host High Speed ports (UDPHS and UHPHS) clocks are enabled by corresponding PIDx bits in PMC_PCER. To save power on this peripheral when they are not used, the user can set these bits in the PMC_PCDR. Corresponding PIDx bits in the PMC_PCSR give the status of these clocks. The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB Host OHCI clocks are controlled by the UHP bit in PMC_SCER. To save power on this peripheral when they are not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the status of this clock. The USB host OHCI requires both the 12/48 MHz signal and the Master Clock. The USBDIV field in PMC_USB register is to be programmed to 9 (division by 10) for normal operations. To further reduce power consumption the user can stop UTMI PLL, in this case USB high-speed operations are not possible. Nevertheless, as the USB OHCI Input clock can be selected with USBS bit (PLLA or UTMI PLL) in PMC_USB register, OHCI full-speed operation remains possible. The user must program the USB OHCI Input Clock and the USBDIV divider in the PMC_USB register to generate a 48 MHz and a 12 MHz signal with an accuracy of 0.25%. The USB clock input is to be defined according to Main Oscillator via the FREQ field. It is defined in the UTMI Clock Trimming Register located in the SFR section (see the "Special Function Registers (SFR)" section of this datasheet for details). This input clock can be 12, 16, 24, or 48 MHz. 26.2.7 DDR2/LPDDR/LPDDR2 Clock The Power Management Controller controls the clocks of the DDR memory. The DDR clock can be enabled and disabled with the DDRCK bit respectively in the PMC_SCER and PMC_SDER. At reset, the DDR clock is disabled to save power consumption. In case MDIV = 00, (PCK = MCK), DDRCK clock is not available. To save PLLA power consumption, the user can choose UPLLCK as an Input clock for the system. In this case the DDR Controller can drive LPDDR or LPDDR2 at up to 120 MHz. 26.2.8 Software Modem Clock The Power Management Controller controls the clocks of the Software Modem. SMDCK is a division of UPLL or PLLA. 26.2.9 Peripheral Clock Controller The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The user can individually enable and disable the clock on the peripherals and select a division factor from MCK. This is done with the help of the Peripheral Control Register (PMC_PCR). In order to save power consumption, the division factor can be 1, 2, 4 or 8. The PMC_PCR is a register that features a command and acts like a mailbox. To write the division factor on a particular peripheral, user needs to write a WRITE command, the peripheral ID and the chosen division factor. To read the current division factor on a particular peripheral, user just needs to write the READ command and the peripheral ID. Code Example to select divider 8 for peripheral 2 and enable its clock: write_register(PMC_PCR,0x01030102) Code Example to read the divider of peripheral 4: SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 233 write_register(PMC_PCR,0x00000004) When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Control registers is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 26.2.10 Programmable Clock Output Controller The PMC controls two signals to be outputs on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock (SLCK), the Master Clock (MAINCK), the PLLACK, the UTMI PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR. Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed. 26.2.11 Main Crystal Clock Failure Detector The clock failure detector monitors the 8 to 48 MHz Crystal or Ceramic Resonator-based oscillator to identify an eventual defect of this oscillator (for example, if the crystal is unconnected). The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled. However, if the 8 to 48 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the clock failure detector is disabled too. A failure is detected by means of a counter incrementing on the 8 to 48 MHz Crystal oscillator or Ceramic Resonatorbased oscillator clock edge and timing logic clocked on the slow clock RC oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal is low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is one slow clock RC oscillator clock period. If, during the high level period of the slow clock RC oscillator, less than eight fast crystal oscillator clock periods have been counted, then a failure is declared. The slow RC oscillator must be enabled. The clock failure detection must be enabled only when system clock MCK selects the fast RC oscillator. Then the status register must be read two slow clock cycles after enabling. The clock failure detection must be disabled when the main crystal is disabled. If a failure of the 8 to 48 MHz Crystal or Ceramic Resonator-based oscillator clock is detected, the CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is not masked. The interrupt remains active until a read operation in the PMC_SR. The user can know the status of the clock failure detector at any time by reading the CFDS bit in the PMC_SR. If the 8 to 48 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source clock of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACK or UPLLCK (CSS = 2 or 3), a clock failure detection automatically forces MAINCK to be the source clock for the master clock (MCK).Then, regardless of the PMC configuration, a clock failure detection automatically forces the 4/8/12 MHz Fast RC oscillator to be the source clock for MAINCK. If the Fast RC oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 234 It takes two slow clock RC oscillator cycles to detect and switch from the 8 to 48 MHz Crystal, or Ceramic Resonatorbased oscillator, to the 4/8/12 MHz Fast RC Oscillator if the Master Clock source is Main Clock, or three slow clock RC oscillator cycles if the Master Clock source is PLLACK or UPLLCK. A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller. With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock failure is detected. This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear Register (PMC_FOCR). The user can know the status of the fault output at any time by reading the FOS bit in the PMC_SR. 26.2.12 Programming Sequence 1. If the fast crystal oscillator is not required, PLL can be directly configured (begin with Step 6. or Step 7.) else the fast crystal oscillator must be started (begin with Step 2.). 2. Enabling the fast crystal oscillator: The fast crystal oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register (CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in the MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the user must wait for MOSCXTS field in the PMC_SR to be set. This can be done either by polling MOSCXTS in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (MOSCXTS) has been enabled in the PMC_IER. 3. Switch the MAINCK to the Main Crystal Oscillator by setting MOSCSEL in CKGR_MOR. 4. Wait for the MOSCSELS to be set in PMC_SR to ensure the switchover is complete. 5. Checking the Main Clock Frequency: The Main Clock Frequency can be measured via the Main Clock Frequency Register (CKGR_MCFR). Read the CKGR_MCFR until the MAINFRDY field is set, after which the user can read the MAINF field in CKGR_MCFR by performing an additional read. This provides the number of main clock cycles that have been counted during a period of 16 slow clock cycles. If MAINF = 0, switch the MAINCK to the Fast RC Oscillator by clearing MOSCSEL in CKGR_MOR. If MAINF 0, proceed to Step 6. 6. Setting PLLA and divider (if not required, proceed to Step 7.): All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR. The DIVA field is used to control divider itself. A value between 0 and 255 can be programmed. Divider output is divider input divided by DIVA parameter. By default DIVA parameter is set to 0 which means that divider and PLLA are turned off. The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 127. If MULA is set to 0, PLLA is turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by (MULA + 1). The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR after the CKGR_PLLAR has been written. Once the CKGR_PLLAR has been written, the user must wait for the LOCKA bit to be set in the PMC_SR. This can be done either by polling LOCKA in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKA) has been enabled in the PMC_IER. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage parameter MULA or DIVA is modified, LOCKA bit goes low to indicate that PLLA is not yet ready. When PLLA is locked, LOCKA is set again. If PLLA and divider are enabled, the PLLA input clock is the main clock. PLLA output clock is PLLA input clock multiplied by 5. Once CKGR_PLLAR has been written, LOCKA bit will be set after eight slow clock cycles. Once CKGR_PLLAR is written, the user has to write `3' in the IPLL_PLLA field of the PLL Charge Pump Current Register (PMC_PLLICPR). The user must perform this step before using the PLLA output clock. The user must wait for the LOCKA bit to be set before using the PLLA output clock. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 235 7. Setting Bias and High-speed PLL (UPLL) for UTMI The UTMI PLL is enabled by setting the UPLLEN field in the CKGR_UCKR. The UTMI Bias must is enabled by setting the BIASEN field in the CKGR_UCKR in the same time. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the PLLCOUNT field in the CKGR_UCKR. Once this register has been correctly configured, the user must wait for LOCKU field in the PMC_SR to be set. This can be done either by polling LOCKU in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKU) has been enabled in the PMC_IER. 8. Selecting Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR. The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the selected clock source is the main clock. The PRES field is used to define the Processor Clock and Master Clock prescaler. The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value. The MDIV field is used to define the Master Clock divider. It is possible to choose between different values (0, 1, 2, 3). The Master Clock output is Processor Clock frequency divided by 1, 2, 3 or 4, depending on the value programmed in MDIV. The PMC PLLA Clock input must be divided by 2 by writing the PLLADIV2 bit. By default, MDIV and PLLLADIV2 are set to 0, which indicates that Processor Clock is equal to the Master Clock. Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR. This can be done either by polling MCKRDY in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (MCKRDY) has been enabled in the PMC_IER. The PMC_MCKR must not be programmed in a single write operation. The programming sequence for PMC_MCKR is as follows: If a new value for CSS field corresponds to PLL Clock, Program the PRES field in PMC_MCKR. Wait for the MCKRDY bit to be set in PMC_SR. Program the CSS field in PMC_MCKR. Wait for the MCKRDY bit to be set in PMC_SR. If a new value for CSS field corresponds to Main Clock or Slow Clock, Program the CSS field in PMC_MCKR. Wait for the MCKRDY bit to be set in the PMC_SR. Program the PRES field in PMC_MCKR. Wait for the MCKRDY bit to be set in PMC_SR. If at some stage parameter CSS or PRES is modified, the MCKRDY bit goes low to indicate that the Master Clock and the Processor Clock are not yet ready. The user must wait for the MCKRDY bit to be set again before using the Master and Processor Clocks. Note: If PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCKA goes high and MCKRDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock. For further information, see see Section 26.2.13.2 "Clock Switching Waveforms". Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 236 The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 9. Selecting Programmable Clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR. 3 programmable clocks can be used. The PMC_SCSR indicates which programmable clock is enabled. By default all programmable clocks are disabled. PMC_PCKx registers are used to configure programmable clocks. The CSS field is used to select the programmable clock divider source. Five clock options are available: main clock, slow clock, master clock, PLLACK, UPLLCK. The slow clock is the default clock source. The PRES field is used to control the programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES value is set to 0 which means that PCKx is equal to slow clock. Once the PMC_PCKx register has been configured, The corresponding programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done either by polling PCKRDYx in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (PCKRDYx) has been enabled in the PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be set. 10. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCERx and PMC_PCDRx. 26.2.13 Clock Switching Details 26.2.13.1 Master Clock Switching Timings Table 26-1 and Table 26-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 26-1. Clock Switching Timings (Worst Case) From To Main Clock SLCK Main Clock - 4 x SLCK + 2.5 x Main Clock SLCK 0.5 x Main Clock + 4.5 x SLCK - 3 x PLL Clock + 5 x SLCK PLL Clock 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK Notes: 1. 2. PLL Clock 3 x PLL Clock + 4 x SLCK + 1 x Main Clock PLL designates either the PLLA or the UPLL Clock. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 237 Table 26-2. Clock Switching Timings between Two PLLs (Worst Case) From To PLLA Clock UPLL Clock PLLA Clock 2.5 x PLLA Clock + 4 x SLCK + PLLACOUNT x SLCK 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock UPLL Clock 3 x UPLL Clock + 4 x SLCK + 1.5 x UPLL Clock 2.5 x UPLL Clock + 4 x SLCK + UPLLCOUNT x SLCK 26.2.13.2 Clock Switching Waveforms Figure 26-9. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 238 Figure 26-10.Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 26-11.Change PLLA Programming Slow Clock PLLA Clock LOCKA MCKRDY Master Clock Slow Clock Write CKGR_PLLAR SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 239 Figure 26-12.Programmable Clock Output Programming PLL Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR PLL Clock is selected PCKx is enabled PCKx is disabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 240 26.2.14 Register Write Protection To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be writeprotected by setting the WPEN bit in the PMC Write Protection Mode Register (PMC_WPMR). If a write access to a write-protected register is detected, the WPVS bit in the PMC Write Protection Status Register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PMC_WPSR. The following registers can be protected: PMC System Clock Enable Register PMC System Clock Disable Register PMC Clock Generator Main Clock Frequency Register PMC Clock Generator PLLA Register PMC Master Clock Register PMC USB Clock Register PMC Programmable Clock Register PLL Charge Pump Current Register PMC Peripheral Clock Enable Register 0 PMC Peripheral Clock Disable Register 1 PMC Oscillator Calibration Register SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 241 26.2.15 Power Management Controller (PMC) User Interface Table 26-3. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only - 0x0004 System Clock Disable Register PMC_SCDR Write-only - 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0005 0x000C Reserved - - 0x0010 Peripheral Clock Enable Register 0 PMC_PCER0 Write-only - 0x0014 Peripheral Clock Disable Register 0 PMC_PCDR0 Write-only - 0x0018 Peripheral Clock Status Register 0 PMC_PCSR0 Read-only 0x0000_0000 0x001C UTMI Clock Register CKGR_UCKR Read/Write 0x1020_0000 0x0020 Main Oscillator Register CKGR_MOR Read/Write 0x0100_0001 0x0024 Main Clock Frequency Register CKGR_MCFR Read/Write 0x0000_0000 0x0028 PLLA Register CKGR_PLLAR Read/Write 0x0000_3F00 0x002C Reserved - - 0x0030 Master Clock Register Read/Write 0x0000_0001 0x0034 Reserved - - 0x0038 USB Clock Register PMC_USB Read/Write 0x0000_0000 0x003C Soft Modem Clock Register PMC_SMD Read/Write 0x0000_0000 0x0040 Programmable Clock 0 Register PMC_PCK0 Read/Write 0x0000_0000 0x0044 Programmable Clock 1 Register PMC_PCK1 Read/Write 0x0000_0000 0x0048 Programmable Clock 2 Register PMC_PCK2 Read/Write 0x0000_0000 - - 0x004C-0x005C - - PMC_MCKR - Reserved - 0x0060 Interrupt Enable Register PMC_IER Write-only - 0x0064 Interrupt Disable Register PMC_IDR Write-only - 0x0068 Status Register PMC_SR Read-only 0x0001_0008 0x006C Interrupt Mask Register PMC_IMR Read-only 0x0000_0000 - - Write-only - - - Read/Write 0x0000_0000 - - 0x0070-0x0074 Reserved 0x0078 Fault Output Clear Register 0x007C Reserved 0x0080 PLL Charge Pump Current Register 0x0084-0x00E0 Reserved - PMC_FOCR - PMC_PLLICPR - 0x00E4 Write ProtectIon Mode Register PMC_WPMR Read/Write 0x0000_0000 0x00E8 Write Protection Status Register PMC_WPSR Read-only 0x0000_0000 - - 0x00EC-0x00FC Reserved - 0x0100 Peripheral Clock Enable Register 1 PMC_PCER1 Write-only - 0x0104 Peripheral Clock Disable Register 1 PMC_PCDR1 Write-only - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 242 Table 26-3. Register Mapping Offset Register Name Access Reset 0x0108 Peripheral Clock Status Register 1 PMC_PCSR1 Read-only 0x0000_0000 0x010C Peripheral Control Register PMC_PCR Read/Write 0x0000_0000 0x0110 Oscillator Calibration Register PMC_OCR Read/Write 0x0040_4040 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 243 26.2.15.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 UHP 5 - 4 SMDCK 3 LCDCK 2 DDRCK 1 - 0 - * DDRCK: DDR Clock Enable 0: No effect. 1: Enables the DDR clock. * LCDCK: LCD2x Clock Enable 0: No effect. 1: Enables the LCD2x clock. * SMDCK: SMD Clock Enable 0: No effect. 1: Enables the soft modem clock. * UHP: USB Host OHCI Clocks Enable 0: No effect. 1: Enables the UHP48M and UHP12M OHCI clocks. * UDP: USB Device Clock Enable 0: No effect. 1: Enables the USB Device clock. * PCKx: Programmable Clock x Output Enable 0: No effect. 1: Enables the corresponding Programmable Clock output. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 244 26.2.15.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 UHP 5 - 4 SMDCK 3 LCDCK 2 DDRCK 1 - 0 PCK * PCK: Processor Clock Disable 0: No effect. 1: Disables the Processor clock. This is used to enter the processor in Idle Mode. * DDRCK: DDR Clock Disable 0: No effect. 1: Disables the DDR clock. * LCDCK: LCD2x Clock Disable 0: No effect. 1: Disables the LCD2x clock. * SMDCK: SMD Clock Disable 0: No effect. 1: Disables the soft modem clock. * UHP: USB Host OHCI Clock Disable 0: No effect. 1: Disables the UHP48M and UHP12M OHCI clocks. * UDP: USB Device Clock Enable 0: No effect. 1: Disables the USB Device clock. * PCKx: Programmable Clock x Output Disable 0: No effect. 1: Disables the corresponding Programmable Clock output. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 245 26.2.15.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 UHP 5 - 4 SMDCK 3 LCDCK 2 DDRCK 1 - 0 PCK * PCK: Processor Clock Status 0: The Processor clock is disabled. 1: The Processor clock is enabled. * DDRCK: DDR Clock Status 0: The DDR clock is disabled. 1: The DDR clock is enabled. * LCDCK: LCD2x Clock Status 0: The LCD2x clock is disabled. 1: The LCD2x clock is enabled. * SMDCK: SMD Clock Status 0: The soft modem clock is disabled. 1: The soft modem clock is enabled. * UHP: USB Host Port Clock Status 0: The UHP48M and UHP12M OHCI clocks are disabled. 1: The UHP48M and UHP12M OHCI clocks are enabled. * UDP: USB Device Port Clock Status 0: The USB Device clock is disabled. 1: The USB Device clock is enabled. * PCKx: Programmable Clock x Output Status 0: The corresponding Programmable Clock output is disabled. 1: The corresponding Programmable Clock output is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 246 26.2.15.4 PMC Peripheral Clock Enable Register 0 Name: PMC_PCER0 Address: 0xFFFFFC10 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 - 0 - This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. * PIDx: Peripheral Clock x Enable 0: No effect. 1: Enables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. Other peripherals can be enabled in PMC_PCER1. Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 247 26.2.15.5 PMC Peripheral Clock Disable Register 0 Name: PMC_PCDR0 Address: 0xFFFFFC14 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 - 0 - This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. * PIDx: Peripheral Clock x Disable 0: No effect. 1: Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. Other peripherals can be disabled in PMC_PCDR1. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 248 26.2.15.6 PMC Peripheral Clock Status Register 0 Name: PMC_PCSR0 Address: 0xFFFFFC18 Access: Read-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 - 0 - * PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled. 1: The corresponding peripheral clock is enabled. Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. Other peripherals status can be read in PMC_PCSR1. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 249 26.2.15.7 PMC UTMI Clock Configuration Register Name: CKGR_UCKR Address: 0xFFFFFC1C Access: Read/Write 31 30 29 28 27 - 26 - 25 - 24 BIASEN 21 20 19 - 18 - 17 - 16 UPLLEN BIASCOUNT 23 22 UPLLCOUNT 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - * UPLLEN: UTMI PLL Enable 0: The UTMI PLL is disabled. 1: The UTMI PLL is enabled. When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved. * UPLLCOUNT: UTMI PLL Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time. * BIASEN: UTMI BIAS Enable 0: The UTMI BIAS is disabled. 1: The UTMI BIAS is enabled. * BIASCOUNT: UTMI BIAS Start-up Time Specifies the number of Slow Clock cycles for the UTMI BIAS startup time. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 250 26.2.15.8 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read/Write 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 CFDEN 24 MOSCSEL 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 - 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 - 6 5 0 4 Warning: Bit 4,5,6 must always be set to 0 when programming the CKGR_MOR. * MOSCXTEN: Main Crystal Oscillator Enable A crystal must be connected between XIN and XOUT. 0: The Main Crystal Oscillator is disabled. 1: The Main Crystal Oscillator is enabled. MOSCXTBY must be set to 0. When MOSCXTEN is set, the MOSCXTS flag is set once the Main Crystal Oscillator startup time is achieved. * MOSCXTBY: Main Crystal Oscillator Bypass 0: No effect. 1: The Main Crystal Oscillator is bypassed. MOSCXTEN must be set to 0. An external clock must be connected on XIN. When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set. Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag. * MOSCRCEN: Main On-Chip RC Oscillator Enable 0: The Main On-Chip RC Oscillator is disabled. 1: The Main On-Chip RC Oscillator is enabled. When MOSCRCEN is set, the MOSCRCS flag is set once the Main On-Chip RC Oscillator startup time is achieved. * MOSCXTST: Main Crystal Oscillator Startup Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time. * KEY: Password Value Name 0x37 PASSWD Description Writing any other value in this field aborts the write operation. * MOSCSEL: Main Oscillator Selection 0: The Main On-Chip RC Oscillator is selected. 1: The Main Crystal Oscillator is selected. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 251 * CFDEN: Clock Failure Detector Enable 0: The Clock Failure Detector is disabled. 1: The Clock Failure Detector is enabled. The clock failure detection must be disabled when the main crystal is disabled. The slow RC oscillator must be enabled. The clock failure detection must be enabled only when system clock MCK selects the fast RC oscillator. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 252 26.2.15.9 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 RCMEAS 19 - 18 - 17 - 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF * MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. * MAINFRDY: Main Clock Ready 0: MAINF value is not valid or the Main Oscillator is disabled. 1: The Main Oscillator has been enabled previously and MAINF value is available. Note: To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at 1, then another read access must be performed on the register to obtain a stable value on the MAINF field. * RCMEAS: RC Oscillator Frequency Measure (write-only) 0: No effect. 1: Restarts a measure of the main RC frequency, MAINF will carry the new frequency as soon as a low to high transition occurs on MAINFRDY flag. The measure is performed on the main frequency (i.e., not limited to RC oscillator only) but if the main clock frequency source is the fast crystal oscillator, the restart of the measure is unneeded because of the well known stability of crystal oscillators. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 253 26.2.15.10 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read/Write 31 - 30 - 29 ONE 23 22 21 28 - 27 - 26 - 25 - 20 19 18 17 MULA 15 14 13 24 MULA 16 OUTA 12 11 OUTA 10 9 8 2 1 0 PLLACOUNT 7 6 5 4 3 DIVA Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR. * DIVA: Divider A Value Name Description 0 0 Divider output is 0 1 BYPASS Divider is bypassed 2 - 255 - Divider output is the selected clock divided by DIVA. * PLLACOUNT: PLLA Counter Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written. * OUTA: PLLA Clock Frequency Range To be programmed to 0. * MULA: PLLA Multiplier 0: The PLLA is deactivated. 1 up to 127: The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1. * ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the CKGR_PLLAR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 254 26.2.15.11 PMC Master Clock Register Name: PMC_MCKR Address: 0xFFFFFC30 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 PLLADIV2 11 - 10 - 9 8 7 - 6 5 PRES 4 3 - 2 - 1 MDIV 0 CSS * CSS: Master/Processor Clock Source Selection Value Name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLACK is selected 3 UPLL_CLK UPLL Clock is selected * PRES: Master/Processor Clock Prescaler Value Name Description 0 CLOCK Selected clock 1 CLOCK_DIV2 Selected clock divided by 2 2 CLOCK_DIV4 Selected clock divided by 4 3 CLOCK_DIV8 Selected clock divided by 8 4 CLOCK_DIV16 Selected clock divided by 16 5 CLOCK_DIV32 Selected clock divided by 32 6 CLOCK_DIV64 Selected clock divided by 64 7 Reserved Reserved SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 255 * MDIV: Master Clock Division Value Name 0 EQ_PCK 1 PCK_DIV2 2 PCK_DIV4 3 PCK_DIV3 Description Master Clock is Prescaler Output Clock divided by 1. Warning: SysClk DDR and DDRCK are not available. Master Clock is Prescaler Output Clock divided by 2. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. Master Clock is Prescaler Output Clock divided by 4. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. Master Clock is Prescaler Output Clock divided by 3. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. * PLLADIV2: PLLA Divisor by 2 Bit PLLADIV2 must always be set to 1 when MDIV is set to 3. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 256 26.2.15.12 PMC USB Clock Register Name: PMC_USB Address: 0xFFFFFC38 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 10 9 8 7 - 6 - 5 - 4 - 3 - 1 - 0 USBS USBDIV 2 - * USBS: USB OHCI Input clock selection 0: USB Clock Input is PLLA. 1: USB Clock Input is UPLL. * USBDIV: Divider for USB OHCI Clock. USB Clock is Input clock divided by USBDIV + 1. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 257 26.2.15.13 PMC SMD Clock Register Name: PMC_SMD Address: 0xFFFFFC3C Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 11 10 SMDDIV 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SMDS * SMDS: SMD input clock selection 0: SMD Clock Input is PLLA. 1: SMD Clock Input is UPLL. * SMDDIV: Divider for SMD Clock. SMD Clock is Input clock divided by SMD + 1. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 258 26.2.15.14 PMC Programmable Clock Register Name: PMC_PCKx[x = 0..2] Address: 0xFFFFFC40 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 PRES 4 3 - 2 1 CSS 0 * CSS: Master Clock Source Selection Value Name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLACK is selected 3 UPLL_CLK UPLL Clock is selected 4 MCK_CLK Master Clock is selected * PRES: Programmable Clock Prescaler Value Name Description 0 CLOCK Selected clock 1 CLOCK_DIV2 Selected clock divided by 2 2 CLOCK_DIV4 Selected clock divided by 4 3 CLOCK_DIV8 Selected clock divided by 8 4 CLOCK_DIV16 Selected clock divided by 16 5 CLOCK_DIV32 Selected clock divided by 32 6 CLOCK_DIV64 Selected clock divided by 64 7 Reserved Reserved SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 259 26.2.15.15 PMC Interrupt Enable Register Name: PMC_IER Address: 0xFFFFFC60 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 CFDEV 17 - 16 MOSCSELS 15 - 14 - 13 - 12 - 11 - 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 - 6 LOCKU 5 - 4 - 3 MCKRDY 2 - 1 LOCKA 0 MOSCXTS * MOSCXTS: Main Crystal Oscillator Status Interrupt Enable * LOCKA: PLLA Lock Interrupt Enable * MCKRDY: Master Clock Ready Interrupt Enable * LOCKU: UTMI PLL Lock Interrupt Enable * PCKRDYx: Programmable Clock Ready x Interrupt Enable * MOSCSELS: Main Oscillator Selection Status Interrupt Enable * CFDEV: Clock Failure Detector Event Interrupt Enable SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 260 26.2.15.16 PMC Interrupt Disable Register Name: PMC_IDR Address: 0xFFFFFC64 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 CFDEV 17 - 16 MOSCSELS 15 - 14 - 13 - 12 - 11 - 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 - 6 LOCKU 5 - 4 - 3 MCKRDY 2 - 1 LOCKA 0 MOSCXTS * MOSCXTS: Main Crystal Oscillator Status Interrupt Disable * LOCKA: PLLA Lock Interrupt Disable * MCKRDY: Master Clock Ready Interrupt Disable * LOCKU: UTMI PLL Lock Interrupt Enable * PCKRDYx: Programmable Clock Ready x Interrupt Disable * MOSCSELS: Main Oscillator Selection Status Interrupt Disable * CFDEV: Clock Failure Detector Event Interrupt Disable SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 261 26.2.15.17 PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 FOS 19 CFDS 18 CFDEV 17 - 16 MOSCSELS 15 - 14 - 13 - 12 - 11 - 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 OSCSELS 6 LOCKU 5 - 4 - 3 MCKRDY 2 - 1 LOCKA 0 MOSCXTS * MOSCXTS: Main XTAL Oscillator Status 0: Main XTAL oscillator is not stabilized. 1: Main XTAL oscillator is stabilized. * LOCKA: PLLA Lock Status 0: PLLA is not locked. 1: PLLA is locked. * MCKRDY: Master Clock Status 0: Master Clock is not ready. 1: Master Clock is ready. * LOCKU: UPLL Clock Status 0: UPLL Clock is not ready. 1: UPLL Clock is ready. * OSCSELS: Slow Clock Oscillator Selection 0: Internal slow clock RC oscillator is selected. 1: External slow clock 32 kHz oscillator is selected. * PCKRDYx: Programmable Clock Ready Status 0: Programmable Clock x is not ready. 1: Programmable Clock x is ready. * MOSCSELS: Main Oscillator Selection Status 0: Selection is in progress. 1: Selection is done. * CFDEV: Clock Failure Detector Event 0: No clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 262 1: At least one clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. * CFDS: Clock Failure Detector Status 0: A clock failure of the fast crystal oscillator clock is not detected. 1: A clock failure of the fast crystal oscillator clock is detected. * FOS: Clock Failure Detector Fault Output Status 0: The fault output of the clock failure detector is inactive. 1: The fault output of the clock failure detector is active. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 263 26.2.15.18 PMC Interrupt Mask Register Name: PMC_IMR Address: 0xFFFFFC6C Access: Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 CFDEV 17 - 16 MOSCSELS 15 - 14 - 13 - 12 - 11 - 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 - 6 - 5 - 4 - 3 MCKRDY 2 - 1 LOCKA 0 MOSCXTS * MOSCXTS: Main Crystal Oscillator Status Interrupt Mask * LOCKA: PLLA Lock Interrupt Mask * MCKRDY: Master Clock Ready Interrupt Mask * PCKRDYx: Programmable Clock Ready x Interrupt Mask * MOSCSELS: Main Oscillator Selection Status Interrupt Mask * CFDEV: Clock Failure Detector Event Interrupt Mask SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 264 26.2.15.19 PMC Fault Output Clear Register Name: PMC_FOCR Address: 0xFFFFFC78 Access: Write-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 FOCLR * FOCLR: Fault Output Clear Clears the clock failure detector fault output. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 265 26.2.15.20 PLL Charge Pump Current Register Name: PMC_PLLICPR Address: 0xFFFFFC80 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 15 - 14 - 13 - 12 - 11 - 10 9 IPLL_PLLA 8 7 - 6 - 5 - 4 - 3 - 2 - 1 0 IVCO_PLLU 16 ICP_PLLU ICP_PLLA * ICP_PLLA: Charge Pump Current PLLA To optimize clock performance, this field must be programmed as specified in "PLL A Characteristics" in the Electrical Characteristics section of the product datasheet. * IPLL_PLLA: Engineering Configuration PLLA Should be written to 3. * ICP_PLLU: Charge Pump Current PLL UTMI Should be written to 0. * IVCO_PLLU: Voltage Control Output Current PLL UTMI Should be written to 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 266 26.2.15.21 PMC Write Protection Mode Register Name: PMC_WPMR Address: 0xFFFFFCE4 Access: Read/Write Reset: See Table 26-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 -- 2 -- 1 -- 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 -- 6 -- 5 -- 4 -- * WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x504D43 ("PMC" in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x504D43 ("PMC" in ASCII). See Section 26.2.14 "Register Write Protection" for the list of registers which can be protected. * WPKEY: Write Protect Key Value Name 0x504D43 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 267 26.2.15.22 PMC Write Protection Status Register Name: PMC_WPSR Address: 0xFFFFFCE8 Access: Read-only Reset: See Table 26-3 31 -- 30 -- 29 -- 28 -- 23 22 21 20 27 -- 26 -- 25 -- 24 -- 19 18 17 16 11 10 9 8 3 -- 2 -- 1 -- 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 -- 6 -- 5 -- 4 -- * WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the PMC_WPSR. 1: A Write Protect Violation has occurred since the last read of the PMC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. * WPVSRC: Write Protect Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 268 26.2.15.23 PMC Peripheral Clock Enable Register 1 Name: PMC_PCER1 Address: 0xFFFFFD00 Access: Write-only 31 PID63 30 PID62 29 PID61 28 PID60 27 PID59 26 PID58 25 PID57 24 PID56 23 PID55 22 PID54 21 PID53 20 PID52 19 PID51 18 PID50 17 PID49 16 PID48 15 PID47 14 PID46 13 PID45 12 PID44 11 PID43 10 PID42 9 PID41 8 PID40 7 PID39 6 PID38 5 PID37 4 PID36 3 PID35 2 PID34 1 PID33 0 PID32 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. * PIDx: Peripheral Clock x Enable 0: No effect. 1: Enables the corresponding peripheral clock. Notes: 1. PID32 to PID63 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. 2. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 269 26.2.15.24 PMC Peripheral Clock Disable Register 1 Name: PMC_PCDR1 Address: 0xFFFFFD04 Access: Write-only 31 PID63 30 PID62 29 PID61 28 PID60 27 PID59 26 PID58 25 PID57 24 PID56 23 PID55 22 PID54 21 PID53 20 PID52 19 PID51 18 PID50 17 PID49 16 PID48 15 PID47 14 PID46 13 PID45 12 PID44 11 PID43 10 PID42 9 PID41 8 PID40 7 PID39 6 PID38 5 PID37 4 PID36 3 PID35 2 PID34 1 PID33 0 PID32 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. * PIDx: Peripheral Clock x Disable 0: No effect. 1: Disables the corresponding peripheral clock. Note: PID32 to PID63 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 270 26.2.15.25 PMC Peripheral Clock Status Register 1 Name: PMC_PCSR1 Address: 0xFFFFFD08 Access: Read-only 31 PID63 30 PID62 29 PID61 28 PID60 27 PID59 26 PID58 25 PID57 24 PID56 23 PID55 22 PID54 21 PID53 20 PID52 19 PID51 18 PID50 17 PID49 16 PID48 15 PID47 14 PID46 13 PID45 12 PID44 11 PID43 10 PID42 9 PID41 8 PID40 7 PID39 6 PID38 5 PID37 4 PID36 3 PID35 2 PID34 1 PID33 0 PID32 * PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled. 1: The corresponding peripheral clock is enabled. Note: PID32 to PID63 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 271 26.2.15.26 PMC Peripheral Control Register Name: PMC_PCR Address: 0xFFFFFD0C Access: Read/Write 31 -- 30 -- 29 -- 28 EN 27 -- 26 -- 25 -- 24 -- 23 -- 22 -- 21 -- 20 -- 19 -- 18 -- 17 15 -- 14 -- 13 -- 12 CMD 11 -- 10 -- 9 -- 8 -- 7 -- 6 -- 5 4 3 2 1 0 16 DIV PID * PID: Peripheral ID Peripheral ID selection from PID2 to the maximum PID number. This refers to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. Only the following peripherals can be configured with divided clock (DIV > 0): ADC, SSCx, CANx, USARTx, UARTx, TWIx, SPIx, and TCx." Among the PIDs supporting the divided clock, some require a DIV value configuration matching the maximum peripheral frequency (refer to table "Maximum Values for each Peripheral" in the "Electrical Characteristics" section of datasheet). * CMD: Command 0: Read mode 1: Write mode * DIV: Divisor value Value Name Description 0 PERIPH_DIV_MCK Peripheral clock is MCK 1 PERIPH_DIV2_MCK Peripheral clock is MCK/2 2 PERIPH_DIV4_MCK Peripheral clock is MCK/4 3 PERIPH_DIV8_MCK Peripheral clock is MCK/8 * EN: Enable 0: Selected Peripheral clock is disabled 1: Selected Peripheral clock is enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 272 26.2.15.27 PMC Oscillator Calibration Register Name: PMC_OCR Address: 0xFFFFFD10 Access: Read/Write 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SEL 6 5 4 3 CAL 2 1 0 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. * CAL: 12 MHz RC Oscillator Calibration bits Calibration bits applied to the RC Oscillator when SEL is set. * SEL: Selection of RC Oscillator Calibration bits 0: Factory determined value. 1: Value written by user in CAL field of this register. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 273 27. Parallel Input/Output Controller (PIO) 27.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of the product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. Each I/O line of the PIO Controller features: An input change interrupt enabling level change detection on any I/O line. Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O line. A glitch filter providing rejection of glitches lower than one-half of PIO clock cycle. A debouncing filter providing rejection of unwanted pulses from key or push button operations. Multi-drive capability similar to an open drain I/O line. Control of the pull-up and pull-down of the I/O line. Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 27.2 Embedded Characteristics Up to 32 Programmable I/O Lines Fully Programmable through Set/Clear Registers Multiplexing of Four Peripheral Functions per I/O Line For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O) Input Change Interrupt Programmable Glitch Filter Programmable Debouncing Filter Multi-drive Option Enables Driving in Open Drain Programmable Pull-Up on Each I/O Line Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-Level Lock of the Configuration by the Connected Peripheral Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write Write Protect Registers Programmable Schmitt Trigger Inputs Programmable I/O Drive SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 274 27.3 Block Diagram Figure 27-1. Block Diagram PIO Controller Interrupt Controller PIO Interrupt PIO Clock PMC Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 27-2. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver General Purpose I/Os External Devices SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 275 27.4 Product Dependencies 27.4.1 Pin Multiplexing Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. 27.4.2 External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. 27.4.3 Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch filtering. Note that the input change interrupt, the interrupt modes on a programmable event and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. 27.4.4 Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO Controller requires the Interrupt Controller to be programmed first. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 276 27.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 27-3. In this description each signal shown represents one of up to 32 possible indexes. Figure 27-3. I/O Line Control Logic PIO_OER[0] VDD PIO_OSR[0] PIO_PUER[0] PIO_ODR[0] PIO_PUSR[0] PIO_PUDR[0] 1 Peripheral A Output Enable 00 01 10 11 Peripheral B Output Enable Peripheral C Output Enable Peripheral D Output Enable 0 0 PIO_PER[0] PIO_ABCDSR1[0] PIO_PDR[0] 00 01 10 11 Peripheral B Output Peripheral C Output Peripheral D Output 1 PIO_PSR[0] PIO_ABCDSR2[0] Peripheral A Output Integrated Pull-Up Resistor PIO_MDER[0] PIO_MDSR[0] 0 PIO_MDDR[0] 0 PIO_SODR[0] 1 PIO_ODSR[0] Pad PIO_CODR[0] 1 PIO_PPDER[0] Integrated Pull-Down Resistor PIO_PPDSR[0] PIO_PPDDR[0] GND Peripheral A Input Peripheral B Input Peripheral C Input Peripheral D Input PIO_PDSR[0] PIO_ISR[0] 0 D PIO Clock 0 Slow Clock PIO_SCDR Clock Divider 1 Programmable Glitch or Debouncing Filter Q DFF D Q DFF EVENT DETECTOR (Up to 32 possible inputs) PIO Interrupt 1 Resynchronization Stage PIO_IER[0] PIO_IMR[0] PIO_IFER[0] PIO_IDR[0] PIO_IFSR[0] PIO_IFSCER[0] PIO_IFSCSR[0] PIO_IFSCDR[0] PIO_IFDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 277 27.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing to the Pull-up Enable register (PIO_PUER) or Pull-up Disable register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in the Pull-up Status register (PIO_PUSR). Reading a one in PIO_PUSR means the pull-up is disabled and reading a zero means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing the Pull-down Enable register (PIO_PPDER) or the Pull-down Disable register (PIO_PPDDR), respectively. Writing in these registers results in setting or clearing the corresponding bit in the Pull-down Status register (PIO_PPDSR). Reading a one in PIO_PPDSR means the pull-up is disabled and reading a zero means the pull-down is enabled. Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. In this case, the write of PIO_PUER for the relevant I/O line is discarded. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the pull-downs are disabled, i.e. PIO_PPDSR resets at the value 0xFFFFFFFF. 27.5.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable register (PIO_PER) and the Disable register (PIO_PDR). The Status register (PIO_PSR) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the ABCD Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO Controller. If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns a one for the corresponding bit. After reset, the I/O lines are controlled by the PIO Controller, i.e. PIO_PSR resets at one. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset, or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the device. 27.5.3 Peripheral A or B or C or D Selection The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by writing PIO_ABCDSR1 and PIO_ABCDSR2. For each pin: The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral A is selected. The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral B is selected. The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2 means peripheral C is selected. The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral D is selected. Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are always connected to the pin input. Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2 in addition to a write in PIO_PDR. After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 278 27.5.4 Output Control When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 determines whether the pin is driven or not. When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing the Output Enable register (PIO_OER) and Output Disable register (PIO_ODR). The results of these write operations are detected in the Output Status register (PIO_OSR). When a bit in this register is at zero, the corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the PIO Controller. The level driven on an I/O line can be determined by writing in the Set Output Data register (PIO_SODR) and the Clear Output Data register (PIO_CODR). These write operations, respectively, set and clear the Output Data Status register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 27.5.5 Synchronous Data Output Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by using PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different registers. To overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only bits unmasked by the Output Write Status register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set by writing to the Output Write Enable register (PIO_OWER) and cleared by writing to the Output Write Disable register (PIO_OWDR). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 27.5.6 Multi-Drive Control (Open Drain) Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The multi-drive feature is controlled by the Multi-driver Enable register (PIO_MDER) and the Multi-driver Disable register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or assigned to a peripheral function. The Multi-driver Status register (PIO_MDSR) indicates the pins that are configured to support external drivers. After reset, the multi-drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 27.5.7 Output Line Timings Figure 27-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 27-4 also shows when the feedback in the Pin Data Status register (PIO_PDSR) is available. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 279 Figure 27-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 27.5.8 Inputs The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 27.5.9 Input Glitch and Debouncing Filters Optional input glitch and debouncing filters are independently programmable on each I/O line. The glitch filter can filter a glitch with a duration of less than 1/2 master clock (MCK) and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock. The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock Disable register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable register (PIO_IFSCER). Writing PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status register (PIO_IFSCSR). The current selection status can be checked by reading the register PIO_IFSCSR. If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period. If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable divided slow clock period. For the debouncing filter, the period of the divided slow clock is performed by writing in the DIV field of the Slow Clock Divider register (PIO_SCDR. Tdiv_slclk = ((DIV+1)*2).Tslow_clock When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle (selected clock represents MCK or divided slow clock depending on PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of one selected clock (MCK or divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock cycle and one selected clock cycle, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle. The filters also introduce some latencies, illustrated in Figure 27-5 and Figure 27-6. The glitch filters are controlled by the Input Filter Enable register (PIO_IFER), the Input Filter Disable register (PIO_IFDR) and the Input Filter Status register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 280 When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters require that the PIO Controller clock is enabled. Figure 27-5. Input Glitch Filter Timing PIO_IFCSR = 0 MCK up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles 1 cycle up to 2.5 cycles PIO_PDSR if PIO_IFSR = 1 up to 2 cycles Figure 27-6. Input Debouncing Filter Timing PIO_IFCSR = 1 Divided Slow Clock Pin Level up to 2 cycles Tmck up to 2 cycles Tmck PIO_PDSR if PIO_IFSR = 0 1 cycle Tdiv_slclk PIO_PDSR if PIO_IFSR = 1 1 cycle Tdiv_slclk up to 1.5 cycles Tdiv_slclk up to 1.5 cycles Tdiv_slclk up to 2 cycles Tmck up to 2 cycles Tmck 27.5.10 Input Edge/Level Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level interrupt is controlled by writing the Interrupt Enable register (PIO_IER) and the Interrupt Disable register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and clearing the corresponding bit in the Interrupt Mask register (PIO_IMR). As input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change interrupt is available regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. By default, the interrupt can be generated at any time an edge is detected on the input. Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable register (PIO_AIMER) and Additional Interrupt Modes Disable register (PIO_AIMDR). The current state of this selection can be read through the Additional Interrupt Modes Mask register (PIO_AIMMR). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 281 These additional modes are: Rising edge detection Falling edge detection Low-level detection High-level detection In order to select an additional interrupt mode: The type of event detection (edge or level) must be selected by writing in the Edge Select register (PIO_ESR) and Level Select register (PIO_LSR) which , respectively, the edge and level detection. The current status of this selection is accessible through the Edge/Level Status register (PIO_ELSR). The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the Falling Edge /Low-Level Select register (PIO_FELLSR) and Rising Edge/High-Level Select register (PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high- or low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible through the Fall/Rise - Low/High Status register (PIO_FRLHSR). When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status register (PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a "level", the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed. Figure 27-7. Event Detector on Input Lines (Figure Represents Line 0) Event Detector Rising Edge Detector 1 Falling Edge Detector 0 0 PIO_REHLSR[0] 1 PIO_FRLHSR[0] PIO_FELLSR[0] Resynchronized input on line 0 Event detection on line 0 1 0 High Level Detector 1 Low Level Detector 0 PIO_LSR[0] PIO_ELSR[0] PIO_ESR[0] PIO_AIMER[0] PIO_AIMMR[0] PIO_AIMDR[0] Edge Detector SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 282 27.5.10.1 Example If generating an interrupt is required on the lines below, the configuration required is described in Section 27.5.10.2 "Interrupt Mode Configuration", Section 27.5.10.3 "Edge or Level Detection Configuration" and Section 27.5.10.4 "Falling/Rising Edge or Low/High-Level Detection Configuration": Rising edge on PIO line 0 Falling edge on PIO line 1 Rising edge on PIO line 2 Low-level on PIO line 3 High-level on PIO line 4 High-level on PIO line 5 Falling edge on PIO line 6 Rising edge on PIO line 7 Any edge on the other lines the configuration required is described below. 27.5.10.2 Interrupt Mode Configuration All the interrupt sources are enabled by writing 32'hFFFF_FFFF in PIO_IER. Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32'h0000_00FF in PIO_AIMER. 27.5.10.3 Edge or Level Detection Configuration Lines 3, 4 and 5 are configured in level detection by writing 32'h0000_0038 in PIO_LSR. The other lines are configured in edge detection by default, if they have not been previously configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32'h0000_00C7 in PIO_ESR. 27.5.10.4 Falling/Rising Edge or Low/High-Level Detection Configuration Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing 32'h0000_00B5 in PIO_REHLSR. The other lines are configured in falling edge or low-level detection by default if they have not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in falling edge/low-level detection by writing 32'h0000_004A in PIO_FELLSR. Figure 27-8. Input Change Interrupt Timings When No Additional Interrupt Modes MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 27.5.11 I/O Lines Lock When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become locked by the action of this peripheral via an input of the PIO Controller. When an I/O line is locked, the write of the corresponding bit in PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER, PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime which I/O line is locked by SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 283 reading the PIO Lock Status register (PIO_LOCKSR). Once an I/O line is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller. 27.5.12 Programmable I/O Drive It is possible to configure the I/O drive for pads PA0 to PA31. For any details, refer to the product electrical characteristics. 27.5.13 Programmable Schmitt Trigger It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the Schmitt trigger is requested when using the QTouchTM Library. 27.5.14 Register Write Protection To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be writeprotected by setting the WPEN bit in the "PIO Write Protection Mode Register" (PIO_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the "PIO Write Protection Status Register" (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PIO_WPSR. The following registers can be write-protected: 27.6 "PIO Enable Register" on page 289 "PIO Disable Register" on page 290 "PIO Output Enable Register" on page 292 "PIO Output Disable Register" on page 293 "PIO Input Filter Enable Register" on page 295 "PIO Input Filter Disable Register" on page 296 "PIO Multi-driver Enable Register" on page 306 "PIO Multi-driver Disable Register" on page 307 "PIO Pull-Up Disable Register" on page 309 "PIO Pull-Up Enable Register" on page 310 "PIO Peripheral ABCD Select Register 1" on page 312 "PIO Peripheral ABCD Select Register 2" on page 313 "PIO Output Write Enable Register" on page 321 "PIO Output Write Disable Register" on page 322 "PIO Pad Pull-Down Disable Register" on page 318 "PIO Pad Pull-Down Status Register" on page 320 I/O Lines Programming Example The programming example shown in Table 27-1 is used to obtain the following configuration. 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor, no pulldown resistor Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 284 I/O line 24 to 27 assigned to peripheral C with Input Change Interrupt, no pull-up resistor and no pull-down resistor I/O line 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor Table 27-1. Programming Example Register Value to be Written PIO_PER 0x0000_FFFF PIO_PDR 0xFFFF_0000 PIO_OER 0x0000_00FF PIO_ODR 0xFFFF_FF00 PIO_IFER 0x0000_0F00 PIO_IFDR 0xFFFF_F0FF PIO_SODR 0x0000_0000 PIO_CODR 0x0FFF_FFFF PIO_IER 0x0F00_0F00 PIO_IDR 0xF0FF_F0FF PIO_MDER 0x0000_000F PIO_MDDR 0xFFFF_FFF0 PIO_PUDR 0xFFF0_00F0 PIO_PUER 0x000F_FF0F PIO_PPDDR 0xFF0F_FFFF PIO_PPDER 0x00F0_0000 PIO_ABCDSR1 0xF0F0_0000 PIO_ABCDSR2 0xFF00_0000 PIO_OWER 0x0000_000F PIO_OWDR 0x0FFF_ FFF0 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 285 27.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns one systematically. Table 27-2. Register Mapping Offset Register Name Access Reset 0x0000 PIO Enable Register PIO_PER Write-only - 0x0004 PIO Disable Register PIO_PDR Write-only - Read-only (1) - - 0x0008 PIO Status Register PIO_PSR 0x000C Reserved 0x0010 Output Enable Register PIO_OER Write-only - 0x0014 Output Disable Register PIO_ODR Write-only - 0x0018 Output Status Register PIO_OSR Read-only 0x0000 0000 0x001C Reserved - - 0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only - 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only - 0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000 0x002C Reserved - - 0x0030 Set Output Data Register PIO_SODR Write-only - 0x0034 Clear Output Data Register PIO_CODR Write-only 0x0038 Output Data Status Register PIO_ODSR Read-only or(2) Read/Write - 0x003C Pin Data Status Register PIO_PDSR Read-only (3) 0x0040 Interrupt Enable Register PIO_IER Write-only - 0x0044 Interrupt Disable Register PIO_IDR Write-only - - - - 0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000 0x004C Interrupt Status Register(4) PIO_ISR Read-only 0x00000000 0x0050 Multi-driver Enable Register PIO_MDER Write-only - 0x0054 Multi-driver Disable Register PIO_MDDR Write-only - 0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000 0x005C Reserved - - 0x0060 Pull-up Disable Register PIO_PUDR Write-only - 0x0064 Pull-up Enable Register PIO_PUER Write-only - Read-only (1) - - 0x0068 Pad Pull-up Status Register 0x006C Reserved - PIO_PUSR - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 286 Table 27-2. Register Mapping (Continued) Offset Register Name Access Reset 0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read/Write 0x00000000 0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read/Write 0x00000000 0x0078 to 0x007C Reserved - - - 0x0080 Input Filter Slow Clock Disable Register PIO_IFSCDR Write-only - 0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only - 0x0088 Input Filter Slow Clock Status Register PIO_IFSCSR Read-only 0x00000000 0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read/Write 0x00000000 0x0090 Pad Pull-down Disable Register PIO_PPDDR Write-only - 0x0094 Pad Pull-down Enable Register PIO_PPDER Write-only - Read-only (1) - - 0x0098 Pad Pull-down Status Register PIO_PPDSR 0x009C Reserved 0x00A0 Output Write Enable PIO_OWER Write-only - 0x00A4 Output Write Disable PIO_OWDR Write-only - 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 - 0x00AC Reserved - - 0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER - Write-only - 0x00B4 Additional Interrupt Modes Disable Register PIO_AIMDR Write-only - 0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x00000000 0x00BC Reserved - - 0x00C0 Edge Select Register PIO_ESR Write-only - 0x00C4 Level Select Register PIO_LSR Write-only - 0x00C8 Edge/Level Status Register PIO_ELSR Read-only 0x00000000 - 0x00CC Reserved - - 0x00D0 Falling Edge/Low-Level Select Register PIO_FELLSR - Write-only - 0x00D4 Rising Edge/ High-Level Select Register PIO_REHLSR Write-only - 0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-only 0x00000000 0x00DC Reserved - - 0x00E0 Lock Status PIO_LOCKSR Read-only 0x00000000 0x00E4 Write Protection Mode Register PIO_WPMR Read/Write 0x0 0x00E8 Write Protection Status Register PIO_WPSR Read-only 0x0 0x00EC to 0x00F8 Reserved - - - 0x0100 Schmitt Trigger Register PIO_SCHMITT Read/Write 0x00000000 0x01040x010C Reserved - - - 0x0110 Reserved - - - 0x0114 Reserved - - - - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 287 Table 27-2. Register Mapping (Continued) Offset Register Name Access Reset 0x0118 I/O Drive Register 1 PIO_DRIVER1 Read/Write 0x00000000 0x011C I/O Drive Register 2 PIO_DRIVER2 Read/Write 0x00000000 0x0120 to 0x014C Reserved - - - Notes: 1. Reset value depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. If an offset is not listed in the table it must be considered as reserved. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 288 27.7.1 PIO Enable Register Name: PIO_PER Address: 0xFFFFF200 (PIOA), 0xFFFFF400 (PIOB), 0xFFFFF600 (PIOC), 0xFFFFF800 (PIOD), 0xFFFFFA00 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: PIO Enable 0: No effect. 1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 289 27.7.2 PIO Disable Register Name: PIO_PDR Address: 0xFFFFF204 (PIOA), 0xFFFFF404 (PIOB), 0xFFFFF604 (PIOC), 0xFFFFF804 (PIOD), 0xFFFFFA04 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: PIO Disable 0: No effect. 1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 290 27.7.3 PIO Status Register Name: PIO_PSR Address: 0xFFFFF208 (PIOA), 0xFFFFF408 (PIOB), 0xFFFFF608 (PIOC), 0xFFFFF808 (PIOD), 0xFFFFFA08 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active). 1: PIO is active on the corresponding I/O line (peripheral is inactive). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 291 27.7.4 PIO Output Enable Register Name: PIO_OER Address: 0xFFFFF210 (PIOA), 0xFFFFF410 (PIOB), 0xFFFFF610 (PIOC), 0xFFFFF810 (PIOD), 0xFFFFFA10 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Output Enable 0: No effect. 1: Enables the output on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 292 27.7.5 PIO Output Disable Register Name: PIO_ODR Address: 0xFFFFF214 (PIOA), 0xFFFFF414 (PIOB), 0xFFFFF614 (PIOC), 0xFFFFF814 (PIOD), 0xFFFFFA14 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Output Disable 0: No effect. 1: Disables the output on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 293 27.7.6 PIO Output Status Register Name: PIO_OSR Address: 0xFFFFF218 (PIOA), 0xFFFFF418 (PIOB), 0xFFFFF618 (PIOC), 0xFFFFF818 (PIOD), 0xFFFFFA18 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 294 27.7.7 PIO Input Filter Enable Register Name: PIO_IFER Address: 0xFFFFF220 (PIOA), 0xFFFFF420 (PIOB), 0xFFFFF620 (PIOC), 0xFFFFF820 (PIOD), 0xFFFFFA20 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Input Filter Enable 0: No effect. 1: Enables the input glitch filter on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 295 27.7.8 PIO Input Filter Disable Register Name: PIO_IFDR Address: 0xFFFFF224 (PIOA), 0xFFFFF424 (PIOB), 0xFFFFF624 (PIOC), 0xFFFFF824 (PIOD), 0xFFFFFA24 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Input Filter Disable 0: No effect. 1: Disables the input glitch filter on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 296 27.7.9 PIO Input Filter Status Register Name: PIO_IFSR Address: 0xFFFFF228 (PIOA), 0xFFFFF428 (PIOB), 0xFFFFF628 (PIOC), 0xFFFFF828 (PIOD), 0xFFFFFA28 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line. 1: The input glitch filter is enabled on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 297 27.7.10 PIO Set Output Data Register Name: PIO_SODR Address: 0xFFFFF230 (PIOA), 0xFFFFF430 (PIOB), 0xFFFFF630 (PIOC), 0xFFFFF830 (PIOD), 0xFFFFFA30 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 298 27.7.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0xFFFFF234 (PIOA), 0xFFFFF434 (PIOB), 0xFFFFF634 (PIOC), 0xFFFFF834 (PIOD), 0xFFFFFA34 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Clear Output Data 0: No effect. 1: Clears the data to be driven on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 299 27.7.12 PIO Output Data Status Register Name: PIO_ODSR Address: 0xFFFFF238 (PIOA), 0xFFFFF438 (PIOB), 0xFFFFF638 (PIOC), 0xFFFFF838 (PIOD), 0xFFFFFA38 (PIOE) Access: Read-only or Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Data Status 0: The data to be driven on the I/O line is 0. 1: The data to be driven on the I/O line is 1. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 300 27.7.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0xFFFFF23C (PIOA), 0xFFFFF43C (PIOB), 0xFFFFF63C (PIOC), 0xFFFFF83C (PIOD), 0xFFFFFA3C (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 301 27.7.14 PIO Interrupt Enable Register Name: PIO_IER Address: 0xFFFFF240 (PIOA), 0xFFFFF440 (PIOB), 0xFFFFF640 (PIOC), 0xFFFFF840 (PIOD), 0xFFFFFA40 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Enable 0: No effect. 1: Enables the Input Change interrupt on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 302 27.7.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0xFFFFF244 (PIOA), 0xFFFFF444 (PIOB), 0xFFFFF644 (PIOC), 0xFFFFF844 (PIOD), 0xFFFFFA44 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Disable 0: No effect. 1: Disables the Input Change interrupt on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 303 27.7.16 PIO Interrupt Mask Register Name: PIO_IMR Address: 0xFFFFF248 (PIOA), 0xFFFFF448 (PIOB), 0xFFFFF648 (PIOC), 0xFFFFF848 (PIOD), 0xFFFFFA48 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Mask 0: Input Change interrupt is disabled on the I/O line. 1: Input Change interrupt is enabled on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 304 27.7.17 PIO Interrupt Status Register Name: PIO_ISR Address: 0xFFFFF24C (PIOA), 0xFFFFF44C (PIOB), 0xFFFFF64C (PIOC), 0xFFFFF84C (PIOD), 0xFFFFFA4C (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Status 0: No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1: At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 305 27.7.18 PIO Multi-driver Enable Register Name: PIO_MDER Address: 0xFFFFF250 (PIOA), 0xFFFFF450 (PIOB), 0xFFFFF650 (PIOC), 0xFFFFF850 (PIOD), 0xFFFFFA50 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Multi-Drive Enable 0: No effect. 1: Enables multi-drive on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 306 27.7.19 PIO Multi-driver Disable Register Name: PIO_MDDR Address: 0xFFFFF254 (PIOA), 0xFFFFF454 (PIOB), 0xFFFFF654 (PIOC), 0xFFFFF854 (PIOD), 0xFFFFFA54 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Multi-Drive Disable 0: No effect. 1: Disables multi-drive on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 307 27.7.20 PIO Multi-driver Status Register Name: PIO_MDSR Address: 0xFFFFF258 (PIOA), 0xFFFFF458 (PIOB), 0xFFFFF658 (PIOC), 0xFFFFF858 (PIOD), 0xFFFFFA58 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Multi-Drive Status 0: The multi-drive is disabled on the I/O line. The pin is driven at high- and low-level. 1: The multi-drive is enabled on the I/O line. The pin is driven at low-level only. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 308 27.7.21 PIO Pull-Up Disable Register Name: PIO_PUDR Address: 0xFFFFF260 (PIOA), 0xFFFFF460 (PIOB), 0xFFFFF660 (PIOC), 0xFFFFF860 (PIOD), 0xFFFFFA60 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Pull-Up Disable 0: No effect. 1: Disables the pull-up resistor on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 309 27.7.22 PIO Pull-Up Enable Register Name: PIO_PUER Address: 0xFFFFF264 (PIOA), 0xFFFFF464 (PIOB), 0xFFFFF664 (PIOC), 0xFFFFF864 (PIOD), 0xFFFFFA64 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Pull-Up Enable 0: No effect. 1: Enables the pull-up resistor on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 310 27.7.23 PIO Pull-Up Status Register Name: PIO_PUSR Address: 0xFFFFF268 (PIOA), 0xFFFFF468 (PIOB), 0xFFFFF668 (PIOC), 0xFFFFF868 (PIOD), 0xFFFFFA68 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Pull-Up Status 0: Pull-up resistor is enabled on the I/O line. 1: Pull-up resistor is disabled on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 311 27.7.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Peripheral Select If the same bit is set to 0 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral B function. If the same bit is set to 1 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral C function. 1: Assigns the I/O line to the Peripheral D function. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 312 27.7.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Peripheral Select. If the same bit is set to 0 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral C function. If the same bit is set to 1 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral B function. 1: Assigns the I/O line to the Peripheral D function. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 313 27.7.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Address: 0xFFFFF280 (PIOA), 0xFFFFF480 (PIOB), 0xFFFFF680 (PIOC), 0xFFFFF880 (PIOD), 0xFFFFFA80 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: PIO Clock Glitch Filtering Select 0: No effect. 1: The glitch filter is able to filter glitches with a duration < Tmck/2. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 314 27.7.27 PIO Input Filter Slow Clock Enable Register Name: PIO_IFSCER Address: 0xFFFFF284 (PIOA), 0xFFFFF484 (PIOB), 0xFFFFF684 (PIOC), 0xFFFFF884 (PIOD), 0xFFFFFA84 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Debouncing Filtering Select 0: No effect. 1: The debouncing filter is able to filter pulses with a duration < Tdiv_slclk/2. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 315 27.7.28 PIO Input Filter Slow Clock Status Register Name: PIO_IFSCSR Address: 0xFFFFF288 (PIOA), 0xFFFFF488 (PIOB), 0xFFFFF688 (PIOC), 0xFFFFF888 (PIOD), 0xFFFFFA88 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Glitch or Debouncing Filter Selection Status 0: The glitch filter is able to filter glitches with a duration < Tmck2. 1: The debouncing filter is able to filter pulses with a duration < Tdiv_slclk/2. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 316 27.7.29 PIO Slow Clock Divider Debouncing Register Name: PIO_SCDR Address: 0xFFFFF28C (PIOA), 0xFFFFF48C (PIOB), 0xFFFFF68C (PIOC), 0xFFFFF88C (PIOD), 0xFFFFFA8C (PIOE) Access: Read/Write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - 7 6 2 1 0 DIV 5 4 3 DIV * DIV: Slow Clock Divider Selection for Debouncing Tdiv_slclk = 2*(DIV+1)*Tslow_clock. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 317 27.7.30 PIO Pad Pull-Down Disable Register Name: PIO_PPDDR Address: 0xFFFFF290 (PIOA), 0xFFFFF490 (PIOB), 0xFFFFF690 (PIOC), 0xFFFFF890 (PIOD), 0xFFFFFA90 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Pull-Down Disable 0: No effect. 1: Disables the pull-down resistor on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 318 27.7.31 PIO Pad Pull-Down Enable Register Name: PIO_PPDER Address: 0xFFFFF294 (PIOA), 0xFFFFF494 (PIOB), 0xFFFFF694 (PIOC), 0xFFFFF894 (PIOD), 0xFFFFFA94 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Pull-Down Enable 0: No effect. 1: Enables the pull-down resistor on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 319 27.7.32 PIO Pad Pull-Down Status Register Name: PIO_PPDSR Address: 0xFFFFF298 (PIOA), 0xFFFFF498 (PIOB), 0xFFFFF698 (PIOC), 0xFFFFF898 (PIOD), 0xFFFFFA98 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Pull-Down Status 0: Pull-down resistor is enabled on the I/O line. 1: Pull-down resistor is disabled on the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 320 27.7.33 PIO Output Write Enable Register Name: PIO_OWER Address: 0xFFFFF2A0 (PIOA), 0xFFFFF4A0 (PIOB), 0xFFFFF6A0 (PIOC), 0xFFFFF8A0 (PIOD), 0xFFFFFAA0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Output Write Enable 0: No effect. 1: Enables writing PIO_ODSR for the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 321 27.7.34 PIO Output Write Disable Register Name: PIO_OWDR Address: 0xFFFFF2A4 (PIOA), 0xFFFFF4A4 (PIOB), 0xFFFFF6A4 (PIOC), 0xFFFFF8A4 (PIOD), 0xFFFFFAA4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in "PIO Write Protection Mode Register" . * P0-P31: Output Write Disable 0: No effect. 1: Disables writing PIO_ODSR for the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 322 27.7.35 PIO Output Write Status Register Name: PIO_OWSR Address: 0xFFFFF2A8 (PIOA), 0xFFFFF4A8 (PIOB), 0xFFFFF6A8 (PIOC), 0xFFFFF8A8 (PIOD), 0xFFFFFAA8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Write Status 0: Writing PIO_ODSR does not affect the I/O line. 1: Writing PIO_ODSR affects the I/O line. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 323 27.7.36 PIO Additional Interrupt Modes Enable Register Name: PIO_AIMER Address: 0xFFFFF2B0 (PIOA), 0xFFFFF4B0 (PIOB), 0xFFFFF6B0 (PIOC), 0xFFFFF8B0 (PIOD), 0xFFFFFAB0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Additional Interrupt Modes Enable 0: No effect. 1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 324 27.7.37 PIO Additional Interrupt Modes Disable Register Name: PIO_AIMDR Address: 0xFFFFF2B4 (PIOA), 0xFFFFF4B4 (PIOB), 0xFFFFF6B4 (PIOC), 0xFFFFF8B4 (PIOD), 0xFFFFFAB4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Additional Interrupt Modes Disable 0: No effect. 1: The interrupt mode is set to the default interrupt mode (both-edge detection). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 325 27.7.38 PIO Additional Interrupt Modes Mask Register Name: PIO_AIMMR Address: 0xFFFFF2B8 (PIOA), 0xFFFFF4B8 (PIOB), 0xFFFFF6B8 (PIOC), 0xFFFFF8B8 (PIOD), 0xFFFFFAB8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Peripheral CD Status 0: The interrupt source is a both-edge detection event. 1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 326 27.7.39 PIO Edge Select Register Name: PIO_ESR Address: 0xFFFFF2C0 (PIOA), 0xFFFFF4C0 (PIOB), 0xFFFFF6C0 (PIOC), 0xFFFFF8C0 (PIOD), 0xFFFFFAC0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Edge Interrupt Selection 0: No effect. 1: The interrupt source is an edge-detection event. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 327 27.7.40 PIO Level Select Register Name: PIO_LSR Address: 0xFFFFF2C4 (PIOA), 0xFFFFF4C4 (PIOB), 0xFFFFF6C4 (PIOC), 0xFFFFF8C4 (PIOD), 0xFFFFFAC4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Level Interrupt Selection 0: No effect. 1: The interrupt source is a level-detection event. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 328 27.7.41 PIO Edge/Level Status Register Name: PIO_ELSR Address: 0xFFFFF2C8 (PIOA), 0xFFFFF4C8 (PIOB), 0xFFFFF6C8 (PIOC), 0xFFFFF8C8 (PIOD), 0xFFFFFAC8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Edge/Level Interrupt Source Selection 0: The interrupt source is an edge-detection event. 1: The interrupt source is a level-detection event. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 329 27.7.42 PIO Falling Edge/Low-Level Select Register Name: PIO_FELLSR Address: 0xFFFFF2D0 (PIOA), 0xFFFFF4D0 (PIOB), 0xFFFFF6D0 (PIOC), 0xFFFFF8D0 (PIOD), 0xFFFFFAD0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Falling Edge/Low-Level Interrupt Selection 0: No effect. 1: The interrupt source is set to a falling edge detection or low-level detection event, depending on PIO_ELSR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 330 27.7.43 PIO Rising Edge/High-Level Select Register Name: PIO_REHLSR Address: 0xFFFFF2D4 (PIOA), 0xFFFFF4D4 (PIOB), 0xFFFFF6D4 (PIOC), 0xFFFFF8D4 (PIOD), 0xFFFFFAD4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Rising Edge /High-Level Interrupt Selection 0: No effect. 1: The interrupt source is set to a rising edge detection or high-level detection event, depending on PIO_ELSR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 331 27.7.44 PIO Fall/Rise - Low/High Status Register Name: PIO_FRLHSR Address: 0xFFFFF2D8 (PIOA), 0xFFFFF4D8 (PIOB), 0xFFFFF6D8 (PIOC), 0xFFFFF8D8 (PIOD), 0xFFFFFAD8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Edge /Level Interrupt Source Selection 0: The interrupt source is a falling edge detection (if PIO_ELSR = 0) or low-level detection event (if PIO_ELSR = 1). 1: The interrupt source is a rising edge detection (if PIO_ELSR = 0) or high-level detection event (if PIO_ELSR = 1). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 332 27.7.45 PIO Lock Status Register Name: PIO_LOCKSR Address: 0xFFFFF2E0 (PIOA), 0xFFFFF4E0 (PIOB), 0xFFFFF6E0 (PIOC), 0xFFFFF8E0 (PIOD), 0xFFFFFAE0 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Lock Status 0: The I/O line is not locked. 1: The I/O line is locked. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 333 27.7.46 PIO Write Protection Mode Register Name: PIO_WPMR Address: 0xFFFFF2E4 (PIOA), 0xFFFFF4E4 (PIOB), 0xFFFFF6E4 (PIOC), 0xFFFFF8E4 (PIOD), 0xFFFFFAE4 (PIOE) Access: Read/Write Reset: See Table 27-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 - WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 - 6 5 - - 4 - - - For more information on write-protecting registers, refer to Section 27.5.14 "Register Write Protection". * WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x50494F ("PIO" in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x50494F ("PIO" in ASCII). See Section 27.5.14 "Register Write Protection" for the list of registers that can be protected. * WPKEY: Write Protection Key. Value Name 0x50494F PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 334 27.7.47 PIO Write Protection Status Register Name: PIO_WPSR Address: 0xFFFFF2E8 (PIOA), 0xFFFFF4E8 (PIOB), 0xFFFFF6E8 (PIOC), 0xFFFFF8E8 (PIOD), 0xFFFFFAE8 (PIOE) Access: Read-only Reset: See Table 27-2 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 - WPVS WPVSRC 15 14 13 12 WPVSRC 7 - 6 - 5 - 4 - - - * WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PIO_WPSR register. 1: A write protection violation has occurred since the last read of the PIO_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. * WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 335 27.7.48 PIO Schmitt Trigger Register Name: PIO_SCHMITT Address: 0xFFFFF300 (PIOA), 0xFFFFF500 (PIOB), 0xFFFFF700 (PIOC), 0xFFFFF900 (PIOD), 0xFFFFFB00 (PIOE) Access: Read/Write Reset: See Table 27-2 31 30 29 28 27 26 25 24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 23 22 21 20 19 18 17 16 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 15 14 13 12 11 10 9 8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8 7 6 5 4 3 2 1 0 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0 * SCHMITTx [x=0..31]: Schmitt Trigger Control 0: Schmitt trigger is enabled. 1: Schmitt trigger is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 336 27.7.49 PIO I/O Drive Register 1 Name: PIO_DRIVER1 Address: 0xFFFFF318 (PIOA), 0xFFFFF518 (PIOB), 0xFFFFF718 (PIOC), 0xFFFFF918 (PIOD), 0xFFFFFB18 (PIOE) Access: Read/Write Reset: See Table 27-2 31 30 29 LINE15 23 22 21 LINE11 15 28 14 20 13 19 6 12 5 18 11 17 9 8 LINE4 2 LINE1 16 LINE8 10 3 24 LINE12 LINE5 4 LINE2 25 LINE9 LINE6 LINE3 26 LINE13 LINE10 LINE7 7 27 LINE14 1 0 LINE0 * LINEx [x=0..15]: Drive of PIO Line x Value Name Description 0 LO_DRIVE Low drive 1 LO_DRIVE Low drive 2 ME_DRIVE Medium drive 3 HI_DRIVE High drive SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 337 27.7.50 PIO I/O Drive Register 2 Name: PIO_DRIVER2 Address: 0xFFFFF31C (PIOA), 0xFFFFF51C (PIOB), 0xFFFFF71C (PIOC), 0xFFFFF91C (PIOD), 0xFFFFFB1C (PIOE) Access: Read/Write Reset: See Table 27-2 31 30 29 LINE31 23 22 21 LINE27 15 27 14 20 13 19 6 12 5 18 11 17 9 8 LINE20 2 LINE17 16 LINE24 10 3 24 LINE28 LINE21 4 LINE18 25 LINE25 LINE22 LINE19 26 LINE29 LINE26 LINE23 7 28 LINE30 1 0 LINE16 * LINEx [x=16..31]: Drive of PIO line x Value Name Description 0 LO_DRIVE Low drive 1 LO_DRIVE Low drive 2 ME_DRIVE Medium drive 3 HI_DRIVE High drive SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 338 28. External Memories The product features: Multiport DDR Controller (MPDDRC) External Bus Interface (EBI) that embeds a NAND Flash controller and a Static Memory Controller (HSMC) Figure 28-1. External Memory Controllers MPDDRC Port 3 Port 2 Port 1 Port 0 LPDDR DDR2 LPDDR2-S4 Device EBI NAND Flash Controller NAND Flash Device Static Memory Controller Static Memory Device Bus Matrix MPDDRC is a standalone multi-port DDRSDR controller. It supports only DDR2, LPDDR, and LPDDR2-S4 devices. Its user interface is located at 0xFFFFEA00. HSMC supports Static Memories and MLC/SLC NAND Flashes. It embeds Multi-Bit ECC. Its user interface is located at 0xFFFFC000. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 339 28.1 MPDDRC Multi-port DDRSDR Controller 28.1.1 Description The DDR2 Controller is dedicated to 8-port DDR2/LPDDR/LPDDR2 support. Data transfers are performed through a 32bit data bus on one chip select. The Controller operates with 1.8V Power Supply for DDR2 and LP-DDR, 1.2V Power Supply for LP-DDR2. 28.1.2 Embedded Characteristics 28.1.2.1 DDR2/LPDDR/LPDDR2 Controller Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes Transaction Latency. Supports AHB Transfers: DWord, Word, Half Word, Byte Access. Supports Low-Power DDR2-SDRAM-S4, DDR2-SDRAM, Low-Power DDR1-SDRAM Numerous Configurations Supported 2K, 4K, 8K, 16K Row Address Memory Parts DDR2 with Four or Eight Internal Banks (DDR2_SDRAM/Low-Power DDR2-SDRAM) DDR2/LPDDR with 32-bit Data Path One Chip Select for DDR2/LPDDR Device (512 Mbytes Address Space) Programming Facilities Multibank Ping-pong Access (Up to 4 or 8 Banks Opened at Same Time = Reduces Average Latency of Transactions) Timing Parameters Specified by Software Automatic Refresh Operation, Refresh Rate is Programmable Automatic Update of DS, TCR and PASR Parameters (Low-power DDR-SDRAM Devices) Energy-saving Capabilities Power-up Initialization by Software CAS Latency of 2, 3, 4, 5, 6 supported Reset function supported (DDR2) Auto Precharge Command Not Used On Die Termination not supported OCD mode not supported Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 340 28.1.3 MPDDR Controller Block Diagram Figure 28-2. Organization of the MPDDRC MPDDRC DDR_A0-DDR_A13 DDR_D0-DDR_D31 DDR_CS Bus Matrix DDR_CKE DDR_RAS, DDR_CAS DDR2 LPDDR LPDDR2-S4 Controller AHB DDR_CLK,#DDR_CLK DDR_DQS[3:0] DDR_DQSN[3:0] DDR_DQM[3:0] DDR_WE DDR_BA[2:0] Address Decoders DDR_CALP DDR_CALN DDR_VREF User Interface APB SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 341 28.1.4 I/O Lines Description Table 28-1. DDR2 I/O Lines Description Name Function Type Active Level DDR2/LPDDR Controller VDDIODDR Power Supply of memory interface Input DDR_VREF Reference Voltage for DDR2 operations, typically 0.9V Input DDR_CALP Pad positive calibration reference for LP-DDR2 Input DDR_CALN Pad negative calibration reference for LP-DDR2 Input DDR_D0 - DDR_D31 Data Bus DDR_A0 - DDR_A13 Address Bus Output DDR_DQM0 - DDR_DQM3 Data Mask Output DDR_DQS0 - DDR_DQS3 Data Strobe Output DDR_DQSN0 DDR_DQSN3 Negative Data Strobe Output DDR_CS Chip Select Output DDR_CLK - DDR_CLK# DDR2 Differential Clock Output DDR_CKE Clock enable Output High DDR_RAS Row signal Output Low DDR_CAS Column signal Output Low DDR_WE Write enable Output Low DDR_BA0 - DDR_BA2 Bank Select Output I/O Low In LPDDR2 mode, DQS and DQSN are connected to the LPDDR2 memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 342 28.1.5 Product Dependencies The pins used for interfacing the DDR2 memory are not multiplexed with the PIO lines. Table 28-2. DDR2 I/O Lines Usage vs Operating Modes Signal Name DDR2 Mode LPDDR2 Mode LPDDR DDR_VREF VDDIODDR/2 VDDIODDR/2 VDDIODDR/2 DDR_CALP GND via 200 resistor GND via 240 resistor GND via 200 resistor DDR_CALN VDDIODDR via 200 resistor VDDIODDR via 240 resistor VDDIODDR via 200 resistor DDR_CK, DDR_CKN CLK and CLKN CLK and CLKN CLK and CLKN DDR_CKE CLKE CLKE CLKE DDR_CS CS CS CS DDR_BA[2..0] BA[2..0] BA[2..0] BA[2..0] DDR_WE WE CA2 WE DDR_RAS - DDR_CAS RAS, CAS CA0, CA1 RAS, CAS DDR_A[13..0] A[13:0] CAx, with x>2 A[13:0] DDR_D[31..0] D[31:0] D[31:0] D[31:0] DQS[3..0], DQSN[3..0] DQS[3:0] DQSN connected to DDR_VREF DQS[3:0] DQSN[3:0] DQS[3:0] DQSN connected to DDR_VREF DQM[3..0] DQM[3..0] DQM[3..0] DQM[3..0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 343 28.1.6 Implementation Example The following hardware configuration is given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 28.1.6.1 2x16-bit DDR2 Hardware Configuration Figure 28-3. 2x16-bit DDR2 Hardware Configuration Software Configuration The following configuration has to be performed: Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency. The DDR2 initialization sequence is described in the sub-section "DDR2 Device Initialization" of the DDRSDRC section. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 344 28.1.6.2 2x16-bit LPDDR2 Hardware Configuration Figure 28-4. 2x16-bit LPDDR2 Hardware Configuration CAx LPDDR2 signals are to be connected as indicated in Table 28-3: Table 28-3. CAx LP-DDR2 Signal Connection DDR Controller Signal LP-DDR2 Signal RAS CA0 CAS CA1 WE CA2 DDR_A0 CA3 DDR_A1 CA4 DDR_A2 CA5 DDR_A3 CA6 DDR_A4 CA7 DDR_A5 CA8 DDR_A6 CA9 Higher addresses Higher CAs Software Configuration The following configuration has to be performed: Initialize the DDR2 Controller depending on the LPDDR2 device and system bus frequency. The DDR2 initialization sequence is described in the sub-section "LPDDR2 Device Initialization" of the DDRSDRC section. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 345 28.2 External Bus Interface (EBI) 28.2.1 Description The External Bus Interface is designed to ensure the successful data transfer between several external devices and the ARM processor-based device. The External Bus Interface of the device consists of a Static Memory Controller (HSMC). This HSMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash. The HSMC generates the signals that control the access to external memory devices or peripheral devices. It has 4 Chip Selects and a 26-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The HSMC can manage wait requests from external devices to extend the current access. The HSMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. The HSMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. The HSMC includes programmable hardware error correcting code with one-bit error correction capability and supports two-bit error detection. In order to improve the overall system performance, the DATA phase of the transfer can be DMAassisted. The External Data Bus can be scrambled/unscrambled by means of user keys. The full description is available in the HSMC section. 28.2.1.1 External Bus Interface (EBI) Integrates Two External Memory Controllers: Static Memory Controller SLC/MLC Nand Flash Controller Additional logic for NAND Flash Optional 16-bit External Data Bus Up to 26-bit Address Bus (up to 64 MBytes linear per chip select) Up to 4 chip selects, Configurable Assignment NAND Flash chip select is programmable: 28.2.1.2 Static Memory Controller (HSMC) 64-MByte Address Space per Chip Select 8- or 16-bit Data Bus Word, Halfword, Byte Transfers Byte Write or Byte Select Lines Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select Programmable Data Float Time per Chip Select External Data Bus Scrambling/Unscrambling Function External Wait Request Automatic Switch to Slow Clock Mode NAND Flash Controller Supporting NAND Flash with Multiplexed Data/Address Buses Supports SLC and MLC NAND Flash Technology Programmable Timing on a per Chip Select Basis SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 346 28.2.1.3 NAND Flash Controller (NFC) Programmable Flash Data Width 8 bits or 16 bits. Supports NAND Flash and SmartMediaTM Devices with 8- or 16-bit Data Path. Supports 1-bit Correction for a Page of 512, 1024, 2048 and 4096 Bytes with 8- or 16-bit Data Path. Supports 1-bit Correction per 512 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data Path. Supports 1-bit Correction per 256 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data Path. Multibit Error Correcting Code (ECC) ECC Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes. Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 bits of errors per block. Programmable block size: 512 Bytes or 1024 Bytes. Programmable number of block per page: 1, 2, 4 or 8 blocks of data per page. Programmable spare area size. Supports spare area ECC protection. Supports 8 kBytes page size using 1024 Bytes/block and 4 kBytes page size using 512 Bytes/block. Multibit Error detection is interrupt driven. Provides hardware acceleration for determining roots of polynomials defined over a finite field Programmable finite Field GF(2^13) or GF(2^14) Finds roots of error-locator polynomial. Programmable finite Field GF(2^13) or GF(2^14) Finds roots of error-locator polynomial. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 347 28.2.2 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 28.2.2.1 8-bit NAND Flash Hardware Configuration Software Configuration The following configuration has to be performed: Select the NAND Flash Chip Select by setting the field CSID in NFCADDR_CMD register. Configure the NFC and HSMC according to the used NAND Flash. Enable the NFC with NFCEN bit in HSMC_CTRL register in HSMC User interface. Reserve A21/A22 for ALE/CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bits A21 and A22 during accesses. Configure a PIO line as an input to manage the Ready/Busy signal. Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 348 28.2.2.2 16-bit NAND Flash Hardware Configuration Software Configuration The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 349 28.2.2.3 NOR Flash on NCS0 Hardware Configuration D[0..15] A[1..22] U1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 NRST NWE 3V3 NCS0 NRD 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 12 11 14 13 26 28 RESET WE WP VPP CE OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 AT49BV6416 3V3 VCCQ 47 VCC 37 VSS VSS 46 27 C2 100NF C1 100NF TSOP48 PACKAGE Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 350 29. Multi-port DDR-SDRAM Controller (MPDDRC) 29.1 Description The Multi-port DDR-SDRAM Controller (MPDDRC) is a multi-port memory controller. It comprises four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to DDR-SDRAM protocol. The MPDDRC extends the memory capabilities of a chip by providing the interface to the external 16-bit or 32-bit DDRSDRAM device. The page size support ranges from 2048 to 16384 and the number of columns from 256 to 4096. It supports dword (64-bits), word (32-bit), half-word (16-bit), and byte (8-bit) accesses. The MPDDRC supports a read or write burst length of eight locations. This enables the command and address bus to anticipate the next command, thus reducing latency imposed by the DDR-SDRAM protocol and improving the DDRSDRAM bandwidth. Moreover, MPDDRC keeps track of the active row in each bank, thus maximizing DDR-SDRAM performance, e.g., the application may be placed in one bank and data in other banks. To optimize performance, avoid accessing different rows in the same bank. The MPDDRC supports CAS latency of 2, 3 and optimizes the read access depending on the frequency. Self-refresh, power-down and deep power-down modes minimize the consumption of the DDR-SDRAM device. OCD (Off-chip Driver) and ODT (On-die Termination) modes are not supported. 29.2 Embedded Characteristics Four advanced high performance bus (AHB) interfaces, management of all accesses maximizes memory bandwidth and minimizes transaction latency Bus transfer: word, half word, byte access Bus transfer: dword, word, half word, byte access Supports low-power DDR2-SDRAM-S4 (LPDDR2), DDR2-SDRAM, low-power DDR1-SDRAM (LPDDR1) Numerous configurations supported 2K, 4K, 8K, 16K row address memory parts DDR-SDRAM with four or eight internal banks (DDR2-SDRAM/ low-power DDR2-SDRAM-S4) DDR-SDRAM with 16-bit data path for system oriented word access DDR-SDRAM with 32-bit data path for system oriented dword access One chip select for SDRAM device (512-Mbyte address space) One chip select for SDRAM device (256-Mbyte address space) Programming Facilities Multibank ping-pong access (up to four or eight banks opened at the same time = reduced average latency of transactions) Timing parameters specified by software Automatic refresh operation, refresh rate is programmable Automatic update of DS, TCR and PASR parameters (low-power DDR-SDRAM devices) Energy-saving capabilities Self-refresh, Power-down, active power-down and deep power-down modes supported DDR-SDRAM power-up initialization by software CAS latency of 2,3 supported Reset function supported (DDR2-SDRAM) Auto-refresh per bank supported (low-power DDR2-SDRAM-S4) Automatic adjust refresh rate (low-power DDR2-SDRAM-S4) Auto-precharge command not used OCD (Off-chip Driver) mode, ODT (On-die Termination) are not supported SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 351 29.3 Dynamic Scrambling with user key (no impact on bandwidth) MPDDRC Module Diagram Figure 29-1. MPDDRC Module Diagram AHB MPDDR Controller DDR Controller AHB Slave Interface 0 Input Stage Power Management clk/nclk AHB Slave Interface 1 ras, cas, we, cke Input Stage Output Stage AHB Slave Interface 2 Input Stage Memory Controller Finite State Machine SDRAM Signal Management Addr, DQM DDR-Devices DQS Arbiter Data odt AHB Slave Interface 3 Input Stage Asynchronous Timing Refresh Management Interconnect Matrix APB Interface APB MPDDRC is partitioned in two blocks (see Figure 29-1): the Interconnect Matrix block that manages concurrent accesses on the AHB bus between four AHB masters and integrates an arbiter the DDR controller that translates AHB requests (read/write) in the DDR-SDRAM protocol SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 352 29.4 Product Dependencies, Initialization Sequence 29.4.1 Low-power DDR1-SDRAM Initialization The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the following sequence: 1. Program the memory device type in the MPDDRC Memory Device Register (MPDDRC_MD). 2. Program the features of the low-power DDR1-SDRAM device in the MPDDRC Configuration Register (number of columns, rows, banks, CAS latency and output drive strength) and in the MPDDRC Timing Parameter 0 Register/MPDDRC Timing Parameter 1 Register (asynchronous timing (TRC, TRAS, etc.)). 3. Program Temperature Compensated Self-refresh (TCR), Partial Array Self-refresh (PASR) and Drive Strength (DS) parameters in the MPDDRC Low-power Register. 4. A minimum pause of 200 s is provided to precede any signal toggle. 5. A NOP command is issued to the low-power DDR1-SDRAM. Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR). The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command. The clocks which drive the low-power DDR1-SDRAM device are now enabled. 6. A NOP command is issued to the low-power DDR1-SDRAM. Program the NOP command in the MPDDRC_MR. The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command. A calibration request is now made to the I/O pad. 7. An All Banks Precharge command is issued to the low-power DDR1-SDRAM. Program All Banks Precharge command in the MPDDRC_MR. The application must write a two to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command. 8. Two auto-refresh (CBR) cycles are provided. Program the Auto Refresh command (CBR) in the MPDDRC_MR. The application must write a four to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR1-SDRAM location twice to acknowledge these commands. 9. An Extended Mode Register set (EMRS) cycle is issued to program the low-power DDR1-SDRAM parameters (TCSR, PASR, DS). The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 Mbits SDRAM (12 rows, 9 columns, 4 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00800000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 4 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x08000000. Note: This address is given as an example only. The real address depends on implementation in the product. 10. A Mode Register set (MRS) cycle is issued to program parameters of the DDR1-SDRAM devices, in particular CAS latency and burst length. The application must write a three to the MODE field in the MPDDRC_MR and perform a write access to the low-power DDR1-SDRAM to acknowledge this command. The write address must be chosen so that signals BA[1:0] are set to 0. For example, the SDRAM write access should be done at the address: BASE_ADDRESS_DDR. 11. The application must enter Normal mode, write a zero to the MODE field in the MPDDRC_MR and perform a write access at any location in the low-power DDR1-SDRAM to acknowledge this command. 12. Perform a write access to any low-power DDR1-SDRAM address. 13. Write the refresh rate into the COUNT field in the MPDDRC Refresh Timer Register (MPDDRC_RTR): refresh rate = delay between refresh cycles. The low-power DDR1-SDRAM device requires a refresh every 15.625 s or 7.81 s. With a 100 MHz frequency, MPDDRC_RTR must be set with (15.625 * 100 MHz) = 1562 i.e., 0x061A or (7.81 * 100 MHz) = 781 i.e., 0x030D. After initialization, the low-power DDR1-SDRAM device is fully functional. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 353 29.4.2 DDR2-SDRAM Initialization The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following sequence: 1. Program the memory device type in the MPDDRC Memory Device Register. 2. Program features of the DDR2-SDRAM device in the MPDDRC Configuration Register (number of columns, rows, banks, CAS latency and output driver impedance control) and in the MPDDRC Timing Parameter 0 Register/MPDDRC Timing Parameter 1 Register (asynchronous timing (TRC, TRAS, etc.). 3. A NOP command is issued to the DDR2-SDRAM. Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR). The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2-SDRAM address to acknowledge this command. The clocks which drive the DDR2-SDRAM device are now enabled. 4. A minimum pause of 200 s is provided to precede any signal toggle. 5. A NOP command is issued to the DDR2-SDRAM. Program the NOP command in the MPDDRC_MR. The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2-SDRAM address to acknowledge this command. CKE is now driven high. 6. An All Banks Precharge command is issued to the DDR2-SDRAM. Program All Banks Precharge command in the MPDDRC_MR. The application must write a two to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2-SDRAM address to acknowledge this command. 7. An Extended Mode Register set (EMRS2) cycle is issued to choose between commercial or high temperature operations. The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1 and signal BA[0] is set to 0. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00800000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x08000000. Note: This address is given as an example only. The real address depends on implementation in the product. 8. An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode Register to 0. The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1 and signal BA[0] is set to 1. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00C00000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x0C000000. 9. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL and to program D.I.C. (Output Driver Impedance Control). The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 0 and signal BA[0] is set to 1. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00400000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x04000000. 10. An additional 200 cycles of clock are required for locking DLL 11. Write a one to the DLL bit (enable DLL reset) in the MPDDRC Configuration Register (MPDDRC_CR). 12. A Mode Register set (MRS) cycle is issued to reset DLL. The application must write a three to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signals BA[1:0] are set to 0. For example, the SDRAM write access should be done at the address: BASE_ADDRESS_DDR. 13. An All Banks Precharge command is issued to the DDR2-SDRAM. Program the All Banks Precharge command in the MPDDRC_MR. The application must write a two to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2-SDRAM address to acknowledge this command. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 354 14. Two auto-refresh (CBR) cycles are provided. Program the Auto Refresh command (CBR) in the MPDDRC_MR. The application must write a four to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2SDRAM location twice to acknowledge these commands. 15. Write a zero to the DLL bit (disable DLL reset) in the MPDDRC_CR. 16. A Mode Register set (MRS) cycle is issued to program parameters of the DDR2-SDRAM device, in particular CAS latency and burst length, and to disable DLL reset. The application must write a three to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signals BA[1:0] are set to 0. For example, with a 16-bit 128 Mbits SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address: BASE_ADDRESS_DDR. 17. Write a seven to the OCD field (default OCD calibration) in the MPDDRC_CR. 18. An Extended Mode Register set (EMRS1) cycle is issued to the default OCD value. The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 0 and signal BA[0] is set to 1. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00400000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x04000000. 19. Write a zero to the OCD field (exit OCD calibration mode) in the MPDDRC_CR. 20. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 0 and signal BA[0] is set to 1. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00400000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x04000000. 21. A Normal mode command is provided. Program the normal mode in the MPDDRC_MR and perform a write access to any DDR2-SDRAM address to acknowledge this command. 22. Perform a write access to any DDR2-SDRAM address. 23. Write the refresh rate into the COUNT field in the MPDDRC Refresh Timer Register (MPDDRC_RTR): refresh rate = delay between refresh cycles. The DDR2-SDRAM device requires a refresh every 15.625 s or 7.81 s. With a 133 MHz frequency, the COUNT field in the MPDDRC_RTR must be set with (15.625 * 133 MHz) = 2079 i.e., 0x081F or (7.81 * 133 MHz) = 1039 i.e., 0x040F. After initialization, the DDR2-SDRAM devices are fully functional. 29.4.3 Low-power DDR2-SDRAM Initialization The initialization sequence is generated by software. The low-power DDR2-SDRAM devices are initialized by the following sequence: 1. Program the memory device type in the MPDDRC Memory Device Register. 2. Program features of the low-power DDR2-SDRAM device into and in the MPDDRC Configuration Register (number of columns, rows, banks, CAS latency and output drive strength) and in the MPDDRC Timing Parameter 0 Register/MPDDRC Timing Parameter 0 Register (asynchronous timing, TRC, TRAS, etc.). 3. A NOP command is issued to the low-power DDR2-SDRAM. Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR). The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The clocks which drive the Low-power DDR2-SDRAM devices are now enabled. 4. A minimum pause of 100 ns must be observed to precede any signal toggle. 5. A NOP command is issued to the low-power DDR2-SDRAM. Program the NOP command in the MPDDRC_MR. The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. CKE is now driven high. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 355 6. A minimum pause of 200 s must be satisfied before a Reset command. 7. A Reset command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a 63 to the MRS field. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Reset command is now issued. 8. A minimum pause of 1 s must be satisfied before any commands. 9. A Mode Register Read command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and must write a zero to the MRS field. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode Register Read command is now issued. 10. A minimum pause of 10 s must be satisfied before any commands. 11. A Calibration command is issued to the low-power DDR2-SDRAM. Program the type of calibration in the MPDDRC Configuration Register (MPDDRC_CR): set the ZQ field to the RESET value. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a 10 to the MRS field. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The ZQ Calibration command is now issued. Program the type of calibration in the MPDDRC_CR: set the ZQ field to the SHORT value. 12. A Mode Register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a one to the MRS field. The Mode Register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular burst length. Perform a write access to any low-power DDR2SDRAM address to acknowledge this command. The Mode Register Write command is now issued. 13. A Mode Register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a two to the MRS field. The Mode Register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular CAS latency. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode Register Write command is now issued. 14. A Mode Register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a three to the MRS field. The Mode Register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular Drive Strength and Slew Rate. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode Register Write command is now issued. 15. A Mode Register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a 16 to the MRS field. Mode Register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular Partial Array Self Refresh (PASR). Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode Register Write command is now issued. 16. Write the refresh rate into the COUNT field in the MPDDRC Refresh Timer Register (MPDDRC_RTR): refresh rate = delay between refresh cycles. The low-power DDR2-SDRAM device requires a refresh every 7.81 s. With a 133 MHz frequency, the COUNT field in the MPDDRC_RTR must be set with (7.81 * 133 MHz) = 1039 i.e., 0x040F. After initialization, the low-power DDR2-SDRAM devices are fully functional. 29.5 Functional Description 29.5.1 DDR-SDRAM Controller Write Cycle The MPDDRC provides burst access or single access in normal mode (MODE = 0). Whatever the access type, the MPDDRC keeps track of the active row in each bank, thus maximizing performance. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 356 The DDR-SDRAM device is programmed with a burst length (bl) equal to 8. This determines the length of a sequential data input by the write command that is set to 8. The latency from write command to data input is fixed to 1 in case of the DDR1-SDRAM devices, and it is fixed to 2 in case of DDR2-SDRAM depending on the programmed latency. To initiate a single access, the MPDDRC checks if the page access is already open. If row/bank addresses match with the previous row/bank addresses, the controller generates a write command. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a write command. To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) command. As the burst length is fixed to 8, in case of single access, it has to stop the burst, otherwise seven invalid values may be written. In case of the DDR-SDRAM device, the burst stop command is not supported for the burst write operation. Thus, in order to interrupt the write operation, the DM (data mask) input signal must be set to 1 to mask invalid data (see Figure 29-2 on page 357 and Figure 29-4 on page 358), and DQS must continue to toggle. To initiate a burst access, the MPDDRC controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the DDR-SDRAM device is carried out. If the next access is a write non-sequential access, then an automatic access break is inserted, the MPDDRC generates a precharge command, activates the new row and initiates a write command. To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) commands. For the definition of timing parameters, please refer to Section 29.8.4 "MPDDRC Timing Parameter 0 Register". Write accesses to the DDR-SDRAM device are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given write command. When the write command is issued, eight columns are selected. All accesses for that burst take place within these eight columns, thus the burst wraps within these eight columns if a boundary is reached. These eight columns are selected by addr[13:3]. addr[2:0] is used to select the starting location within the block. In case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the DDRSDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next access is at 0x00. Since the boundary is reached, the burst is wrapped. The MPDDRC takes this feature of the DDR-SDRAM device into account. In case of a transfer starting at address 0x04/0x08/0x0C or starting at address 0x10/0x14/0x18/0x1C, two write commands are issued to avoid wrapping when the boundary is reached. The last write command is subject to DM input logic level. If DM is registered high, the corresponding data input is ignored and the write access is not done. This avoids additional writing. Figure 29-2. Single Write Access, Row Closed, DDR-SDRAM Devices SDCLK Row a A[12:0] COMMAND BA[1:0] NOP PRCHG NOP ACT col a NOP WRITE NOP 00 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da t RP = 2 3 Db t RCD = 2 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 357 Figure 29-3. Single Write Access, Row Closed, DDR2-SDRAM Devices SDCLK Row a A[12:0] COMMAND NOP PRCHG NOP col a ACT NOP WRITE NOP 00 BA[1:0] DQS[1:0] DM[1:0] 3 D[15:0] 0 Da t RP = 2 3 Db t RCD = 2 Figure 29-4. Burst Write Access, Row Closed, DDR-SDRAM Devices SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da t RP = 2 Db Dc Dd 3 De Df Dg Dh t RCD = 2 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 358 Figure 29-5. Burst Write Access, Row Closed, DDR2-SDRAM Devices SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da t RP = 2 Db Dc Dd 3 De Df Dg Dh t RCD = 2 A write command can be followed by a read command. To avoid breaking the current write burst, tWTR/tWRD (bl/2 + 2 = 6 cycles) should be met. See Figure 29-6 on page 359. Figure 29-6. Write Command Followed by a Read Command without Burst Write Interrupt, DDR-SDRAM Devices SDCLK A[12:0] col a COMMAND BA[1:0] NOP col a WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] D[15:0] 3 0 Da 3 Db Dc Dd De Df Dg Dh Da Db t WRD = bl/2 + 2 = 8/2 + 2 = 6 t WR =1 In case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle prior to the read command to avoid writing invalid data. See Figure 29-7 on page 360. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 359 Figure 29-7. SINGLE Write Access followed by a Read Access, DDR-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] col a Row a NOP PRCHG NOP ACT NOP WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] 3 0 D[15:0] 3 Da Db Db Da Data masked Figure 29-8. SINGLE Write Access followed by a Read Access, DDR2-SDRAM Devices SDCLK A[12:0] Row a COMMAND NOP PRCHG NOP BA[1:0] col a ACT NOP WRITE NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da 3 Da Db Db Data masked t WTR 29.5.2 DDR-SDRAM Controller Read Cycle The MPDDRC provides burst access or single access in normal mode (mode = 0). Whatever the access type, the MPDDRC keeps track of the active row in each bank, thus maximizing performance of the MPDDRC. The DDR-SDRAM devices are programmed with a burst length equal to 8 which determines the length of a sequential data output by the read command that is set to 8. The latency from read command to data output is equal to 2, 3. This value is programmed during the initialization phase (see Section 29.4 "Product Dependencies, Initialization Sequence"). To initiate a single access, the MPDDRC checks if the page access is already open. If row/bank addresses match with the previous row/bank addresses, the controller generates a read command. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/read (tRCD) command. After a read command, additional wait states are generated to comply with CAS latency. The MPDDRC supports a CAS latency of two to three (2 to 3 clocks delay). As the burst length is fixed to 8, in case of a single access or a burst access inferior to 8 data requests, it has to stop the burst, otherwise an additional seven or X values could be read. The Burst Stop command (BST) is used to stop output during a burst read. If the DDR2-SDRAM Burst Stop command is not supported by the JEDEC standard, in a single read access, an additional seven unwanted data will be read. To initiate a burst access, the MPDDRC checks the transfer type signal. If the next accesses are sequential read accesses, reading to the SDRAM device is carried out. If the next access is a read non-sequential access, then an SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 360 automatic page break can be inserted. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. If page access is already open, a read command is generated. To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/read (tRCD) commands. The MPDDRC supports a CAS latency of two to three (2 to 3 clocks delay). During this delay, the controller uses internal signals to anticipate the next access and improve the performance of the controller. Depending on the latency, the MPDDRC anticipates two to three read accesses. In case of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy mode, etc.), the next access is treated as an incrementing burst of unspecified length, and depending on the latency, the MPDDRC anticipates two to three read accesses. For the definition of timing parameters, refer to Section 29.8.3 "MPDDRC Configuration Register". Read accesses to the DDR-SDRAM are burst oriented and the burst length is programmed to 8. The burst length determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, eight columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps within these eight columns if the boundary is reached. These eight columns are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block. In case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the DDRSDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next access is 0x00. Since the boundary is reached, the burst wraps. The MPDDRC takes into account this feature of the SDRAM device. In case of the DDR-SDRAM device, transfers start at address 0x04/0x08/0x0C. Two read commands are issued to avoid wrapping when the boundary is reached. The last read command may generate additional reading (1 read cmd = 4 DDR words). To avoid additional reading, it is possible to use the burst stop command to truncate the read burst and to decrease power consumption. The DDR2-SDRAM devices do not support the burst stop command. Figure 29-9. Single Read Access, Row Closed, Latency = 2, DDR-SDRAM Devices SDCLK A[12:0] COMMAND Row a NOP BA[1:0] 0 DM[3:0] 3 PRCHG NOP ACT col a NOP D[31:0] READ BST NOP DaDb t RP t RCD Latency = 2 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 361 Figure 29-10.Single Read Access, Row Closed, Latency = 3, DDR2-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] NOP PRCHG NOP Row a Col a ACT NOP READ 0 DQS[1] DQS[0] DM[1:0] 3 D[15:0] Da t RP t RCD Db Latency = 3 Figure 29-11.Burst Read Access, Latency = 2, DDR-SDRAM Devices SDCLKN SDCLK A[12:0] COMMAND BA[1:0] Col a NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Dc Db Dd De Df Dg Dh Latency = 2 Figure 29-12.Burst Read Access, Latency = 3, DDR2-SDRAM Devices SDCLKN SDCLK A[12:0] COMMAND BA[1:0] Col a NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Dc Dd De Df Dg Dh Latency = 3 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 362 29.5.2.1 All Banks Auto Refresh The All Banks Auto Refresh command performs a refresh operation on all banks. An auto refresh command is used to refresh the MPDDRC. Refresh addresses are generated internally by the DDR-SDRAM device and incremented after each auto-refresh automatically. The MPDDRC generates these auto-refresh commands periodically. A timer is loaded in the MPDDRC_RTR with the value that indicates the number of clock cycles between refresh cycles (see Section 29.8.2 "MPDDRC Refresh Timer Register"). When the MPDDRC initiates a refresh of the DDR-SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the DDR-SDRAM device, the slave indicates that the device is busy. A refresh request does not interrupt a burst transfer in progress. This feature is activated by setting Per-bank Refresh bit (REF_PB) to 0 in the MPDDRC_RTR (see Section 29.8.2 "MPDDRC Refresh Timer Register"). 29.5.2.2 Per-bank Auto Refresh The low-power DDR2-SDRAM embeds a new Per-bank Refresh command which performs a refresh operation on the bank scheduled by the bank counter in the memory device. The Per-bank Refresh command is executed in a fixed sequence order of round-robin type: "0-1-2-3-4-5-6-7-0-1-...". The bank counter is automatically cleared upon issuing a RESET command or when exiting from self-refresh mode, in order to ensure the synchronism between SDRAM memory device and the MPDDRC controller. The bank addressing for the Per-bank Refresh count is the same as established in the Single-bank Precharge command. This feature is activated by setting the Per-bank Refresh bit (REF_PB) to 1 in the MPDDRC_RTR (see Section 29.8.2 "MPDDRC Refresh Timer Register"). This feature masks the latency due to the refresh procedure. The target bank is inaccessible during the Per-bank Refresh cycle period (tRFCpb), however other banks within the device are accessible and may be addressed during the "Per-bank Refresh" cycle. During the REFpb operation, any bank other than the one being refreshed can be maintained in active state or accessed by a read or a write command. When the "Per-bank Refresh" cycle is completed, the affected bank will be in idle state. 29.5.2.3 Adjust Auto Refresh Rate The low-power DDR2-SDRAM embeds an internal register, Mode Register 19 (Refresh Mode). The content of this register allows to adjust the interval of auto-refresh operations according to temperature variation. This feature is activated by setting the Adjust Refresh bit [ADJ_REF] to 1 in the MPDDRC_RTR (see Section 29.8.2 "MPDDRC Refresh Timer Register"). When this feature is enabled, a mode register read command (MRR) is performed every 16 * tREFI (average time between REFRESH commands). Depending on the read value, the auto refresh interval will be modified. In case of high temperature, the interval is reduced and in case of low temperature, the interval is increased. 29.5.3 Power Management 29.5.3.1 Self-refresh Mode This mode is activated by writing a one to the Low-power Command bit (LPCB) in the MPDDRC_LPR register. Self-refresh mode is used in power-down mode, i.e., when no access to the DDR-SDRAM device is possible. In this case, power consumption is very low. In self-refresh mode, the DDR-SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto refresh cycles. During self-refresh period CKE is driven low. As soon as the DDR-SDRAM device is selected, the MPDDRC provides a sequence of commands and exits self-refresh mode. The MPDDRC re-enables self-refresh mode as soon as the DDR-SDRAM device is not selected. It is possible to define when self-refresh mode is to be enabled by configuring the TIMEOUT field in the MPDDRC_LPR register: 0: Self-refresh mode is enabled as soon as the DDR-SDRAM device is not selected. 1: Self-refresh mode is enabled 64 clock cycles after completion of the last access. 2: Self-refresh mode is enabled 128 clock cycles after completion of the last access. This controller also interfaces the low-power DDR-SDRAM. To optimize power consumption, the Low Power DDR SDRAM provides programmable self-refresh options comprised of Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array). Disabled banks are not refreshed in self-refresh mode. This feature permits to reduce the self-refresh current. In case of low-power DDR1-SDRAM, the Extended Mode register controls this feature. It includes Temperature Compensated Selfrefresh (TSCR) and Partial Array Self-refresh (PASR) parameters and the drive strength (DS) (see Section 29.8.7 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 363 "MPDDRC Low-power Register"). In case of low-power DDR2-SDRAM, the mode registers 16 and 17 control this feature, including PASR Bank Mask (BK_MASK) and PASR Segment Mask (SEG_MASK) parameters and drives strength (DS) (see Section 29.8.8 "MPDDRC Low-power DDR2 Low-power Register" on page 388). These parameters are set during the initialization phase. After initialization, as soon as the PASR/DS/TCSR fields or BK_MASK/SEG_MASK/DS are modified, the memory device Extended Mode Register or Mode Registers 3/16/17 are automatically accessed. Thus if MPDDRC does not share an external bus with another controller, PASR/DS/TCSR and BK_MASK/SEG_MASK/DS bits are updated before entering self-refresh mode or during a refresh command. If MPDDRC does share an external bus with another controller, PASR/DS/TCSR and BK_MASK/SEG_MASK/DS bits are also updated during a pending read or write access. This type of update is a function of the UPD_MR bit (see Section 29.8.7 "MPDDRC Low-power Register"). The low-power DDR1-SDRAM must remain in self-refresh mode during the minimum of TRFC periods (see Section 29.8.5 "MPDDRC Timing Parameter 1 Register"), and may remain in self-refresh mode for an indefinite period. The DDR2-SDRAM must remain in self-refresh mode during the minimum of tCKE periods (see the memory device datasheet), and may remain in self-refresh mode for an indefinite period. The low-power DDR2-SDRAM must remain in self-refresh mode for the minimum of tCKESR periods (see the memory device datasheet) and may remain in self-refresh mode for an indefinite period. Figure 29-13.Self-refresh Mode Entry, Time-out = 0 SDCK A[12:0] NOP READ COMMAND BST NOP PRCHG NOP ARFSH NOP CKE BA[1:0] 0 DQS[0:1] DM[1:0] 3 D[15:0] Da Db t RP Enter Self-refresh Mode Figure 29-14.Self-refresh Mode Entry, Time-out = 1 or 2 SDCLK A[12:0] COMMAND NOP READ BST NOP PRCHG NOP ARFSH NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] D[15:0] 3 Da Db 64 or 128 Wait states t RP Enter Self-refresh Mode SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 364 Figure 29-15.Self-refresh Mode Exit SDCLK A[12:0] COMMAND NOP VALID NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Exit Self-refresh Mode Clock must be stable before exiting self-refresh mode t XNRD / t XSRD t XSR (DDR device) (Low-power DDR device) 29.5.3.2 Power-down Mode This mode is activated by writing a 10 to the Low-power Command bit (LPCB). Power-down mode is used when no access to the DDR-SDRAM device is possible. In this mode, power consumption is greater than in self-refresh mode. This state is similar to normal mode (no low-power mode/no self-refresh mode), but the CKE pin is low and the input and output buffers are deactivated as soon the DDR-SDRAM device is no longer accessible. In contrast to self-refresh mode, the DDR-SDRAM device cannot remain in low-power mode longer than one refresh period (64 ms). As no auto-refresh operations are performed in this mode, the MPDDRC carries out the refresh operation. For DDR1-SDRAM, in order to exit low-power mode, a NOP command is required. For the low-power DDR1SDRAM devices, a NOP command must be generated for a minimum period defined in the TXP field of the MPDDRC Timing Parameter 1 Register. In addition, low-power DDR-SDRAM and DDR2-SDRAM must remain in power-down mode for a minimum period corresponding to tCKE (see the memory device datasheet). The exit procedure is faster than in self-refresh mode. See Figure 29-16 on page 366. The MPDDRC returns to powerdown mode as soon as the DDR-SDRAM device is not selected. It is possible to define when power-down mode is enabled by configuring the TIMEOUT field in the MPDDRC_LPR register: 0: Power-down mode is enabled as soon as the DDR-SDRAM device is not selected. 1: Power-down mode is enabled 64 clock cycles after completion of the last access. 2: Power-down mode is enabled 128 clock cycles after completion of the last access. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 365 Figure 29-16.Power-down Entry/Exit, Time-out = 0 SDCK A[12:0] COMMAND READ BST NOP READ CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Exit Power-down Mode Enter Power-down Mode 29.5.3.3 Deep Power-down Mode The deep power-down mode is a feature of low-power DDR-SDRAM. When this mode is activated, all internal voltage generators inside the device are stopped and all data is lost. Deep power-down mode is activated by writing a three to the Low-power Command bit (LPCB). When this mode is enabled, the MPDDRC leaves normal mode (mode = 0) and the controller is frozen. Before enabling this mode, the user must assume there is no access in progress. To exit deep power-down mode, the Low-power Command bit (LPCB) must be written to zero and the initialization sequence must be generated by software. See Section 29.4.1 "Low-power DDR1-SDRAM Initialization" or Section 29.4.3 "Low-power DDR2-SDRAM Initialization". Figure 29-17.Deep Power-down Mode Entry SDCLK A[12:0] COMMAND NOP READ BST NOP PRCHG NOP DEEPOWER NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] D[15:0] 3 Da Db t RP Enter Deep Power-down Mode 29.5.3.4 Change Frequency During Power-down Mode with Low-power DDR2-SDRAM Devices To change frequency, power-down mode must be activated by writing a two to the Low-power Command bit (LPCB) and a one to the Change Frequency Command bit (CHG_FR) in the MPDDRC Low-power Register. Once the low-power DDR2-SDRAM is in precharge power-down mode, the clock frequency may change. The device input clock frequency changes only within minimum and maximum operating frequencies as specified by low-power DDR2-SDRAM providers. Once the input clock frequency is changed, new stable clocks must be provided to the device before exiting from the precharge power-down mode. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 366 Depending on the new clock frequency, the user can change the CAS latency in the user interface. (See "CAS: CAS Latency" on page 378.) It is recommended to check that no access is in progress. Once the controller detects a change of latency during the change frequency procedure, a Load Mode Register command is performed. During a change frequency procedure, the Change Frequency Command bit (CHG_FR) is set to 0 automatically. 29.5.3.5 Reset Mode The reset mode is a feature of DDR2-SDRAM. This mode is activated by writing a three to the Low-power Command bit (LPCB) and a one to the Clock Frozen Command bit (CLK_FR) in the MPDDRC Low-power Register. When this mode is enabled, the MPDDRC leaves normal mode (mode = 0) and the controller is frozen. Before enabling this mode, the user must assume there is no access in progress. To exit reset mode, the Low-power Command bit (LPCB) must be written to zero, the Clock Frozen Command bit (CLK_FR) must be written to zero and the initialization sequence must be generated by software. (See Section 29.4.2 "DDR2-SDRAM Initialization"). 29.5.4 Multi-port Functionality The DDR-SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing system performance. An access to DDR-SDRAM is performed if banks and rows are open (or active). To activate a row in a particular bank, the last open row must be deactivated and a new row must be open. Two DDR-SDRAM commands must be performed to open a bank: Precharge command and Activate command with respect to tRP timing. Before performing a read or write command, tRCD timing must be checked. This operation generates a significant bandwidth loss (see Figure 29-18.). Figure 29-18.tRP and tRCD Timings SDCK A[12:0] COMMAND BA[1:0] NOP PRCHG NOP ACT NOP READ BST NOP 0 DQS[1:0] DM1:0] 3 D[15:0] Da t RP t RCD Db Latency = 2 4 cycles before performing a read command SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 367 The multi-port controller is designed to mask these timings and thus improve the bandwidth of the system. The MPDDRC is a multi-port controller whereby four masters can simultaneously reach the controller. This feature improves the bandwidth of the system because it can detect four requests on the AHB slave inputs and thus anticipate the commands that follow, Precharge command and Activate command in bank X during the current access in bank Y. This masks tRP and tRCD timings (see Figure 29-19). In the best case, all accesses are done as if the banks and rows were already open. The best condition is met when the four masters work in different banks. In the case of four simultaneous read accesses, when the four or eight banks and associated rows are open, the controller reads with a continuous flow and masks the CAS latency for each access. To allow a continuous flow, the read command must be set at 2 or 3 cycles (CAS latency) before the end of the current access. The arbitration scheme must be changed since the round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus a master with a high priority arises before the end of the current access, then this master will not be serviced. Figure 29-19.Anticipate Precharge/Activate Command in Bank 2 during Read Access in Bank 1 SDCK A[12:0] COMMAND BA[1:0] NOP 0 READ PRECH 1 NOP ACT READ 2 NOP 1 DQS[1:0] DM1:0] 3 D[15:0] Da Db Dc Dd De Df Dg Dh Di Dj Dk Dl t RP Anticipate command, Precharge/Active Bank 2 Read Access in Bank 1 The arbitration mechanism reduces latency when a conflict occurs, that is when two or more masters try to access the DDR-SDRAM device at the same time. The arbitration type is round-robin arbitration. This algorithm dispatches requests from different masters to the DDRSDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is serviced first, then the others are serviced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput for the DDR-SDRAM device, arbitration must only take place during the following cycles: 1. Idle cycles: when no master is connected to the DDR-SDRAM device. 2. Single cycles: when a slave is currently performing a single access. 3. End of Burst cycles: when the current cycle is the last cycle of a burst transfer. 4. 29.6 For bursts of defined length, predicted end of burst matches the size of the transfer. For bursts of undefined length, predicted end of burst is generated at the end of each four-beat boundary inside the INCR transfer. Anticipated Access: when an anticipated read access is done while the current access is not complete, the arbitration scheme can be changed if the anticipated access is not the next access serviced by the arbitration scheme. Scrambling/Unscrambling Function The external data bus can be scrambled in order to prevent intellectual property data located in off-chip memories from being easily recovered by analyzing data at the package pin level of either the microcontroller or the memory device. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 368 The scrambling and unscrambling are performed on-the-fly without additional wait states. The scrambling method depends on two user-configurable key registers, MPDDRC_KEY1 in the "MPDDRC OCMS KEY1 Register" and MPDDRC_KEY2 in the "MPDDRC OCMS KEY2 Register" . These key registers are only accessible in write mode. The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost. The scrambling/unscrambling function can be enabled or disabled by programming the "MPDDRC OCMS Register" . 29.7 Software Interface/SDRAM Organization, Address Mapping The DDR-SDRAM address space is organized into banks, rows and columns. The MPDDRC maps different memory types depending on values set in the MPDDRC Configuration Register (see Section 29.8.3 "MPDDRC Configuration Register"). The tables that follow illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths. The MPDDRC supports address mapping in linear mode. Sequential mode is a method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank. Interleaved mode is a method for address mapping where banks alternate at each SDRAM end page of the current bank. The MPDDRC makes the DDR-SDRAM device access protocol transparent to the user. The tables that follow illustrate the DDR-SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated. 29.7.1 DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width Table 29-1. Sequential Mapping for DDR-SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 Bk[1:0] 15 14 13 12 11 10 9 8 7 Row[10:0] Bk[1:0] 4 3 2 1 M0 M0 Column[10:0] Row[10:0] 0 M0 Column[9:0] Row[10:0] Bk[1:0] 5 Column[8:0] Row[10:0] Bk[1:0] 6 M0 Column[11:0] Table 29-2. Interleaved Mapping for DDR-SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[10:0] Row[10:0] 10 Bk[1:0] Row[10:0] Row[10:0] 11 Bk[1:0] Bk[1:0] Bk[1:0] 9 8 7 6 5 4 3 2 Column[8:0] Column[9:0] Column[10:0] 1 0 M0 M0 M0 M0 Column[11:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 369 Table 29-3. Sequential Mapping for DDR-SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 7 Row[11:0] Bk[1:0] 4 3 2 1 M0 M0 Column[10:0] Row[11:0] 0 M0 Column[9:0] Row[11:0] Bk[1:0] 5 Column[8:0] Row[11:0] Bk[1:0] 6 M0 Column[11:0] Table 29-4. Interleaved Mapping for DDR-SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[11:0] 11 10 9 8 7 Bk[1:0] Row[11:0] 4 3 2 1 M0 M0 Column[10:0] Bk[1:0] 0 M0 Column[9:0] Bk[1:0] Row[11:0] 5 Column[8:0] Bk[1:0] Row[11:0] 6 M0 Column[11:0] Table 29-5. Sequential Mapping for DDR-SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 7 Row[12:0] Bk[1:0] 4 3 2 1 M0 M0 Column[10:0] Row[12:0] 0 M0 Column[9:0] Row[12:0] Bk[1:0] 5 Column[8:0] Row[12:0] Bk[1:0] 6 M0 Column[11:0] Table 29-6. Interleaved Mapping for DDR-SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[12:0] 11 10 9 8 7 Bk[1:0] Row[12:0] 4 3 2 1 M0 M0 Column[10:0] Bk[1:0] 0 M0 Column[9:0] Bk[1:0] Row[12:0] 5 Column[8:0] Bk[1:0] Row[12:0] 6 M0 Column[11:0] Table 29-7. Sequential Mapping for DDR-SDRAM Configuration: 16K Rows, 512/1024/2048 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 Bk[1:0] Bk[1:0] Bk[1:0] 17 16 Row[13:0] Row[13:0] Row[13:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Column[8:0] Column[9:0] Column[10:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 1 0 M0 M0 M0 370 Table 29-8. Interleaved Mapping for DDR-SDRAM Configuration: 16K Rows, 512/1024/2048 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[13:0] 11 10 9 8 7 Bk[1:0] Row[13:0] 5 4 3 2 1 M0 Column[9:0] Bk[1:0] 0 M0 Column[8:0] Bk[1:0] Row[13:0] 6 M0 Column[10:0] Table 29-9. Sequential Mapping for DDR-SDRAM Configuration: 8K Rows,1024/ Columns, 8 banks CPU Address Line 27 26 25 24 23 22 21 20 19 Bk[2:0] 18 17 16 15 14 13 12 11 10 9 8 7 Row[12:0] 6 5 4 3 2 1 0 M0 Column[9:0] Table 29-10. Interleaved Mapping for DDR-SDRAM Configuration: 8K Rows,1024/ Columns, 8 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Row[12:0] 12 11 10 9 8 7 Bk[2:0] 6 5 4 3 2 1 0 M0 Column[9:0] Table 29-11. Sequential Mapping for DDR-SDRAM Configuration: 16K Rows,1024/ Columns, 8 banks CPU Address Line 27 26 25 24 23 22 21 20 19 Bk[2:0] 18 17 16 15 14 13 12 11 10 9 8 7 Row[13:0] 6 5 4 3 2 1 0 M0 Column[9:0] Table 29-12. Interleaved Mapping for DDR-SDRAM Configuration: 16K Rows,1024/ Columns, 8 banks CPU Address Line 27 26 25 24 23 22 21 20 Row[13:0] 19 18 17 16 15 14 13 12 Bk[2:0] 11 10 9 8 7 6 5 4 3 2 Column[9:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 1 0 M0 371 29.7.2 DDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width Table 29-13. Sequential Mapping DDR-SDRAM Configuration Mapping: 2K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 Row[10:0] Bk[1:0] 6 5 4 3 2 Column[8:0] Row[10:0] Bk[1:0] 7 0 M[1:0] Column[9:0] Row[10:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-14. Interleaved Mapping DDR-SDRAM Configuration Mapping: 2K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Row[10:0] 12 11 10 9 8 Bk[1:0] Row[10:0] 6 5 4 3 2 Column[8:0] Bk[1:0] Row[10:0] 7 0 M[1:0] Column[9:0] Bk[1:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-15. Sequential Mapping DDR-SDRAM Configuration Mapping: 4K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 17 16 15 14 13 12 11 10 9 8 Row[11:0] Bk[1:0] 6 5 4 3 2 Column[8:0] Row[11:0] Bk[1:0] 7 0 M[1:0] Column[9:0] Row[11:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-16. Interleaved Mapping DDR-SDRAM Configuration Mapping: 4K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Row[11:0] 12 11 10 9 8 Bk[1:0] Row[11:0] 6 5 4 3 2 Column[8:0] Bk[1:0] Row[11:0] 7 0 M[1:0] Column[9:0] Bk[1:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-17. Sequential Mapping DDR-SDRAM Configuration Mapping: 8K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 17 16 15 14 13 12 11 10 9 8 Row[12:0] Bk[1:0] 6 5 4 3 2 Column[8:0] Row[12:0] Bk[1:0] 7 0 M[1:0] Column[9:0] Row[12:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-18. Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Row[13:0] Row[13:0] Row[13:0] 12 11 Bk[1:0] Bk[1:0] Bk[1:0] 10 9 8 7 6 5 4 3 2 Column[8:0] Column[9:0] Column[10:0] 1 0 M[1:0] M[1:0] M[1:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 372 Table 29-19. Sequential Mapping DDR-SDRAM Configuration Mapping: 8K Rows /1024 Columns, 8 banks CPU Address Line 28 27 26 25 24 23 22 21 20 Bk[2:0] 19 18 17 16 15 14 13 12 11 10 9 8 Row[12:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-20. Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows /1024 Columns, 8 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 Row[12:0] 13 12 11 10 9 8 Bk[2:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-21. Sequential Mapping DDR-SDRAM Configuration Mapping: 16K Rows /1024 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 Bk[1:0] 19 18 17 16 15 14 13 12 11 10 9 8 Row[13:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-22. Interleaved Mapping DDR-SDRAM Configuration Mapping: 16K Rows /1024 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 Row[13:0] 13 12 11 10 9 8 Bk[1:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-23. Sequential Mapping DDR-SDRAM Configuration Mapping: 16K Rows /1024 Columns, 8 banks CPU Address Line 28 27 26 25 24 23 22 21 20 Bk[2:0] 19 18 17 16 15 14 13 12 11 10 9 8 Row[13:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-24. Interleaved Mapping DDR-SDRAM Configuration Mapping: 16K Rows /1024 Columns, 8 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 Row[13:0] 15 14 13 Bk[2:0] 12 11 10 9 8 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Notes: 1. M[1:0] is the byte address inside a 32-bit word. 2. Bk[2] = BA2, Bk[1] = BA1, Bk[0] = BA0 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 373 29.8 AHB Multi-port DDR-SDRAM Controller (MPDDRC) User Interface The User Interface is connected to the APB bus. The MPDDRC is programmed using the registers listed in Table 29-25. Table 29-25. Register Mapping Offset Register Name Access Reset 0x00 MPDDRC Mode Register MPDDRC_MR Read/Write 0x00000000 0x04 MPDDRC Refresh Timer Register MPDDRC_RTR Read/Write 0x00000000 0x08 MPDDRC Configuration Register MPDDRC_CR Read/Write 0x024 0x0C MPDDRC Timing Parameter 0 Register MPDDRC_TPR0 Read/Write 0x20227225 0x10 MPDDRC Timing Parameter 1 Register MPDDRC_TPR1 Read/Write 0x3C80808 0x14 MPDDRC Timing Parameter 2 Register MPDDRC_TPR2 Read/Write 0x00042062 0x18 Reserved - - 0x1C MPDDRC Low-power Register MPDDRC_LPR Read/Write 0x0 0x20 MPDDRC Memory Device Register MPDDRC_MD Read/Write 0x10 0x24 MPDDRC High Speed Register MPDDRC_HS Read/Write 0x00000000 0x28 MPDDRC LPDDR2 Low-power Register MPDDRC_LPDDR2_LPR Read/Write 0x00000000 0x2C MPDDRC LPDDR2 Calibration and MR4 Register MPDDRC_LPDDR2_CAL_MR4 Read/Write 0x00000000 0x30 MPDDRC LPDDR2 Timing Calibration Register MPDDRC_LPDDR2_TIM_CAL Read/Write 0x040 0x34 MPDDRC IO Calibration MPDDRC_IO_CALIBR Read/Write 0x00870002 0x38 MPDDRC OCMS Register MPDDRC_OCMS Read/Write 0x00000000 0x3C MPDDRC OCMS KEY1 Register MPDDRC_OCMS_KEY1 Write-only 0x00000000 0x40 MPDDRC OCMS KEY2 Register MPDDRC_OCMS_KEY2 Write-only 0x00000000 0x44-0x70 Reserved - - - 0x74 MPDDRC DLL Master Offset Register MPDDRC_DLL_MO Read/Write 0x-(1) 0x78 MPDDRC DLL Slave Offset Register MPDDRC_DLL_SOF Read/Write 0x-(1) 0x7C MPDDRC DLL Status Master Register MPDDRC_DLL_MS Read-only 0x00000000 0x80 MPDDRC DLL Status Slave 0 Register MPDDRC_DLL_SS0 Read-only 0x00000000 0x84 MPDDRC DLL Status Slave 1 Register MPDDRC_DLL_SS1 Read-only 0x00000000 0x88 MPDDRC DLL Status Slave 2 Register MPDDRC_DLL_SS2 Read-only 0x00000000 0x8C MPDDRC DLL Status Slave 3 Register MPDDRC_DLL_SS3 Read-only 0x00000000 0x94xE0 Reserved - - - 0xE4 MPDDRC Write Protect Control Register MPDDRC_WPMR Read/Write 0x00000000 0xE8 MPDDRC Write Protect Status Register MPDDRC_WPSR Read-only 0x00000000 0x158-0x1CC Reserved - - - 0x1DC-0x1F8 Reserved - - - Note: - 1. Values in the DLL Master Offset Register and in the DLL Slave Offset Register vary with the product implementation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 374 29.8.1 MPDDRC Mode Register Name: MPDDRC_MR Address: 0xFFFFEA00 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 2 1 0 MRS 7 6 5 4 3 - - - - - MODE * MODE: MPDDRC Command Mode This field defines the command issued by the MPDDRC when the SDRAM device is accessed. This register is used to initialize the SDRAM device and to activate deep power-down mode. Value Name Description 0 NORMAL_CMD Normal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 1 NOP_CMD The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 2 PRCGALL_CMD 3 LMR_CMD 4 RFSH_CMD 5 The MPDDRC issues the All Banks Precharge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. The MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDRSDRAM. The MPDDRC issues an Auto-Refresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Precharge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed EXT_LMR_CMD regardless of the cycle. To activate this mode, the command must be followed by a write to the DDRSDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. 6 DEEP_CMD 7 LPDDR2_CMD Deep power mode: Access to deep power-down mode The MPDDRC issues an LPDDR2 Mode Register command when the low-power DDR2-SDRAM device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR2-SDRAM. * MRS: Mode Register Select LPDDR2 Configure this 8-bit field to program all mode registers included in the low-power DDR2-SDRAM device. This field is unique to the low-power DDR2-SDRAM devices. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 375 29.8.2 MPDDRC Refresh Timer Register Name: MPDDRC_RTR Address: 0xFFFFEA04 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - REF_PB ADJ_REF 11 10 9 8 1 0 MR4_VALUE 15 14 13 12 - - - - 7 6 5 4 COUNT 3 2 COUNT * COUNT: MPDDRC Refresh Timer Count This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh sequence is initiated. The SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the MPDDRC clock frequency (MCK: Master Clock) and the number of rows in the device. For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of the COUNT field is configured: ((64 x 10)/8192) x 100 x 106 = 781 or 0x030D. 3 The low-power DDR2-SDRAM devices support Per Bank Refresh operation. In this configuration, average time between refresh command is 0.975 s. The value of the COUNT field is configured depending on this value. For example, the value of a 100 MHz Master clock refresh timer is 98 or 0x0062. * ADJ_REF: Adjust Refresh Rate Reset value is 0. 0: Adjust refresh rate is not enabled. 1: Adjust refresh rate is enabled. This mode is unique to the low-power DDR2-SDRAM devices. * REF_PB: Refresh Per Bank Reset value is 0. 0: Refresh all banks during auto-refresh operation. 1: Refresh the scheduled bank by the bank counter in the memory interface. This mode is unique to the low-power DDR2-SDRAM devices. * MR4_VALUE: Content of MR4 Register Reset value is 3. This field (read-only) gives the content of MR4 register. This field is updated when MRR command is generated and Adjust Refresh Rate bit is enabled. Update is done when read value is different from MR4_VALUE. LP-DDR2 JEDEC memory standards impose derating LP-DDR2 AC timings (tRCD, tRC, tRAS, tRP and tRRD) when the value of MR4 is equal to 6. If the application needs to work in extreme conditions, the derating value must be added to AC timings before the power up sequence. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 376 This mode is unique to the low-power DDR2-SDRAM devices. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 377 29.8.3 MPDDRC Configuration Register Name: MPDDRC_CR Address: 0xFFFFEA08 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 - - - - - - - - 19 18 17 16 - ENRDM DQMS 23 22 21 20 UNAL DECOD NDQS NB 15 14 13 12 - 11 OCD 7 6 5 DLL 10 ZQ 4 3 CAS 2 NR 9 8 DIS_DLL DIC_DS 1 0 NC * NC: Number of Column Bits Reset value is 9 column bits. Value Name Description 0 9_COL_BITS 9 bit to define the column number, up to 512 column 1 10_COL_BITS 10 bit to define the column number, up to 1024 columns 2 11_COL_BITS 11 bit to define the column number, up to 2048 columns 3 12_COL_BITS 12 bit to define the column number, up to 4096 columns * NR: Number of Row Bits Reset value is 12 row bits. Value Name 0 11_ROW_BITS Description 11 bit to define the row number, up to 2048 rows 1 12_ROW_BITS 12 bit to define the row number, up to 4096 rows 2 13_ROW_BITS 13 bit to define the row number, up to 8192 rows 3 14_ROW_BITS 14 bit to define the row number, up to 16384 rows * CAS: CAS Latency Reset value is 2 cycles. Value Name Description 2 DDR_CAS2 LPDDR1 CAS Latency 2 3 DDR_CAS3 DDR2/LPDDR2/LPDDR1 CAS Latency 3 * DLL: Reset DLL Reset value is 0. This bit defines the value of Reset DLL. 0 (RESET_DISABLED): Disable DLL reset. 1 (RESET_ENABLED): Enable DLL reset. This value is used during the power-up sequence. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 378 This bit is found only in the DDR2-SDRAM devices. * DIC_DS: Output Driver Impedance Control (Drive Strength) Reset value is 0. This bit name is described as "DS" in some memory datasheets. It defines the output drive strength. This value is used during the power-up sequence. Value Name Description 0 DDR2_NORMALSTRENGTH Normal driver strength 1 DDR2_WEAKSTRENGTH Weak driver strength This bit is found only in the DDR2-SDRAM devices. * DIS_DLL: DISABLE DLL Reset value is 0. 0: Enable DLL. 1: Disable DLL. This value is used during the power-up sequence. It is only found in the DDR2-SDRAM devices. * ZQ: ZQ Calibration Reset value is 0. Value Name Description 0 INIT 1 LONG Long calibration Calibration command after initialization 2 SHORT Short calibration 3 RESET ZQ Reset This parameter is used to calibrate DRAM On resistance (Ron) values over PVT. This field is found only in the low-power DDR2-SDRAM devices. * OCD: Off-chip Driver Reset value is 7. Note: SDRAM Controller supports only two values for OCD (default calibration and exit from calibration). These values MUST always be programmed during the initialization sequence. The default calibration must be programmed first, after which the exit calibration and maintain settings must be programmed. This field is found only in the DDR2-SDRAM devices. Value Name 0 DDR2_EXITCALIB 7 DDR2_DEFAULT_CALI B Description Exit from OCD calibration mode and maintain settings OCD calibration default * DQMS: Mask Data is Shared Reset value is 0. 0 (NOT_SHARED): DQM is not shared with another controller. 1 (SHARED): DQM is shared with another controller. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 379 * ENRDM: Enable Read Measure Reset value is 0. 0 (OFF): DQS/DDR_DATA phase error correction is disabled. 1 (ON): DQS/DDR_DATA phase error correction is enabled. * NB: Number of Banks Reset value is 4 banks. If LC_LPDDR1 is set to 1, NB is not relevant. Value Name Description 0 4_BANKS 4 banks memory devices 1 8_BANKS 8 banks. Only possible when using the DDR2-SDRAM and low-power DDR2-SDRAM devices. * NDQS: Not DQS Reset value is 1; not DQS is disabled. 0: (ENABLED) Not DQS is enabled. 1: (DISABLED) Not DQS is disabled. This field is found only in the DDR2-SDRAM devices. * DECOD: Type of Decoding Reset value is 0. Value Name Description 0 SEQUENTIAL Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank. 1 INTERLEAVED Method for address mapping where banks alternate at each SDRAM end page of the current bank. * UNAL: Support Unaligned Access Reset value is 0; unaligned access is not supported. 0 (UNSUPPORTED): Unaligned access is not supported. 1 (SUPPORTED): Unaligned access is supported. This mode is enabled with masters which have an AXI interface. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 380 29.8.4 MPDDRC Timing Parameter 0 Register Name: MPDDRC_TPR0 Address: 0xFFFFEA0C Access: Read/Write Reset: See Table 29-25 31 30 29 28 TMRD 23 22 27 26 21 20 19 14 18 13 6 17 16 9 8 1 0 TRP 12 11 10 TRC 7 24 TWTR TRRD 15 25 RDC_WRRD TWR 5 TRCD 4 3 2 TRAS * TRAS: Active to Precharge Delay Reset value is 5 SDCK(1) clock cycles. This field defines the delay between an Activate command and a Precharge command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. * TRCD: Row to Column Delay Reset value is 2 SDCK(1) clock cycles. This field defines the delay between an Activate command and a Read/Write command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. * TWR: Write Recovery Delay Reset value is 2 SDCK(1) clock cycles. This field defines the Write Recovery Time in number of SDCK(1) clock cycles. The number of cycles is between 1 and 15. * TRC: Row Cycle Delay Reset value is 7 SDCK(1) clock cycles. This field defines the delay between an Activate command and Refresh command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15 * TRP: Row Precharge Delay Reset value is 2 SDCK(1) clock cycles. This field defines the delay between a Precharge command and another command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. * TRRD: Active BankA to Active BankB Reset value is 2 SDCK(1) clock cycles. This field defines the delay between an Activate command in BankA and an Activate command in BankB in number of SDCK(1) clock cycles. The number of cycles is between 1 and 15. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 381 * TWTR: Internal Write to Read Delay Reset value is 0. This field defines the internal Write to Read command time in number of SDCK(1) clock cycles. The number of cycles is between 1 and 7. * RDC_WRRD: Reduce Write to Read Delay Reset value is 0. This field reduces the delay between write to read access for the low-power DDR-SDRAM devices with a latency equal to 2. To use this feature, the TWTR field must be equal to 0. Note that some devices do not support this feature. * TMRD: Load Mode Register Command to Activate or Refresh Command Reset value is 2 SDCK(1) clock cycles. This field defines the delay between a Load mode register command and an Activate or Refresh command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. For low-power DDR2-SDRAM, this field is equivalent to TMRW timing. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 382 29.8.5 MPDDRC Timing Parameter 1 Register Name: MPDDRC_TPR1 Address: 0xFFFFEA10 Access: Read/Write Reset: See Table 29-25 31 30 29 28 - - - - 23 22 21 20 27 26 25 24 TXP 19 18 17 16 11 10 9 8 2 1 0 TXSRD 15 14 13 12 TXSNR 7 6 5 - - - 4 3 TRFC * TRFC: Row Cycle Delay Reset value is 8 SDCK(1) clock cycles. This field defines the delay between a Refresh command or a Refresh and Activate command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 31. In case of low-power DDR2-SDRAM, this field is equivalent to tRFCab timing. If the user enables the function "Refresh Per Bank" (see "REF_PB: Refresh Per Bank" on page 376), this field is equivalent to tRFCpb. * TXSNR: Exit Self-refresh Delay to Non Read Command Reset value is 8 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Non Read command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 255. This field is used by the DDR-SDRAM devices. In case of low-power DDR-SDRAM, this field is equivalent to tXSR timing. * TXSRD: Exit Self-refresh Delay to Read Command Reset value is 200 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Read command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 255. This field is found only in the DDR2-SDRAM devices . * TXP: Exit Power-down Delay to First Command Reset value is 3 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Valid command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 383 29.8.6 MPDDRC Timing Parameter 2 Register Name: MPDDRC_TPR2 Address: 0xFFFFEA14 Access: Read/Write Reset: See Table 29-25 31 30 - - 23 22 29 28 27 26 21 20 19 18 25 24 17 16 9 8 1 0 TFAW 15 14 13 12 11 10 TRTP 7 6 5 TRPA 4 3 2 TXARDS TXARD * TXARD: Exit Active Power Down Delay to Read Command in Mode "Fast Exit" Reset value is 2 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Read command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. This field is found only in the DDR2-SDRAM devices. * TXARDS: Exit Active Power Down Delay to Read Command in Mode "Slow Exit" Reset value is 6 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Read command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. This field is found only in the DDR2-SDRAM devices. * TRPA: Row Precharge All Delay Reset value is 0 SDCK(1) clock cycles. This field defines the delay between a Precharge All Banks command and another command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. This field is found only in the DDR2-SDRAM devices. * TRTP: Read to Precharge Reset value is 2 SDCK(1) clock cycles. This field defines the delay between Read command and a Precharge command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 7. * TFAW: Four Active Windows Reset value is 4 SDCK(1) clock cycles. DDR2 devices with eight banks (1 Gbit or larger) have an additional requirement concerning tFAW timing. This requires that no more than four Activate commands may be issued in any given tFAW (MIN) period. The number of cycles is between 0 and 15. This field is found only in the DDR2-SDRAM and LPDDR2-SDRAM devices. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 384 29.8.7 MPDDRC Low-power Register Name: MPDDRC_LPR Address: 0xFFFFEA1C Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - APDE 15 14 11 10 9 8 - - 7 6 - UPD_MR 13 12 TIMEOUT 5 - 4 PASR DS 3 2 LPDDR2_PWOFF CLK_FR 1 0 LPCB * LPCB: Low-power Command Bit Reset value is 0. Value Name Description 0 NOLOWPOWER Low-power feature is inhibited. No power-down, self-refresh and deep-power modes are issued to the DDR-SDRAM device. 1 SELFREFRESH The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the self-refresh mode when accessed and reenters it after the access. 2 POWERDOWN The MPDDRC issues a Power-down command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the power-down mode when accessed and reenters it after the access. 3 DEEPPOWERDOWN The MPDDRC issues a Deep Power-down command to the low-power DDR-SDRAM device. * CLK_FR: Clock Frozen Command Bit Reset value is 0. This field sets the clock low during power-down mode. Some DDR-SDRAM devices do not support freezing the clock during power-down mode. Refer to the device datasheet for details. 0 (DISABLED): Clock(s) is/are not frozen. 1 (ENABLED): Clock(s) is/are frozen. * LPDDR2_PWOFF: LPDDR2 Power Off Bit Reset value is 0. LPDDR2 power off sequence must be controlled to preserve the LPDDR2 device. The power failure is handled at system level (IRQ or FIQ) and the LPDDR2 power off sequence is applied using the LPDDR2_PWOFF bit. LPDDR2_PWOFF bit is used to impose CKE low before a power off sequence. Uncontrolled power off sequence can be applied only up to 400 times in the life of a LPDDR2 device. 1 (ENABLED): A power off sequence is applied to the LPDDR2 device. CKE is forced low. 0 (DISABLED): No power off sequence applied to LPDDR2. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 385 * PASR: Partial Array Self-refresh Reset value is 0. This field is unique to low-power DDR1-SDRAM. It is used to specify whether only one-quarter, one-half or all banks of the DDRSDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. The values of this field are dependant on the low-power DDR-SDRAM devices. After the initialization sequence, as soon as the PASR field is modified, the Extended Mode Register in the external device memory is accessed automatically and PASR bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. * DS: Drive Strength Reset value is 0. This field is unique to low-power DDR-SDRAM. It selects the driver strength of the DDR- SDRAM output. After the initialization sequence, as soon as the DS field is modified, the Extended Mode Register is accessed automatically and DS bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. * TIMEOUT: Time Between Last Transfer and Low Power Mode Reset value is 0. This field defines when low-power mode is activated. Value Name Description 0 NONE SDRAM low-power mode is activated immediately after the end of the last transfer. 1 DELAY_64_CLK SDRAM low-power mode is activated 64 clock cycles after the end of the last transfer. 2 DELAY_128_CLK SDRAM low-power mode is activated 128 clock cycles after the end of the last transfer. * APDE: Active Power Down Exit Time Reset value is 1. This mode is unique to the DDR2-SDRAM devices. This mode manages the active power-down mode which determines performance versus power saving. Value Name Description 0 DDR2_FAST_EXIT Fast Exit from Power Down. The DDR2-SDRAM devices only. 1 DDR2_SLOW_EXIT Slow Exit from Power Down. The DDR2-SDRAM devices only. After the initialization sequence, as soon as the APDE field is modified, the Extended Mode Register (located in the memory of the external device) is accessed automatically and APDE bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access * UPD_MR: Update Load Mode Register and Extended Mode Register Reset value is 0. This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This update is function of DDRSDRC integration in a system. DDRSDRC can either share or not, an external bus with another controller. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 386 Value Name Description 0 NO_UPDATE 1 UPDATE_SHAREDBUS DDRSDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device. 2 UPDATE_NOSHAREDBUS DDRSDRC does not share an external bus. Automatic update is done before entering in selfrefresh mode. Update of Load Mode and Extended Mode registers is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 387 29.8.8 MPDDRC Low-power DDR2 Low-power Register Name: MPDDRC_LPDDR2_LPR Address: 0xFFFFEA28 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 DS 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 SEG_MASK 15 14 13 12 SEG_MASK 7 6 5 4 BK_MASK_PASR * BK_MASK_PASR: Bank Mask Bit/PASR Partial Array Self-Refresh (the low-power DDR2-SDRAM-S4 devices only) Reset value is 0. After the initialization sequence, as soon as the BK_MASK_PASR field is modified, Mode Register 16 is accessed automatically and BK_MASK_PASR bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. 0: Refresh is enabled (= unmasked). 1: Refresh is disabled (= masked). This mode is unique to the low-power DDR2-SDRAM-S4 devices. In self-refresh mode, each bank of LPDDR2 can be independently configured whether a self-refresh operation is taking place or not. After the initialization sequence, as soon as the BK_MASK_PASR field is modified, the Extended Mode Register is accessed automatically and BK_MASK_PASR bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. * SEG_MASK: Segment Mask Bit Reset value is 0. After the initialization sequence, as soon as the SEG_MASK field is modified, Mode Register 17 is accessed automatically and SEG_MASK bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. 0: Segment is refreshed (= unmasked). 1: Segment is not refreshed (= masked). This mode is unique to the low-power DDR2-SDRAM-S4 devices. The number of Segment Mask bits differs with the density. For 1 Gbit density, 8 segments are used. In self-refresh mode, when the Segment Mask bit is configured, the refresh operation is masked in the segment. * DS: Drive strength Reset value is 0. After the initialization sequence, as soon as the DS field is modified, Mode Register 3 is accessed automatically and DS bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 388 This field is unique to low-power DDR2-SDRAM. It selects the driver strength of DDR2-SDRAM I/O. * SR: Slew Rate Reset value is 0. After the initialization sequence, as soon as the SR field is modified, Mode Register 3 is accessed automatically and SR bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access This field is unique to low-power DDR2-SDRAM. It selects the slew rate of low-power DDR2-SDRAM I/O. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 389 29.8.9 MPDDRC Low-power DDR2 Calibration and MR4 Register Name: MPDDRC_LPDDR2_CAL_MR4 Address: 0xFFFFEA2C Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MR4_READ 23 22 21 20 MR4_READ 15 14 13 12 COUNT_CAL 7 6 5 4 COUNT_CAL * COUNT_CAL: LPDDR2 Calibration Timer Count This 16-bit field is loaded into a timer which generates the calibration pulse. Each time the calibration pulse is generated, a ZQCS calibration sequence is initiated. The ZQCS Calibration command is used to calibrate DRAM Ron values over PVT. One method for calculating the interval between ZQCS commands gives the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application. The interval could be defined by the following formula: ZQCorrection/((TSens x Tdriftrate) + (VSens x Vdriftrate)) Where TSens = max(dRONdTM) and VSens = max(dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 0.75%/C, VSens = 0.2%/mV, Tdriftrate = 1C/sec and Vdriftrate = 15 mV/s, then the interval between ZQCS commands is calculated as: 1.5/((0.75 x 1) + (0.2 x 15)) = 0.4s In this example, the LPDDR2-SDRAM devices require a calibration every 0.4s. The value to be loaded depends on average time between REFRESH commands, tREF. For example, for an LPDDR2-SDRAM with the time between refresh of 7.8 s, the value of the Calibration Timer Count field is programmed: (0.4/7.8 x 10-6) = 0xC852. * MR4_READ: Mode Register 4 Read Interval MR4_READ defines the time period between MR4 reads (for LPDDR2-SDRAM). The formula is (MR4_READ+1) * tREF. The value to be loaded depends on the average time between REFRESH commands, tREF. For example, for an LPDDR2-SDRAM with the time between refresh of 7.8 s, if the MR4_READ value is 2, the time period between MR4 reads is 23.4 s. The LPDDR2-SDRAM devices feature a temperature sensor whose status can be read from MR4 register. This sensor can be used to determine an appropriate refresh rate. Temperature sensor data may be read from MR4 register using the Mode Register Read protocol. The Adjust Refresh Rate bit (ADJ_REF) in the Refresh Timer Register (MPDDRC_RTR) must be written to a one to activate these reads. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 390 29.8.10 MPDDRC Low-power DDR2 Timing Calibration Register Name: MPDDRC_LPDDR2_TIM_CAL Address: 0xFFFFEA30 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ZQCS * ZQCS: ZQ Calibration Short Reset value is 6 SDCK(1) clock cycles This field defines the delay between ZQ Calibration command and any Valid commands in number of SDCK(1) clock cycles. The number of cycles is between 0 and 255. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 391 29.8.11 MPDDRC I/O Calibration Register Name: MPDDRC_IO_CALIBR Address: 0xFFFFEA34 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 9 8 CALCODEN CALCODEP 15 14 13 12 11 - - - - - 7 6 5 4 3 - - - - - 10 TZQIO 2 1 0 RDIV * RDIV: Resistor Divider, Output Driver Impedance Reset value is 2. This corresponds to 40 ohms. With the LPDDR2-SDRAM device, the RDIV field must be equal to the DS (Drive Strength) field (see "DS: Drive Strength" on page 386). RDIV is used with the external precision resistor RZQ to define the output driver impedance. The value of RZQ is either 240 ohms (LPDDR2 mode) or 200 ohms (the DDR2/LPDDR1 device). Value Name 1 RZQ_34 2 RZQ_40_RZQ_33_3 3 RZQ_48_RZQ_40 Description LPDDR2 RZQ = 34.3 ohms, DDR2/LPDDR1: Not applicable LPDDR2:RZQ = 40 ohms, DDR2/LPDDR1: RZQ = 33.3 ohms LPDDR2:RZQ = 48 ohms, DDR2/LPDDR1: RZQ = 40 ohms 4 RZQ_60_RZQ_50 6 RZQ_80_RZQ_66_7 LPDDR2: RZQ = 80 ohms, DDR2/LPDDR1: RZQ = 66.7 ohms LPDDR2:RZQ = 60 ohms, DDR2/LPDDR1: RZQ = 50 ohms 7 RZQ_120_RZQ_100 LPDDR2:RZQ = 120 ohms, DDR2/LPDDR1: RZQ = 100 ohms * TZQIO: IO Calibration This field defines the delay between an IO Calibration command and any valid commands in number of SDCK(1) clock cycles. The number of cycles is between 0 and 7. The TZQIO configuration code must be correctly set depending on the clock frequency using the following formula: TZQIO = (DDRCLK * 20 ns) + 1. * CALCODEP: Number of Transistor P This register is read-only. Reset value is 7. This value gives the number of transistor P to perform the calibration. * CALCODEN: Number of Transistor N This register is read-only. Reset value is 8. This value gives the number of transistor N to perform the calibration. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 392 29.8.12 MPDDRC OCMS Register Name: MPDDRC_OCMS Address: 0xFFFFEA38 Access: Read/Write Reset: See Table 29-25 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SCR_EN * SCR_EN: Scrambling Enable 0: Disables "Off-chip" scrambling for SDRAM access. 1: Enables "Off-chip" scrambling for SDRAM access. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 393 29.8.13 MPDDRC OCMS KEY1 Register Name: MPDDRC_OCMS_KEY1 Address: 0xFFFFEA3C Access: Write once Reset: See Table 29-25 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1 23 22 21 20 KEY1 15 14 13 12 KEY1 7 6 5 4 KEY1 * KEY1: Off-chip Memory Scrambling (OCMS) Key Part 1 When Off-chip Memory Scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 394 29.8.14 MPDDRC OCMS KEY2 Register Name: MPDDRC_OCMS_KEY2 Address: 0xFFFFEA40 Access: Write once Reset: See Table 29-25 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2 23 22 21 20 KEY2 15 14 13 12 KEY2 7 6 5 4 KEY2 * KEY2: Off-chip Memory Scrambling (OCMS) Key Part 2 When Off-chip Memory Scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 395 29.8.15 MPDDRC Memory Device Register Name: MPDDRC_MD Address: 0xFFFFEA20 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - DBW - MD * MD: Memory Device Indicates the type of memory used. Reset value is that for the DDR-SDRAM device. Value Name 3 LPDDR_SDRAM 6 DDR2_SDRAM 7 LPDDR2_SDRAM Description Low-power DDR1-SDRAM DDR2-SDRAM Low-power DDR2-SDRAM * DBW: Data Bus Width Reset value is 16 bits. 0 (DBW_32_BITS): Data bus width is 32 bits. 1 (DBW_16_BITS): Data bus width is 16 bits.(1) Note: 1. Only 32-bit value is used. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 396 29.8.16 DDRSDRC High Speed Register Name: MPDDRC_HS Address: 0xFFFFEA24 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - DIS_ANTICIP_READ - - * DIS_ANTICIP_READ: Disable Anticip Read Access This field allows DDR read access optimization with the multi-port. As this feature is based on the "bank open policy", the software must map different buffers in different DDR banks to take advantage of that feature. 0: Anticip_read access is enabled (default). 1: Anticip_read access is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 397 29.8.17 MPDDRC Write Protect Mode Register Name: MPDDRC_WPMR Address: 0xFFFFEAE4 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- WPEN * WPEN: Write Protection Enable 0: Disables the Write Protection if WPKEY corresponds to 0x444452 ("DDR" in ASCII). 1: Enables the Write Protection if WPKEY corresponds to 0x444452 ("DDR" in ASCII). * WPKEY: Write Protection KEY Value Name 0x444452 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 398 29.8.18 MPDDRC Write Protect Status Register Name: MPDDRC_WPSR Address: 0xFFFFEAE8 Access: Read-only Reset: See Table 29-25 31 30 29 28 27 26 25 24 -- -- -- -- -- -- -- -- 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- WPVS * WPVS: Write Protection Enable 0: No Write Protection Violation occurred since the last read of this register (MPDDRC_WPSR). 1: A Write Protection Violation occurred since the last read of this register (MPDDRC_WPSR). If this violation is an unauthorized attempt to write a control register, the associated violation is reported into the WPVSRC field. * WPVSRC: Write Protection Violation Source When WPVS is active, it indicates the register (through address or code) that should have been written if Write Protection had not been previously enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 399 29.8.19 MPDDRC DLL Master Offset Register Name: MPDDRC_DLL_MO Address: 0xFFFFEA74 Access: Read/Write Reset: See Table 29-25 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 SELOFF 15 - 14 - 13 - 12 11 10 CLK90OFF 9 8 7 - 6 - 5 - 4 - 3 2 1 0 MOFF * MOFF: DLL Master Delay Line Offset The value stored by this field is unsigned. When this field is written, the programmable Master delay line offset is written. When this field is read: - If SELOFF = 0: the hard-coded Master delay line offset is read. - If SELOFF = 1: the programmable Master delay line offset is read. * CLK90OFF: DLL CLK90 Delay Line Offset The value stored by this field is signed. When this field is written, the programmable CLK90 delay line offset is written. When this field is read: - If SELOFF = 0: the hard-coded CLK90 delay line offset is read. - If SELOFF = 1: the programmable CLK90 delay line offset is read. * SELOFF: DLL Offset Selection 0: The hard-coded Master/Slave x/CLK90 delay line offsets are selected. 1: The programmable Master/Slave x/CLK90 delay line offsets are selected. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 400 29.8.20 MPDDRC DLL Slave Offset Register Name: MPDDRC_DLL_SOF Address: 0xFFFFEA78 Access: Read/Write Reset: See Table 29-25 31 - 30 - 29 - 28 27 26 S3OFF 25 24 23 - 22 - 21 - 20 19 18 S2OFF 17 16 15 - 14 - 13 - 12 11 10 S1OFF 9 8 7 - 6 - 5 - 4 3 2 S0OFF 1 0 * SxOFF: DLL Slave x Delay Line Offset ([x = 0..3]) The value stored by this field is signed. When this field is written, the programmable Slave x delay line offset is written. When this field is read: - If MPDDRC_DLL MOR.SELOFF = 0: the hard-coded Slave x delay line offset is read. - If MPDDRC_DLL MOR.SELOFF = 1: the programmable Slave x delay line offset is read. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 401 29.8.21 MPDDRC DLL Master Status Register Name: MPDDRC_DLL_MS Address: 0xFFFFEA7C Access: Read-only Reset: See Table 29-25 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 11 10 9 8 3 - 2 MDOVF 1 MDDEC 0 MDINC MDVAL 7 - 6 - 5 - 4 - * MDINC: DLL Master Delay Increment 0: The DLL is not incrementing the Master delay counter. 1: The DLL is incrementing the Master delay counter. * MDDEC: DLL Master Delay Decrement 0: The DLL is not decrementing the Master delay counter. 1: The DLL is decrementing the Master delay counter. * MDOVF: DLL Master Delay Overflow Flag 0: The Master delay counter has not reached its maximum value, or the Master is not locked yet 1: The Master delay counter has reached its maximum value, the Master delay counter increment is stopped and the DLL forces the Master lock. If this flag is set, it means the MPDDRC clock frequency is too low compared to Master delay line number of elements. * MDVAL: DLL Master Delay Value Value of the Master delay counter. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 402 29.8.22 MPDDRC DLL Status Slave x Register Name: MPDDRC_DLL_SSx Address: 0xFFFFEA80 Access: Read-only Reset: See Table 29-25 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 - 24 - 19 18 17 16 11 10 9 8 3 - 2 SDERF 1 SDCUDF 0 SDCOVF SDCVAL 15 14 13 12 SDVAL 7 - 6 - 5 - 4 - * SDCOVF: DLL Slave x Delay Correction Overflow Flag 0: Due to the correction, the Slave x delay counter has not reached its maximum value, or the Slave x is not locked yet. 1: Due to the correction, the Slave x delay counter has reached its maximum value, the correction is not optimal because it has not been entirely applied. * SDCUDF: DLL Slave x Delay Correction Underflow Flag 0: Due to the correction, the Slave x delay counter has not reached its minimum value, or the Slave x is not locked yet. 1: Due to the correction, the Slave x delay counter has reached its minimum value, the correction is not optimal because it has not been entirely applied. * SDERF: DLL Slave x Delay Correction Error Flag 0: The DLL has succeeded in computing the Slave x delay correction, or the Slave x is not locked yet. 1: The DLL has not succeeded in computing the Slave x delay correction. * SDVAL: DLL Slave x Delay Value Value of the Slave x delay counter. * SDCVAL: DLL Slave x Delay Correction Value Value of the correction applied to the Slave x delay. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 403 30. Static Memory Controller (SMC) 30.1 Description This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash. The SMC generates the signals that control the access to external memory devices or peripheral devices. It has 4 Chip Selects and a 26-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. The SMC includes programmable hardware error correcting code with one-bit error correction capability and supports two-bit error detection. In order to improve the overall system performance, the DATA phase of the transfer can be DMAassisted. The External Data Bus can be scrambled/unscrambled by means of user keys. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 404 30.2 Embedded Characteristics 64-Mbyte Address Space per Chip Select 8- or 16-bit Data Bus Word, Halfword, Byte Transfers Byte Write or Byte Select Lines Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select Programmable Data Float Time per Chip Select External Data Bus Scrambling/Unscrambling Function External Wait Request Automatic Switch to Slow Clock Mode Hardware Configurable Number of Chip Selects from 1 to 4 Programmable Timing on a per Chip Select Basis NAND Flash Controller Supporting NAND Flash with Multiplexed Data/Address Buses Supports SLC and MLC NAND Flash Technology Supports NAND Flash Devices with 8-bit Data Path Multibit Error Correcting Code (ECC) ECC Algorithm Based on Binary Shortened Bose, Chaudhuri and Hocquenghem (BCH) Codes Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 Bits of Errors per Block Programmable Block Size: 512 Bytes or 1024 Bytes Programmable Number of Block per Page: 1, 2, 4 or 8 Blocks of Data per Page Programmable Spare Area Size up to 512 bytes Supports Spare Area ECC Protection Supports 8 Kbytes Page Size Using 1024 Bytes/block and 4 Kbytes Page Size Using 512 Bytes/block MultibIt Error Detection Is Interrupt Driven Provides Hardware Acceleration for Determining Roots of Polynomials Defined over a Finite Field Programmable Finite Field GF(2^13) or GF(2^14) Finds Roots of Error-locator Polynomial Programmable Number of Roots SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 405 30.3 Block Diagram SMC AHB Interface NAND Flash Controller (NFC) AHB Arbiter SMC Scrambler Figure 30-1. Block Diagram D[15:0] A[0]/NBS0 A[20:1] A21/NANDALE A22/NANDCLE A[25:23] NCS[3:0] SMC Interface SRAM AHB Interface SRAM Scrambler ECC User Interface NFC (8 Kbytes) Internal SRAM Control & Status Registers NRD NWR0/NWE NWR1/NBS1 NANDOE NANDWE NANDRDY NWAIT APB Interface SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 406 30.4 I/O Lines Description Table 30-1. I/O Line Description Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWR0/NWE Write 0/Write Enable Signal Output Low A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low A[25:1] Address Bus Output - D[15:0] Data Bus I/O - NWAIT External Wait Signal Input Low NANDRDY NAND Flash Ready/Busy Input - NANDWE NAND Flash Write Enable Output Low NANDOE NAND Flash Output Enable Output Low NANDALE NAND Flash Address Latch Enable Output - NANDCLE NAND Flash Command Latch Enable Output - 30.5 Multiplexed Signals Table 30-2. Static Memory Controller (SMC) Multiplexed Signals Multiplexed Signals Related Function NWR0 NWE Byte-write or Byte-select access, see Figure 30-4 "Memory Connection for an 8-bit Data Bus" and Figure 30-5 "Memory Connection for a 16-bit Data Bus" A0 NBS0 8-bit or 16-bit data bus, see Section 30.9.1 "Data Bus Width" A22 NANDCLE NAND Flash Command Latch Enable A21 NANDALE NAND Flash Address Latch Enable NWR1 NBS1 Byte-write or Byte-select access, see Figure 30-4 and Figure 30-5 A1 - 8-/16-bit data bus, see Section 30.9.1 "Data Bus Width" Byte-write or Byte-select access, see Figure 30-4 and Figure 30-5 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 407 30.6 Application Example 30.6.1 Hardware Interface Figure 30-2. SMC Connections to Static Memory Devices D0-D15 A0/NBS0 NWR0/NWE NWR1/NBS1 A1 D0 - D7 128K x 8 SRAM D8-D15 D0 - D7 CS NWR0/NWE NCS0 NCS1 NCS2 NCS3 A2 - A18 A0 - A16 NRD OE WE D0-D7 CS A0 - A16 NRD 128K x 8 SRAM NWR1/NBS1 A2 - A18 OE WE A2 - A23 Static Memory Controller 30.7 Product Dependencies 30.7.1 I/O Lines The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. 30.7.2 Power Management The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SMC clock. 30.7.3 Interrupt The SMC has an interrupt line connected to the Nested Vector Interrupt Controller (NVIC). Handling the SMC interrupt requires programming the NVIC before configuring the SMC. Table 30-3. Peripheral IDs 30.8 Instance ID SMC 5 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 30-3). A[25:0] is only significant for 8-bit memory; A[25:1] is used for 16-bit memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 408 Figure 30-3. Memory Connections for External Devices NCS[0] - NCS[3] NRD SMC NWE NCS3 A[25:0] NCS2 D[15:0] NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[25:0] 8 or 16 30.9 Connection to External Devices 30.9.1 Data Bus Width D[15:0] or D[7:0] A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the field DBW in the SMC Mode Register (HSMC_MODE) for the corresponding chip select. Figure 30-4 shows how to connect a 512K x 8-bit memory on NCS2. Figure 30-5 shows how to connect a 512K x 16-bit memory on NCS2. 30.9.2 Byte Write or Byte Select Access Each chip select with a 16-bit data bus can operate with one of two different types of write access: Byte write or Byte select access. This is controlled by the BAT field of the HSMC_MODE register for the corresponding chip select. Figure 30-4. Memory Connection for an 8-bit Data Bus SMC D[7:0] D[7:0] A[18:2] A[18:2] A1 A1 A0 A0 NWE Write Enable NRD Output Enable NCS[2] Memory Enable SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 409 Figure 30-5. Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Memory Enable 30.9.2.1 Byte Write Access Byte write access supports one write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively Byte0 (lower byte) and Byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory. 30.9.2.2 Byte Select Access In this mode, read/write operations can be enabled/disabled at Byte level. One Byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write. For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively Byte0 (lower byte) and Byte1 (upper byte) of a 16-bit bus. Byte Select Access is used to connect one 16-bit device. Figure 30-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[7:0] D[15:8] A[24:2] SMC A1 NWR0 A[23:1] A[0] Write Enable NWR1 NRD NCS[3] Read Enable Memory Enable D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 410 30.9.2.3 Signal Multiplexing Depending on the Byte Access Type (BAT), only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 30-4 shows signal multiplexing depending on the data bus width and the Byte Access Type. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 is unused. When Byte Write option is selected, NBS0 is unused. Table 30-4. SMC Multiplexed Signal Translation Signal Name 16-bit Bus Device Type 8-bit Bus 1 x 16-bit 2 x 8-bit 1 x 8-bit Byte Select Byte Write - NBS0_A0 NBS0 - A0 NWE_NWR0 NWE NWR0 NWE NBS1_NWR1 NBS1 NWR1 - A1 A1 A1 Byte Access Type (BAT) A1 30.10 Standard Read and Write Protocols In the following sections, the Byte Access Type is not considered. Byte select lines (NBS0 to NBS1) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..3] chip select lines. 30.10.1 Read Waveforms The read cycle is shown on Figure 30-7. The read cycle starts with the address setting on the memory address bus, i.e.,: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 411 Figure 30-7. Standard Read Cycle MCK A[25:2] NBS0,NBS1, A0, A1 NRD NCS D[15:0] NRD_SETUP NCS_RD_SETUP NRD_PULSE NCS_RD_PULSE NRD_HOLD NCS_RD_HOLD NRD_CYCLE 30.10.1.1 NRD Waveform The NRD signal is characterized by a setup timing, a pulse width and a hold timing: 1. NRD_SETUP: The NRD setup time is defined as the setup of address before the NRD falling edge. 2. NRD_PULSE: The NRD pulse length is the time between NRD falling edge and NRD rising edge. 3. NRD_HOLD: The NRD hold time is defined as the hold time of address after the NRD rising edge. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 412 30.10.1.2 NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: The NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: The NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCS_RD_HOLD: The NCS hold time is defined as the hold time of address after the NCS rising edge. 30.10.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, the user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 30.10.2 Read Mode As NCS and NRD waveforms are defined independently of one another, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the HSMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation. 30.10.2.1 Read is Controlled by NRD (READ_MODE = 1) Figure 30-8 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to `Z' after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of the Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS. Figure 30-8. READ_MODE = 1: Data is Sampled by SMC before the Rising Edge of NRD MCK A[25:2] NBS0,NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 413 30.10.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 30-9 shows the typical read cycle. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of the Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD. Figure 30-9. READ_MODE = 0: Data is Sampled by SMC before the Rising Edge of NCS MCK A[25:2] NBS0,NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 414 30.10.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 30-10. The write cycle starts with the address setting on the memory address bus. 30.10.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing: 1. NWE_SETUP: The NWE setup time is defined as the setup of address and data before the NWE falling edge. 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge. 3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge. The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3. 30.10.3.2 NCS Waveforms The NCS signal waveforms in write operations are not the same as those applied in read operations, but are separately defined: 1. NCS_WR_SETUP: The NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_WR_PULSE: The NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCS_WR_HOLD: The NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 30-10.Write Cycle MCK A[25:2] NBS0, NBS1, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP NWE_PULSE NCS_WR_PULSE NWE_HOLD NCS_WR_HOLD NWE_CYCLE 30.10.3.3 Write Cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 415 NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE 30.10.4 Write Mode The WRITE_MODE parameter in the HSMC_MODE register of the corresponding chip select indicates which signal controls the write operation. 30.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1) Figure 30-11 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. Figure 30-11.WRITE_MODE = 1. The write operation is controlled by NWE MCK A[25:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] 30.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 30-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 416 Figure 30-12.WRITE_MODE = 0. The write operation is controlled by NCS MCK A[25:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] 30.10.5 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one register according to their type: The HSMC_SETUP register groups the definition of all setup parameters: NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP The HSMC_PULSE register groups the definition of all pulse parameters: NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE The HSMC_CYCLE register groups the definition of all cycle parameters: NRD_CYCLE, NWE_CYCLE Table 30-5 shows how the timing parameters are coded and their permitted range. Table 30-5. Coding and Range of Timing Parameters Permitted Range Coded Value Number of Bits Effective Value setup [5:0] 6 128 x setup[5] + setup[4:0] pulse [6:0] cycle [8:0] 7 9 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] Coded Value Effective Value 0 setup 31 0..31 32 setup 63 128..(128 + 31) 0 pulse 63 0..63 64 pulse 127 256..(256 + 63) 0 cycle 127 0..127 128 cycle 255 256..(256 + 127) 256 cycle 383 512..(512 + 127) 384 cycle 511 768..(768 + 127) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 417 30.10.6 Reset Values of Timing Parameters Table 30-6 gives the default value of timing parameters at reset. Table 30-6. Reset Values of Timing Parameters Register Reset Value Description HSMC_SETUP - All setup timings are set to 1 HSMC_PULSE - All pulse timings are set to 1 HSMC_CYCLE - The read and write operations last 3 Master Clock cycles and provide one hold cycle WRITE_MODE 1 Write is controlled with NWE READ_MODE 1 Read is controlled with NRD 30.10.7 Usage Restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to an unpredictable behavior of the SMC. 30.10.7.1 For Read Operations Null but positive setup and hold of address and NRD and/or NCS cannot be guaranteed at the memory interface because of the propagation delay of these signals through external logic and pads. When positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals. 30.10.7.2 For Write Operations If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See Section 30.12.2 "Early Read Wait State" on page 419. 30.10.7.3 For Read and Write Operations A null value for pulse parameters is forbidden and may lead to an unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 30.11 Scrambling/Unscrambling Function The external data bus D[15:0] can be scrambled in order to prevent intellectual property data located in off-chip memories from being easily recovered by analyzing data at the package pin level of either the microcontroller or the memory device. The scrambling and unscrambling are performed on-the-fly without additional wait states. The scrambling method depends on two user-configurable key registers, HSMC_KEY1 and HSMC_KEY2. These key registers are only accessible in write mode. The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost. The scrambling/unscrambling function can be enabled or disabled by programming the HSMC_OCMS register. One bit is dedicated to enabling/disabling the NAND Flash scrambling, and one bit is dedicated to enabling/disabling the off chip SRAM scrambling. When at least one external SRAM is scrambled, the SMSC field must be set in the HSMC_OCMS register. When multiple chip selects (external SRAM) are handled, it is possible to configure the scrambling function per chip select using the OCMS field in the HSMC_TIMINGS registers. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 418 To scramble the NAND Flash contents, the SRSE field must be set in the HSMC_OCMS register. When the NAND Flash memory content is scrambled, the on-chip SRAM page buffer associated for the transfer is also scrambled. 30.12 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 30.12.1 Chip Select Wait States The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NBS0 to NBS1, NWR0 to NWR1, NCS[0..3], and NRD lines. They are all set to 1. Figure 30-13 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2. Figure 30-13.Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, A0,A1 NRD NWE NCS0 NCS2 NRD_CYCLE NWE_CYCLE D[15:0] Read to Write Chip Select Wait State Wait State 30.12.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid: if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 30-14). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 419 in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 30-15). The write operation must end with an NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly. in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 30-16. Figure 30-14.Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, A0, A1 NWE NRD No hold No setup D[15:0] Write cycle Early Read wait state Read cycle SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 420 Figure 30-15.Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, A0,A1 NCS NRD No hold No setup D[15:0] Read cycle Write cycle Early Read (WRITE_MODE = 0) wait state (READ_MODE = 0 or READ_MODE = 1) Figure 30-16.Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] NBS0, NBS1, A0, A1 Internal write controlling signal External write controlling signal (NWE) No hold Read setup = 1 NRD D[15:0] Write cycle Early Read Read cycle (WRITE_MODE = 1) wait state (READ_MODE = 0 or READ_MODE = 1) 30.12.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 421 When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called "Reload User Configuration Wait State" is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Configuration Wait State is inserted, even if the change does not concern the current Chip Select. 30.12.3.1 User Procedure To insert a Reload Configuration Wait State, the SMC detects a write access to any HSMC_MODE register of the user interface. If only the timing registers are modified (HSMC_SETUP, HSMC_PULSE, HSMC_CYCLE registers) in the user interface, the user must validate the modification by writing the HSMC_MODE register, even if no change was made on the mode parameters. 30.12.3.2 Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see Section 30.15 "Slow Clock Mode" on page 432). 30.12.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 30-13 on page 419. 30.13 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: before starting a read access to a different external memory before starting a write access to the same device or to a different external one. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the HSMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long tDF will not slow down the execution of a program from internal memory. The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the HSMC_MODE register for the corresponding chip select. 30.13.1 READ_MODE Setting READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 30-17 illustrates the Data Float Period in NRD-controlled mode (READ_MODE = 1), assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 30-18 shows the read operation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 422 Figure 30-17.TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[25:2] NBS0, NBS1, A0, A1 NRD NCS tpacc D[15:0] TDF = 2 clock cycles NRD controlled read operation Figure 30-18.TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, A0,A1 NRD NCS tpacc D[15:0] TDF = 3 clock cycles NCS controlled read operation 30.13.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the HSMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 30-19 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 423 NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled). Figure 30-19.TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK A[25:2] NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[15:0] Read access on NCS0 (NRD controlled) Read to Write Wait State Write access on NCS0 (NWE controlled) 30.13.3 TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, TDF wait states are inserted at the end of the read transfer, so that the data float period ends when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional TDF wait states will be inserted. Figure 30-20, Figure 30-21 and Figure 30-22 illustrate the cases: read access followed by a read access on another chip select, read access followed by a write access on another chip select, read access followed by a write access on the same chip select, with no TDF optimization. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 424 Figure 30-20.TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[15:0] 5 TDF WAIT STATES read2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 30-21. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects MCK A[25:2] NBS0, NBS1, A0, A1 read1 controlling signal (NRD) read1 hold = 1 write2 controlling signal (NWE) write2 setup = 1 TDF_CYCLES = 4 D[15:0] read1 cycle TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select Wait State Wait State write2 cycle TDF_MODE = 0 (optimization disabled) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 425 Figure 30-22.TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[15:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 30.14 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the HSMC_MODE register on the corresponding chip select must be set to either `10' (frozen mode) or `11' (ready mode). When the EXNW_MODE is set to `00' (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 30.14.1 Restriction When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Slow Clock Mode (Section 30.15 "Slow Clock Mode" on page 432). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. NWAIT is then examined by the SMC in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on the SMC behavior. 30.14.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after an internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 30-23. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 30-24. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 426 Figure 30-23.Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A[25:2] NBS0, NBS1, A0,A1 FROZEN STATE 4 3 2 1 1 1 1 0 3 2 2 2 2 1 NWE 6 5 4 0 NCS D[15:0] NWAIT Internally synchronized NWAIT signal Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 427 Figure 30-24.Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A[25:2] NBS0, NBS1, A0,A1 FROZEN STATE NCS 4 1 NRD 3 2 2 2 1 0 2 1 0 2 1 0 0 5 5 5 4 3 NWAIT Internally synchronized NWAIT signal Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE = 5, NCS_RD_HOLD = 3 Assertion is ignored 30.14.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 30-25 and Figure 30-26. After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 30-26. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 428 Figure 30-25.NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, A0,A1 Wait STATE 4 3 2 1 0 0 0 3 2 1 1 1 NWE 6 5 4 0 NCS D[15:0] NWAIT Internally synchronized NWAIT signal Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 429 Figure 30-26.NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, A0,A1 Wait STATE 6 5 4 3 2 1 0 0 6 5 4 3 2 1 1 NCS NRD 0 NWAIT Internally synchronized NWAIT signal Read cycle EXNW_MODE = 11 (Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE = 7 30.14.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 30-27. When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 430 Figure 30-27.NWAIT Latency MCK A[25:2] NBS0, NBS1, A0,A1 WAIT STATE 4 3 2 1 0 0 0 NRD Minimal pulse length NWAIT Internally synchronized NWAIT signal NWAIT latency 2 Resynchronization cycles Read cycle EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 431 30.15 Slow Clock Mode The SMC is able to automatically apply a set of "slow clock mode" read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects. 30.15.1 Slow Clock Mode Waveforms Figure 30-28 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 30-7 indicates the value of read and write parameters in slow clock mode. Figure 30-28. Write/Read Cycles in Slow Clock Mode MCK MCK A[25:2] A[25:2] NBS0, NBS1, A0,A1 NBS0, NBS1, A0,A1 1 NWE NRD 1 1 1 1 NCS NCS NRD_CYCLE = 2 NWE_CYCLE = 3 SLOW CLOCK MODE WRITE Table 30-7. SLOW CLOCK MODE READ Read and Write Timing Parameters in Slow Clock Mode Read Parameters Duration (cycles) Write Parameters Duration (cycles) NRD_SETUP 1 NWE_SETUP 1 NRD_PULSE 1 NWE_PULSE 1 NCS_RD_SETUP 0 NCS_WR_SETUP 0 NCS_RD_PULSE 2 NCS_WR_PULSE 3 NRD_CYCLE 2 NWE_CYCLE 3 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 432 30.15.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 30-29. The external device may not be fast enough to support such timings. Figure 30-30 illustrates the recommended procedure to properly switch from one mode to the other. Figure 30-29.Clock Rate Transition occurs while the SMC is performing a Write Operation Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, A0, A1 NWE 1 1 1 1 1 1 2 3 2 NCS NWE_CYCLE = 3 SLOW CLOCK MODE WRITE NWE_CYCLE = 7 SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 433 Figure 30-30.Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode Internal signal from PMC MCK A[25:2] NBS0, NBS1, A0, A1 NWE 1 1 1 2 3 2 NCS SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State 30.16 Register Write Protection To prevent any single software error that may corrupt SMC behavior, selected registers can be write-protected by setting the WPEN bit in the HSMC Write Protection Mode Register (HSMC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the HSMC Write Protection Status Register (HSMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the HSMC_WPSR. The following registers can be write-protected: HSMC Setup Register HSMC Pulse Register HSMC Cycle Register HSMC Timings Register HSMC Mode Register 30.17 NAND Flash Controller Operations 30.17.1 NFC Overview The NAND Flash Controller (NFC) handles all the command, address and data sequences of the NAND low level protocol. An SRAM is used as an internal read/write buffer when data is transferred from or to the NAND. 30.17.2 NFC Control Registers NAND Flash Read and NAND Flash Program operations can be performed through the NFC Command Registers. In order to minimize CPU intervention and latency, commands are posted in a command buffer. This buffer provides zero wait state latency. The detailed description of the command encoding scheme is explained below. The NFC handles an automatic transfer between the external NAND Flash and the chip via the NFC SRAM. It is done via NFC Command Registers. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 434 The NFC Command Registers are very efficient to use. When writing to these registers: the address of the register (NFCADDR_CMD) is the command used the data of the register (NFCDATA_ADDT) is the address to be sent to the NAND Flash So, in one single access the command is sent and immediately executed by the NFC. Two commands can even be programmed within a single access (CMD1, CMD2) depending on the VCMD2 value. The NFC can send up to five address cycles. Figure 30-31 below shows a typical NAND Flash Page Read Command of a NAND Flash Memory and correspondence with NFC Address Command Register. Figure 30-31.NFC/NAND Flash Access Example 00h Col. Add1 Col. Add2 30h Row Address Column Address CMD1 Row Add1 Row Add2 Row Add3 ADD cycles (0 to 5) Depends on ACYCLE value CMD2 If VCMD2 = 1 For more details refer to Section 30.17.2.2 "NFC Address Command" on page 436. Reading the NFC command register (to any address) will give the status of the NFC. This is especially useful to know if the NFC is busy, for example. 30.17.2.1 Building NFC Address Command Example The base address is made of HOST_ADDR address. Page read operation example: // Build the Address Command (NFCADDR_CMD) AddressCommand = (HOST_ADDR | NFCCMD=1 | // NFC Command Enable NFCWR=0 |// NFC Read Data from NAND Flash DATAEN=1 | // NFC Data phase Enable. CSID=1 | // Chip Select ID = 1 ACYCLE= 5 | // Number of address cycle. VCMD2=1 | // CMD2 is sent after Address Cycles CMD2=0x30 | // CMD2 = 30h CMD1=0x0) // CMD1 = Read Command = 00h // Set the Address for Cycle 0 HSMC_ADDR = Col. Add1 // Write command with the Address Command built above *AddressCommand = (Col. Add2 |// ADDR_CYCLE1 Row Add1 | // ADDR_CYCLE2 Row Add2 |// ADDR_CYCLE3 Row Add3 )// ADDR_CYCLE4 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 435 30.17.2.2 NFC Address Command Name: NFCADDR_CMD Access: Read/Write Reset: 0x00000000 31 - 23 30 - 29 - 28 - 27 - 26 NFCWR 25 DATAEN 22 21 20 ACYCLE 19 18 VCMD2 17 12 11 10 9 CSID 15 14 13 6 5 16 CMD2 CMD2 7 24 CSID 8 CMD1 4 3 2 CMD1 1 - 0 - * CMD1: Command Register Value for Cycle 1 If NFCCMD is set, when a read or write access occurs, the NFC sends this command. * CMD2: Command Register Value for Cycle 2 If NFCCMD and VCMD2 field are set to one, the NFC sends this command after CMD1. * VCMD2: Valid Cycle 2 Command When set to true, the CMD2 field is issued after the address cycle. * ACYCLE: Number of Address required for the current command When ACYCLE field is different from zero, ACYCLE Address cycles are performed after Command Cycle 1. The maximum number of cycles is 5. * CSID: Chip Select Identifier Chip select used * DATAEN: NFC data phase enable When set to true, the NFC will automatically read or write data after the command. * NFCWR: NFC Write Enable 0: NFC reads data from the NAND Flash. 1: NFC writes data into the NAND Flash. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 436 30.17.2.3 NFC Data Address Name: NFCDATA_ADDT Access: Write-only Reset: 0x00000000 31 30 29 28 27 ADDR_CYCLE4 26 25 24 23 22 21 20 19 ADDR_CYCLE3 18 17 16 15 14 13 12 11 ADDR_CYCLE2 10 9 8 7 6 5 4 3 ADDR_CYCLE1 2 1 0 * ADDR_CYCLE1: NAND Flash Array Address Cycle 1 When less than five address cycles are used, ADDR_CYCLE1 is the first byte written to the NAND Flash. When five address cycles are used, ADDR_CYCLE1 is the second byte written to NAND Flash. * ADDR_CYCLE2: NAND Flash Array Address Cycle 2 When less than five address cycles are used, ADDR_CYCLE2 is the second byte written to the NAND Flash. When five address cycles are used, ADDR_CYCLE2 is the third byte written to the NAND Flash. * ADDR_CYCLE3: NAND Flash Array Address Cycle 3 When less than five address cycles are used, ADDR_CYCLE3 is the third byte written to the NAND Flash. When five address cycles are used, ADDR_CYCLE3 is the fourth byte written to the NAND Flash. * ADDR_CYCLE4: NAND Flash Array Address Cycle 4 When less than five address cycles are used, ADDR_CYCLE4 is the fourth byte written to the NAND Flash. When five address cycles are used, ADDR_CYCLE4 is the fifth byte written to the NAND Flash. Note: If five address cycles are used, the first address cycle is ADDR_CYCLE0. Refer to HSMC_ADDR register. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 437 30.17.2.4 NFC DATA Status Name: NFCDATA_STATUS Access: Read-only Reset: 0x00000000 31 - 23 30 - 29 - 28 - 27 NFCBUSY 26 NFCWR 25 DATAEN 22 21 20 ACYCLE 19 18 VCMD2 17 12 11 10 9 CSID 15 14 13 6 5 16 CMD2 CMD2 7 24 CSID 8 CMD1 4 3 CMD1 2 1 - 0 - * CMD1: Command Register Value for Cycle 1 When a Read or Write Access occurs, the Physical Memory Interface drives the IO bus with CMD1 field during the Command Latch cycle 1. * CMD2: Command Register Value for Cycle 2 When VCMD2 field is set to true, the Physical Memory Interface drives the IO bus with CMD2 field during the Command Latch cycle 2. * VCMD2: Valid Cycle 2 Command When set to true, the CMD2 field is issued after addressing cycle. * ACYCLE: Number of Address required for the current command When ACYCLE field is different from zero, ACYCLE Address cycles are performed after Command Cycle 1. * CSID: Chip Select Identifier Chip select used * DATAEN: NFC Data phase enable When set to true, the NFC data phase is enabled. * NFCWR: NFC Write Enable 0: NFC is in read mode. 1: NFC is in write mode. * NFCBUSY: NFC Busy Status Flag If set to true, it indicates that the NFC is busy. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 438 30.17.3 NFC Initialization Prior to any Command and Data Transfer, the SMC User Interface must be configured to meet the device timing requirements. Write enable Configuration Use NWE_SETUP, NWE_PULSE and NWE_CYCLE to define the write enable waveform according to the device datasheet. Use TADL field in the HSMC_TIMINGS register to configure the timing between the last address latch cycle and the first rising edge of WEN for data input. Figure 30-32.Write Enable Timing Configuration mck wen t WEN_SETUP t WEN_PULSE t WEN_HOLD t WEN_CYCLES Figure 30-33.Write Enable Timing for NAND Flash Device Data Input Mode mck ale wen t ADL Read Enable Configuration Use NRD_SETUP, NRD_PULSE and NRD_CYCLE to define the read enable waveform according to the device datasheet. Use TAR field in the HSMC_TIMINGS register to configure the timings between the address latch enable falling edge to read the enable falling edge. Use TCLR field in the HSMC_TIMINGS register to configure the timings between the command latch enable falling edge to read the enable falling edge. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 439 Figure 30-34.Read Enable Timing Configuration Working with NAND Flash Device mck cen ale cle ren tCLR tAR tREN_SETUP tREN_PULSE tREH tREN_CYCLE Ready/Busy Signal Timing configuration working with a NAND Flash device Use TWB field in HSMC_TIMINGS register to configure the maximum elapsed time between the rising edge of the wen signal and the falling edge of the rbn signal. Use TRR field in the HSMC_TIMINGS register to program the number of clock cycles between the rising edge of the rbn signal and the falling edge of the ren signal. Figure 30-35.Ready/Busy Timing Configuration mck rbn ren wen tWB busy tRR SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 440 30.17.3.1 NAND Flash Controller Timing Engine When the NFC Command register is written, the NFC issues a NAND Flash Command and optionally performs a data transfer between the NFC SRAM and the NAND Flash device. The NAND Flash Controller Timing Engine guarantees valid NAND Flash timings, depending on the set of parameters decoded from the address bus. These timings are defined in the HSMC_TIMINGS register. For information on the timing used depending on the command, see Figure 30-36. Figure 30-36.NAND Flash Controller Timing Engine Timing Check Engine NFCEN = 1 NFCWR = 1 TADL = 1 Wait TADL NFCEN = 1 NFCWR = 0 TWB ! = 0 Wait TWB NFCEN = 0 VCMD2 = 1 TCLR ! = 0 Wait TCLR !NFCEN = 1 VCMD2 = 0 ACYCLE! = 0 NFCWR = 1 TADL ! = 0 Wait TADL !NFCEN = 1 VCMD2 = 0 ACYCLE! = 0 NFCWR = 0 TAR ! = 0 Wait TAR !NFCEN = 1 VCMD2 = 0 ACYCLE! = 0 TCLR ! = 0 Wait TCLR See the NFC Address Command register description and the HSMC Timings Register. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 441 30.17.4 NFC SRAM 30.17.4.1 NFC SRAM Mapping If the NFC is used to read and write Data from and to the NAND Flash, the configuration depends on the page size, the relevant field is PAGESIZE in HSMC_CFG register. See Table 30-8 to Table 30-12 for detailed mapping. The NFC SRAM size is 8 Kbytes. The NFC can handle the NAND Flash with a page size of 8 Kbytes or of a lower size (such as 2 Kbytes for example). In case of a 4-Kbyte or lower page size, the NFC SRAM can be split into two banks. The field BANK in the HSMC_BANK register is used to select where NAND flash data are written or read. For 8 Kbytes page size this field is not relevant. Note that a "ping-pong" mode (write or read to a bank while the NFC writes or reads to another bank) is accessible with the NFC (using two different banks). If the NFC is not used, the NFC SRAM can be used for a general purpose by the application. Table 30-8. NFC SRAM Bank Mapping for 512 bytes Offset Use Access 0x00000000-0x000001FF Main Area Bank 0 Read/Write 0x00000200-0x000003FF Spare Area Bank 0 Read/Write 0x00001200-0x000013FF Main Area Bank 1 Read/Write 0x00001400-0x000015FF Spare Area Bank 1 Read/Write Table 30-9. NFC SRAM Bank Mapping for 1 Kbyte Offset Use Access 0x00000000-0x000003FF Main Area Bank 0 Read/Write 0x00000400-0x000005FF Spare Area Bank 0 Read/Write 0x00001200-0x000015FF Main Area Bank 1 Read/Write 0x00001600-0x000017FF Spare Area Bank 1 Read/Write Table 30-10. NFC SRAM Bank Mapping for 2 Kbytes Offset Use Access 0x00000000-0x000007FF Main Area Bank 0 Read/Write 0x00000800-0x000009FF Spare Area Bank 0 Read/Write 0x00001200-0x000019FF Main Area Bank 1 Read/Write 0x00001A00-0x00001BFF Spare Area Bank 1 Read/Write Table 30-11. NFC SRAM Bank Mapping for 4 Kbytes Offset Use Access 0x00000000-0x00000FFF Main Area Bank 0 Read/Write 0x00001000-0x000011FF Spare Area Bank 0 Read/Write 0x00001200-0x000021FF Main Area Bank 1 Read/Write 0x00002200-0x000023FF Spare Area Bank 1 Read/Write SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 442 Table 30-12. NFC SRAM Bank Mapping for 8 Kbytes, only one bank is available Offset Use Access 0x00000000-0x00001FFF Main Area Bank 0 Read/Write 0x00002000-0x000023FF Spare Area Bank 0 Read/Write 30.17.4.2 NFC SRAM Access Prioritization Algorithm When the NAND Flash Controller (NFC) is reading from or writing to an NFC SRAM bank, the other bank is available. If an NFC SRAM access occurs when the NFC performs a read or write operation in the same bank, then the access is discarded. The write operation is not performed. The read operation returns undefined data. If this situation is encountered, the AWB status flag located in the NFC Status Register is raised and indicates that a shared resource access violation has occurred. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 443 30.17.5 NAND Flash Operations This section describes the software operations needed to issue commands to the NAND Flash device and to perform data transfers using the NFC. 30.17.5.1 Page Read Figure 30-37.Page Read Flow Chart Configure the device writing in the User Interface Using NFC Write the NFC Command registers Enable XFRDONE interrupt (SMC_IER) Wait for Interrupt Copy data from NFC SRAM to application memory (via DMA for example) Check Error Correcting Codes Note that, instead of using the interrupt, one can poll the NFCBUSY flag. For more information on the NFC Control Register, see Section 30.17.2.2 "NFC Address Command". SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 444 30.17.5.2 Program Page Figure 30-38.Program Page Flow Chart Configure the device writing in the User interface Write data in the NFC SRAM (CPU or DMA) Enable XFRDONE Write the Command Register through the AHB interface Wait for interrupt Write ECC Wait for Ready/Busy interrupt Writing the ECC cannot be done using the NFC; it needs to be done "manually". Note that, instead of using the interrupt, one can poll the NFCBUSY flag. For more information on the NFC Control Register, see Section 30.17.2.2 "NFC Address Command". SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 445 30.18 PMECC Controller Functional Description The Programmable Multibit Error Correcting Code (PMECC) controller is a programmable binary BCH (Bose, Chaudhuri and Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for both SLC and MLC NAND devices. It supports redundancy for correction of 2, 4, 8, 12, or 24 errors per sector of data. The sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is appended to the page and written in the spare area. This operation is performed by the processor. It moves the content of the PMECCX registers into the NAND flash memory. The number of registers depends on the selected error correction capability (see Table 30-13 on page 448). This operation shall be executed for each sector. At decoding time, the PMECC module generates the remainders of the received codeword by the minimal polynomials. When all remainders for a given sector are set to zero, no error occurred. When the remainders are different from zero, the codeword is corrupted and further processing is required. The PMECC module generates an interrupt indicating that an error occurred. The processor must read the PMECC Interrupt Status Register (HSMC_PMECCISR). This register indicates which sector is corrupted. The processor must execute the following decoding steps to find the error location within a sector: 1. Syndrome computation. 2. Finding the error location polynomial. 3. Finding the roots of the error location polynomial. All decoding steps involve finite field computation. It means that a library of finite field arithmetic must be available to perform addition, multiplication and inversion. These arithmetic operations can be performed through the use of a memory mapped look-up table, or direct software implementation. The software implementation presented is based on look-up tables. Two tables named gf_log and gf_antilog are used. If alpha is the primitive element of the field, then a power of alpha is in the field. Assuming that beta = alpha ^ index, then beta belongs to the field, and gf_log(beta) = gf_log(alpha ^ index) = index. The gf_antilog table provides exponent inverse of the element; if beta = alpha ^ index, then gf_antilog(index) = beta. The first step consists in the syndrome computation. The PMECC module computes the remainders and the software must substitute the power of the primitive element. The procedure implementation is given in Section 30.19.1 "Remainder Substitution Procedure" on page 452. The second step is the most software intensive. It is the Berlekamp's iterative algorithm for finding the error-location polynomial. The procedure implementation is given in Section 30.19.2 "Find the Error Location Polynomial Sigma(x)" on page 453. The Last step is finding the root of the error location polynomial. This step can be very software intensive. Indeed there is no straightforward method of finding the roots, except evaluating each element of the field in the error location polynomial. However, a hardware accelerator can be used to find the roots of the polynomial. The PMERRLOC module provides this kind of hardware acceleration. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 446 Figure 30-39.Software Hardware Multibit Error Correction Dataflow NAND Flash PROGRAM PAGE Operation Software NAND Flash READ PAGE Operation Hardware Accelerator Configure PMECC : error correction capability sector size/page size NAND write field set to true spare area desired layout Move the NAND Page to external Memory whether using DMA or Processor Software Hardware Accelerator Configure PMECC : error correction capability sector size/page size NAND write field set to false spare area desired layout PMECC computes redundancy as the data is written into external memory Move the NAND Page from external Memory whether using DMA or Processor PMECC computes polynomial remainders as the data is read from external memory PMECC modules indicate if at least one error is detected. Copy redundancy from PMECC user interface to user-defined spare area using DMA or Processor. If a sector is corrupted use the substitute() function to determine the syndromes. When the table of syndromes is completed, use the get_sigma() function to get the error location polynomial. Find the error positions finding the roots of the error location polynomial And correct the bits. This step can be hardware-assisted using the PMERRLOC module. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 447 30.18.1 MLC/SLC Write Page Operation Using PMECC When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR field of the PMECCFG register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then the SPAREEN bit of the PMECCFG register is set to one. When the NAND spare area contains only redundancy information, the SPAREEN bit is set to zero. When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation can be done with DMA assistance. Table 30-13. Relevant Redundancy Registers BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes 0 PMECC0 PMECC0 1 PMECC0, PMECC1 PMECC0, PMECC1 2 PMECC0, PMECC1, PMECC2, PMECC3 PMECC0, PMECC1, PMECC2, PMECC3 3 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6 4 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9, PMECC10 Table 30-14. Number of Relevant ECC Bytes per Sector, Copied from LSByte to MSByte BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes 0 4 bytes 4 bytes 1 7 bytes 7 bytes 2 13 bytes 14 bytes 3 20 bytes 21 bytes 4 39 bytes 42 bytes 30.18.1.1 SLC/MLC Write Operation with Spare Enable Bit Set When the SPAREEN field of the PMECCFG register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. This mode is entered by writing 1 in the DATA field of the PMECCTRL register. When the encoding process is over, the redundancy shall be written to the spare area in user mode. The USER field of the PMECCTRL register must be set to one. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 448 Figure 30-40.NAND Write Operation with Spare Encoding Write NAND operation with SPAREEN set to one pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 sparesize Sector 3 Spare 512 or 1024 bytes ecc_area start_addr end_addr ECC computation enable signal 30.18.1.2 SLC/MLC Write Operation with Spare Disable When the SPAREEN field of PMECCFG is set to zero, the spare area is not encoded with the stream of data. This mode is entered by writing 1 to the DATA field of the PMECCTRL register. Figure 30-41.NAND Write Operation Write NAND operation with SPAREEN set to zero pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 Sector 3 512 or 1024 bytes ECC computation enable signal 30.18.2 MLC/SLC Read Page Operation Using PMECC Table 30-15. Relevant Remainder Registers BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes 0 PMECCREM0 PMECCREM0 1 PMECCREM0, PMECCREM1 PMECCREM0, PMECCREM1 2 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3 3 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM4, PMECCREM5, PMECCREM6, PMECCREM7 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM4, PMECCREM5, PMECCREM6, PMECCREM7 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 449 Table 30-15. Relevant Remainder Registers (Continued) BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes 4 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM4, PMECCREM5, PMECCREM6, PMECCREM7, PMECCREM8, PMECCREM9, PMECCREM10, PMECCREM11 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM4, PMECCREM5, PMECCREM6, PMECCREM7, PMECCREM8, PMECCREM9, PMECCREM10, PMECCREM11 30.18.2.1 MLC/SLC Read Operation with Spare Decoding When the spare area is protected, it contains valid data. As the redundancy may be included in the middle of the information stream, the user shall program the start address and the end address of the ECC area. The controller will automatically skip the ECC area. This mode is entered writing 1 in the DATA field of the PMECCTRL register. When the page has been fully retrieved from the NAND, the ECC area shall be read using the user mode, writing 1 to the USER field of the PMECCTRL register. Figure 30-42.Read Operation with Spare Decoding Read NAND operation with SPAREEN set to One and AUTO set to Zero pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 sparesize Sector 3 Spare 512 or 1024 bytes ecc_area start_addr end_addr Remainder computation enable signal 30.18.2.2 MLC/SLC Read Operation If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode is entered writing 1 in the DATA field of the PMECCTRL register. When AUTO field is set to one, the ECC is retrieved automatically; otherwise, the ECC must be read using the user mode. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 450 Figure 30-43.Read Operation Read NAND operation with SPAREEN set to Zero and AUTO set to One pagesize = n * sectorsize Sector 0 Sector 1 sparesize Sector 2 Sector 3 Spare 512 or 1024 bytes ecc_area ECC_BLK2 ECC_BLK1 ECC_BLK0 ECC_BLK3 end_addr start_addr Remainder computation enable signal 30.18.2.3 MLC/SLC User Read ECC Area This mode allows a manual retrieve of the ECC. It is entered writing 1 in the USER field of the PMECCTRL register. Figure 30-44.Read User Mode ecc_area_size ECC ecc_area addr = 0 end_addr Remainder computation enable signal SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 451 30.18.2.4 MLC Controller Working with NAND Flash Controller Table 30-16. MLC Controller Configuration when the Host Controller is Used NFC Transfer Type PMECC RSPARE WSPARE SPAREEN AUTO User Mode Program Page main area is protected, spare is not protected, spare is written manually 0 0 0 0 Not used Program Page main area is protected, spare is protected, spare is written by NFC 0 1 1 0 Not used Read Page main area is protected, spare is not protected, spare is not retrieved by NFC 0 0 0 0 Used Read Page main area is protected, spare is not protected, spare is retrieved by NFC 1 0 0 1 Not used Read Page main area is protected, spare is protected, spare is retrieved by NFC 1 0 1 0 Used 30.19 Software Implementation 30.19.1 Remainder Substitution Procedure The substitute function evaluates the remainder polynomial, with different values of the field primitive element. The addition arithmetic operation is performed with the exclusive OR. The multiplication arithmetic operation is performed through the gf_log and gf_antilog look-up tables. The REM2NP1 and REMN2NP3 fields of the PMECCREMN registers contain only odd remainders. Each bit indicates whether the coefficient of the remainder polynomial is set to zero or not. NB_ERROR_MAX defines the maximum value of the error correcting capability. NB_ERROR defines the error correcting capability selected at encoding/decoding time. NB_FIELD_ELEMENTS defines the number of elements in the field. si[] is a table that holds the current syndrome value. An element of that table belongs to the field. This is also a shared variable for the next step of the decoding operation. oo[] is a table that contains the degree of the remainders. int { int int for { substitute() i; j; (i = 1; i < 2 * NB_ERROR_MAX; i++) si[i] = 0; } for (i = 1; i < 2*NB_ERROR; i++) { for (j = 0; j < oo[i]; j++) { SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 452 if (REM2NPX[i][j]) { si[i] = gf_antilog[(i * j)%NB_FIELD_ELEMENTS] ^ si[i]; } } } return 0; } 30.19.2 Find the Error Location Polynomial Sigma(x) The sample code below gives a Berlekamp iterative procedure for finding the value of the error location polynomial. The input of the procedure is the si[] table defined in the remainder substitution procedure. The output of the procedure is the error location polynomial named smu (sigma mu). The polynomial coefficients belong to the field. The smu[NB_ERROR+1][] is a table that contains all these coefficients. NB_ERROR_MAX defines the maximum value of the error correcting capability. NB_ERROR defines the error correcting capability selected at encoding/decoding time. NB_FIELD_ELEMENTS defines the number of elements in the field. int get_sigma() { int i; int j; int k; /* mu */ int mu[NB_ERROR_MAX+2]; /* sigma ro */ int sro[2*NB_ERROR_MAX+1]; /* discrepancy */ int dmu[NB_ERROR_MAX+2]; /* delta order */ int delta[NB_ERROR_MAX+2]; /* index of largest delta */ int ro; int largest; int diff; /* */ /* First Row */ /* */ /* Mu */ mu[0] = -1; /* Actually -1/2 */ /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[0][i] = 0; smu[0][0] = 1; /* discrepancy set to 1 */ dmu[0] = 1; /* polynom order set to 0 */ lmu[0] = 0; /* delta set to -1 */ delta[0] = (mu[0] * 2 - lmu[0]) >> 1; /* */ /* Second Row */ /* */ /* Mu */ SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 453 mu[1] = 0; /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[1][i] = 0; smu[1][0] = 1; /* discrepancy set to Syndrome 1 */ dmu[1] = si[1]; /* polynom order set to 0 */ lmu[1] = 0; /* delta set to 0 */ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; for (i=1; i <= NB_ERROR; i++) { mu[i+1] = i << 1; /*************************************************/ /* */ /* */ /* Compute Sigma (Mu+1) */ /* And L(mu) */ /* check if discrepancy is set to 0 */ if (dmu[i] == 0) { /* copy polynom */ for (j=0; j<2*NB_ERROR_MAX+1; j++) { smu[i+1][j] = smu[i][j]; } /* copy previous polynom order to the next */ lmu[i+1] = lmu[i]; } else { ro = 0; largest = -1; /* find largest delta with dmu != 0 */ for (j=0; j<i; j++) { if (dmu[j]) { if (delta[j] > largest) { largest = delta[j]; ro = j; } } } /* initialize signal ro */ for (k = 0; k < 2*NB_ERROR_MAX+1; k ++) { sro[k] = 0; } /* compute difference */ diff = (mu[i] - mu[ro]); /* compute X ^ (2(mu-ro)) */ for (k = 0; k < (2*NB_ERROR_MAX+1); k ++) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 454 { sro[k+diff] = smu[ro][k]; } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*NB_ERROR_MAX+1; k ++) { /* dmu[ro] is not equal to zero by definition */ /* check that operand are different from 0 */ if (sro[k] && dmu[i]) { /* galois inverse */ sro[k] = gf_antilog[(gf_log[dmu[i]] + (NB_FIELD_ELEMENTSgf_log[dmu[ro]]) + gf_log[sro[k]]) % NB_FIELD_ELEMENTS]; } } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*NB_ERROR_MAX+1; k++) { smu[i+1][k] = smu[i][k] ^ sro[k]; if (smu[i+1][k]) { /* find the order of the polynom */ lmu[i+1] = k << 1; } } } /* */ /* */ /* End Compute Sigma (Mu+1) */ /* And L(mu) */ /*************************************************/ /* In either case compute delta */ delta[i+1] = (mu[i+1] * 2 - lmu[i+1]) >> 1; /* In either case compute the discrepancy */ for (k = 0 ; k <= (lmu[i+1]>>1); k++) { if (k == 0) dmu[i+1] = si[2*(i-1)+3]; /* check if one operand of the multiplier is null, its index is -1 */ else if (smu[i+1][k] && si[2*(i-1)+3-k]) dmu[i+1] = gf_antilog[(gf_log[smu[i+1][k]] + gf_log[si[2*(i-1)+3-k]])%nn] ^ dmu[i+1]; } } return 0; } 30.19.3 Find the Error Position The output of the get_sigma() procedure is a polynomial stored in the smu[NB_ERROR+1][] table. The error positions are the roots of that polynomial. The degree of that polynomial is a very important information, as it gives the number of errors. PMERRLOC module provides hardware accelerator for that step. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 455 30.19.3.1 Error Location The PMECC Error Location controller provides hardware acceleration for determining roots of polynomials over two finite fields: GF(2^13) and GF(2^14). It integrates 32 fully programmable coefficients. These coefficients belong to GF(2^13) or GF(2^14). The coefficient programmed in the PMERRLOC{i} is the coefficient of X ^ i in the polynomial. The search operation is started as soon as a write access is detected in the ELEN register and can be disabled writing to the ELDIS register. The ENINIT field of the ELEN register shall be initialized with the number of galois field elements to test. The set of the roots can be limited to a valid range. Table 30-17. ENINIT Field Value for a Sector Size of 512 Bytes Error Correcting Capability ENINIT Value 2 4122 4 4148 8 4200 12 4252 24 4408 Table 30-18. ENINIT Field Value for a Sector Size of 1024 Bytes Error Correcting Capability ENINIT Value 2 8220 4 8248 8 8304 12 8360 24 8528 When the PMECC engine is searching for roots, the BUSY field of the ELSR register remains asserted. An interrupt is asserted at the end of the computation, and the DONE bit of the PMECC Error Location Interrupt Status Register (HSMC_ELSIR) is set. The ERR_CNT field of the HSMC_ELISR indicates the number of errors. The error position can be read in the PMERRLOCX registers. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 456 30.20 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 30-19. For each chip select, a set of four registers is used to program the parameters of the external device. In Table 30-19, "CS_number" denotes the chip select number. Sixteen bytes per chip select are required. Table 30-19. Register Mapping Offset Register Name Access Reset 0x000 HSMC NFC Configuration Register HSMC_CFG Read/Write 0x0 0x004 HSMC NFC Control Register HSMC_CTRL Write-only 0x0 0x008 HSMC NFC Status Register HSMC_SR Read-only 0x0 0x00C HSMC NFC Interrupt Enable Register HSMC_IER Write-only 0x0 0x010 HSMC NFC Interrupt Disable Register HSMC_IDR Write-only 0x0 0x014 HSMC NFC Interrupt Mask Register HSMC_IMR Read-only 0x0 0x018 HSMC NFC Address Cycle Zero Register HSMC_ADDR Read/Write 0x0 0x01C HSMC Bank Address Register HSMC_BANK Read/Write 0x0 0x020-0x06C Reserved - - - 0x70 PMECC Configuration Register HSMC_PMECCFG Read/Write 0x0 0x74 PMECC Spare Area Size Register HSMC_PMECCSAREA Read/Write 0x0 0x78 PMECC Start Address Register HSMC_PMECCSADDR Read/Write 0x0 0x7C PMECC End Address Register HSMC_PMECCEADDR Read/Write 0x0 0x80 Reserved - - - 0x84 PMECC Control Register HSMC_PMECCTRL Write-only 0x0 0x88 PMECC Status Register HSMC_PMECCSR Read-only 0x0 0x8C PMECC Interrupt Enable register HSMC_PMECCIER Write-only 0x0 0x90 PMECC Interrupt Disable Register HSMC_PMECCIDR Write-only - 0x94 PMECC Interrupt Mask Register HSMC_PMECCIMR Read-only 0x0 0x98 PMECC Interrupt Status Register HSMC_PMECCISR Read-only 0x0 0x9C-AC Reserved - - - 0x0B0+sec_num*(0x40)+0x00 PMECC Redundancy 0 Register HSMC_PMECC0 Read-only 0x0 0x0B0+sec_num*(0x40)+0x04 PMECC Redundancy 1 Register HSMC_PMECC1 Read-only 0x0 0x0B0+sec_num*(0x40)+0x08 PMECC Redundancy 2 Register HSMC_PMECC2 Read-only 0x0 0x0B0+sec_num*(0x40)+0x0C PMECC Redundancy 3 Register HSMC_PMECC3 Read-only 0x0 0x0B0+sec_num*(0x40)+0x10 PMECC Redundancy 4 Register HSMC_PMECC4 Read-only 0x0 0x0B0+sec_num*(0x40)+0x14 PMECC Redundancy 5 Register HSMC_PMECC5 Read-only 0x0 0x0B0+sec_num*(0x40)+0x18 PMECC Redundancy 6 Register HSMC_PMECC6 Read-only 0x0 0x0B0+sec_num*(0x40)+0x1C PMECC Redundancy 7 Register HSMC_PMECC7 Read-only 0x0 0x0B0+sec_num*(0x40)+0x20 PMECC Redundancy 8 Register HSMC_PMECC8 Read-only 0x0 0x0B0+sec_num*(0x40)+0x24 PMECC Redundancy 9 Register HSMC_PMECC9 Read-only 0x0 0x0B0+sec_num*(0x40)+0x28 PMECC Redundancy 10 Register HSMC_PMECC10 Read-only 0x0 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 457 Table 30-19. Register Mapping (Continued) Offset Register Name Access Reset 0x2B0+sec_num*(0x40)+0x00 PMECC Remainder 0 Register HSMC_REM0 Read-only 0x0 0x2B0+sec_num*(0x40)+0x04 PMECC Remainder 1 Register HSMC_REM1 Read-only 0x0 0x2B0+sec_num*(0x40)+0x08 PMECC Remainder 2 Register HSMC_REM2 Read-only 0x0 0x2B0+sec_num*(0x40)+0x0C PMECC Remainder 3 Register HSMC_REM3 Read-only 0x0 0x2B0+sec_num*(0x40)+0x10 PMECC Remainder 4 Register HSMC_REM4 Read-only 0x0 0x2B0+sec_num*(0x40)+0x14 PMECC Remainder 5 Register HSMC_REM5 Read-only 0x0 0x2B0+sec_num*(0x40)+0x18 PMECC Remainder 6 Register HSMC_REM6 Read-only 0x0 0x2B0+sec_num*(0x40)+0x1C PMECC Remainder 7 Register HSMC_REM7 Read-only 0x0 0x2B0+sec_num*(0x40)+0x20 PMECC Remainder 8 Register HSMC_REM8 Read-only 0x0 0x2B0+sec_num*(0x40)+0x24 PMECC Remainder 9 Register HSMC_REM9 Read-only 0x0 0x2B0+sec_num*(0x40)+0x28 PMECC Remainder 10 Register HSMC_REM10 Read-only 0x0 0x2B0+sec_num*(0x40)+0x2C PMECC Remainder 11 Register HSMC_REM11 Read-only 0x0 0x4A0-0x4FC Reserved - - - 0x500 PMECC Error Location Configuration Register HSMC_ELCFG Read/Write 0x0 0x504 PMECC Error Location Primitive Register HSMC_ELPRIM Read-only 0x401A 0x508 PMECC Error Location Enable Register HSMC_ELEN Write-only 0x0 0x50C PMECC Error Location Disable Register HSMC_ELDIS Write-only 0x0 0x510 PMECC Error Location Status Register HSMC_ELSR Read 0x0 0x514 PMECC Error Location Interrupt Enable register HSMC_ELIER Write-only 0x0 0x518 PMECC Error Location Interrupt Disable Register HSMC_ELIDR Write-only 0x0 0x51C PMECC Error Location Interrupt Mask Register HSMC_ELIMR Read 0x0 0x520 PMECC Error Location Interrupt Status Register HSMC_ELISR Read 0x0 0x524-0x52C Reserved - - - 0x528 PMECC Error Location SIGMA 0 Register HSMC_SIGMA0 Read/Write 0x1 ... ... ... ... ... 0x588 PMECC Error Location SIGMA 24 Register HSMC_SIGMA24 Read/Write 0x0 0x58C PMECC Error Location 0 Register HSMC_ERRLOC0 Read-only 0x0 ... ... ... ... ... 0x5E8 PMECC Error Location 23 Register HSMC_ERRLOC23 Read-only 0x0 0x5EC-0x5FC Reserved - - - 0x14*CS_number+0x600 HSMC Setup Register HSMC_SETUP Read/Write - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 458 Table 30-19. Register Mapping (Continued) Offset Register Name Access Reset 0x14*CS_number+0x604 HSMC Pulse Register HSMC_PULSE Read/Write - 0x14*CS_number+0x608 HSMC Cycle Register HSMC_CYCLE Read/Write - 0x14*CS_number+0x60C HSMC Timings Register HSMC_TIMINGS Read/Write - 0x14*CS_number+0x610 HSMC Mode Register HSMC_MODE Read/Write - 0x6A0 HSMC Off Chip Memory Scrambling Register HSMC_OCMS Read/Write 0x0 0x6A4 HSMC Off Chip Memory Scrambling KEY1 Register HSMC_KEY1 Write-once 0x0 0x6A8 HSMC Off Chip Memory Scrambling KEY2 Register HSMC_KEY2 Write-once 0x0 0x6AC-0x6E0 Reserved - - - 0x6E4 HSMC Write Protection Mode Register HSMC_WPMR Read/Write 0x0 0x6E8 HSMC Write Protection Status Register HSMC_WPSR Read-only 0x0 0x6FC Reserved - - - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 459 30.20.1 HSMC NFC Configuration Register Name: HSMC_CFG Address: 0xFFFFC000 Access: Read/Write Reset: 0x00000000 31 - 30 29 28 27 NFCSPARESIZE 26 25 24 23 - 22 21 DTOMUL 20 19 18 17 16 15 - 14 - 13 RBEDGE 12 EDGECTRL 11 - 10 - 9 RSPARE 8 WSPARE 7 - 6 - 5 - 4 - 3 - 2 1 PAGESIZE 0 DTOCYC * PAGESIZE: Page Size of the NAND Flash Device Value Name Description 0 PS512 Main area 512 bytes 1 PS1024 Main area 1024 bytes 2 PS2048 Main area 2048 bytes 3 PS4096 Main area 4096 bytes 4 PS8192 Main area 8192 bytes * WSPARE: Write Spare Area 0: The NFC skips the spare area in write mode. 1: The NFC writes both main area and spare area in write mode. * RSPARE: Read Spare Area 0: The NFC skips the spare area in read mode. 1: The NFC reads both main area and spare area in read mode. * EDGECTRL: Rising/Falling Edge Detection Control 0: Rising edge is detected 1: Falling edge is detected * RBEDGE: Ready/Busy Signal Edge Detection 0: When set to zero, RB_EDGE fields indicate the level of the Ready/Busy lines. 1: When set to one, RB_EDGE fields indicate only transition on Ready/Busy lines. * DTOCYC: Data Timeout Cycle Number * DTOMUL: Data Timeout Multiplier SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 460 These fields determine the maximum number of Master Clock cycles that the SMC waits until the detection of a rising edge on Ready/Busy signal. Data Timeout Multiplier is defined by DTOMUL as shown in the following table: Value Name Description 0 X1 DTOCYC 1 X16 DTOCYC x 16 2 X128 DTOCYC x 128 3 X256 DTOCYC x 256 4 X1024 DTOCYC x 1024 5 X4096 DTOCYC x 4096 6 X65536 DTOCYC x 65536 7 X1048576 DTOCYC x 1048576 If the data timeout set by DTOCYC and DTOMUL has been exceeded, the Data Timeout Error flag (DTOE) in the NFC Status Register (NFC_SR) raises. * NFCSPARESIZE: NAND Flash Spare Area Size Retrieved by the Host Controller The spare size is set to (NFCSPARESIZE+1) * 4 bytes. The spare area is only retrieved when RSPARE or WSPARE is activated. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 461 30.20.2 HSMC NFC Control Register Name: HSMC_CTRL Address: 0xFFFFC004 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 NFCDIS 0 NFCEN * NFCEN: NAND Flash Controller Enable 0: No effect 1: Enable the NAND Flash controller. * NFCDIS: NAND Flash Controller Disable 0: No effect 1: Disable the NAND Flash controller. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 462 30.20.3 HSMC NFC Status Register Name: HSMC_SR Address: 0xFFFFC008 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 RB_EDGE0 23 NFCASE 22 AWB 21 UNDEF 20 DTOE 19 - 18 - 17 CMDDONE 16 XFRDONE 15 - 14 13 NFCSID 12 11 NFCWR 10 - 9 - 8 NFCBUSY 7 - 6 - 5 RB_FALL 4 RB_RISE 3 - 2 - 1 - 0 SMCSTS * SMCSTS: NAND Flash Controller Status (this field cannot be reset) 0: NAND Flash Controller disabled 1: NAND Flash Controller enabled * RB_RISE: Selected Ready Busy Rising Edge Detected When set to one, this flag indicates that a rising edge on the Ready/Busy Line has been detected. This flag is reset after a status read operation. The Ready/Busy line selected is the decoding of the set NFCCSID, RBNSEL fields. * RB_FALL: Selected Ready Busy Falling Edge Detected When set to one, this flag indicates that a falling edge on the Ready/Busy Line has been detected. This flag is reset after a status read operation. The Ready/Busy line is selected through the decoding of the set NFCSID, RBNSEL fields. * NFCBUSY: NFC Busy (this field cannot be reset) When set to one, this flag indicates that the Controller is activated and accesses the memory device. * NFCWR: NFC Write/Read Operation (this field cannot be reset) When a command is issued, this field indicates the current Read or Write Operation. * NFCSID: NFC Chip Select ID (this field cannot be reset) When a command is issued, this field indicates the value of the targeted chip select. * XFRDONE: NFC Data Transfer Terminated When set to one, this flag indicates that the NFC has terminated the Data Transfer. This flag is reset after a status read operation. * CMDDONE: Command Done When set to one, this flag indicates that the NFC has terminated the Command. This flag is reset after a status read operation. * DTOE: Data Timeout Error When set to one, this flag indicates that the Data timeout set be by DTOMUL and DTOCYC has been exceeded. This flag is reset after a status read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 463 * UNDEF: Undefined Area Error When set to one, this flag indicates that the processor performed an access in an undefined memory area. This flag is reset after a status read operation. * AWB: Accessing While Busy If set to one, this flag indicates that an AHB master has performed an access during the busy phase. This flag is reset after a status read operation. * NFCASE: NFC Access Size Error If set to one, this flag indicates that an illegal access has been detected in the NFC Memory Area. Only Word Access is allowed within the NFC memory area. This flag is reset after a status read operation. * RB_EDGEx: Ready/Busy Line x Edge Detected If set to one, this flag indicates that an edge has been detected on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the HSMC_CFG register, only rising or falling edge is detected. This flag is reset after a status read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 464 30.20.4 HSMC NFC Interrupt Enable Register Name: HSMC_IER Address: 0xFFFFC00C Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 RB_EDGE0 23 NFCASE 22 AWB 21 UNDEF 20 DTOE 19 - 18 - 17 CMDDONE 16 XFRDONE 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 RB_FALL 4 RB_RISE 3 - 2 - 1 - 0 - * RB_RISE: Ready Busy Rising Edge Detection Interrupt Enable 0: No effect 1: Interrupt source enabled * RB_FALL: Ready Busy Falling Edge Detection Interrupt Enable 0: No effect 1: Interrupt source enabled * XFRDONE: Transfer Done Interrupt Enable 0: No effect 1: Interrupt source enabled * CMDDONE: Command Done Interrupt Enable 0: No effect 1: Interrupt source enabled * DTOE: Data Timeout Error Interrupt Enable 0: No effect 1: Interrupt source enabled * UNDEF: Undefined Area Access Interrupt Enable 0: No effect 1: Interrupt source enabled * AWB: Accessing While Busy Interrupt Enable 0: No effect 1: Interrupt source enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 465 * NFCASE: NFC Access Size Error Interrupt Enable 0: No effect 1: Interrupt source enabled * RB_EDGEx: Ready/Busy Line x Interrupt Enable 0: No effect 1: Interrupt source enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 466 30.20.5 HSMC NFC Interrupt Disable Register Name: HSMC_IDR Address: 0xFFFFC010 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 RB_EDGE0 23 NFCASE 22 AWB 21 UNDEF 20 DTOE 19 - 18 - 17 CMDDONE 16 XFRDONE 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 RB_FALL 4 RB_RISE 3 - 2 - 1 - 0 - * RB_RISE: Ready Busy Rising Edge Detection Interrupt Disable 0: No effect 1: Interrupt source disabled * RB_FALL: Ready Busy Falling Edge Detection Interrupt Disable 0: No effect 1: Interrupt source disabled * XFRDONE: Transfer Done Interrupt Disable 0: No effect 1: Interrupt source disabled * CMDDONE: Command Done Interrupt Disable 0: No effect 1: Interrupt source disabled * DTOE: Data Timeout Error Interrupt Disable 0: No effect 1: Interrupt source disabled * UNDEF: Undefined Area Access Interrupt Disable 0: No effect 1: Interrupt source disabled * AWB: Accessing While Busy Interrupt Disable 0: No effect 1: Interrupt source disabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 467 * NFCASE: NFC Access Size Error Interrupt Disable 0: No effect 1: Interrupt source disabled * RB_EDGEx: Ready/Busy Line x Interrupt Disable 0: No effect 1: Interrupt source disabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 468 30.20.6 HSMC NFC Interrupt Mask Register Name: HSMC_IMR Address: 0xFFFFC014 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 RB_EDGE0 23 NFCASE 22 AWB 21 UNDEF 20 DTOE 19 - 18 - 17 CMDDONE 16 XFRDONE 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 RB_FALL 4 RB_RISE 3 - 2 - 1 - 0 - * RB_RISE: Ready Busy Rising Edge Detection Interrupt Mask 0: Interrupt source disabled 1: Interrupt source enabled * RB_FALL: Ready Busy Falling Edge Detection Interrupt Mask 0: Interrupt source disabled 1: Interrupt source enabled * XFRDONE: Transfer Done Interrupt Mask 0: Interrupt source disabled 1: Interrupt source enabled * CMDDONE: Command Done Interrupt Mask 0: Interrupt source disabled 1: Interrupt source enabled * DTOE: Data Timeout Error Interrupt Mask 0: Interrupt source disabled 1: Interrupt source enabled * UNDEF: Undefined Area Access Interrupt Mask5 0: Interrupt source disabled 1: Interrupt source enabled * AWB: Accessing While Busy Interrupt Mask 0: Interrupt source disabled 1: Interrupt source enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 469 * NFCASE: NFC Access Size Error Interrupt Mask 0: Interrupt source disabled 1: Interrupt source enabled * RB_EDGEx: Ready/Busy Line x Interrupt Mask 0: Interrupt source disabled 1: Interrupt source enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 470 30.20.7 HSMC NFC Address Cycle Zero Register Name: HSMC_ADDR Address: 0xFFFFC018 Access: Read/Write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 ADDR_CYCLE0 2 1 0 * ADDR_CYCLE0: NAND Flash Array Address Cycle 0 When five address cycles are used, ADDR_CYCLE0 is the first byte written to the NAND Flash (used by the NFC). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 471 30.20.8 HSMC NFC Bank Register Name: HSMC_BANK Address: 0xFFFFC01C Access: Read/Write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 BANK * BANK: Bank Identifier 0: Bank 0 is used. 1: Bank 1 is used. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 472 30.20.9 PMECC Configuration Register Name: HSMC_PMECCFG Address: 0xFFFFC070 Access: Read/Write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 AUTO 19 - 18 - 17 - 16 SPAREEN 15 - 14 - 13 - 12 NANDWR 11 - 10 - 9 7 - 6 - 5 - 4 SECTORSZ 3 - 2 1 BCH_ERR 8 PAGESIZE 0 * BCH_ERR: Error Correcting Capability Value Name Description 0 BCH_ERR2 2 errors 1 BCH_ERR4 4 errors 2 BCH_ERR8 8 errors 3 BCH_ERR12 12 errors 4 BCH_ERR24 24 errors * SECTORSZ: Sector Size 0: The ECC computation is based on a sector of 512 bytes. 1: The ECC computation is based on a sector of 1024 bytes. * PAGESIZE: Number of Sectors in the Page Value Name Description 0 PAGESIZE_1SEC 1 sector for main area (512 or 1024 bytes) 1 PAGESIZE_2SEC 2 sectors for main area (1024 or 2048 bytes) 2 PAGESIZE_4SEC 4 sectors for main area (2048 or 4096 bytes) 3 PAGESIZE_8SEC 8 sectors for main area (4096 or 8192 bytes) * NANDWR: NAND Write Access 0: NAND read access 1: NAND write access SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 473 * SPAREEN: Spare Enable - for NAND write access: 0: The spare area is skipped 1: The spare area is protected with the last sector of data. - for NAND read access: 0: The spare area is skipped. 1: The spare area contains protected data or only redundancy information. * AUTO: Automatic Mode Enable This bit is only relevant in NAND Read Mode, when spare enable is activated. 0: Indicates that the spare area is not protected. In that case, the ECC computation takes into account the ECC area located in the spare area. (within the start address and the end address). 1: Indicates that the spare area is error protected. In this case, the ECC computation takes into account the whole spare area minus the ECC area in the ECC computation operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 474 30.20.10 PMECC Spare Area Size Register Name: HSMC_PMECCSAREA Address: 0xFFFFC074 Access: Read/Write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 SPARESIZE 7 6 5 4 3 2 1 0 SPARESIZE * SPARESIZE: Spare Area Size Number of bytes in the spare area. The spare area size is equal to (SPARESIZE + 1) bytes. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 475 30.20.11 PMECC Start Address Register Name: HSMC_PMECCSADDR Address: 0xFFFFC078 Access: Read/Write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 STARTADDR 7 6 5 4 3 2 1 0 STARTADDR * STARTADDR: ECC Area Start Address This register is programmed with the start ECC start address. When STARTADDR is equal to 0, then the first ECC byte is located at the first byte of the spare area. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 476 30.20.12 PMECC End Address Register Name: HSMC_PMECCEADDR Address: 0xFFFFC07C Access: Read/Write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 ENDADDR 7 6 5 4 3 2 1 0 ENDADDR * ENDADDR: ECC Area End Address This register is programmed with the start ECC end address. When ENDADDR is equal to N, then the first ECC byte is located at byte N of the spare area. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 477 30.20.13 PMECC Control Register Name: HSMC_PMECCTRL Address: 0xFFFFC084 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 DISABLE 4 ENABLE 3 - 2 USER 1 DATA 0 RST * RST: Reset the PMECC Module 0: No effect 1: Reset the PMECC controller. * DATA: Start a Data Phase 0: No effect 1: The PMECC controller enters a Data phase. * USER: Start a User Mode Phase 0: No effect 1: The PMECC controller enters a User mode phase. * ENABLE: PMECC Enable 0: No effect 1: Enable the PMECC controller. * DISABLE: PMECC Enable 0: No effect 1: Disable the PMECC controller. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 478 30.20.14 PMECC Status Register Name: HSMC_PMECCSR Address: 0xFFFFC088 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 ENABLE 3 - 2 - 1 - 0 BUSY * BUSY: The kernel of the PMECC is busy 0: PMECC controller finite state machine reached idle state 1: PMECC controller finite state machine is processing the incoming byte stream * ENABLE: PMECC Enable bit 0: PMECC controller disabled 1: PMECC controller enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 479 30.20.15 PMECC Interrupt Enable Register Name: HSMC_PMECCIER Address: 0xFFFFC08C Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ERRIE * ERRIE: Error Interrupt Enable 0: No effect 1: The Multibit Error interrupt is enabled. An interrupt will be raised if at least one error is detected in at least one sector. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 480 30.20.16 PMECC Interrupt Disable Register Name: HSMC_PMECCIDR Address: 0xFFFFC090 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ERRID * ERRID: Error Interrupt Disable 0: No effect 1: Multibit Error interrupt disabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 481 30.20.17 PMECC Interrupt Mask Register Name: HSMC_PMECCIMR Address: 0xFFFFC094 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ERRIM * ERRIM: Error Interrupt Mask 0: Multibit Error disabled 1: Multibit Error enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 482 30.20.18 PMECC Interrupt Status Register Name: HSMC_PMECCISR Address: 0xFFFFC098 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 ERRIS * ERRIS: Error Interrupt Status Register When set to one, bit i of the HSMC_PMECCISR indicates that sector i is corrupted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 483 30.20.19 PMECC Redundancy x Register Name: HSMC_PMECCx [x=0..10] [sec_num=0..7] Address: 0xFFFFC0B0 [0][0] .. 0xFFFFC0D8 [10][0] 0xFFFFC0F0 [0][1] .. 0xFFFFC118 [10][1] 0xFFFFC130 [0][2] .. 0xFFFFC158 [10][2] 0xFFFFC170 [0][3] .. 0xFFFFC198 [10][3] 0xFFFFC1B0 [0][4] .. 0xFFFFC1D8 [10][4] 0xFFFFC1F0 [0][5] .. 0xFFFFC218 [10][5] 0xFFFFC230 [0][6] .. 0xFFFFC258 [10][6] 0xFFFFC270 [0][7] .. 0xFFFFC298 [10][7] Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ECC 23 22 21 20 ECC 15 14 13 12 ECC 7 6 5 4 ECC * ECC: BCH Redundancy This register contains the remainder of the division of the codeword by the generator polynomial. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 484 30.20.20 PMECC Remainder x Register Name: HSMC_REMx [x=0..11] [sec_num=0..7] Address: 0xFFFFC2B0 [0][0] .. 0xFFFFC2DC [11][0] 0xFFFFC2F0 [0][1] .. 0xFFFFC31C [11][1] 0xFFFFC330 [0][2] .. 0xFFFFC35C [11][2] 0xFFFFC370 [0][3] .. 0xFFFFC39C [11][3] 0xFFFFC3B0 [0][4] .. 0xFFFFC3DC [11][4] 0xFFFFC3F0 [0][5] .. 0xFFFFC41C [11][5] 0xFFFFC430 [0][6] .. 0xFFFFC45C [11][6] 0xFFFFC470 [0][7] .. 0xFFFFC49C [11][7] Access: Read-only Reset: 0x00000000 31 - 30 - 29 23 22 21 28 27 26 25 24 18 17 16 10 9 8 2 1 0 REM2NP3 20 19 REM2NP3 15 - 14 - 13 7 6 5 12 11 REM2NP1 4 3 REM2NP1 * REM2NP1: BCH Remainder 2 * N + 1 When sector size is set to 512 bytes, bit REM2NP1[13] is not used and read as zero. If bit i of the REM2NP1 field is set to one, then the coefficient of the X ^ i is set to one; otherwise, the coefficient is zero. * REM2NP3: BCH Remainder 2 * N + 3 When sector size is set to 512 bytes, bit REM2NP3[29] is not used and read as zero. If bit i of the REM2NP3 field is set to one, then the coefficient of the X ^ i is set to one; otherwise, the coefficient is zero. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 485 30.20.21 PMECC Error Location Configuration Register Name: HSMC_ELCFG Address: 0xFFFFC500 Access: Read/Write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 19 18 ERRNUM 17 16 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SECTORSZ * ERRNUM: Number of Errors * SECTORSZ: Sector Size 0: The ECC computation is based on a 512 bytes sector. 1: The ECC computation is based on a 1024 bytes sector. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 486 30.20.22 PMECC Error Location Primitive Register Name: HSMC_ELPRIM Address: 0xFFFFC504 Access: Read-only Reset: 0x401A 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 11 10 9 8 3 2 1 0 PRIMITIV 7 6 5 4 PRIMITIV * PRIMITIV: Primitive Polynomial This field indicates the Primitive Polynomial used in the ECC computation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 487 30.20.23 PMECC Error Location Enable Register Name: HSMC_ELEN Address: 0xFFFFC508 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 12 11 10 9 8 7 6 5 2 1 0 ENINIT 4 3 ENINIT * ENINIT: Error Location Enable Initial bit number in the codeword. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 488 30.20.24 PMECC Error Location Disable Register Name: HSMC_ELDIS Address: 0xFFFFC50C Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DIS * DIS: Disable Error Location Engine 0: No effect 1: Disable the Error location engine. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 489 30.20.25 PMECC Error Location Status Register Name: HSMC_ELSR Address: 0xFFFFC510 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 BUSY * BUSY: Error Location Engine Busy 0: Error location engine is disabled. 1: Error location engine is enabled and is finding roots of the polynomial. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 490 30.20.26 PMECC Error Location Interrupt Enable Register Name: HSMC_ELIER Address: 0xFFFFC514 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DONE * DONE: Computation Terminated Interrupt Enable 0: No effect 1: Interrupt Enable. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 491 30.20.27 PMECC Error Location Interrupt Disable Register Name: HSMC_ELIDR Address: 0xFFFFC518 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DONE * DONE: Computation Terminated Interrupt Disable 0: No effect 1: Interrupt disable. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 492 30.20.28 PMECC Error Location Interrupt Mask Register Name: HSMC_ELIMR Address: 0xFFFFC51C Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DONE * DONE: Computation Terminated Interrupt Mask 0: Computation Terminated interrupt disabled 1: Computation Terminated interrupt enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 493 30.20.29 PMECC Error Location Interrupt Status Register Name: HSMC_ELISR Address: 0xFFFFC520 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 11 10 ERR_CNT 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DONE * DONE: Computation Terminated Interrupt Status When set to one, this indicates that the error location engine has completed the root finding algorithm. * ERR_CNT: Error Counter value This field indicates the number of roots of the polynomial. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 494 30.20.30 PMECC Error Location SIGMAx Register Name: HSMC_SIGMAx [x=0..24] Address: 0xFFFFC528 [0] .. 0xFFFFC588 [24] Access: Read/Write Reset: 0x1 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 12 11 10 9 8 7 6 5 2 1 0 SIGMAx 4 3 SIGMAx * SIGMAx: Coefficient of degree x in the SIGMA polynomial. SIGMAx belongs to the finite field GF(2^13) when the sector size is set to 512 bytes. SIGMAx belongs to the finite field GF(2^14) when the sector size is set to 1024 bytes. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 495 30.20.31 PMECC Error Location x Register Name: HSMC_ERRLOCx [x=0..23] Address: 0xFFFFC58C Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 12 11 10 9 8 7 6 5 2 1 0 ERRLOCN 4 3 ERRLOCN * ERRLOCN: Error Position within the Set {sector area, spare area} ERRLOCN points to 1 when the first bit of the main area is corrupted. If the sector size is set to 512 bytes, the ERRLOCN points to 4096 when the last bit of the sector area is corrupted. If the sector size is set to 1024 bytes, the ERRLOCN points to 8192 when the last bit of the sector area is corrupted. If the sector size is set to 512 bytes, the ERRLOCN points to 4097 when the first bit of the spare area is corrupted. If the sector size is set to 1024 bytes, the ERRLOCN points to 8193 when the first bit of the spare area is corrupted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 496 30.20.32 HSMC Setup Register Name: HSMC_SETUPx [x=0..3] Address: 0xFFFFC600 [0], 0xFFFFC614 [1], 0xFFFFC628 [2], 0xFFFFC63C [3] Access: Write-only Reset: - 31 - 30 - 29 28 27 26 NCS_RD_SETUP 25 24 23 - 22 - 21 20 19 18 17 16 15 - 14 - 13 12 11 10 NCS_WR_SETUP 9 8 7 - 6 - 5 4 3 1 0 NRD_SETUP 2 NWE_SETUP This register can only be written if the WPEN bit is cleared in the HSMC Write Protection Mode Register. * NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128 * NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles. * NCS_WR_SETUP: NCS Setup Length in Write Access In write access, the NCS signal setup length is defined as: NCS setup length = (128 * NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles. * NRD_SETUP: NRD Setup Length The NRD signal setup length is defined as: NRD setup length = (128 * NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles. * NCS_RD_SETUP: NCS Setup Length in Read Access In Read access, the NCS signal setup length is defined as: NCS setup length = (128 * NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 497 30.20.33 HSMC Pulse Register Name: HSMC_PULSEx [x=0..3] Address: 0xFFFFC604 [0], 0xFFFFC618 [1], 0xFFFFC62C [2], 0xFFFFC640 [3] Access: Write-only Reset: - 31 - 30 - 29 28 27 26 NCS_RD_PULSE 25 24 23 - 22 - 21 20 19 18 17 16 15 - 14 - 13 12 11 10 NCS_WR_PULSE 9 8 7 - 6 - 5 4 3 1 0 NRD_PULSE 2 NWE_PULSE This register can only be written if the WPEN bit is cleared in the HSMC Write Protection Mode Register. * NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256 * NWE_PULSE[6]+NWE_PULSE[5:0]) clock cycles. The NWE pulse must be at least one clock cycle. * NCS_WR_PULSE: NCS Pulse Length in WRITE Access In Write access, The NCS signal pulse length is defined as: NCS pulse length = (256 * NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles. The NCS pulse must be at least one clock cycle. * NRD_PULSE: NRD Pulse Length The NRD signal pulse length is defined as: NRD pulse length = (256 * NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles. The NRD pulse width must be as least 1 clock cycle. * NCS_RD_PULSE: NCS Pulse Length in READ Access In READ mode, The NCS signal pulse length is defined as: NCS pulse length = (256 * NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 498 30.20.34 HSMC Cycle Register Name: HSMC_CYCLEx [x=0..3] Address: 0xFFFFC608 [0], 0xFFFFC61C [1], 0xFFFFC630 [2], 0xFFFFC644 [3] Access: Read/Write Reset: - 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 - 24 NRD_CYCLE 19 18 17 16 11 - 10 - 9 - 8 NWE_CYCLE 3 2 1 0 NRD_CYCLE 15 - 14 - 13 - 12 - 7 6 5 4 NWE_CYCLE This register can only be written if the WPEN bit is cleared in the HSMC Write Protection Mode Register. * NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as: Write cycle length = (NWE_CYCLE[8:7] * 256) + NWE_CYCLE[6:0] clock cycles. * NRD_CYCLE: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read cycle length = (NRD_CYCLE[8:7] * 256) + NRD_CYCLE[6:0] clock cycles. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 499 30.20.35 HSMC Timings Register Name: HSMC_TIMINGSx [x=0..3] Address: 0xFFFFC60C [0], 0xFFFFC620 [1], 0xFFFFC634 [2], 0xFFFFC648 [3] Access: Read/Write Reset: - 31 NFSEL 30 29 RBNSEL 28 23 - 27 22 - 21 - 20 - 19 15 - 14 - 13 - 12 OCMS 11 7 6 5 4 3 26 25 24 17 16 9 8 1 0 TWB 18 TRR 10 TAR 2 TADL TCLR This register can only be written if the WPEN bit is cleared in the HSMC Write Protection Mode Register. * TCLR: CLE to REN Low Delay Command Latch Enable falling edge to Read Enable falling edge timing. Latch Enable Falling to Read Enable Falling = (TCLR[3] * 64) + TCLR[2:0] clock cycles. * TADL: ALE to Data Start Last address latch cycle to the first rising edge of WEN for data input. Last address latch to first rising edge of WEN = (TADL[3] * 64) + TADL[2:0] clock cycles. * TAR: ALE to REN Low Delay Address Latch Enable falling edge to Read Enable falling edge timing. Address Latch Enable to Read Enable = (TAR[3] * 64) + TAR[2:0] clock cycles. * OCMS: Off Chip Memory Scrambling Enable When set to one, the memory scrambling is activated. * TRR: Ready to REN Low Delay Ready/Busy signal to Read Enable falling edge timing. Read to REN = (TRR[3] * 64) + TRR[2:0] clock cycles. * TWB: WEN High to REN to Busy Write Enable rising edge to Ready/Busy falling edge timing. Write Enable to Read/Busy = (TWB[3] * 64) + TWB[2:0] clock cycles. * RBNSEL: Ready/Busy Line Selection This field indicates the selected Ready/Busy Line from the RBN bundle. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 500 * NFSEL: NAND Flash Selection If this bit is set to one, the chip select is assigned to NAND Flash write enable and read enable lines drive the Error Correcting Code module. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 501 30.20.36 HSMC Mode Register Name: HSMC_MODEx [x=0..3] Address: 0xFFFFC610 [0], 0xFFFFC624 [1], 0xFFFFC638 [2], 0xFFFFC64C [3] Access: Read/Write Reset: - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 TDF_MODE 19 18 17 TDF_CYCLES 16 15 - 14 - 13 - 12 DBW 11 - 10 - 7 - 6 - 5 4 3 - 2 - EXNW_MODE 9 - 8 BAT 1 0 WRITE_MODE READ_MODE This register can only be written if the WPEN bit is cleared in the HSMC Write Protection Mode Register. * READ_MODE: Selection of the Control Signal for Read Operation 1 (NRD_CTRL): The Read operation is controlled by the NRD signal. 0 (NCS_CTRL): The Read operation is controlled by the NCS signal. * WRITE_MODE: Selection of the Control Signal for Write Operation 1 (NWE_CTRL): The Write operation is controlled by the NWE signal. 0 (NCS_CTRL): The Write operation is controller by the NCS signal. * EXNW_MODE: NWAIT Mode The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase Read and Write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal. Value Name Description 0 DISABLED Disabled 1 -- Reserved 2 FROZEN Frozen Mode 3 READY Ready Mode * Disabled: The NWAIT input signal is ignored on the corresponding Chip Select. * Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. * Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 502 * BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus. 1 (BYTE_WRITE): Byte write access type: - Write operation is controlled using NCS, NWR0, NWR1. - Read operation is controlled using NCS and NRD. 0 (BYTE_SELECT): Byte select access type: - Write operation is controlled using NCS, NWE, NBS0, NBS1. - Read operation is controlled using NCS, NRD, NBS0, NBS1. * DBW: Data Bus Width Value Name Description 0 BIT_8 8-bit bus 1 BIT_16 16-bit bus * TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set. * TDF_MODE: TDF Optimization 1: TDF optimization enabled - The number of TDF wait states is optimized using the setup period of the next read/write access. 0: TDF optimization disabled - The number of TDF wait states is inserted before the next access begins. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 503 30.20.37 HSMC Off Chip Memory Scrambling Register Name: HSMC_OCMS Address: 0xFFFFC6A0 Access: Read/Write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 SRSE 0 SMSE * SMSE: Static Memory Controller Scrambling Enable 0: Disable "Off Chip" Scrambling for SMC access. 1: Enable "Off Chip" Scrambling for SMC access. (If OCMS field is set to 1 in the relevant HSMC_TIMINGS register.) * SRSE: SRAM Scrambling Enable 0: Disable SRAM Scrambling for SRAM access. 1: Enable SRAM Scrambling for SRAM access. (If OCMS field is set to 1 in the relevant HSMC_TIMINGS register.) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 504 30.20.38 HSMC Off Chip Memory Scrambling Key1 Register Name: HSMC_KEY1 Address: 0xFFFFC6A4 Access: Write-once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1 23 22 21 20 KEY1 15 14 13 12 KEY1 7 6 5 4 KEY1 * KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1 When Off Chip Memory Scrambling is enabled by setting the HSMC_OMCS and HSMC_TIMINGS registers in accordance, the data scrambling depends on KEY1 and KEY2 values. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 505 30.20.39 HSMC Off Chip Memory Scrambling Key2 Register Name: HSMC_KEY2 Address: 0xFFFFC6A8 Access: Write-once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2 23 22 21 20 KEY2 15 14 13 12 KEY2 7 6 5 4 KEY2 * KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2 When Off Chip Memory Scrambling is enabled by setting the HSMC_OMCS and HSMC_TIMINGS registers in accordance, the data scrambling depends on KEY2 and KEY1 values. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 506 30.20.40 HSMC Write Protection Mode Register Name: HSMC_WPMR Address: 0xFFFFC6E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 - 2 - 1 - 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 - 6 - 5 - 4 - * WPEN: Write Protection Enable 0: Disables Write Protection if WPKEY value corresponds to 0x534D43 ("SMC" in ASCII) 1: Enables Write Protection if WPKEY value corresponds to 0x534D43 ("SMC" in ASCII) See Section 30.16 "Register Write Protection" for list of write-protected registers. * WPKEY: Write Protect Key Value Name Description 0x534D43 PASSWD Writing any other value in this field aborts the write operation of bit WPEN. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 507 30.20.41 HSMC Write Protection Status Register Name: HSMC_WPSR Address: 0xFFFFC6E8 Access: Read-only 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 - 24 - 19 18 17 16 11 10 9 8 3 - 2 - 1 - 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 - 6 - 5 - 4 - * WPVS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of the HSMC_WPSR. 1: A Write Protect Violation has occurred since the last read of the HSMC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. * WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 508 31. DMA Controller (DMAC) 31.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also known as a dual-access transfer. The DMAC is programmed via the APB interface. 31.2 Embedded Characteristics 3 AHB-Lite Master Interfaces DMA Module Supports the Following Transfer Schemes: Peripheral-to-Memory, Memory-to-Peripheral, Peripheralto-Peripheral and Memory-to-Memory Source and Destination Operate independently on BYTE (8-bit), HALF-WORD (16-bit) and WORD (32-bit) Supports Hardware and Software Initiated Transfers Supports Multiple Buffer Chaining Operations Supports Incrementing/decrementing/fixed Addressing Mode Independently for Source and Destination Supports Programmable Address Increment/decrement on User-defined Boundary Condition to Enable Picture-inPicture Mode Programmable Arbitration Policy, Modified Round Robin and Fixed Priority are Available Supports Specified Length and Unspecified Length AMBA AHB Burst Access to Maximize Data Bandwidth AMBA APB Interface Used to Program the DMA Controller 8 DMA Channels on DMAC0 8 DMA Channels on DMAC1 16 External Request Lines on DMAC0 22 External Request Lines on DMAC1 Embedded FIFO Channel Locking and Bus Locking Capability SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 509 31.3 DMA Controller Peripheral Connections The DMA Controller handles the transfer between peripherals and memory and receives triggers from the peripherals listed in tables that follow. For each listed DMA Channel Number, the SIF and/or DIF bitfields in the DMAC_CTRLBx register must be programmed with a value compatible to the MATRIX "Master to Slave Access" definition provided in the "Bus Matrix (MATRIX)" section of the product datasheet. See Section 31.8.17 "DMAC Channel x [x = 0..7] Control B Register" (where x is the DMA Channel Number). Depending on transfer descriptor location, the DSCR_IF bitfield must be programmed with a value compatible to the MATRIX "Master to Slave Access" definition provided in the "Bus Matrix (MATRIX)" section of the product datasheet. See Section 31.8.15 "DMAC Channel x [x = 0..7] Descriptor Address Register" (where x is the DMA Channel Number). 31.3.1 DMA Controller 0 The DMA Controller 0 handles the transfer between peripherals and memory and receives triggers from the peripherals connected on APB0 (see Table 31-1). Table 31-1. DMA Channels Definition (DMAC0) Instance name Channel T/R Interface number HSMCI0 Receive/transmit 0 SPI0 Transmit 1 SPI0 Receive 2 USART0 Transmit 3 USART0 Receive 4 USART1 Transmit 5 USART1 Receive 6 TWI0 Transmit 7 TWI0 Receive 8 TWI1 Transmit 9 TWI1 Receive 10 UART0 Transmit 11 UART0 Receive 12 SSC0 Transmit 13 SSC0 Receive 14 SMD Transmit 15 SMD Receive 16 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 510 31.3.2 DMA Controller 1 The DMA Controller 1 handles the transfer between peripherals and memory and receives triggers from the peripherals connected on APB1 (see Table 31-2). Table 31-2. DMA Channels Definition (DMAC1) Instance name Channel T/R Interface Number HSMCI1 Receive/transmit 0 HSMCI2 Receive/transmit 1 ADC Receive 2 SSC1 Transmit 3 SSC1 Receive 4 UART1 Transmit 5 UART1 Receive 6 USART2 Transmit 7 USART2 Receive 8 USART3 Transmit 9 USART3 Receive 10 TWI2 Transmit 11 TWI2 Receive 12 DBGU Transmit 13 DBGU Receive 14 SPI1 Transmit 15 SPI1 Receive 16 SHA Transmit 17 AES Transmit 18 AES Receive 19 TDES Transmit 20 TDES Receive 21 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 511 31.4 Block Diagram Figure 31-1. DMA Controller (DMAC) Block Diagram DMA Channel n DMA Destination Atmel APB rev2 Interface DMA Channel 2 Status Registers DMA Channel 1 DMA Channel 0 DMA Channel 0 Write data path to destination DMA Atmel APB Interface Configuration Registers DMA Destination Control State Machine Destination Pointer Management DMA Interrupt Controller DMA Interrupt DMA FIFO Controller DMA FIFO Trigger Manager Up to 64 bytes External Triggers Soft Triggers DMA Channel 0 Read data path from source DMA REQ/ACK Interface DMA Hardware Handshaking Interface DMA Source Control State Machine Source Pointer Management DMA Source Requests Pool DMA Read Datapath Bundles DMA Global Control and Data Mux DMA Global Request Arbiter Requests & Data Interconnect DMAC Master Interface 0 AMBA AHB Layer 0 DMAC Master Interface 1 AMBA AHB Layer 1 DMAC Master Interface 2 AMBA AHB Layer 2 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 512 31.5 Functional Description 31.5.1 Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral). Memory: Source or destination that is always "ready" for a DMAC transfer and does not require a handshaking interface to interact with the DMAC. Programmable Arbitration Policy: Modified Round Robin and Fixed Priority are available by means of the ARB_CFG bit in the Global Configuration Register ("DMAC Global Configuration Register" ). The fixed priority is linked to the channel number. The highest DMAC channel number has the highest priority. Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination peripheral on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned dynamically by programming the channel registers. Master interface: DMAC is a master on the AHB bus reading data from the source and writing it to the destination over the AHB bus. Slave interface: The APB interface over which the DMAC is programmed. The slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMAC and source or destination peripheral to control the transfer of a single or chunk transfer between them. This interface is used to request, acknowledge, and control a DMAC transaction. A channel can receive a request through one of two types of handshaking interface: hardware or software. Hardware handshaking interface: Uses hardware signals to control the transfer of a single or chunk transfer between the DMAC and the source or destination peripheral. Software handshaking interface: Uses software registers to control the transfer of a single or chunk transfer between the DMAC and the source or destination peripheral. No special DMAC handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing an existing peripheral to the DMAC without modifying it. Transfer hierarchy: Figure 31-2 on page 514 illustrates the hierarchy between DMAC transfers, buffer transfers, chunk or single, and AMBA transfers (single or burst) for non-memory peripherals. Figure 31-3 on page 514 shows the transfer hierarchy for memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 513 Figure 31-2. DMAC Transfer Hierarchy for Non-Memory Peripheral DMAC Transfer Buffer Buffer Chunk Transfer AMBA Burst Transfer DMA Transfer Level Buffer Transfer Level Buffer Chunk Transfer Chunk Transfer AMBA Single Transfer AMBA Burst Transfer AMBA Burst Transfer Single Transfer DMA Transaction Level AMBA Single Transfer AMBA Transfer Level Figure 31-3. DMAC Transfer Hierarchy for Memory DMAC Transfer Buffer AMBA Burst Transfer Buffer AMBA Burst Transfer DMA Transfer Level Buffer AMBA Burst Transfer AMBA Single Transfer Buffer Transfer Level AMBA Transfer Level Buffer: A buffer of DMAC data. The amount of data (length) is determined by the flow controller. For transfers between the DMAC and memory, a buffer is broken directly into a sequence of AMBA bursts and AMBA single transfers. For transfers between the DMAC and a non-memory peripheral, a buffer is broken into a sequence of DMAC transactions (single and chunks). These are in turn broken into a sequence of AMBA transfers. Transaction: A basic unit of a DMAC transfer as determined by either the hardware or software handshaking interface. A transaction is only relevant for transfers between the DMAC and a source or destination peripheral if the source or destination peripheral is a non-memory device. There are two types of transactions: single transfer and chunk transfer. Single transfer: The length of a single transaction is always 1 and is converted to a single AMBA access. Chunk transfer: The length of a chunk is programmed into the DMAC. The chunk is then converted into a sequence of AHB access.DMAC executes each AMBA burst transfer by performing incremental bursts that are no longer than 16 beats. DMAC transfer: Software controls the number of buffers in a DMAC transfer. Once the DMAC transfer has completed, then hardware within the DMAC disables the channel and can generate an interrupt to signal the completion of the DMAC transfer. You can then re-program the channel for a new DMAC transfer. Single-buffer DMAC transfer: Consists of a single buffer. Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The source and destination can independently select which method to use. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 514 Linked lists (buffer chaining) - A descriptor pointer (DSCR) points to the location in system memory where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer (buffer descriptor) and a descriptor pointer register. The DMAC fetches the LLI at the beginning of every buffer when buffer chaining is enabled. Replay - The DMAC automatically reloads the channel registers at the end of each buffers to the value when the channel was first enabled. Contiguous buffers - Where the address of the next buffer is selected to be a continuation from the end of the previous buffer. Picture-in-Picture Mode: DMAC contains a Picture-in-Picture mode support. When this mode is enabled, addresses are automatically incremented by a programmable value when the DMAC channel transfer count reaches a user defined boundary. Figure 31-4 on page 515 illustrates a memory mapped image 4:2:2 encoded located at image_base_address in memory. A user defined start address is defined at Picture_start_address. The incremented value is set to memory_hole_size = image_width - picture_width, and the boundary is set to picture_width. Figure 31-4. Picture-In-Picture Mode Support DMAC PIP transfers Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for the master bus interface for the duration of a DMAC transfer, buffer, or chunk. Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hmastlock for the duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel locking is asserted for the duration of bus locking at a minimum. 31.5.2 Memory Peripherals Figure 31-3 on page 514 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 515 interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data, and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus. 31.5.3 Handshaking Interface Handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. The operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow controller. The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over the AMBA bus. A non-memory peripheral can request a DMAC transfer through the DMAC using one of two handshaking interfaces: Hardware handshaking Software handshaking Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface. 31.5.3.1 Software Handshaking When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller. The interrupt service routine then uses the software registers to initiate and control a DMAC transaction. These software registers are used to implement the software handshaking interface. The SRC_H2SEL/DST_H2SEL bit in the DMAC_CFGx channel configuration register must be set to zero to enable software handshaking. When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is not used, and the values in these registers are ignored. Chunk Transactions Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x is the channel number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk transfer request, where x is the channel number. Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[2x] or DMAC_CREQ[2x+1]. Single Transactions Writing a 1 to the DMAC_SREQ[2x] register starts a source single transaction request, where x is the channel number. Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single transfer request, where x is the channel number. Upon completion of the chunk transaction, the hardware clears the DMAC_SREQ[x] or DMAC_SREQ[2x+1]. The software can poll the relevant channel bit in the DMAC_CREQ[2x]/DMAC_CREQ[2x+1] and DMAC_SREQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested chunk or single transaction has completed. 31.5.4 DMAC Transfer Types A DMAC transfer may consist of single or multi-buffer transfers. On successive buffers of a multi-buffer transfer, the DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are reprogrammed using either of the following methods: Buffer chaining using linked lists Replay mode Contiguous address between buffers On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx registers in the DMAC are reprogrammed using either of the following methods: Buffer chaining using linked lists SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 516 Replay mode When buffer chaining using linked lists is the multi-buffer method of choice, and on successive buffers, the DMAC_DSCRx register in the DMAC is re-programmed using the following method: Buffer chaining using linked lists A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the DMAC_CFGx register, are used by the DMAC to set up and describe the buffer transfer. 31.5.4.1 Multi-buffer Transfers Buffer Chaining Using Linked Lists In this case, the DMAC re-programs the channel registers prior to the start of each buffer by fetching the buffer descriptor for that buffer from system memory. This is known as an LLI update. DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that stores the address in memory of the next buffer descriptor. Each buffer descriptor contains the corresponding buffer descriptor (DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx DMAC_CTRLBx). To set up buffer chaining, a sequence of linked lists must be programmed in memory. The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx registers are fetched from system memory on an LLI update. The updated content of the DMAC_CTRLAx register is written back to memory on buffer completion. Figure 31-5 on page 517 shows how to use chained linked lists in memory to define multi-buffer transfers using buffer chaining. The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0) (LLI(0) base address) different from zero. Other fields and registers are ignored and overwritten when the descriptor is retrieved from memory. The last transfer descriptor must be written to memory with its next descriptor address set to 0. Figure 31-5. Multi Buffer Transfer Using Linked List System Memory LLI(0) DSCRx(0) LLI(1) DSCRx(1)= DSCRx(0) + 0x10 DSCRx(2)= DSCRx(1) + 0x10 CTRLBx= DSCRx(0) + 0xC CTRLBx= DSCRx(1) + 0xC CTRLAx= DSCRx(0) + 0x8 CTRLBx= DSCRx(1) + 0x8 DADDRx= DSCRx(0) + 0x4 DADDRx= DSCRx(1) + 0x4 SADDRx= DSCRx(1) + 0x0 SADDRx= DSCRx(0) + 0x0 DSCRx(1) DSCRx(2) (points to 0 if LLI(1) is the last transfer descriptor Descriptor Integrity Check When the Descriptor Integrity Check is enabled, a cyclic redundancy check information is attached to the descriptor. When fetched from the memory, the descriptor is verified through the use of a CRC16-CCIT (0x1021 polynom) by the DMAC channel. If a CRC error is detected, then the DICERR flag is set in the DMAC_EBCISR register. The CRC16 is computed from MSB to LSB. The BTSIZE and DONE fields of the DMAC_CTRLAx register are ignored and set to zero. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 517 Figure 31-6. Linked List with CRC16 Attached LLI(1) LLI(0) System Memory DSCRx(0) CRCx(1)= DSCRx(0) + 0x14 CRCx(2)= DSCRx(1) + 0x14 DSCRx(1)= DSCRx(0) + 0x10 DSCRx(2)= DSCRx(1) + 0x10 CTRLBx= DSCRx(0) + 0xC CTRLBx= DSCRx(1) + 0xC CTRLAx= DSCRx(0) + 0x8 CTRLBx= DSCRx(1) + 0x8 DADDRx= DSCRx(0) + 0x4 DADDRx= DSCRx(1) + 0x4 SADDRx= DSCRx(1) + 0x0 SADDRx= DSCRx(0) + 0x0 DSCRx(1) DSCRx(2) (points to 0 if LLI(1) is the last transfer descriptor SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 518 31.5.4.2 Programming DMAC for Multiple Buffer Transfers Table 31-3. Multiple Buffers Transfer Management Table Transfer Type AUTO SRC_REP DST_REP SRC_DSCR DST_DSCR BTSIZE DSCR SADDR DADDR Other Fields 1) Single Buffer or Last buffer of a multiple buffer transfer 0 - - - - USR 0 USR USR USR 2) Multi Buffer transfer with contiguous DADDR 0 - 0 0 1 LLI USR LLI CONT LLI 3) Multi Buffer transfer with contiguous SADDR 0 0 - 1 0 LLI USR CONT LLI LLI 4) Multi Buffer transfer with LLI support 0 - - 0 0 LLI USR LLI LLI LLI 5) Multi Buffer transfer with DADDR reloaded 0 - 1 0 1 LLI USR LLI REP LLI 6) Multi Buffer transfer with SADDR reloaded 0 1 - 1 0 LLI USR REP LLI LLI 7) Multi Buffer transfer with BTSIZE reloaded and contiguous DADDR 1 - 0 0 1 REP USR LLI CONT LLI 8) Multi Buffer transfer with BTSIZE reloaded and contiguous SADDR 1 0 - 1 0 REP USR CONT LLI LLI 9) Automatic mode channel is stalling BTsize is reloaded 1 0 0 1 1 REP USR CONT CONT REP 10) Automatic mode BTSIZE, SADDR and DADDR reloaded 1 1 1 1 1 REP USR REP REP REP 11) Automatic mode BTSIZE, SADDR reloaded and DADDR contiguous 1 1 0 1 1 REP USR REP CONT REP Notes: 1. USR means that the register field is manually programmed by the user. 2. CONT means that address are contiguous. 3. REP means that the register field is updated with its previous value. If the transfer is the first one, then the user must manually program the value. 4. Channel stalled is true if the relevant BTC interrupt is not masked. 5. LLI means that the register field is updated with the content of the linked list item. Replay Mode of Channel Registers During automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer and the new values used for the new buffer. Depending on the row number in Table 31-3 on page 519, some or all of the DMAC_SADDRx, DMAC_DADDRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at the start of a buffer transfer. Contiguous Address Between Buffers In this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer. Enabling the source or destination address to be contiguous between buffers is a function of DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.DST_REP, DMAC_CFGx.SRC_REP and DMAC_CTRLAx.DST_DSCR registers. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 519 Suspension of Transfers Between Buffers At the end of every buffer transfer, an end of buffer interrupt is asserted if: Note: the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = `1', where x is the channel number. The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the destination. At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if: the channel end of the Chained Buffer Transfer Completed Interrupt is unmasked, DMAC_EBCIMR.CBTCx = `1', when n is the channel number. 31.5.4.3 Ending Multi-buffer Transfers All multi-buffer transfers must end as shown in Row 1 of Table 31-3 on page 519. At the end of every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last buffer and the DMAC transfer is terminated. For rows 9, 10 and 11 of Table 31-3 on page 519, (DMAC_DSCRx = 0 and DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is disabled by writing a `1' in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts the DMAC into Row 1 state. For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so that LLI.DMAC_DSCRx is set to 0. 31.5.5 Programming a Channel Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used. The different transfer types are shown in Table 31-3 on page 519. The "BTSIZE, SADDR and DADDR" columns indicate where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are enabled. 31.5.5.1 Programming Examples Single-buffer Transfer (Row 1) 1. Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register, DMAC_EBCISR. 3. Program the following channel registers: 1. Write the starting source address in the DMAC_SADDRx register for channel x. 2. Write the starting destination address in the DMAC_DADDRx register for channel x. 3. Write the next descriptor address in the DMA_DSCRx register for channel x with 0x0. 4. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1 as shown in Table 31-3 on page 519. Program the DMAC_CTRLBx register with both AUTO fields set to 0. 5. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers for channel x. For example, in the register, you can program the following: i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. ii. Set up the transfer characteristics, such as: Transfer width for the source in the SRC_WIDTH field. Transfer width for the destination in the DST_WIDTH field. Source AHB Master interface layer in the SIF field where source resides. Destination AHB Master Interface layer in the DIF field where destination resides. Incrementing/decrementing or fixed address for source in SRC_INC field. Incrementing/decrementing or fixed address for destination in DST_INC field. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 520 6. Write the channel configuration information into the DMAC_CFGx register for channel x. i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a `1' activates the hardware handshaking interface to handle source/destination requests. Writing a `0' activates the software handshaking interface to handle source/destination requests. ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 7. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x. 8. If destination Picture-in-Picture mode is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x. 4. After the DMAC selected channel has been programmed, enable the channel by writing a `1' to the DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE register is enabled. 5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 6. Once the transfer completes, the hardware sets the interrupts and disables the channel. At this time, you can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Handler Status Register (DMAC_CHSR.ENAx) bit until it is cleared by hardware, to detect when the transfer is complete. Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory (see Figure 31-7 on page 523) for channel x. For example, in the register, you can program the following: 3. 4. 1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. 2. Set up the transfer characteristics, such as: i. Transfer width for the source in the SRC_WIDTH field. ii. Transfer width for the destination in the DST_WIDTH field. iii. Source AHB master interface layer in the SIF field where source resides. iv. Destination AHB master interface layer in the DIF field where destination resides. v. Incrementing/decrementing or fixed address for source in SRC_INCR field. vi. Incrementing/decrementing or fixed address for destination DST_INCR field. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a `1' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `0' activates the software handshaking interface to handle source/destination requests. 2. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are set as shown in Row 4 of Table 31-3 on page 519. The LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in Row 1 of Table 31-3. Figure 31-5 on page 517 shows a Linked List example with two list items. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 521 5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory (except the last) are non-zero and point to the base address of the next Linked List Item. 6. Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all LLI entries in memory point to the start source/destination buffer address preceding that LLI fetch. 7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLI entries in memory are cleared. 8. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x. 9. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x. 10. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the status register: DMAC_EBCISR. 11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in Table 31-3 on page 519. 12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 13. Finally, enable the channel by writing a `1' to the DMAC_CHER.ENAx bit, where x is the channel number. The transfer is performed. 14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the DMAC_DSCRx(0). 15. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripheral). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 16. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE bits have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 17. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching the next LLI from the memory location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer continues until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match described in Row 1 of Table 31-3 on page 519. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 31-7 on page 523. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 522 Figure 31-7. Multi-buffer with Linked List Address for Source and Destination Address of Destination Layer Address of Source Layer Buffer 2 SADDR(2) Buffer 2 DADDR(2) Buffer 1 SADDR(1) Buffer 1 DADDR(1) Buffer 0 Buffer 0 DADDR(0) SADDR(0) Source Buffers Destination Buffers If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.BTSIZE, then this can be achieved using the type of multi-buffer transfer as shown in Figure 31-8 on page 524. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 523 Figure 31-8. Multi-buffer with Linked Address for Source and Destination Buffers are Contiguous Address of Source Layer Address of Destination Layer Buffer 2 DADDR(3) Buffer 2 Buffer 2 SADDR(3) DADDR(2) Buffer 2 Buffer 1 SADDR(2) DADDR(1) Buffer 1 SADDR(1) Buffer 0 DADDR(0) Buffer 0 SADDR(0) Source Buffers Destination Buffers The DMAC transfer flow is shown in Figure 31-9 on page 525. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 524 Figure 31-9. DMAC Transfer Flow for Source and Destination Linked List Address Channel enabled by software LLI Fetch Hardware reprograms SADDRx, DADDRx, CTRLA/Bx, DSCRx DMAC buffer transfer Writeback of DMAC_CTRLAx register in system memory Chained Buffer Transfer Completed Interrupt generated here Is DMAC in Row 1 of DMAC State Machine Table? DMAC Chained Buffer Transfer Completed Interrupt generated here no yes Channel disabled by hardware Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10) 1. Read the Channel Handler Status register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. Program the following channel registers: SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 525 1. Write the starting source address in the DMAC_SADDRx register for channel x. 2. Write the starting destination address in the DMAC_DADDRx register for channel x. 3. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 10 as shown in Table 31-3 on page 519. Program the DMAC_DSCRx register with 0. 4. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx register for channel x. For example, in the register, you can program the following: i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. ii. Set up the transfer characteristics, such as: Transfer width for the source in the SRC_WIDTH field. Transfer width for the destination in the DST_WIDTH field. Source AHB master interface layer in the SIF field where source resides. Destination AHB master interface layer in the DIF field where destination resides. Incrementing/decrementing or fixed address for source in SRC_INCR field. Incrementing/decrementing or fixed address for destination in DST_INCR field. 5. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 6. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. 7. Write the channel configuration information into the DMAC_CFGx register for channel x. Ensure that the reload bits, DMAC_CFGx.SRC_REP, DMAC_CFGx.DST_REP and DMAC_CTRLBx.AUTO are enabled. i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_h2SEL bits, respectively. Writing a `1' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `0' activates the software handshaking interface to handle source/destination requests. ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 3. After the DMAC selected channel has been programmed, enable the channel by writing a `1' to the DMAC_CHER.ENAx bit where the channel number is. Make sure that bit 0 of the DMAC_EN register is enabled. 4. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripherals). The DMAC acknowledges on completion of each chunk/single transaction and carries out the buffer transfer. 5. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx, DMAC_DADDRx and DMAC_CTRLAx registers. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC then samples the row number as shown in Table 31-3 on page 519. If the DMAC is in Row 1, then the DMAC transfer has completed. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. So you can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Enable in the Channel Status Register (DMAC_CHSR.ENAx) until it is disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed. 6. The DMAC transfer proceeds as follows: 1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = `1', where x is the channel number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed. It then stalls until the STALx bit of DMAC_CHSR register is cleared by software, writing `1' to DMAC_CHER.KEEPx bit, where x is the channel number. If the next buffer is to be the last buffer in the DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit in the DMAC_CTRLBx.AUTO bit. This puts the DMAC into Row 1 as shown in Table 31-3 on page 519. If SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 526 the next buffer is not the last buffer in the DMAC transfer, then the reload bits should remain enabled to keep the DMAC in Row 4. 2. If the Buffer Transfer Completed Interrupt is masked (DMAC_EBCIMR.BTCx = `0', where x is the channel number), the hardware does not stall until it detects a write to the Buffer Transfer Completed Interrupt Enable register DMAC_EBCIER register, but starts the next buffer transfer immediately. In this case, the software must clear the automatic mode bit in the DMAC_CTRLB to put the DMAC into ROW 1 of Table 313 on page 519 before the last buffer of the DMAC transfer has completed. The transfer is similar to that shown in Figure 31-10 on page 527. The DMAC transfer flow is shown in Figure 31-11 on page 528. Figure 31-10.Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded Address of Source Layer Address of Destination Layer Block0 Block1 Block2 SADDR DADDR BlockN Source Buffers Destination Buffers SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 527 Figure 31-11.DMAC Transfer Flow for Source and Destination Address Auto-reloaded Channel enabled by software Buffer Transfer Replay mode for SADDRx, DADDRx, CTRLAx, CTRLBx Buffer Transfer Completed Interrupt generated here DMAC Chained Buffer Transfer Completed Interrupt generated here yes Is DMAC in Row 1 of DMAC State Machine table? Channel disabled by hardware no EBCIMR[x]=1? no yes Stall until STALLx is cleared by writing to KEEPx field Multi-buffer Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 6) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Set up the chain of linked list items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: 3. Note: 4. 1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control peripheral by programming the FC of the DMAC_CTRLBx register. 2. Set up the transfer characteristics, such as: i. Transfer width for the source in the SRC_WIDTH field. ii. Transfer width for the destination in the DST_WIDTH field. iii. Source AHB master interface layer in the SIF field where source resides. iv. Destination AHB master interface layer in the DIF field where destination resides. v. Incrementing/decrementing or fixed address for source in SRC_INCR field. vi. Incrementing/decrementing or fixed address for destination DST_INCR field. Write the starting source address in the DMAC_SADDRx register for channel x. The values in the LLI.DMAC_SADDRx register locations of each of the Linked List Items (LLIs) set up in memory, although fetched during an LLI fetch, are not used. Write the channel configuration information into the DMAC_CFGx register for channel x. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 528 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a `1' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `0' activates the software handshaking interface source/destination requests. 2. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 5. Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except the last one) are set as shown in Row 6 of Table 31-3 on page 519 while the LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in Row 1 of Table 31-3. Figure 31-5 on page 517 shows a Linked List example with two list items. 6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last one) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_DADDRx register locations of all LLIs in memory point to the start destination buffer address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register locations of all LLIs in memory is cleared. 9. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 10. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register for channel x. 11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the DMAC_EBCISR register. 12. Program the DMAC_CTLx and DMAC_CFGx registers according to Row 6 as shown in Table 31-3 on page 519. 13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 14. Finally, enable the channel by writing a `1' to the DMAC_CHER.ENAx bit, where x is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled. 15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register, although fetched, is not used. 16. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripherals). DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 17. The DMAC_CTRLAx register is written out to the system memory. The DMAC_CTRLAx register is written out to the same location on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out, because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAx.DONE fields have been updated by hardware within the DMAC. The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate buffer completion. Therefore, the software can poll the LLI.DMAC_CTRLAx.DONE field of the DMAC_CTRLAx register in the LLi to ascertain when a buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was cleared at the start of the transfer. 18. The DMAC reloads the DMAC_SADDRx register from the initial value. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC samples the row number as shown in Table 31-3 on page 519. If the DMAC is in Row 1, then the DMAC transfer has completed. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. You can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Enable. (DMAC_CHSR.ENAx) bit until it is cleared by SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 529 hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 31-3 on page 519, the following step is performed. 19. The DMAC fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. Note that the DMAC_SADDRx is not re-programmed as the reloaded value is used for the next DMAC buffer transfer. If the next buffer is the last buffer of the DMAC transfer, then the DMAC_CTRLBx and DMAC_DSCRx registers just fetched from the LLI should match Row 1 of Table 31-3 on page 519. The DMAC transfer might look like that shown in Figure 31-12 on page 530. Figure 31-12.Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address Address of Destination Layer Address of Source Layer Buffer0 DADDR(0) Buffer1 DADDR(1) SADDR Buffer2 DADDR(2) BufferN DADDR(N) Source Buffers Destination Buffers The DMAC Transfer flow is shown in Figure 31-13 on page 531. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 530 Figure 31-13.DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address Channel enabled by software LLI Fetch Hardware reprograms DADDRx, CTRLAx, CTRLBx, DSCRx DMAC buffer transfer Writeback of control status information in LLI Reload SADDRx Buffer Transfer Completed Interrupt generated here yes DMAC Chained Buffer Transfer Completed Interrupt generated here Is DMAC in Row 1 of DMAC State Machine Table? Channel disabled by hardware no Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the Interrupt Status Register. 3. Program the following channel registers: 1. Write the starting source address in the DMAC_SADDRx register for channel x. 2. Write the starting destination address in the DMAC_DADDRx register for channel x. 3. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 11 as shown in Table 31-3 on page 519. Program the DMAC_DSCRx register with `0'. DMAC_CTRLBx.AUTO field is set to `1' to enable automatic mode support. 4. Write the control information for the DMAC transfer in the DMAC_CTRLBx and DMAC_CTRLAx register for channel x. For example, in this register, you can program the following: i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. ii. Set up the transfer characteristics, such as: Transfer width for the source in the SRC_WIDTH field. Transfer width for the destination in the DST_WIDTH field. Source AHB master interface layer in the SIF field where source resides. Destination AHB master interface master layer in the DIF field where destination resides. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 531 Incrementing/decrementing or fixed address for source in SRC_INCR field. Incrementing/decrementing or fixed address for destination in DST_INCR field. 5. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 6. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. 7. Write the channel configuration information into the DMAC_CFGx register for channel x. i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a `1' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `0' activates the software handshaking interface to handle source/destination requests. ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 4. After the DMAC channel has been programmed, enable the channel by writing a `1' to the DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of the DMAC_EN.ENABLE register is enabled. 5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 6. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx register. The DMAC_DADDRx register remains unchanged. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC then samples the row number as shown in Table 31-3 on page 519. If the DMAC is in Row 1, then the DMAC transfer has completed. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. So you can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the enable (ENAx) field in the Channel Status Register (DMAC_CHSR.ENAx bit) until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed. 7. The DMAC transfer proceeds as follows: 1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = `1', where x is the channel number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed. It then stalls until STALx bit of DMAC_CHSR is cleared by writing in the KEEPx field of DMAC_CHER register, where x is the channel number. If the next buffer is to be the last buffer in the DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit, DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in Table 31-3 on page 519. If the next buffer is not the last buffer in the DMAC transfer, then the automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as shown in Table 31-3 on page 519. 2. If the Buffer Transfer Completed Interrupt is masked (DMAC_EBCIMR.BTCx = `0', where x is the channel number), the hardware does not stall until it detects a write to the Buffer Transfer Completed Interrupt Enable register, but starts the next buffer transfer immediately. In this case, the software must clear the automatic mode bit, DMAC_CTRLBx.AUTO, to put the device into ROW 1 of Table 31-3 on page 519 before the last buffer of the DMAC transfer has completed. The transfer is similar to that shown in Figure 31-14 on page 533. The DMAC Transfer flow is shown in Figure 31-15 on page 534. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 532 Figure 31-14.Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address Address of Destination Layer Address of Source Layer Buffer2 DADDR(2) Buffer1 DADDR(1) Buffer0 SADDR DADDR(0) Source Buffers Destination Buffers SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 533 Figure 31-15.DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address Channel enabled by software Buffer Transfer Replay mode for SADDRx, Contiguous mode for DADDRx CTRLAx, CTRLBx Buffer Transfer Completed Interrupt generated here Buffer Transfer Completed Interrupt generated here yes Is DMAC in Row 1 of DMAC State Machine Table? Channel disabled by hardware no no DMA_EBCIMR[x]=1? yes Stall until STALLx field is cleared by software writing KEEPx field Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Set up the linked list in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: 3. 1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. 2. Set up the transfer characteristics, such as: i. Transfer width for the source in the SRC_WIDTH field. ii. Transfer width for the destination in the DST_WIDTH field. iii. Source AHB master interface layer in the SIF field where source resides. iv. Destination AHB master interface layer in the DIF field where destination resides. v. Incrementing/decrementing or fixed address for source in SRC_INCR field. vi. Incrementing/decrementing or fixed address for destination DST_INCR field. Write the starting destination address in the DMAC_DADDRx register for channel x. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 534 Note: 4. The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a `1' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `0' activates the software handshaking interface to handle source/destination requests. 2. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripherals. This requires programming the SRC_PER and DST_PER bits, respectively. 5. Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are set as shown in Row 2 of Table 31-3 on page 519, while the LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in Row 1 of Table 31-3. Figure 31-5 on page 517 shows a Linked List example with two list items. 6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_SADDRx register locations of all LLIs in memory point to the start source buffer address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLIs in memory is cleared. 9. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 10. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register for channel x. 11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. 12. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according to Row 2 as shown in Table 31-3 on page 519 13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 14. Finally, enable the channel by writing a `1' to the DMAC_CHER.ENAx bit. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled. 15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx registers are fetched. The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The DMAC_DADDRx register in the DMAC remains unchanged. 16. Source and destination requests single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 17. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to the system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, then automatically reprograms the SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 535 DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of Table 31-3 on page 519. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 31-16 on page 536. Note that the destination address is decrementing. Figure 31-16.DMAC Transfer with Linked List Source Address and Contiguous Destination Address Address of Source Layer Address of Destination Layer Buffer 2 SADDR(2) Buffer 2 DADDR(2) Buffer 1 Buffer 1 SADDR(1) DADDR(1) Buffer 0 DADDR(0) Buffer 0 SADDR(0) Source Buffers Destination Buffers The DMAC transfer flow is shown in Figure 31-17 on page 537. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 536 Figure 31-17.DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address Channel enabled by software LLI Fetch Hardware reprograms SADDRx, CTRLAx,CTRLBx, DSCRx DMAC buffer transfer Writeback of control information of LLI Buffer Transfer Completed Interrupt generated here Is DMAC in Row 1 ? DMAC Chained Buffer Transfer Completed Interrupt generated here no yes Channel disabled by hardware 31.5.6 Disabling a Channel Prior to Transfer Completion Under normal operation, the software enables a channel by writing a `1' to the Channel Handler Enable Register, DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 537 1. If the software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data. 2. The software can now poll the DMAC_CHSR.EMPTx bit until it indicates that the channel n FIFO is empty, where n is the channel number. 3. The DMAC_CHER.ENAx bit can then be cleared by software once the channel n FIFO is empty, where n is the channel number. When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the DMAC_CHSRx.SUSPx bit is high, the DMAC_CHSRx.EMPTx is asserted once the contents of the FIFO does not permit a single word of DMAC_CTRLAx.DST_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form a single transfer of DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the suspension state by writing a `1' to the DMAC_CHER.RESx field register. The DMAC transfer completes in the normal manner. n defines the channel number. Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement. 31.5.6.1 Abnormal Transfer Termination A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit, DMAC_CHDR.ENAx, where x is the channel number. This does not mean that the channel is disabled immediately after the DMAC_CHSR.ENAx bit is cleared over the APB interface. Consider this as a request to disable the channel. The DMAC_CHSR.ENAx must be polled and then it must be confirmed that the channel is disabled by reading back 0. The software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register (DMAC_EN.ENABLE bit). Again, this does not mean that all channels are disabled immediately after the DMAC_EN.ENABLE is cleared over the APB slave interface. Consider this as a request to disable all channels. The DMAC_CHSR.ENABLE must be polled and then it must be confirmed that all channels are disabled by reading back `0'. 31.6 Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals, such as a source FIFO, this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement. DMAC Software Requirements There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel. You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte, half-word and word aligned address depending on the source width and destination width. After the software disables a channel by writing into the channel disable register, it must re-enable the channel only after it has polled a 0 in the corresponding channel enable status register. This is because the current AHB Burst must terminate properly. If you program the BTSIZE field in the DMAC_CTRLA as zero, and the DMAC has been defined as the flow controller, then the channel is automatically disabled. When hardware handshaking interface protocol is fully implemented, a peripheral is expected to deassert any sreq or breq signals on receiving the ack signal irrespective of the request the ack was asserted in response to. Multiple Transfers involving the same peripheral must not be programmed and enabled on different channels, unless this peripheral integrates several hardware handshaking interfaces. When a Peripheral has been defined as the flow controller, the targeted DMAC Channel must be enabled before the Peripheral. If you do not ensure this and the First DMAC request is also the last transfer, the DMAC Channel might miss a Last Transfer Flag. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 538 31.7 When the AUTO Field is set to TRUE, then the BTSIZE Field is automatically reloaded from its previous value. BTSIZE must be initialized to a non zero value if the first transfer is initiated with the AUTO field set to TRUE, even if LLI mode is enabled, because the LLI fetch operation will not update this field. Write Protection Registers To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be writeprotected by setting the WPEN bit in the "DMAC Write Protect Mode Register" (DMAC_WPMR). If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect Status Register (MCI_WPSR) is set, and the WPVSRC field indicates in which register the write access has been attempted. The WPVS flag is reset by writing the DMAC Write Protect Mode Register (DMAC_WPMR) with the appropriate access key, WPKEY. The protected registers are: "DMAC Global Configuration Register" on page 541 "DMAC Enable Register" on page 542 "DMAC Channel x [x = 0..7] Source Address Register" on page 553 "DMAC Channel x [x = 0..7] Destination Address Register" on page 554 "DMAC Channel x [x = 0..7] Descriptor Address Register" on page 555 "DMAC Channel x [x = 0..7] Control A Register" on page 556 "DMAC Channel x [x = 0..7] Control B Register" on page 558 "DMAC Channel x [x = 0..7] Configuration Register" on page 560 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 539 31.8 DMA Controller (DMAC) User Interface Table 31-5. Register Mapping Offset Register Name Access Reset 0x000 DMAC Global Configuration Register DMAC_GCFG Read-write 0x10 0x004 DMAC Enable Register DMAC_EN Read-write 0x0 0x008 DMAC Software Single Request Register DMAC_SREQ Read-write 0x0 0x00C DMAC Software Chunk Transfer Request Register DMAC_CREQ Read-write 0x0 0x010 DMAC Software Last Transfer Flag Register DMAC_LAST Read-write 0x0 0x014 Reserved 0x018 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. DMAC_EBCIER Write-only - 0x01C DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. DMAC_EBCIDR Write-only - 0x020 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. DMAC_EBCIMR Read-only 0x0 0x024 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. DMAC_EBCISR Read-only 0x0 0x028 DMAC Channel Handler Enable Register DMAC_CHER Write-only - 0x02C DMAC Channel Handler Disable Register DMAC_CHDR Write-only - 0x030 DMAC Channel Handler Status Register DMAC_CHSR Read-only 0x00FF0000 0x034 Reserved - - - 0x038 Reserved - - - 0x03C+ch_num*(0x28)+(0x0) DMAC Channel Source Address Register DMAC_SADDR Read-write 0x0 0x03C+ch_num*(0x28)+(0x4) DMAC Channel Destination Address Register DMAC_DADDR Read-write 0x0 0x03C+ch_num*(0x28)+(0x8) DMAC Channel Descriptor Address Register DMAC_DSCR Read-write 0x0 0x03C+ch_num*(0x28)+(0xC) DMAC Channel Control A Register DMAC_CTRLA Read-write 0x0 0x03C+ch_num*(0x28)+(0x10) DMAC Channel Control B Register DMAC_CTRLB Read-write 0x0 0x03C+ch_num*(0x28)+(0x14) DMAC Channel Configuration Register DMAC_CFG Read-write 0x01000000 0x03C+ch_num*(0x28)+(0x18) DMAC Channel Source Picture-in-Picture Configuration Register DMAC_SPIP Read-write 0x0 0x03C+ch_num*(0x28)+(0x1C) DMAC Channel Destination Picture-in-Picture Configuration Register DMAC_DPIP Read-write 0x0 0x03C+ch_num*(0x28)+(0x20) Reserved - - - 0x03C+ch_num*(0x28)+(0x24) Reserved - - - 0x1E4 DMAC Write Protect Mode Register DMAC_WPMR Read-write 0x0 0x1E8 DMAC Write Protect Status Register DMAC_WPSR Read-only 0x0 0x01EC- 0x1FC Reserved - - - SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 540 31.8.1 DMAC Global Configuration Register Name: DMAC_GCFG Address: 0xFFFFE600 (0), 0xFFFFE800 (1) Access: Read-write Reset: 0x00000010 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 DICEN 7 - 6 - 5 - 4 ARB_CFG 3 - 2 - 1 - 0 - Note: Bit fields 0, 1, 2, and 3 have a default value of 0. This should not be changed. This register can only be written if the WPEN bit is cleared in "DMAC Write Protect Mode Register" . * ARB_CFG: Arbiter Configuration Value Name Description 0 FIXED Fixed priority arbiter (see "Basic Definitions" ) 1 ROUND_ROBIN Modified round robin arbiter. * DICEN: Descriptor Integrity Check 0: Descriptor Integrity Check Interface is Disabled. 1: Descriptor Integrity Check Interface is Enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 541 31.8.2 DMAC Enable Register Name: DMAC_EN Address: 0xFFFFE604 (0), 0xFFFFE804 (1) Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ENABLE This register can only be written if the WPEN bit is cleared in "DMAC Write Protect Mode Register" . * ENABLE: General Enable of DMA 0: DMA Controller is disabled. 1: DMA Controller is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 542 31.8.3 DMAC Software Single Request Register Name: DMAC_SREQ Address: 0xFFFFE608 (0), 0xFFFFE808 (1) Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 DSREQ7 14 SSREQ7 13 DSREQ6 12 SSREQ6 11 DSREQ5 10 SSREQ5 9 DSREQ4 8 SSREQ4 7 DSREQ3 6 SSREQ3 5 DSREQ2 4 SSREQ2 3 DSREQ1 2 SSREQ1 1 DSREQ0 0 SSREQ0 * DSREQx: Destination Request Request a destination single transfer on channel i. * SSREQx: Source Request Request a source single transfer on channel i. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 543 31.8.4 DMAC Software Chunk Transfer Request Register Name: DMAC_CREQ Address: 0xFFFFE60C (0), 0xFFFFE80C (1) Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 DCREQ7 14 SCREQ7 13 DCREQ6 12 SCREQ6 11 DCREQ5 10 SCREQ5 9 DCREQ4 8 SCREQ4 7 DCREQ3 6 SCREQ3 5 DCREQ2 4 SCREQ2 3 DCREQ1 2 SCREQ1 1 DCREQ0 0 SCREQ0 * DCREQx: Destination Chunk Request Request a destination chunk transfer on channel i. * SCREQx: Source Chunk Request Request a source chunk transfer on channel i. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 544 31.8.5 DMAC Software Last Transfer Flag Register Name: DMAC_LAST Address: 0xFFFFE610 (0), 0xFFFFE810 (1) Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 DLAST7 14 SLAST7 13 DLAST6 12 SLAST6 11 DLAST5 10 SLAST5 9 DLAST4 8 SLAST4 7 DLAST3 6 SLAST3 5 DLAST2 4 SLAST2 3 DLAST1 2 SLAST1 1 DLAST0 0 SLAST0 * DLASTx: Destination Last Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer. * SLASTx: Source Last Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 545 31.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register Name: DMAC_EBCIER Address: 0xFFFFE618 (0), 0xFFFFE818 (1) Access: Write-only Reset: 0x00000000 31 DICERR7 30 DICERR6 29 DICERR5 28 DICERR4 27 DICERR3 26 DICERR2 25 DICERR1 24 DICERR0 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 * BTCx: Buffer Transfer Completed [7:0] Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the BTC field to enable the interrupt for channel i. * CBTCx: Chained Buffer Transfer Completed [7:0] Chained Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the CBTC field to enable the interrupt for channel i. * ERRx: Access Error [7:0] Access Error Interrupt Enable Register. Set the relevant bit in the ERR field to enable the interrupt for channel i. * DICERRx: Descriptor Integrity Check Error [7:0] Descriptor Integrity Check Error Interrupt Enable Register. Set the relevant bit in the DICERR field to enable the interrupt for channel i. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 546 31.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register Name: DMAC_EBCIDR Address: 0xFFFFE61C (0), 0xFFFFE81C (1) Access: Write-only Reset: 0x00000000 31 DICERR7 30 DICERR6 29 DICERR5 28 DICERR4 27 DICERR3 26 DICERR2 25 DICERR1 24 DICERR0 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 * BTCx: Buffer Transfer Completed [7:0] Buffer transfer completed Disable Interrupt Register. When set, a bit of the BTC field disables the interrupt from the relevant DMAC channel. * CBTCx: Chained Buffer Transfer Completed [7:0] Chained Buffer transfer completed Disable Register. When set, a bit of the CBTC field disables the interrupt from the relevant DMAC channel. * ERRx: Access Error [7:0] Access Error Interrupt Disable Register. When set, a bit of the ERR field disables the interrupt from the relevant DMAC channel. * DICERRx: Descriptor Integrity Check Error [7:0] Descriptor Integrity Check Error Interrupt Disable Register, When set, a bit of the DICERR field disables the interrupt from the relevant DMAC channel. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 547 31.8.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register Name: DMAC_EBCIMR Address: 0xFFFFE620 (0), 0xFFFFE820 (1) Access: Read-only Reset: 0x00000000 31 DICERR7 30 DICERR6 29 DICERR5 28 DICERR4 27 DICERR3 26 DICERR2 25 DICERR1 24 DICERR0 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 * BTCx: Buffer Transfer Completed [7:0] 0: Buffer Transfer Completed Interrupt is disabled for channel i. 1: Buffer Transfer Completed Interrupt is enabled for channel i. * CBTCx: Chained Buffer Transfer Completed [7:0] 0: Chained Buffer Transfer interrupt is disabled for channel i. 1: Chained Buffer Transfer interrupt is enabled for channel i. * ERRx: Access Error [7:0] 0: Transfer Error Interrupt is disabled for channel i. 1: Transfer Error Interrupt is enabled for channel i. * DICERRx: Descriptor Integrity Check Error [7:0] 0: Descriptor Integrity Check Error Interrupt is disabled for channel i. 1: Descriptor Integrity Check Error Interrupt is enabled for channel i. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 548 31.8.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register Name: DMAC_EBCISR Address: 0xFFFFE624 (0), 0xFFFFE824 (1) Access: Read-only Reset: 0x00000000 31 DICERR7 30 DICERR6 29 DICERR5 28 DICERR4 27 DICERR3 26 DICERR2 25 DICERR1 24 DICERR0 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 * BTCx: Buffer Transfer Completed [7:0] When BTC[i] is set, Channel i buffer transfer has terminated. * CBTCx: Chained Buffer Transfer Completed [7:0] When CBTC[i] is set, Channel i Chained buffer has terminated. LLI Fetch operation is disabled. * ERRx: Access Error [7:0] When ERR[i] is set, Channel i has detected an AHB Read or Write Error Access. * DICERRx: Descriptor Integrity Check Error [7:0] When DICERR[i] is set, Channel i has detected a Descriptor Integrity Check Error. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 549 31.8.10 DMAC Channel Handler Enable Register Name: DMAC_CHER Address: 0xFFFFE628 (0), 0xFFFFE828 (1) Access: Write-only Reset: 0x00000000 31 KEEP7 30 KEEP6 29 KEEP5 28 KEEP4 27 KEEP3 26 KEEP2 25 KEEP1 24 KEEP0 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 SUSP7 14 SUSP6 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 ENA7 6 ENA6 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 * ENAx: Enable [7:0] When set, a bit of the ENA field enables the relevant channel. * SUSPx: Suspend [7:0] When set, a bit of the SUSP field freezes the relevant channel and its current context. * KEEPx: Keep on [7:0] When set, a bit of the KEEP field resumes the current channel from an automatic stall state. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 550 31.8.11 DMAC Channel Handler Disable Register Name: DMAC_CHDR Address: 0xFFFFE62C (0), 0xFFFFE82C (1) Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 RES7 14 RES6 13 RES5 12 RES4 11 RES3 10 RES2 9 RES1 8 RES0 7 DIS7 6 DIS6 5 DIS5 4 DIS4 3 DIS3 2 DIS2 1 DIS1 0 DIS0 * DISx: Disable [7:0] Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated. Software must poll DIS[7:0] field in the DMAC_CHSR register to be sure that the channel is disabled. * RESx: Resume [7:0] Write one to this field to resume the channel transfer restoring its context. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 551 31.8.12 DMAC Channel Handler Status Register Name: DMAC_CHSR Address: 0xFFFFE630 (0), 0xFFFFE830 (1) Access: Read-only Reset: 0x00FF0000 31 STAL7 30 STAL6 29 STAL5 28 STAL4 27 STAL3 26 STAL2 25 STAL1 24 STAL0 23 EMPT7 22 EMPT6 21 EMPT5 20 EMPT4 19 EMPT3 18 EMPT2 17 EMPT1 16 EMPT0 15 SUSP7 14 SUSP6 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 ENA7 6 ENA6 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 * ENAx: Enable [7:0] A one in any position of this field indicates that the relevant channel is enabled. * SUSPx: Suspend [7:0] A one in any position of this field indicates that the channel transfer is suspended. * EMPTx: Empty [7:0] A one in any position of this field indicates that the relevant channel is empty. * STALx: Stalled [7:0] A one in any position of this field indicates that the relevant channel is stalling. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 552 31.8.13 DMAC Channel x [x = 0..7] Source Address Register Name: DMAC_SADDRx [x = 0..7] Address: 0xFFFFE63C (0)[0], 0xFFFFE664 (0)[1], 0xFFFFE68C (0)[2], 0xFFFFE6B4 (0)[3], 0xFFFFE6DC (0)[4], 0xFFFFE704 (0)[5], 0xFFFFE72C (0)[6], 0xFFFFE754 (0)[7], 0xFFFFE83C (1)[0], 0xFFFFE864 (1)[1], 0xFFFFE88C (1)[2], 0xFFFFE8B4 (1)[3], 0xFFFFE8DC (1)[4], 0xFFFFE904 (1)[5], 0xFFFFE92C (1)[6], 0xFFFFE954 (1)[7] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SADDR 23 22 21 20 SADDR 15 14 13 12 SADDR 7 6 5 4 SADDR This register can only be written if the WPEN bit is cleared in "DMAC Write Protect Mode Register" . * SADDR: Channel x Source Address This register must be aligned with the source transfer width. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 553 31.8.14 DMAC Channel x [x = 0..7] Destination Address Register Name: DMAC_DADDRx [x = 0..7] Address: 0xFFFFE640 (0)[0], 0xFFFFE668 (0)[1], 0xFFFFE690 (0)[2], 0xFFFFE6B8 (0)[3], 0xFFFFE6E0 (0)[4], 0xFFFFE708 (0)[5], 0xFFFFE730 (0)[6], 0xFFFFE758 (0)[7], 0xFFFFE840 (1)[0], 0xFFFFE868 (1)[1], 0xFFFFE890 (1)[2], 0xFFFFE8B8 (1)[3], 0xFFFFE8E0 (1)[4], 0xFFFFE908 (1)[5], 0xFFFFE930 (1)[6], 0xFFFFE958 (1)[7] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DADDR 23 22 21 20 DADDR 15 14 13 12 DADDR 7 6 5 4 DADDR This register can only be written if the WPEN bit is cleared in "DMAC Write Protect Mode Register" . * DADDR: Channel x Destination Address This register must be aligned with the destination transfer width. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 554 31.8.15 DMAC Channel x [x = 0..7] Descriptor Address Register Name: DMAC_DSCRx [x = 0..7] Address: 0xFFFFE644 (0)[0], 0xFFFFE66C (0)[1], 0xFFFFE694 (0)[2], 0xFFFFE6BC (0)[3], 0xFFFFE6E4 (0)[4], 0xFFFFE70C (0)[5], 0xFFFFE734 (0)[6], 0xFFFFE75C (0)[7], 0xFFFFE844 (1)[0], 0xFFFFE86C (1)[1], 0xFFFFE894 (1)[2], 0xFFFFE8BC (1)[3], 0xFFFFE8E4 (1)[4], 0xFFFFE90C (1)[5], 0xFFFFE934 (1)[6], 0xFFFFE95C (1)[7] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 DSCR 23 22 21 20 DSCR 15 14 13 12 DSCR 7 6 5 4 DSCR 0 DSCR_IF This register can only be written if the WPEN bit is cleared in "DMAC Write Protect Mode Register" . * DSCR_IF: Descriptor Interface Selection Value Name Description 00 AHB_IF0 The buffer transfer descriptor is fetched via AHB-Lite Interface 0 (first DMA Master Interface) 01 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1 (second DMA Master Interface) 10 AHB_IF2 The buffer transfer descriptor is fetched via AHB-Lite Interface 2 (third DMA Master Interface) * DSCR: Buffer Transfer Descriptor Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 555 31.8.16 DMAC Channel x [x = 0..7] Control A Register Name: DMAC_CTRLAx [x = 0..7] Address: 0xFFFFE648 (0)[0], 0xFFFFE670 (0)[1], 0xFFFFE698 (0)[2], 0xFFFFE6C0 (0)[3], 0xFFFFE6E8 (0)[4], 0xFFFFE710 (0)[5], 0xFFFFE738 (0)[6], 0xFFFFE760 (0)[7], 0xFFFFE848 (1)[0], 0xFFFFE870 (1)[1], 0xFFFFE898 (1)[2], 0xFFFFE8C0 (1)[3], 0xFFFFE8E8 (1)[4], 0xFFFFE910 (1)[5], 0xFFFFE938 (1)[6], 0xFFFFE960 (1)[7] Access: Read-write Reset: 0x00000000 31 DONE 30 - 29 28 23 - 22 21 DCSIZE 20 15 14 13 12 DST_WIDTH 27 - 26 - 25 24 19 - 18 17 SCSIZE 16 11 10 9 8 3 2 1 0 SRC_WIDTH BTSIZE 7 6 5 4 BTSIZE This register can only be written if the WPEN bit is cleared in "DMAC Write Protect Mode Register" on page 564 * BTSIZE: Buffer Transfer Size The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the number of source width transfers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of transfers completed on the Source Interface. When this field is set to 0, the DMAC module is automatically disabled when the relevant channel is enabled. * SCSIZE: Source Chunk Transfer Size. Value Name Description 000 CHK_1 1 data transferred 001 CHK_4 4 data transferred 010 CHK_8 8 data transferred 011 CHK_16 16 data transferred * DCSIZE: Destination Chunk Transfer Size Value Name Description 000 CHK_1 1 data transferred 001 CHK_4 4 data transferred 010 CHK_8 8 data transferred 011 CHK_16 16 data transferred SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 556 * SRC_WIDTH: Transfer Width for the Source Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfer size is set to 16-bit width 10 WORD the transfer size is set to 32-bit width 11 DWORD the transfer size is set to 64-bit width * DST_WIDTH: Transfer Width for the Destination Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfer size is set to 16-bit width 10 WORD the transfer size is set to 32-bit width 11 DWORD the transfer size is set to 64-bit width * DONE: Current Descriptor Stop Command and Transfer Completed Memory Indicator 0: The transfer is performed. 1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the content of this register. The DONE field is written back to memory at the end of the current descriptor transfer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 557 31.8.17 DMAC Channel x [x = 0..7] Control B Register Name: DMAC_CTRLBx [x = 0..7] Address: 0xFFFFE64C (0)[0], 0xFFFFE674 (0)[1], 0xFFFFE69C (0)[2], 0xFFFFE6C4 (0)[3], 0xFFFFE6EC (0)[4], 0xFFFFE714 (0)[5], 0xFFFFE73C (0)[6], 0xFFFFE764 (0)[7], 0xFFFFE84C (1)[0], 0xFFFFE874 (1)[1], 0xFFFFE89C (1)[2], 0xFFFFE8C4 (1)[3], 0xFFFFE8EC (1)[4], 0xFFFFE914 (1)[5], 0xFFFFE93C (1)[6], 0xFFFFE964 (1)[7] Access: Read-write Reset: 0x00000000 31 AUTO 30 IEN 29 23 - 22 21 15 - 14 - 13 - 7 - 6 - 5 28 27 - 26 - 25 20 DST_DSCR 19 - 18 - 17 - 16 SRC_DSCR 12 DST_PIP 11 - 10 - 9 - 8 SRC_PIP 4 3 - 2 - 1 DST_INCR FC DIF 24 SRC_INCR 0 SIF This register can only be written if the WPEN bit is cleared in "DMAC Write Protect Mode Register" . * SIF: Source Interface Selection Field Value Name Description 00 AHB_IF0 The source transfer is done via AHB_Lite Interface 0 (first DMA Master Interface) 01 AHB_IF1 The source transfer is done via AHB_Lite Interface 1 (second DMA Master Interface) 10 AHB_IF2 The source transfer is done via AHB_Lite Interface 2 (third DMA Master Interface) * DIF: Destination Interface Selection Field Value Name Description 00 AHB_IF0 The destination transfer is done via AHB_Lite Interface 0 (first DMA Master Interface) 01 AHB_IF1 The destination transfer is done via AHB_Lite Interface 1 (second DMA Master Interface) 10 AHB_IF2 The destination transfer is done via AHB_Lite Interface 2 (third DMA Master Interface) * SRC_PIP: Source Picture-in-Picture Mode 0 (DISABLE): Picture-in-Picture mode is disabled. The source data area is contiguous. 1 (ENABLE): Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount. * DST_PIP: Destination Picture-in-Picture Mode 0 (DISABLE): Picture-in-Picture mode is disabled. The Destination data area is contiguous. 1 (ENABLE): Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 558 * SRC_DSCR: Source Address Descriptor 0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source. * DST_DSCR: Destination Address Descriptor 0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination. * FC: Flow Control This field defines which device controls the size of the buffer transfer, also referred to as the Flow Controller. Value Name Description 00 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 01 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 10 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 11 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller * SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source Value Name Description 00 INCREMENTING The source address is incremented 01 DECREMENTING The source address is decremented 10 FIXED The source address remains unchanged * DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination Value Name Description 00 INCREMENTING The destination address is incremented 01 DECREMENTING The destination address is decremented 10 FIXED The destination address remains unchanged * IEN: Interrupt Enable Not 0: When the buffer transfer is completed, the BTCx flag is set in the EBCISR status register. This bit is active low. 1: When the buffer transfer is completed, the BTCx flag is not set. If this bit is cleared, when the buffer transfer is completed, the BTCx flag is set in the EBCISR status register. * AUTO: Automatic Multiple Buffer Transfer 0 (DISABLE): Automatic multiple buffer transfer is disabled. 1 (ENABLE): Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 559 31.8.18 DMAC Channel x [x = 0..7] Configuration Register Name: DMAC_CFGx [x = 0..7] Address: 0xFFFFE650 (0)[0], 0xFFFFE678 (0)[1], 0xFFFFE6A0 (0)[2], 0xFFFFE6C8 (0)[3], 0xFFFFE6F0 (0)[4], 0xFFFFE718 (0)[5], 0xFFFFE740 (0)[6], 0xFFFFE768 (0)[7], 0xFFFFE850 (1)[0], 0xFFFFE878 (1)[1], 0xFFFFE8A0 (1)[2], 0xFFFFE8C8 (1)[3], 0xFFFFE8F0 (1)[4], 0xFFFFE918 (1)[5], 0xFFFFE940 (1)[6], 0xFFFFE968 (1)[7] Access: Read-write Reset: 0x0100000000 31 - 30 - 29 23 - 22 LOCK_IF_L 15 14 DST_PER_MSB 7 28 27 - 26 25 AHB_PROT 24 21 LOCK_B 20 LOCK_IF 19 - 18 - 17 - 16 SOD 13 DST_H2SEL 12 DST_REP 11 10 SRC_PER_MSB 9 SRC_H2SEL 8 SRC_REP 5 4 1 0 FIFOCFG 6 3 DST_PER 2 SRC_PER This register can only be written if the WPEN bit is cleared in "DMAC Write Protect Mode Register" on page 564 * SRC_PER: Source with Peripheral identifier Channel x Source Request is associated with peripheral identifier coded SRC_PER handshaking interface. * DST_PER: Destination with Peripheral identifier Channel x Destination Request is associated with peripheral identifier coded DST_PER handshaking interface. * SRC_REP: Source Reloaded from Previous 0 (CONTIGUOUS_ADDR): When automatic mode is activated, source address is contiguous between two buffers. 1 (RELOAD_ADDR): When automatic mode is activated, the source address and the control register are reloaded from previous transfer. * SRC_H2SEL: Software or Hardware Selection for the Source 0 (SW): Software handshaking interface is used to trigger a transfer request. 1 (HW): Hardware handshaking interface is used to trigger a transfer request. * SRC_PER_MSB: SRC_PER Most Significant Bits This field indicates the Most Significant bits of the SRC_PER field. * DST_REP: Destination Reloaded from Previous 0 (CONTIGUOUS_ADDR): When automatic mode is activated, destination address is contiguous between two buffers. 1 (RELOAD_ADDR): When automatic mode is activated, the destination and the control register are reloaded from the previous transfer. * DST_H2SEL: Software or Hardware Selection for the Destination 0 (SW): Software handshaking interface is used to trigger a transfer request. 1 (HW): Hardware handshaking interface is used to trigger a transfer request. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 560 * DST_PER_MSB: DST_PER Most Significant Bits This field indicates the Most Significant bits of the DST_PER field. * SOD: Stop On Done 0 (DISABLE): STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 (ENABLE): STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. * LOCK_IF: Interface Lock 0 (DISABLE): Interface Lock capability is disabled 1 (ENABLE): Interface Lock capability is enabled * LOCK_B: Bus Lock 0 (DISABLE): AHB Bus Locking capability is disabled. 1(ENABLE): AHB Bus Locking capability is enabled. * LOCK_IF_L: Master Interface Arbiter Lock 0 (CHUNK): The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 (BUFFER): The Master Interface Arbiter is locked by the channel x for a buffer transfer. * AHB_PROT: AHB Protection AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of protection. HPROT[3] HPROT[2] HPROT[1] HPROT[0] 1 AHB_PROT[0] Description Data access 0: User Access 1: Privileged Access 0: Not Bufferable AHB_PROT[1] 1: Bufferable 0: Not cacheable AHB_PROT[2] 1: Cacheable * FIFOCFG: FIFO Configuration Value Name Description 00 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 01 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 10 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 561 31.8.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register Name: DMAC_SPIPx [x = 0..7] Address: 0xFFFFE654 (0)[0], 0xFFFFE67C (0)[1], 0xFFFFE6A4 (0)[2], 0xFFFFE6CC (0)[3], 0xFFFFE6F4 (0)[4], 0xFFFFE71C (0)[5], 0xFFFFE744 (0)[6], 0xFFFFE76C (0)[7], 0xFFFFE854 (1)[0], 0xFFFFE87C (1)[1], 0xFFFFE8A4 (1)[2], 0xFFFFE8CC (1)[3], 0xFFFFE8F4 (1)[4], 0xFFFFE91C (1)[5], 0xFFFFE944 (1)[6], 0xFFFFE96C (1)[7] Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 24 SPIP_BOUNDARY 23 22 21 20 19 SPIP_BOUNDARY 18 17 16 15 14 13 12 11 10 9 8 3 2 1 0 SPIP_HOLE 7 6 5 4 SPIP_HOLE * SPIP_HOLE: Source Picture-in-Picture Hole This field indicates the value to add to the address when the programmable boundary has been reached. * SPIP_BOUNDARY: Source Picture-in-Picture Boundary This field indicates the number of source transfers to perform before the automatic address increment operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 562 31.8.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register Name: DMAC_DPIPx [x = 0..7] Address: 0xFFFFE658 (0)[0], 0xFFFFE680 (0)[1], 0xFFFFE6A8 (0)[2], 0xFFFFE6D0 (0)[3], 0xFFFFE6F8 (0)[4], 0xFFFFE720 (0)[5], 0xFFFFE748 (0)[6], 0xFFFFE770 (0)[7], 0xFFFFE858 (1)[0], 0xFFFFE880 (1)[1], 0xFFFFE8A8 (1)[2], 0xFFFFE8D0 (1)[3], 0xFFFFE8F8 (1)[4], 0xFFFFE920 (1)[5], 0xFFFFE948 (1)[6], 0xFFFFE970 (1)[7] Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 24 DPIP_BOUNDARY 23 22 21 20 19 DPIP_BOUNDARY 18 17 16 15 14 13 12 11 10 9 8 3 2 1 0 DPIP_HOLE 7 6 5 4 DPIP_HOLE * DPIP_HOLE: Destination Picture-in-Picture Hole This field indicates the value to add to the address when the programmable boundary has been reached. * DPIP_BOUNDARY: Destination Picture-in-Picture Boundary This field indicates the number of source transfers to perform before the automatic address increment operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 563 31.8.21 DMAC Write Protect Mode Register Name: DMAC_WPMR Address: 0xFFFFE7E4 (0), 0xFFFFE9E4 (1) Access: Read-write Reset: See Table 31-5 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 - - - - - - - WPEN * WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444D41 ("DMA" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444D41 ("DMA" in ASCII). Protects the registers: * "DMAC Global Configuration Register" on page 541 * "DMAC Enable Register" on page 542 * "DMAC Channel x [x = 0..7] Source Address Register" on page 553 * "DMAC Channel x [x = 0..7] Destination Address Register" on page 554 * "DMAC Channel x [x = 0..7] Descriptor Address Register" on page 555 * "DMAC Channel x [x = 0..7] Control A Register" on page 556 * "DMAC Channel x [x = 0..7] Control B Register" on page 558 * "DMAC Channel x [x = 0..7] Configuration Register" on page 560 * WPKEY: Write Protect KEY Value 0x444D41 Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 564 31.8.22 DMAC Write Protect Status Register Name: DMAC_WPSR Address: 0xFFFFE7E8 (0), 0xFFFFE9E8 (1) Access: Read-only Reset: See Table 31-5 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 - - - - - - - WPVS * WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DMAC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the DMAC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. * WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading DMAC_WPSR automatically clears all fields. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 565 32. AHB LCD Controller (LCDC) 32.1 Description The LCD controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an LCD module. The LCD has one display input buffer per overlay that fetches pixels through the dual AHB master interface and a lookup table to allow palletized display configurations. The LCD controller is programmable on a per overlay basis, and supports different LCD resolutions, window sizes, image formats and pixel depths. The LCD is connected to the ARM Advanced High Performance Bus (AHB) as a master for reading pixel data. It also integrates an APB interface to configure its registers. 32.2 Embedded Characteristics Dual AHB Master Interface Supports Single Scan Active TFT Display Supports 12-, 16-, 18- and 24-bit Output Mode through the Spatial Dithering Unit Asynchronous Output Mode Supported (at synthesis time) 1, 2, 4, 8 bits per pixel (palletized) 12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized) Supports One Base Layer (background) Supports Two Overlay Layer Windows Supports One High End Overlay (HEO) Window Supports One Hardware Cursor, Fixed or Free Size Hardware Cursor Fixed Size on the following patterns: 32x32, 64x64 and 128x128 Little Endian Memory Organization Programmable Timing Engine, with Integer Clock Divider Programmable Polarity for Data, Line Synchro and Frame Synchro. Display Size up to 2048x2048, or up to 720p in video format Color Lookup Table with up to 256 entries and Predefined 8-bit Alpha Programmable Negative and Positive Row Striding for all Layers Programmable Negative and Positive Pixel Striding for all Overlay1, Overlay2 and HEO layers High End Overlay supports 4:2:0 Planar Mode and Semiplanar Mode High End Overlay supports 4:2:2 Planar Mode, Semiplanar Mode and Packed High End Overlay includes Chroma Upsampling Unit Horizontal and Vertical Rescaling unit with Edge Interpolation and Independent Non Integer Ratio Hidden Layer Removal supported. Integrates Fully Programmable Color Space Conversion Overlay1, Overlay2 and High End Overlay Integrate Rotation Engine: 90, 180, 270 Blender Function Supports Arbitrary 8-bit Alpha Value and Chroma Keying DMA User interface uses Linked List Structure and Add-to-queue Structure SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 566 32.3 Block Diagram Figure 32-1. Block Diagram 32-bit APB Interface Configuration Registers SYSCTRL Unit PP Layer HCC Layer CLUT AHB Bus OVR2 Layer 64-bit Dual AHB Master Interface ROT LCD_DAT[23:0] CLUT DEAG Unit LCD_VSYNC OVR1 Layer ROT LCD_HSYNC CLUT GAB Unit HEO Layer LTE Unit LCD_PCLK ROT CSC LCD_DEN 2DSC CUE CLUT LCD_PWM LCD_DISP Base Layer CLUT HEO : High End Overlay HCC: Hardware Cursor Channel CUE : Chroma Upsampling Engine GAB : Global Alpha Blender CSC : Color Space Conversion LTE: LCD Timing Engine 2DSC : Two Dimension Scaler ROT : Hardware Rotation DEAG : DMA Engine Address Generation SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 567 32.4 I/O Lines Description Name Description Type LCD_PWM Contrast control signal, using Pulse Width Modulation Output LCD_HSYNC Horizontal Synchronization Pulse Output LCD_VSYNC Vertical Synchronization Pulse Output LCD_DAT[23:0] LCD 24-bit data bus Output LCD_DEN Data Enable Output LCD_DISP Display Enable signal Output LCD_PCLK Pixel Clock Output 32.5 Product Dependencies 32.5.1 I/O Lines The pins used for interfacing the LCD Controller may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the LCD Controller are not used by the application, they can be used for other purposes by the PIO Controller. Table 32-1. I/O Lines Instance Signal I/O Line Peripheral LCDC LCDDAT0 PA0 A LCDC LCDDAT1 PA1 A LCDC LCDDAT2 PA2 A LCDC LCDDAT3 PA3 A LCDC LCDDAT4 PA4 A LCDC LCDDAT5 PA5 A LCDC LCDDAT6 PA6 A LCDC LCDDAT7 PA7 A LCDC LCDDAT8 PA8 A LCDC LCDDAT9 PA9 A LCDC LCDDAT10 PA10 A LCDC LCDDAT11 PA11 A LCDC LCDDAT12 PA12 A LCDC LCDDAT13 PA13 A LCDC LCDDAT14 PA14 A LCDC LCDDAT15 PA15 A LCDC LCDDAT16 PA16 A LCDC LCDDAT16 PC14 C LCDC LCDDAT17 PA17 A LCDC LCDDAT17 PC13 C SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 568 Table 32-1. I/O Lines LCDC LCDDAT18 PA18 A LCDC LCDDAT18 PC12 C LCDC LCDDAT19 PA19 A LCDC LCDDAT19 PC11 C LCDC LCDDAT20 PA20 A LCDC LCDDAT20 PC10 C LCDC LCDDAT21 PA21 A LCDC LCDDAT21 PC15 C LCDC LCDDAT22 PA22 A LCDC LCDDAT22 PE27 C LCDC LCDDAT23 PA23 A LCDC LCDDAT23 PE28 C LCDC LCDDEN PA29 A LCDC LCDDISP PA25 A LCDC LCDHSYNC PA27 A LCDC LCDPCK PA28 A LCDC LCDPWM PA24 A LCDC LCDVSYNC PA26 A 32.5.2 Power Management The LCD Controller is not continuously clocked. The user must first enable the LCD Controller clock in the Power Management Controller before using it (PMC_PCER). 32.5.3 Interrupt Sources The LCD Controller interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller. Using the LCD Controller interrupt requires prior programming of the AIC. Table 32-2. Peripheral IDs Instance ID LCDC 36 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 569 32.6 Functional Description The LCD module integrates the following digital blocks: DMA Engine Address Generation (DEAG). This block performs data prefetch and requests access to the AHB interface. Input Overlay FIFO stores the stream of pixels. Color Lookup Table (CLUT). These 256 RAM-based lookup table entries are selected when the color depth is set to 1, 2, 4 or 8 bpp. Chroma Upsampling Engine (CUE). This block is selected when the input image sampling format is YUV (Y'CbCr) 4:2:0 and converts it to higher quality 4:4:4 image. Color Space Conversion (CSC) changes the color spare from YUV to RGB. Two Dimension Scaler (2DSC) resizes the image. Global Alpha Blender (GAB) performs programmable 256 level alpha blending. Output FIFO stores the blended pixel prior to display. LCD Timing Engine provides a fully programmable HSYNC-VSYNC interface. The DMA controller reads the image through the AHB master interface. The LCD controller engine formats the display data, then the GAB performs alpha blending if required, and writes the final pixel into the output FIFO. The programmable timing engine drives a valid pixel onto the LCD_DAT[23:0] display bus. 32.6.1 Timing Engine Configuration 32.6.1.1 Pixel Clock Period Configuration The pixel clock (PCLK) generated by the timing engine is the source clock (SCLK) divided by the field CLKDIV in the LCDC_LCDCFG0 register. The source clock can be selected between the system clock and the 2x system clock with the field CLKSEL located in the LCDC_LCDCFG0 register. The Pixel Clock period formula is given below: SCLK PCLK = -------------------------------CLKDIV + 2 The Pixel Clock polarity is also programmable. 32.6.1.2 Horizontal and Vertical Synchronization Configuration The following fields are used to configure the timing engine: HSPW field VSPW field VFPW field VBPW field HFPW field HBPW field PPL field RPF field The polarity of output signals is also programmable. 32.6.1.3 Timing Engine Power Up Software Operation The following sequence is used to enable the display: 1. Configure LCD timing parameters, signal polarity and clock period. 2. Enable the Pixel Clock by writing one to the CLKEN field of the LCDC_LCDEN register. 3. Poll CLKSTS field of the LCDC_LCDSR register to check that the clock is running. 4. Enable Horizontal and Vertical Synchronization by writing one to the SYNCEN field of the LCDC_LCDEN register. 5. Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is up. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 570 6. Enable the display power signal by writing one to the DISPEN field of the LCDC_LCDEN register. 7. Poll DISPSTS field of the LCDC_LCDSR register to check that the power signal is activated. The GUARDTIME field of the LCDC_LCDCFG5 register is used to configure the number of frames before the assertion of the DISP signal. 32.6.1.4 Timing Engine Power Down Software Operation The following sequence is used to disable the display: 1. Disable the DISP signal by writing DISPDIS field of the LCDC_LCDDIS register. 2. Poll DISPSTS field of the LCDC_LCDSR register to verify that the DISP is no longer activated. 3. Disable the HSYNC and VSYNC signals by writing one to SYNCDIS field of the LCDC_LCDDIS register. 4. Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is off. 5. Disable the Pixel clock by writing one in the CLKDIS field of the LCDC_LCDDIS register. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 571 32.6.2 DMA Software Operations 32.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure The DMA Channel Descriptor (DSCR) must be aligned on a 64-bit boundary. The DMA Channel Descriptor structure contains three fields: DSCR.CHXADDR: Frame Buffer base address register DSCR.CHXCTRL: Transfer Control register. DSCR.CHXNEXT: Next Descriptor Address register. Table 32-3. DMA Channel Descriptor Structure System Memory Structure Field for Channel CHX DSCR + 0x0 ADDR DSCR + 0x4 CTRL DSCR + 0x8 NEXT 32.6.2.2 Programming a DMA Channel 1. Check the status of the channel by reading the CHXCHSR register. 2. Write the channel descriptor (DSCR) structure in the system memory by writing DSCR.CHXADDR Frame base address, DSCR.CHXCTRL channel control and DSCR.CHXNEXT next descriptor location. 3. If more than one descriptor is expected, the field DFETCH of DSCR.CHXCTRL is set to one to enable the descriptor fetch operation. 4. Write the DSCR.CHXNEXT register with the address location of the descriptor structure and set DFETCH field of the DSCR.CHXCTRL register to one. 5. Enable the relevant channel by writing one to the CHEN field of the CHXCHER register. 6. An interrupt may be raised if unmasked when the descriptor has been loaded. 32.6.2.3 Disabling a DMA channel 1. Clearing the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure will disable the channel at the end of the frame. 2. Setting the DSCR.CHXNEXT field of the DSCR structure will disable the channel at the end of the frame. 3. Writing one to the CHDIS field of the CHXCHDR register will disable the channel at the end of the frame. 4. Writing one to the CHRST field of the CHXCHDR register will disable the channel immediately. This may occur in the middle of the image. 5. Polling CHSR field in the CHXCHSR register until the channel is successfully disabled. 32.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor 1. Write the new descriptor structure in the system memory. 2. Write the address of the new structure in the CHXHEAD register. 3. Add the new structure to the queue of descriptors by writing one to the A2QEN field of the CHXCHER register. 4. The new descriptor will be added to the queue on the next frame. 5. An interrupt will be raised if unmasked, when the head descriptor structure has been loaded by the DMA channel. 32.6.2.5 DMA Interrupt Generation The DMA controller operation sets the following interrupt flags in the interrupt status register CHXISR: DMA field indicates that the DMA transfer is completed. DSCR field indicates that the descriptor structure is loaded in the DMA controller. ADD field indicates that a descriptor has been added to the descriptor queue. DONE field indicates that the channel transfer has terminated and the channel is automatically disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 572 32.6.2.6 DMA Address Alignment Requirements When programming the DSCR.CHXADDR field of the DSCR structure the following requirement must be met. Table 32-4. DMA Address Alignment when CLUT Mode is Selected CLUT Mode DMA Address Alignment 1 bpp 8 bits 2 bpp 8 bits 4 bpp 8 bits 8 bpp 8 bits Table 32-5. DMA Address Alignment when RGB Mode is Selected RGB Mode DMA Address Alignment 12 bpp RGB 444 16 bits 16 bpp ARGB 4444 16 bits 16 bpp RGBA 4444 16 bits 16 bpp RGB 565 16 bits 16 bpp TRGB 1555 16 bits 18 bpp RGB 666 32 bits 18 bpp RGB 666 PACKED 8 bits 19 bpp TRGB 1666 32 bits 19 bpp TRGB 1666 8 bits 24 bpp RGB 888 32 bits 24 bpp RGB 888 PACKED 8 bits 25 bpp TRGB 1888 32 bits 32 bpp ARGB 8888 32 bits 32 bpp RGBA 8888 32 bits Table 32-6. DMA Address Alignment when YUV Mode is Selected YUV Mode DMA Address Alignment 32 bpp AYCrCb 32 bits 16 bpp YCrCb 4:2:2 32 bits Y 8 bits 16 bpp semiplanar YCrCb 4:2:2 CrCb 16 bits Y 8 bits 16 bpp planar YCrCb 4:2:2 Cr 8 bits Cb 8 bits Y 8 bits 12 bpp YCrCb 4:2:0 CrCb 16 bits SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 573 Table 32-6. DMA Address Alignment when YUV Mode is Selected YUV Mode DMA Address Alignment Y 8 bits 12 bpp YCrCb 4:2:0 Cr 8 bits Cb 8 bits 32.6.3 Overlay Software Configuration 32.6.3.1 System Bus Access Attributes These attributes are defined to improve bandwidth of the overlay. LOCKDIS field: when set to one the AHB lock signal is not asserted when the PSTRIDE value is different from zero (rotation in progress). ROTDIS field: when set to one the Pixel Striding optimization is disabled. DLBO field: when set to one only defined burst lengths are performed when the DMA channel retrieves the data from the memory. BLEN field: defines the maximum burst length of the DMA channel. SIF field: defines the targeted DMA interface. 32.6.3.2 Color Attributes CLUTMODE field: selects one color lookup mode RGBMODE field: selects the RGB mode. YUVMODE field: selects the Luminance Chrominance mode. 32.6.3.3 Window Position, Size, Scaling and Striding Attributes XPOS: YPOS fields define the position of the overlay window. XSIZE: YSIZE fields define the size of the displayed window. XMEMSIZE: YMEMSIZE fields define the size of the image frame buffer. XSTRIDE: PSTRIDE fields define the line and pixel striding. XFACTOR: YFACTOR fields define the scaling ratio. The position and size attributes are to be programmed to keep the window within the display area. When the color lookup mode is enabled the following restrictions apply on the horizontal and vertical window size: Table 32-7. Color Lookup Mode and Window Size CLUT MODE x-y Size Requirement 1 bpp multiple of 8 pixels 2 bpp multiple of 4 pixels 4 bpp multiple of 2 pixels 8 bpp free size Pixel striding is disabled when CLUT mode is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 574 When YUV mode is enabled the following restrictions apply on the window size: Table 32-8. YUV Mode and Window Size YUV MODE x-y Requirement, Scaling Turned Off x-y Requirement, Scaling Turned On AYUV free size x-y size is greater than 5 YUV 4:2:2 packed xsize is greater than 2 pixels x-y size is greater than 5 YUV 4:2:2 semiplanar xsize is greater than 2 pixels x-y size is greater than 5 YUV 4:2:2 planar xsize is greater than 2 pixels x-y size is greater than 5 YUV 4:2:0 semiplanar xsize is greater that 2 pixels x-y size is greater than 5 YUV 4:2:0 planar xsize is greater than 2 pixels x-y size is greater than 5 In RGB mode, there is no restriction on the line length. 32.6.3.4 Overlay Blender Attributes When two or more video layers are used, alpha blending is performed to define the final image displayed. Each window has its own blending attributes. CRKEY Field: enables the chroma keying and match logic. INV Field: performs bit inversion at pixel level. ITER2BL Field: when set the iterated data path is selected. ITER Field. REVALPHA Field: uses the reverse alpha value. GAEN Field: enables the global alpha value in the data path. LAEN Field: enables the local alpha value from the pixel. OVR Field: when set the overlay is selected as an input of the blender. DMA Field: the DMA data path is activated. REP Field: enables the bit replication to fill the 24-bit internal data path. DSTKEY Field: when set, Destination keying is enabled. GA Field: defines the global alpha value. 32.6.3.5 Overlay Attributes Software Operation 1. When required, write the overlay attributes configuration registers. 2. Set UPDATEEN field of the CHXCHER register. 3. Poll UPDATESR field in the CHXCHSR, the update applies when that field is reset. 32.6.4 RGB Frame Buffer Memory Bitmap 32.6.4.1 1 bpp Through Color Lookup Table Table 32-9. 1 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 0x2 0x1 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 1 bpp p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 575 32.6.4.2 2 bpp Through Color Lookup Table Table 32-10. 2 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 2 bpp 0x2 p15 p14 p13 p12 0x1 p11 p10 p9 p8 0x0 p7 p6 p5 8 7 p4 6 5 p3 4 3 p2 2 1 p1 0 p0 32.6.4.3 4 bpp Through Color Lookup Table Table 32-11. 4 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 0x2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 p7 Pixel 4 bpp p6 0x1 p5 0x0 p4 p3 8 7 6 p2 5 4 3 2 p1 1 0 p0 32.6.4.4 8 bpp Through Color Lookup Table Table 32-12. 8 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 0x2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 8 bpp p3 0x1 0x0 p2 8 7 6 5 4 p1 3 2 1 0 2 1 0 p0 32.6.4.5 12 bpp Memory Mapping, RGB 4:4:4 Table 32-13. 12 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 12 bpp 0x2 - R1[3:0] 0x1 G1[3:0] B1[3:0] 0x0 - 8 7 6 R0[3:0] 5 4 3 G0[3:0] B0[3:0] 32.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 Table 32-14. 16 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 A1[3:0] R1[3:0] 0x1 G1[3:0] B1[3:0] 0x0 A0[3:0] R0[3:0] 8 7 6 5 G0[3:0] 4 3 2 1 0 B0[3:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 576 32.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 Table 32-15. 16 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 R1[3:0] G13:0] 0x1 B1[3:0] A1[3:0] 0x0 R0[3:0] 8 7 6 G0[3:0] 5 4 3 B0[3:0] 2 1 0 A0[3:0] 32.6.4.8 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 Table 32-16. 16 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16bpp 0x2 R1[4:0] G1[5:0] 0x1 B1[4:0] 0x0 R0[4:0] 8 7 6 5 4 3 G0[5:0] 2 1 0 B0[4:0] 32.6.4.9 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 Table 32-17. 16 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 0x2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 4 bpp A1 R1[4:0] G1[4:0] 0x1 B1[4:0] A0 0x0 8 R0[4:0] 7 6 5 4 3 G0[4:0] 2 1 0 B0[4:0] 32.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 Table 32-18. 18 bpp Unpacked Memory Mapping, Little Endian Organization Mem addr 0x3 0x2 0x1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 18 bpp R0[5:0] 0x0 8 7 6 5 4 G0[5:0] 3 2 1 0 1 0 1 0 B0[5:0] 32.6.4.11 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 Table 32-19. 18 bpp Packed Memory Mapping, Little Endian Organization at Address 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 0x2 0x1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 18 bpp G1[1:0] B1[5:0] R0[5:0] 0x0 8 7 6 5 4 G0[5:0] 3 2 B0[5:0] Table 32-20. 18 bpp Packed Memory Mapping, Little Endian Organization at Address 0x4, 0x5, 0x6, 0x7 Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 18 bpp 0x6 R2[3:0] G2[5:0] 0x5 B2[5:0] 0x4 8 7 6 R1[5:2] 5 4 3 2 G1[5:2] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 577 Table 32-21. 18 bpp Packed Memory Mapping, Little Endian Organization at Address 0x8, 0x9, 0xA, 0xB Mem addr 0xB 0xA 0x9 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 18 bpp G4[1:0] B4[5:0] 0x8 R3[5:0] 8 7 6 G3[5:0] 5 4 3 2 B3[3:0] 1 0 R2[5:4] 32.6.4.12 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 Table 32-22. 19 bpp Unpacked Memory Mapping, Little Endian Organization Mem addr 0x3 0x2 0x1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 19 bpp A0 0x0 R0[5:0] 8 7 6 5 4 G0[5:0] 3 2 1 0 1 0 1 0 B0[5:0] 32.6.4.13 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 Table 32-23. 19 bpp Packed Memory Mapping, Little Endian Organization at Address 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 0x2 0x1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 19 bpp G1[1:0] B1[5:0] A0 0x0 R0[5:0] 8 7 6 5 4 G0[5:0] 3 2 B0[5:0] Table 32-24. 19 bpp Packed Memory Mapping, Little Endian Organization at Address 0x4, 0x5, 0x6, 0x7 Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 19 bpp 0x6 R2[3:0] 0x5 G2[5:0] 0x4 B2[5:0] 8 A1 7 6 5 4 3 R1[5:2] 2 G1[5:2] Table 32-25. 18 bpp Packed Memory Mapping, Little Endian Organization at Address 0x8, 0x9, 0xA, 0xB Mem addr 0xB 0xA Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 19 bpp G4[1:0] B4[5:0] 0x9 A3 R3[5:0] 0x8 8 7 6 G3[5:0] 5 4 3 2 B3[3:0] 1 0 R2[5:4] 32.6.4.14 24 bpp Unpacked Memory Mapping, RGB 8:8:8 Table 32-26. 24 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 24 bpp 0x2 0x1 R0[7:0] 0x0 G0[7:0] 8 7 6 5 4 3 2 1 0 B0[7:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 578 32.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:8 Table 32-27. 24 bpp Packed Memory Mapping, Little Endian Organization at Address 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 24 bpp 0x2 B1[7:0] 0x1 R0[7:0] 0x0 8 7 6 5 G0[7:0] 4 3 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 B0[7:0] Table 32-28. 24 bpp Packed Memory Mapping, Little Endian Organization at Address 0x4, 0x5, 0x6, 0x7 Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 24 bpp 0x6 G2[7:0] 0x5 B2[7:0] 0x4 8 7 6 5 R1[7:0] 4 3 G1[7:0] 32.6.4.16 25 bpp Memory Mapping, ARGB 1:8:8:8 Table 32-29. 25 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 0x2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 25 bpp A0 0x1 R0[7:0] 0x0 8 7 6 5 G0[7:0] 4 3 B0[7:0] 32.6.4.17 32 bpp Memory Mapping, ARGB 8:8:8:8 Table 32-30. 32 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 32 bpp 0x2 A0[7:0] 0x1 R0[7:0] 0x0 8 7 6 5 G0[7:0] 4 3 B0[7:0] 32.6.4.18 32 bpp Memory Mapping, RGBA 8:8:8:8 Table 32-31. 32 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 32 bpp 0x2 R0[7:0] 0x1 G0[7:0] 0x0 8 7 6 5 B0[7:0] 4 3 A0[7:0] 32.6.5 YUV Frame Buffer Memory Mapping 32.6.5.1 AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping Table 32-32. 32 bpp Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 A0[7:0] 0x1 Y0[7:0] 0x0 Cb0[7:0] 8 7 6 5 4 3 Cr0[7:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 579 32.6.5.2 4:2:2 Interleaved Mode Frame Buffer Memory Mapping Table 32-33. 16 bpp 4:2:2 interleaved Mode 0 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 Cr0[7:0] 0x1 Y1[7:0] 0x0 8 7 6 5 Cb0[7:0] 4 3 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 Y0[7:0] Table 32-34. 16 bpp 4:2:2 interleaved Mode 1 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 Y1[7:0] 0x1 Cr0[7:0] 0x0 8 7 6 5 Y0[7:0] 4 3 Cb0[7:0] Table 32-35. 16 bpp 4:2:2 interleaved Mode 2 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 Cb0[7:0] 0x1 Y1[7:0] 0x0 8 7 6 5 Cr0[7:0] 4 3 Y0[7:0] Table 32-36. 16 bpp 4:2:2 interleaved Mode 3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 Y1[7:0] 0x1 Cb0[7:0] 0x0 8 7 6 5 Y0[7:0] 4 3 Cr0[7:0] 32.6.5.3 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping Table 32-37. 4:2:2 Semiplanar Luminance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 Y3[7:0] 0x1 Y2[7:0] 0x0 8 7 6 5 Y1[7:0] 4 3 Y0[7:0] Table 32-38. 4:2:2 Semiplanar Chrominance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 Cb2[7:0] 0x1 Cr2[7:0] 0x0 Cb0[7:0] 8 7 6 5 4 3 Cr0[7:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 580 32.6.5.4 4:2:2 Planar Mode Frame Buffer Memory Mapping Table 32-39. 4:2:2 Planar Mode Luminance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 Y3[7:0] 0x1 Y2[7:0] 0x0 8 7 6 5 Y1[7:0] 4 3 2 1 0 1 0 Y0[7:0] Table 32-40. 4:2:2 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 C3[7:0] 0x1 C2[7:0] 0x0 8 7 6 5 C1[7:0] 4 3 2 C0[7:0] 32.6.5.5 4:2:0 Planar Mode Frame Buffer Memory Mapping In Planar Mode, the three video components Y, Cr and Cb are split into 3 memory areas and stored in a raster-scan order. These three memory planes are contiguous and always aligned on a 32-bit boundary. Table 32-41. 4:2:0 Planar Mode Luminance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 12 bpp 0x2 Y3[7:0] 0x1 Y2[7:0] 0x0 8 7 6 5 Y1[7:0] 4 3 2 1 0 2 1 0 1 0 1 0 Y0[7:0] Table 32-42. 4:2:0 Planar Mode Luminance Memory Mapping, Little Endian Organization for Byte 0x4, 0x5, 0x6, 0x7 Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 12 bpp 0x6 Y7[7:0] 0x5 Y6[7:0] 0x4 8 7 6 5 Y5[7:0] 4 3 Y4[7:0] Table 32-43. 4:2:0 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 12 bpp 0x2 C3[7:0] 0x1 C2[7:0] 0x0 8 7 6 5 C1[7:0] 4 3 2 C0[7:0] Table 32-44. 4:2:0 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x4, 0x5, 0x6, 0x7 Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 12 bpp 0x6 C7[7:0] 0x5 C6:[7:0] 0x4 C5[7:0] 8 7 6 5 4 3 2 C4[7:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 581 32.6.5.6 4:2:0 Semiplanar Frame Buffer Memory Mapping Table 32-45. 4:2:0 Semiplanar Mode Luminance Memory Mapping, Little Endian Organization Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 12 bpp 0x6 Y3[7:0] 0x5 Y2[7:0] 0x4 8 7 6 5 Y1[7:0] 4 3 2 1 0 2 1 0 Y0[7:0] Table 32-46. 4:2:0 Semiplanar Mode Chrominance Memory Mapping, Little Endian Organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 12 bpp 0x2 Cb1[7:0] 0x1 Cr1[7:0] 0x0 Cb0[7:0] 8 7 6 5 4 3 Cr0[7:0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 582 32.6.6 Chrominance Upsampling Unit Both 4:2:2 and 4:2:0 input formats are supported by the LCD module. In 4:2:2, the two chrominance components are sampled at half the sample rate of the luminance. The horizontal chrominance resolution is halved. When this input format is selected, the chrominance upsampling unit uses two chrominances to interpolate the missing component. In 4:2:0, Cr and Cb components are subsampled at a factor of two vertically and horizontally. When this input mode is selected, the chrominance upsampling unit uses two and four chroma components to generate the missing horizontal and vertical components. Figure 32-2. 4:2:2 Upsampling Algorithm Vertical and Horizontal upsampling 4:2:2 to 4:4:4 conversion 0 or 180 degree C[0,0] C[x/2,0] C[x,0] C[0,y/2] C[x/2,y/2] C[x,y/2] C[0,y] C[x/2,y] C[x,y] Y sample Cr Cb calculated at encoding time Cr Cb interpolated from 2 Chroma Component SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 583 Figure 32-3. 4:2:2 Packed Upsampling Algorithm Vertical and Horizontal upsampling 4:2:2 to 4:4:4 conversion 90 or 270 degree C[0,0] C[x/2,0] C[x,0] C[0,y/2] C[x/2,y/2] C[x,y/2] C[0,y] C[x/2,y] C[x,y] Y sample Cr Cb calculated at encoding time Cr Cb from the previous line (interpolated) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 584 Figure 32-4. 4:2:2 Semiplanar and Planar Upsampling Algorithm - 90 or 270 Degree Rotation Activated Vertical and Horizontal upsampling 4:2:2 to 4:4:4 conversion 90 or 270 degree C[0,0] C[x/2,0] C[x,0] C[0,y/2] C[x/2,y/2] C[x,y/2] C[0,y] C[x/2,y] C[x,y] Y sample Cr Cb calculated at encoding time Cr Cb interpolated SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 585 Figure 32-5. 4:2:0 Upsampling Algorithm Vertical and Horizontal upsampling 4:2:0 to 4:4:4 conversion C[0,0] C[x/2,0] C[x,0] C[0,y/2] C[x/2,y/2] C[x,y/2] C[0,y] C[x/2,y] C[x,y] Y sample Cr Cb calculated at encoding time Cr Cb interpolated from 2 Chroma Component Cr Cb interpolated from 4 Chroma Component x Cr [ 0, 0 ] + Cr [ 0, x ] Chroma ---, 0 = ----------------------------------------------2 2 y Cr [ 0, 0 ] + C [ 0, y ] Chroma 0, --- = --------------------------------------------2 2 x y Cr [ 0, 0 ] + Cr [ x, 0 ] + Cr [ y, 0 ] + Cr [ x, y ] Chroma ---, --- = ----------------------------------------------------------------------------------------------------2 2 4 y Cr [ x, 0 ] + Cr [ x, y ] Chroma x, --- = ----------------------------------------------2 2 x Cr [ 0, y ] + Cr [ x, y ] Chroma ---, y = ----------------------------------------------2 2 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 586 32.6.6.1 Chrominance Upsampling Algorithm 1. Read line n from chrominance cache and interpolate [x/2,0] chrominance component filling the 1 x 2 kernel with line n. If the chrominance cache is empty, then fetch the first line from external memory and interpolate from the external memory. Duplicate the last chrominance at the end of line. 2. Fetch line n+1 from external memory, write line n + 1 to chrominance cache, read line n from the chrominance cache. interpolate [0,y/2], [x/2,y/2] and [x, y/2] filling the 2x2 kernel with line n and n+1. Duplicate the last chrominance line to generate the last interpolated line. 3. Repeat step 1 and step 2. 32.6.7 Line and Pixel Striding The LCD module includes a mechanism to increment the memory address by a programmable amount when the end of line has been reached, this offset is referred to as XSTRIDE and is defined on a per overlay basis. It also contains a PSTRIDE field that allows a programmable jump at the pixel level. Pixel stride is the value from one pixel to the next. 32.6.7.1 Line Striding When the end of line has been reached, the DMA address counter points to the next pixel address. The channel DMA address register is added to the XSTRIDE field, and then updated. If XSTRIDE is set to zero, the DMA address register remains unchanged. The XSTRIDE field of the channel configuration register is aligned to the pixel size boundary. The XSTRIDE field is a two's complement number. The following formula applies at the line boundary and indicates how the DMA controller computes the next pixel address. The function Sizeof() returns the number of bytes required to store a pixel. NextPixelAddress = CurrentPixelAddress + Sizeof ( pixel ) + XSTRIDE 32.6.7.2 Pixel Striding The DMA channel engine may optionally fetch non contiguous pixels. The channel DMA address register is added to the PSTRIDE field and then updated. If PSTRIDE is set to zero, the DMA address register remains unchanged and pixels are contiguous. The PSTRIDE field of the channel configuration register is aligned to the pixel size boundary. The PSTRIDE is a two's complement number. The following formula applies at the pixel boundary and indicates how the DMA controller computes the next pixel address. The function Sizeof() returns the number of bytes required to store a pixel. NextPixelAddress = CurrentPixelAddress + Sizeof ( pixel ) + PSTRIDE 32.6.8 Color Space Conversion Unit The color space conversion unit converts Luminance Chrominance color space into the Red Green Blue color space. The conversion matrix is defined below and is fully programmable through the LCD user interface ** R CSCRY CSCRU CSCRV Y - Yoff G = CSCGY CSCGU CSCGV * Cb - Cboff B CSCBY CSCBU CSCBV Cr - Croff Color space conversion coefficients are defined with the following equation: 8 9 1 CSC ij = ----- - 2 c 9 + 7 2 cn 2 n n=0 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 587 Color space conversion coefficients are defined with one sign bit, 2 integer bits and 7 fractional bits. The range of the CSCij coefficients is defined below with a step of 1/128. - 4 CSC ij 3,9921875 Additionally a set scaling factor {Yoff, Cboff, Croff} can be applied. 32.6.9 Two Dimension Scaler The High End Overlay (HEO) data path includes a hardware scaler that allows an image resize in both horizontal and vertical directions. 32.6.9.1 Video Scaler Description The scaling operation is based on a vertical and horizontal resampling algorithm. The sampling rate of the original image is increased when the video is upscaled, and decreased when the video is downscaled. A Vertical resampler is used to perform a vertical interpolation by a factor of vI, and a decimation by a factor of vD. A Horizontal resampler is used to perform a vertical interpolation by a factor of hI, and a decimation by a factor of hD. Both horizontal and vertical low pass filters are designed to minimize the aliasing effect. The frequency response of the low pass filter has the following characteristics: I H() = -) when 0 min ( ---,--ID 0 otherwise Taking into account the linear phase condition and anticipating the filter length M, the desired frequency response is modified. M - j --- Ie 2 H() = -) when 0 min ( ---,--ID 0 otherwise SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 588 Figure 32-6. Video Resampler Architecture Input video stream Vertical Resampler Vertical upsampler Low Pass Filter vI Vertical downsampler vD output video stream Horizontal Resampler Horizontal upsampler Low Pass Filter hI Horizontal downsampler hD The impulse response of the low pass filter defined is: c I x ------ when n = 0 h(n) = c sin ( c n ) I x - x ---------------------- otherwise ---- c n Or, for the filter of length M: c M I x ------ when n = ---- 2 M h( n) = sin c n - ----- 2 c I x - x --------------------------------------- otherwise ---- M c n - ----- 2 This ideal filter is non-causal and cannot be realized. The unit sample response h(n) is infinite in duration and must be truncated depending on the expected length M of the filter. This truncation is equivalent to the multiplication of the impulse response by a window function w(n). Table 32-47. Window Function for a Filter Length M Name of the Window Function Barlett Time Domain Sequence w(n) M-1 2 x n - -------------2 1 - ----------------------------------M-1 Blackman 2n- + 0,08 x cos ------------4n0,42 - 0,5 x cos ------------M-1 M-1 Hamming 2n0,54 - 0,46 x cos ------------M-1 Hanning 2n0,5 - 0,5 x cos ------------M-1 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 589 The horizontal resampler includes an 8-phase 5-tap filter equivalent to a 40-tap FIR described in Figure 32-8. The vertical resampler includes an 8-phase 3-tap filter equivalent to a 24-tap FIR described in Figure 32-8. Figure 32-7. Horizontal Resampler Filter Architecture x(n) Coefficient storage coeff2 coeff3 coeff4 coeff0 coeff1 y(m) Figure 32-8. Vertical Resampler Filter Architecture x(n) Coefficient storage -1 -1 L coeff2 L coeff1 coeff0 y(m) 32.6.9.2 Horizontal Scaler The XMEMSIZE field of the LCDC_HEOCFG4 register indicates the horizontal size minus one of the image in the system memory. The XSIZE field of the LCDC_HEOCFG3 register contains the horizontal size minus one of the window.The SCALEN field of the LCDC_HEOCFG13 register is set to one. The scaling factor is programmed in the XFACTOR field of the LCDC_HEOCFG13 register. Use the following algorithm to find the XFACTOR value. 8 x 256 x XMEMSIZE - 256 x XPHIDEF XFACTOR 1st = floor --------------------------------------------------------------------------------------------------------- XSIZE XFACTOR 1st = XFACTOR 1st + 1 XFACTOR 1st x XSIZE + 256 x XPHIDEF XMEMSIZE max = floor ----------------------------------------------------------------------------------------------------------- 2048 XFACTOR = XFACTOR 1st - 1 XFACTOR = XFACTOR 1st when ( XMEMSIZE max > XMEMSIZE ) otherwise 32.6.9.3 Vertical Scaler The YMEMSIZE field of the LCDC_HEOCFG4 register indicates the vertical size minus one of the image in the system memory. The YSIZE field of the LCDC_HEOCFG3 register contains the vertical size minus one of the window. The SCALEN field of the LCDC_HEOCFG13 register is set to one. The scaling factor is programmed in the YFACTOR field of the LCDC_HEOCFG13 register. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 590 8 x 256 x YMEMSIZE - 256 x YPHIDEF YFACTOR 1st = floor -------------------------------------------------------------------------------------------------------- YSIZE YFACTOR 1st = YFACTOR 1st + 1 YFACTOR 1st x YSIZE + 256 x YPHIDEF YMEMSIZE max = floor ---------------------------------------------------------------------------------------------------------- 2048 YFACTOR = YFACTOR 1st - 1 YFACTOR = YFACTOR 1st when ( YMEMSIZEmax > YMEMSIZE ) otherwise 32.6.10 Hardware Cursor The LCD module integrates a hardware cursor database. This layer features only a minimal set of color among 1, 2, 4 and 8 bpp palletized and 16 bpp to 32 bpp true color. The cursor size is limited to 128 x 128 pixels. 32.6.11 Color Combine Unit 32.6.11.1 Window Overlay The LCD module provides hardware support for multiple "overlay plane" that can be used to display windows on top of the image without destroying the image located below. The overlay image can use any color depth. Using the overlay alleviates the need to re-render the occluded portion of the image. When pixels are combined together through the alpha blending unit, a new color is created. This new pixel is called an iterated pixel and is passed to the next blending stage. Then, this pixel may be combined again with another pixel. The VIDPRI field located in the LCDC_HEOCFG12 register configures the video priority algorithm used to display the layers. When VIDPRI field is set to zero, the OVR1 layer is located above the HEO layer. When VIDPRI field is set to one, OVR1 is located below the HEO layer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 591 Figure 32-9. Overlay Example with Two Different Video Prioritization Algorithms HEO width OVR1 width Base width Base height o0(x,y) HEO o1(x,y) HEO height Overlay1 OVR1 OVR1 height HCC Base Image Video Prioritization Algorithm 1 : HCC > OVR1 > HEO > BASE Base Image HEO HCC Overlay1 OVR1 Video Prioritization Algorithm 2 : HCC > HEO > OVR1 > BASE 32.6.11.2 Base Layer, with Window Overlay Optimization When the base layer is combined with at least one active overlay, the whole base layer frame is retrieved from the memory though it is not visible. A set of registers is used to disable the Base DMA when this condition is met. These registers are listed below: LCDC_CFG5: DISCXPOS field discard area horizontal position LCDC_CFG5: DISCYPOS field discard area vertical position LCDC_CFG6: DISCXSIZE field discard area horizontal size LCDC_CFG6: DISCYSIZE field discard area vertical size LCDC_CFG4: DISCEN field discard area enable SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 592 Figure 32-10.Base Layer Discard Area Base width Base height Base Image discxsize Base width Base height {discxpos, discypos} Overlay1 discysize Discarded Area Base Image HEO width Base width Base height HEO Video HEO height Base Image SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 593 32.6.11.3 Overlay Blending The blending function requires two pixels (one iterated from the previous blending stage and one from the current overlay color) and a set of blending configuration parameters. These parameters define the color operation. Figure 32-11.Alpha Blender Function iter[n-1] GA OVR From LAEN Shadow REVALPHA Registers ITER ITER2BL CRKEY INV DMA GAEN RGBKEY RGBMASK OVRDEF la ovr blending function iter[n] Figure 32-12.Alpha Blender Database la ovr iter[n-1] OVR ITER OVRDEF GA "0" "0" GAEN 0 0 0 DMA LAEN "0" 0 0 Alpha * ovr + (1 - Alpha) * iter[n-1] REVALPHA ovr RGBKEY RGBMASK CRKEY ovr iter[n-1] 0 MATCH LOGIC 0 Inverted INV 0 iter[n] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 594 32.6.11.4 Global Alpha Blender Figure 32-13.Global Alpha Blender base ovr1la ovr1 iter[n-1] la ovr2la ovr2 heola heo hcrla hcr ovr blending function iter[n] iter[n-1] la ovr blending function iter[n] iter[n-1] la ovr blending function iter[n] iter[n-1] la ovr blending function iter[n] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 595 32.6.11.5 Window Blending Figure 32-14.256-level Alpha Blending Base Image OVR1 25 % HEO 75 % Video Prioritization Algorithm 1 : OVR1 > HEO > BASE 32.6.11.6 Color Keying Color keying involves a method of bit-block image transfer (Blit). This entails blitting one image onto another where not all the pixels are copied. Blitting usually involves two bitmaps, a source bitmap and a destination bitmap. A raster operation (ROP) is performed to define whether the iterated color or the overlay color is to be visible or not. Source Color Keying If the masked overlay color matches the color key then the iterated color is selected, Source Color Keying is activated using the following configuration. Select the Overlay to Blit Set DSTKEY field to zero Activate Color Keying setting CRKEY field to 1 Program Color Key writing RKEY, GKEY and BKEY fields Program Color Mask writing RKEY, GKEY and BKEY fields When the Mask register is set to zero, the comparison is disabled and the raster operation is activated. Destination Color Keying If the iterated masked color matches the color key then the overlay color is selected, Destination Color Keying is activated using the following configuration: Select the Overlay to Blit Set DSTKEY field to one Activate Color Keying setting CRKEY field to 1 Program Color Key writing RKEY, GKEY and BKEY fields Program Color Mask writing RKEY, GKEY and BKEY fields When the Mask register is set to zero, the comparison is disabled and the raster operation is activated. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 596 32.6.12 LCDC PWM Controller This block generates the LCD contrast control signal (LCD_PWM) to make possible the control of the display's contrast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can be converted to an analog voltage with a simple passive filter. The PWM module has a free-running counter whose value is compared against a compare register (PWMCVAL field of the LCDC_LCDCFG6 register). If the value in the counter is less than that in the register, the output brings the value of the polarity (PWMPOL field) bit in the PWM control register: LCDC_LCDCFG6. Otherwise, the opposite value is output. Thus, a periodic waveform with a pulse width proportional to the value in the compare register is generated. Due to the comparison mechanism, the output pulse has a width between zero and 255 PWM counter cycles. Thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) x VDD can be obtained (for the positive polarity case, or between (1/256) x VDD and VDD for the negative polarity case). Other voltage values can be obtained by adding active external circuitry. For PWM mode, the counter frequency can be adjusted to four different values using the PWMPS field of the LCDC_LCDCFG6 register. The PWM module can be fed with the slow clock or the system clock, depending on the CLKPWMSEL field of the LCDC_CFG0 register. 32.6.13 Post Processing Controller The output stream of pixels can be either displayed on the screen or written to the memory using the Post Processing Controller (PPC). When the PPC is used, the screen display is disabled, but synchronization signals remain active (if enabled). The stream of pixel can be written in RGB mode or encoded in YCbCr 422 mode. A programmable color space conversion stage is available. ** Y CSCYR CSCYG CSCYB R Yoff U = CSCUR CSCUG CSCUB * G + Uoff V CSCVR CSCVG CSCUB B Voff 32.6.14 LCD Overall Performance 32.6.14.1 Color Lookup Table (CLUT) Table 32-48. CLUT Pixel Performance CLUT MODE Pixels/Cycle ROTATION SCALING 1 bpp 64 Not supported Supported 2 bpp 32 Not supported Supported 3 bpp 16 Not supported Supported 4 bpp 8 Not supported Supported SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 597 32.6.14.2 RGB Mode Fetch Performance Table 32-49. RGB Mode Performance Pixels/Cycle Rotation Peak Random Memory Access (pixels/cycle) RGB Mode SCALING Burst Mode or Rotation Optimization Available Memory Burst Mode Rotation Optimization(1) Normal Mode 12 bpp 4 1 0.2 Supported 16 bpp 4 1 0.2 Supported 18 bpp 2 1 0.2 Supported 18 bpp RGB PACKED 2.666 Not supported 0.2 Supported 19 bpp 2 1 0.2 Supported 19 bpp PACKED 2.666 Not Supported 0.2 Supported 24 bpp 2 1 0.2 Supported 24 bpp PACKED 2.666 Not Supported 0.2 Supported 25 bpp 2 1 0.2 Supported 32 bpp 2 1 0.2 Supported Note: 1. Rotation optimization = AHB lock asserted on consecutive single access. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 598 32.6.14.3 YUV Mode Fetch Performance Table 32-50. Single Stream for 0 Wait State Memory Pixels/Cycle Rotation Peak Random Memory Access (pixels/cycle) YUV Mode SCALING burst mode or rotation optimization is available memory burst mode Rotation Optimization Normal Mode 32 bpp AYUV 2 1 0.2 Supported 16 bpp 422 4 Not Supported Not Supported Supported Note: rotation optimization = AHB lock asserted on consecutive single access Table 32-51. Multiple Stream for 0 Wait State Memory Comp/Cycle Rotation Peak Random Memory Access (pixels/cycle) YUV Mode SCALING burst mode or rotation optimization is available memory burst mode Rotation Optimization Normal Mode 16 bpp 422 semiplanar 8 Y, 4 UV 1 Y, 1 UV (2 streams) 0.2 Y 0.2 UV (2 streams) 16 bpp 422 planar 8 Y, 8 U, 8 V 1 Y, 1 U, 1 V (3 streams) 0.2 Y, 0.2 U, 0.2 V (3 streams) Supported 12 bpp 4:2:0 semiplanar 8 Y, 4 UV 1 Y, 1 UV (2 streams) 0.2 Y 0.2 UV (2 streams) 12 bpp 4:2:0 planar 8 Y, 8 U, 8 V 1 Y, 1 U, 1 V (3 streams) 0.2 Y, 0.2 U, 0.2 V (3 streams) Supported Note: Supported Supported In order to provide more bandwidth, when multiple streams are used to transfer Y, UV, U or V components, two AHB interfaces are recommended or multiple AXI ID are required. Table 32-52. YUV Planar Overall Performance 1 AHB Interface for 0 Wait State Memory Pix/Cycle YUV Mode Rotation Peak Random Memory Access (pixels/cycle) SCALING burst mode or rotation optimization is available memory burst mode Rotation Optimization Normal Mode 16 bpp 422 semiplanar 4 0.66 0.132 Supported 16 bpp 422 planar 4 0.5 0.1 Supported 12 bpp 4:2:0 semiplanar 5.32 0.8 0.16 Supported 12 bpp 4:2:0 planar 5.32 0.66 0.132 Supported In order to provide more bandwidth, when multiple streams are used to transfer Y, UV, U or V components, two AHB interfaces are recommended or multiple AXI ID are required. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 599 32.6.15 Input FIFO The LCD module includes one input FIFO per overlay. These input FIFOs are used to buffer the AHB burst and serialize the stream of pixels. 32.6.16 Output FIFO The LCD module includes one output FIFO that stores the blended pixel. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 600 32.6.17 Output Timing Generation 32.6.17.1 Active Display Timing Mode Figure 32-15.Active Display Timing LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] HSW VSW VBP HBP LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] HSW HBP HFP PPL HSW HBP LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] PPL HFP HSW VFP SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 601 Figure 32-16.Vertical Synchronization Timing (part 1) VSPDLYS = 0 VSPDLYE = 0 VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VSPSU = 0 VBP HBP VBP HBP VBP HBP VBP HBP VBP HBP VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 0 VSPDLYE = 1 VSW VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 1 VSW VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VSPSU = 1 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSW SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 602 Figure 32-17.Vertical Synchronization Timing (part 2) VSPDLYS = 1 VSPDLYE = 0 VSPSU = 0 VSPHO = 1 VSPSU = 1 VSPHO = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VBP HBP VBP HBP LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSW SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 603 Figure 32-18.DISP Signal Timing Diagram VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC lcd display off LCD_DISP lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP lcd display off lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP lcd display off lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP lcd display on lcd display off SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 604 32.6.18 Output Format 32.6.18.1 Active Mode Output Pin Assignment Table 32-53. Active Mode Output with 24 bits Bus Interface Configuration Pin ID TFT 24 bits TFT 18 bits TFT 16 bits TFT 12 bits LCD_DAT[23] R[7] - - - LCD_DAT[22] R[6] - - - LCD_DAT[21] R[5] - - - LCD_DAT[20] R[4] - - - LCD_DAT[19] R[3] - - - LCD_DAT[18] R[2] - - - LCD_DAT[17] R[1] R[5] - - LCD_DAT[16] R[0] R[4] - - LCD_DAT[15] G[7] R[3] R[4] - LCD_DAT[14] G[6] R[2] R[3] - LCD_DAT[13] G[5] R[1] R[2] - LCD_DAT[12] G[4] R[0] R[1] - LCD_DAT[11] G[3] G[5] R[0] R[3] LCD_DAT[10] G[2] G[4] G[5] R[2] LCD_DAT[9] G[1] G[3] G[4] R[1] LCD_DAT[8] G[0] G[2] G[3] R[0] LCD_DAT[7] B[7] G[1] G[2] G[3] LCD_DAT[6] B[6] G[0] G[1] G[2] LCD_DAT[5] B[5] B[5] G[0] G[1] LCD_DAT[4] B[4] B[4] B[4] G[0] LCD_DAT[3] B[3] B[3] B[3] B[3] LCD_DAT[2] B[2] B[2] B[2] B[2] LCD_DAT[1] B[1] B[1] B[1] B[1] LCD_DAT[0] B[0] B[0] B[0] B[0] SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 605 32.7 LCD Controller (LCDC) User Interface Table 32-54. Register Mapping Offset Register Name Access Reset 0x00000000 LCD Controller Configuration Register 0 LCDC_LCDCFG0 Read-write 0x00000000 0x00000004 LCD Controller Configuration Register 1 LCDC_LCDCFG1 Read-write 0x00000000 0x00000008 LCD Controller Configuration Register 2 LCDC_LCDCFG2 Read-write 0x00000000 0x0000000C LCD Controller Configuration Register 3 LCDC_LCDCFG3 Read-write 0x00000000 0x00000010 LCD Controller Configuration Register 4 LCDC_LCDCFG4 Read-write 0x00000000 0x00000014 LCD Controller Configuration Register 5 LCDC_LCDCFG5 Read-write 0x00000000 0x00000018 LCD Controller Configuration Register 6 LCDC_LCDCFG6 Read-write 0x00000000 0x0000001C Reserved - - - 0x00000020 LCD Controller Enable Register LCDC_LCDEN Write-only - 0x00000024 LCD Controller Disable Register LCDC_LCDDIS Write-only - 0x00000028 LCD Controller Status Register LCDC_LCDSR Read-only 0x00000000 0x0000002C LCD Controller Interrupt Enable Register LCDC_LCDIER Write-only - 0x00000030 LCD Controller Interrupt Disable Register LCDC_LCDIDR Write-only - 0x00000034 LCD Controller Interrupt Mask Register LCDC_LCDIMR Read-only 0x00000000 0x00000038 LCD Controller Interrupt Status Register LCDC_LCDISR Read-only 0x00000000 0x0000003C LCD Controller Attribute Register LCDC_ATTR Write-only - 0x00000040 Base Layer Channel Enable Register LCDC_BASECHER Write-only 0x00000000 0x00000044 Base Layer Channel Disable Register LCDC_BASECHDR Write-only 0x00000000 0x00000048 Base Layer Channel Status Register LCDC_BASECHSR Read-only 0x00000000 0x0000004C Base Layer Interrupt Enable Register LCDC_BASEIER Write-only 0x00000000 0x00000050 Base Layer Interrupt Disabled Register LCDC_BASEIDR Write-only 0x00000000 0x00000054 Base Layer Interrupt Mask Register LCDC_BASEIMR Read-only 0x00000000 0x00000058 Base Layer Interrupt status Register LCDC_BASEISR Read-only 0x00000000 0x0000005C Base DMA Head Register LCDC_BASEHEAD Read-write 0x00000000 0x00000060 Base DMA Address Register LCDC_BASEADDR Read-write 0x00000000 0x00000064 Base DMA Control Register LCDC_BASECTRL Read-write 0x00000000 0x00000068 Base DMA Next Register LCDC_BASENEXT Read-write 0x00000000 0x0000006C Base Configuration register 0 LCDC_BASECFG0 Read-write 0x00000000 0x00000070 Base Configuration register 1 LCDC_BASECFG1 Read-write 0x00000000 0x00000074 Base Configuration register 2 LCDC_BASECFG2 Read-write 0x00000000 0x00000078 Base Configuration register 3 LCDC_BASECFG3 Read-write 0x00000000 0x0000007C Base Configuration register 4 LCDC_BASECFG4 Read-write 0x00000000 0x00000080 Base Configuration register 5 LCDC_BASECFG5 Read-write 0x00000000 0x00000084 Base Configuration register 6 LCDC_BASECFG6 Read-write 0x00000000 0x88-0x13C Reserved - - - 0x00000140 Overlay 1 Channel Enable Register LCDC_OVRCHER1 Write-only 0x00000000 0x00000144 Overlay 1 Channel Disable Register LCDC_OVRCHDR1 Write-only 0x00000000 0x00000148 Overlay 1 Channel Status Register LCDC_OVRCHSR1 Read-only 0x00000000 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 606 Table 32-54. Register Mapping (Continued) Offset Register Name Access Reset 0x0000014C Overlay 1 Interrupt Enable Register LCDC_OVRIER1 Write-only 0x00000000 0x00000150 Overlay 1 Interrupt Disable Register LCDC_OVRIDR1 Write-only 0x00000000 0x00000154 Overlay 1 Interrupt Mask Register LCDC_OVRIMR1 Read-only 0x00000000 0x00000158 Overlay 1 Interrupt Status Register LCDC_OVRISR1 Read-only 0x00000000 0x0000015C Overlay 1 DMA Head Register LCDC_OVRHEAD1 Read-write 0x00000000 0x00000160 Overlay 1 DMA Address Register LCDC_OVRADDR1 Read-write 0x00000000 0x00000164 Overlay 1 DMA Control Register LCDC_OVRCTRL1 Read-write 0x00000000 0x00000168 Overlay 1 DMA Next Register LCDC_OVRNEXT1 Read-write 0x00000000 0x0000016C Overlay 1 Configuration 0 Register LCDC_OVR1CFG0 Read-write 0x00000000 0x00000170 Overlay 1 Configuration 1 Register LCDC_OVR1CFG1 Read-write 0x00000000 0x00000174 Overlay 1 Configuration 2 Register LCDC_OVR1CFG2 Read-write 0x00000000 0x00000178 Overlay 1 Configuration 3 Register LCDC_OVR1CFG3 Read-write 0x00000000 0x0000017C Overlay 1 Configuration 4 Register LCDC_OVR1CFG4 Read-write 0x00000000 0x00000180 Overlay 1 Configuration 5 Register LCDC_OVR1CFG5 Read-write 0x00000000 0x00000184 Overlay 1 Configuration 6 Register LCDC_OVR1CFG6 Read-write 0x00000000 0x00000188 Overlay 1 Configuration 7 Register LCDC_OVR1CFG7 Read-write 0x00000000 0x0000018C Overlay 1 Configuration 8Register LCDC_OVR1CFG8 Read-write 0x00000000 0x00000190 Overlay 1 Configuration 9 Register LCDC_OVR1CFG9 Read-write 0x00000000 0x194-0x23C Reserved - - - 0x00000240 Overlay 2 Channel Enable Register LCDC_OVRCHER2 Write-only 0x00000000 0x00000244 Overlay 2 Channel Disable Register LCDC_OVRCHDR2 Write-only 0x00000000 0x00000248 Overlay 2 Channel Status Register LCDC_OVRCHSR2 Read-only 0x00000000 0x0000024C Overlay 2 Interrupt Enable Register LCDC_OVRIER2 Write-only 0x00000000 0x00000250 Overlay 2 Interrupt Disable Register LCDC_OVRIDR2 Write-only 0x00000000 0x00000254 Overlay 2 Interrupt Mask Register LCDC_OVRIMR2 Read-only 0x00000000 0x00000258 Overlay 2 Interrupt status Register LCDC_OVRISR2 Read-only 0x00000000 0x0000025C Overlay 2 DMA Head Register LCDC_OVRHEAD2 Read-write 0x00000000 0x00000260 Overlay 2 DMA Address Register LCDC_OVRADDR2 Read-write 0x00000000 0x00000264 Overlay 2 DMA Control Register LCDC_OVRCTRL2 Read-write 0x00000000 0x00000268 Overlay 2 DMA Next Register LCDC_OVRNEXT2 Read-write 0x00000000 0x0000026C Overlay 2 Configuration 0 Register LCDC_OVR2CFG0 Read-write 0x00000000 0x00000270 Overlay 2 Configuration 1 Register LCDC_OVR2CFG1 Read-write 0x00000000 0x00000274 Overlay 2 Configuration 2 Register LCDC_OVR2CFG2 Read-write 0x00000000 0x00000278 Overlay 2 Configuration 3 Register LCDC_OVR2CFG3 Read-write 0x00000000 0x0000027C Overlay 2 Configuration 4 Register LCDC_OVR2CFG4 Read-write 0x00000000 0x00000280 Overlay 2 Configuration 5 Register LCDC_OVR2CFG5 Read-write 0x00000000 0x00000284 Overlay 2 Configuration 6 Register LCDC_OVR2CFG6 Read-write 0x00000000 0x00000288 Overlay 2 Configuration 7 Register LCDC_OVR2CFG7 Read-write 0x00000000 0x0000028C Overlay 2 Configuration 8 Register LCDC_OVR2CFG8 Read-write 0x00000000 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 607 Table 32-54. Register Mapping (Continued) Offset 0x00000290 0x294-33C Register Overlay 2 Configuration 9 Register Reserved Name Access Reset LCDC_OVR2CFG9 Read-write 0x00000000 - - - 0x00000340 High-End Overlay Channel Enable Register LCDC_HEOCHER Write-only 0x00000000 0x00000344 High-End Overlay Channel Disable Register LCDC_HEOCHDR Write-only 0x00000000 0x00000348 High-End Overlay Channel Status Register LCDC_HEOCHSR Read-only 0x00000000 0x0000034C High-End Overlay Interrupt Enable Register LCDC_HEOIER Write-only 0x00000000 0x00000350 High-End Overlay Interrupt Disable Register LCDC_HEOIDR Write-only 0x00000000 0x00000354 High-End Overlay Interrupt Mask Register LCDC_HEOIMR Read-only 0x00000000 0x00000358 High-End Overlay Interrupt Status Register LCDC_HEOISR Read-only 0x00000000 0x0000035C High-End Overlay DMA Head Register LCDC_HEOHEAD Read-write 0x00000000 0x00000360 High-End Overlay DMA Address Register LCDC_HEOADDR Read-write 0x00000000 0x00000364 High-End Overlay DMA Control Register LCDC_HEOCTRL Read-write 0x00000000 0x00000368 High-End Overlay DMA Next Register LCDC_HEONEXT Read-write 0x00000000 0x0000036C High-End Overlay U DMA Head Register LCDC_HEOUHEAD Read-write 0x00000000 0x00000370 High-End Overlay U DMA Address Register LCDC_HEOUADDR Read-write 0x00000000 0x00000374 High-End Overlay U DMA control Register LCDC_HEOUCTRL Read-write 0x00000000 0x00000378 High-End Overlay U DMA Next Register LCDC_HEOUNEXT Read-write 0x00000000 0x0000037C High-End Overlay V DMA Head Register LCDC_HEOVHEAD Read-write 0x00000000 0x00000380 High-End Overlay V DMA Address Register LCDC_HEOVADDR Read-write 0x00000000 0x00000384 High-End Overlay V DMA control Register LCDC_HEOVCTRL Read-write 0x00000000 0x00000388 High-End Overlay VDMA Next Register LCDC_HEOVNEXT Read-write 0x00000000 0x0000038C High-End Overlay Configuration Register 0 LCDC_HEOCFG0 Read-write 0x00000000 0x00000390 High-End Overlay Configuration Register 1 LCDC_HEOCFG1 Read-write 0x00000000 0x00000394 High-End Overlay Configuration Register 2 LCDC_HEOCFG2 Read-write 0x00000000 0x00000398 High-End Overlay Configuration Register 3 LCDC_HEOCFG3 Read-write 0x00000000 0x0000039C High-End Overlay Configuration Register 4 LCDC_HEOCFG4 Read-write 0x00000000 0x000003A0 High-End Overlay Configuration Register 5 LCDC_HEOCFG5 Read-write 0x00000000 0x000003A4 High-End Overlay Configuration Register 6 LCDC_HEOCFG6 Read-write 0x00000000 0x000003A8 High-End Overlay Configuration Register 7 LCDC_HEOCFG7 Read-write 0x00000000 0x000003AC High-End Overlay Configuration Register 8 LCDC_HEOCFG8 Read-write 0x00000000 0x000003B0 High-End Overlay Configuration Register 9 LCDC_HEOCFG9 Read-write 0x00000000 0x000003B4 High-End Overlay Configuration Register 10 LCDC_HEOCFG10 Read-write 0x00000000 0x000003B8 High-End Overlay Configuration Register 11 LCDC_HEOCFG11 Read-write 0x00000000 0x000003BC High-End Overlay Configuration Register 12 LCDC_HEOCFG12 Read-write 0x00000000 0x000003C0 High-End Overlay Configuration Register 13 LCDC_HEOCFG13 Read-write 0x00000000 0x000003C4 High-End Overlay Configuration Register 14 LCDC_HEOCFG14 Read-write 0x00000000 0x000003C8 High-End Overlay Configuration Register 15 LCDC_HEOCFG15 Read-write 0x00000000 0x000003CC High-End Overlay Configuration Register 16 LCDC_HEOCFG16 Read-write 0x00000000 0x000003D0 High-End Overlay Configuration Register 17 LCDC_HEOCFG17 Read-write 0x00000000 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 608 Table 32-54. Register Mapping (Continued) Offset Register Name Access Reset 0x000003D4 High-End Overlay Configuration Register 18 LCDC_HEOCFG18 Read-write 0x00000000 0x000003D8 High-End Overlay Configuration Register 19 LCDC_HEOCFG19 Read-write 0x00000000 0x000003DC High-End Overlay Configuration Register 20 LCDC_HEOCFG20 Read-write 0x00000000 0x000003E0 High-End Overlay Configuration Register 21 LCDC_HEOCFG21 Read-write 0x00000000 0x000003E4 High-End Overlay Configuration Register 22 LCDC_HEOCFG22 Read-write 0x00000000 0x000003E8 High-End Overlay Configuration Register 23 LCDC_HEOCFG23 Read-write 0x00000000 0x000003EC High-End Overlay Configuration Register 24 LCDC_HEOCFG24 Read-write 0x00000000 0x000003F0 High-End Overlay Configuration Register 25 LCDC_HEOCFG25 Read-write 0x00000000 0x000003F4 High-End Overlay Configuration Register 26 LCDC_HEOCFG26 Read-write 0x00000000 0x000003F8 High-End Overlay Configuration Register 27 LCDC_HEOCFG27 Read-write 0x00000000 0x000003FC High-End Overlay Configuration Register 28 LCDC_HEOCFG28 Read-write 0x00000000 0x00000400 High-End Overlay Configuration Register 29 LCDC_HEOCFG29 Read-write 0x00000000 0x00000404 High-End Overlay Configuration Register 30 LCDC_HEOCFG30 Read-write 0x00000000 0x00000408 High-End Overlay Configuration Register 31 LCDC_HEOCFG31 Read-write 0x00000000 0x0000040C High-End Overlay Configuration Register 32 LCDC_HEOCFG32 Read-write 0x00000000 0x00000410 High-End Overlay Configuration Register 33 LCDC_HEOCFG33 Read-write 0x00000000 0x00000414 High-End Overlay Configuration Register 34 LCDC_HEOCFG34 Read-write 0x00000000 0x00000418 High-End Overlay Configuration Register 35 LCDC_HEOCFG35 Read-write 0x00000000 0x0000041C High-End Overlay Configuration Register 36 LCDC_HEOCFG36 Read-write 0x00000000 0x00000420 High-End Overlay Configuration Register 37 LCDC_HEOCFG37 Read-write 0x00000000 0x00000424 High-End Overlay Configuration Register 38 LCDC_HEOCFG38 Read-write 0x00000000 0x00000428 High-End Overlay Configuration Register 39 LCDC_HEOCFG39 Read-write 0x00000000 0x0000042C High-End Overlay Configuration Register 40 LCDC_HEOCFG40 Read-write 0x00000000 0x00000430 High-End Overlay Configuration Register 41 LCDC_HEOCFG41 Read-write 0x00000000 0x434-0x43C Reserved - - - 0x00000440 Hardware Cursor Channel Enable Register LCDC_HCRCHER Write-only 0x00000000 0x00000444 Hardware Cursor Channel disable Register LCDC_HCRCHDR Write-only 0x00000000 0x00000448 Hardware Cursor Channel Status Register LCDC_HCRCHSR Read-only 0x00000000 0x0000044C Hardware Cursor Interrupt Enable Register LCDC_HCRIER Write-only 0x00000000 0x00000450 Hardware Cursor Interrupt Disable Register LCDC_HCRIDR Write-only 0x00000000 0x00000454 Hardware Cursor Interrupt Mask Register LCDC_HCRIMR Read-only 0x00000000 0x00000458 Hardware Cursor Interrupt Status Register LCDC_HCRISR Read-only 0x00000000 0x0000045C Hardware Cursor DMA Head Register LCDC_HCRHEAD Read-write 0x00000000 0x00000460 Hardware cursor DMA Address Register LCDC_HCRADDR Read-write 0x00000000 0x00000464 Hardware Cursor DMA Control Register LCDC_HCRCTRL Read-write 0x00000000 0x00000468 Hardware Cursor DMA NExt Register LCDC_HCRNEXT Read-write 0x00000000 0x0000046C Hardware Cursor Configuration 0 Register LCDC_HCRCFG0 Read-write 0x00000000 0x00000470 Hardware Cursor Configuration 1 Register LCDC_HCRCFG1 Read-write 0x00000000 0x00000474 Hardware Cursor Configuration 2 Register LCDC_HCRCFG2 Read-write 0x00000000 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 609 Table 32-54. Register Mapping (Continued) Offset Register Name Access Reset 0x00000478 Hardware Cursor Configuration 3 Register LCDC_HCRCFG3 Read-write 0x00000000 0x0000047C Hardware Cursor Configuration 4 Register LCDC_HCRCFG4 Read-write 0x00000000 0x00000480 Reserved - - - 0x00000484 Hardware Cursor Configuration 6 Register LCDC_HCRCFG6 Read-write 0x00000000 0x00000488 Hardware Cursor Configuration 7 Register LCDC_HCRCFG7 Read-write 0x00000000 0x0000048C Hardware Cursor Configuration 8 Register LCDC_HCRCFG8 Read-write 0x00000000 0x00000490 Hardware Cursor Configuration 9 Register LCDC_HCRCFG9 Read-write 0x00000000 0x494-0x53C Reserved - - - 0x00000540 Post Processing Channel Enable Register LCDC_PPCHER Write-only 0x00000000 0x00000544 Post Processing Channel Disable Register LCDC_PPCHDR Write-only 0x00000000 0x00000548 Post Processing Channel Status Register LCDC_PPCHSR Read-only 0x00000000 0x0000054C Post Processing Interrupt Enable Register LCDC_PPIER Write-only 0x00000000 0x00000550 Post Processing Interrupt Disable Register LCDC_PPIDR Write-only 0x00000000 0x00000554 Post Processing Interrupt Mask Register LCDC_PPIMR Read-only 0x00000000 0x00000558 Post Processing Interrupt Status Register LCDC_PPISR Read-only 0x00000000 0x0000055C Post Processing Head Register LCDC_PPHEAD Read-write 0x00000000 0x00000560 Post Processing Address Register LCDC_PPADDR Read-write 0x00000000 0x00000564 Post Processing Control Register LCDC_PPCTRL Read-write 0x00000000 0x00000568 Post Processing Next Register LCDC_PPNEXT Read-write 0x00000000 0x0000056C Post Processing Configuration Register 0 LCDC_PPCFG0 Read-write 0x00000000 0x00000570 Post Processing Configuration Register 1 LCDC_PPCFG1 Read-write 0x00000000 0x00000574 Post Processing Configuration Register 2 LCDC_PPCFG2 Read-write 0x00000000 0x00000578 Post Processing Configuration Register 3 LCDC_PPCFG3 Read-write 0x00000000 0x0000057C Post Processing Configuration Register 4 LCDC_PPCFG4 Read-write 0x00000000 0x00000580 Post Processing Configuration Register 5 LCDC_PPCFG5 Read-write 0x00000000 0x584-0x5FC Reserved - - - LCDC_BASECLUT0 Read-write 0x00000000 ... ... ... LCDC_BASECLUT255 Read-write 0x00000000 LCDC_OVR1CLUT0 Read-write 0x00000000 ... ... ... LCDC_OVR1CLUT255 Read-write 0x00000000 LCDC_OVR2CLUT0 Read-write 0x00000000 ... ... ... LCDC_OVR2CLUT255 Read-write 0x00000000 LCDC_HEOCLUT0 Read-write 0x00000000 ... ... ... LCDC_HEOCLUT255 Read-write 0x00000000 LCDC_HCRCLUT0 Read-write 0x00000000 0x600 ... Base CLUT Register 0 ... 0x8FC Base CLUT Register 255 0xA00 Overlay 1 CLUT Register 0 ... ... 0xDFC Overlay 1 CLUT Register 255 0xE00 Overlay 2 CLUT Register 0 ... ... 0x11FC Overlay 2 CLUT Register 255 0x1200 High End Overlay CLUT Register 0 ... ... 0x15FC High End Overlay CLUT Register 255 0x1600 Hardware Cursor CLUT Register 0 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 610 Table 32-54. Register Mapping (Continued) Offset Register ... 0x19FC ... Hardware Cursor CLUT Register 255 0x1A00-0x1FE4 Reserved Note: Name Access Reset ... ... ... LCDC_HCRCLUT255 Read-write 0x00000000 - - - 1. The CLUT registers are located in the RAM. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 611 32.7.1 LCD Controller Configuration Register 0 Name: LCDC_LCDCFG0 Address: 0xF0030000 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 - 7 - 14 - 6 - 13 CGDISPP 5 - 28 - 20 27 - 19 CLKDIV 12 11 CGDISHCR CGDISHEO 4 3 - CLKPWMSEL 26 - 18 25 - 17 24 - 16 10 CGDISOVR2 2 CLKSEL 9 CGDISOVR1 1 - 8 CGDISBASE 0 CLKPOL * CLKPOL: LCD Controller Clock Polarity 0: Data/Control signals are launched on the rising edge of the Pixel Clock. 1: Data/Control signals are launched on the falling edge of the Pixel Clock. * CLKSEL: LCD Controller Clock Source Selection 0: The Asynchronous output stage of the LCD controller is fed by the System Clock. 1: The Asynchronous output state of the LCD controller is fed by the 2x System Clock. * CLKPWMSEL: LCD Controller PWM Clock Source Selection 0: The slow clock is selected and feeds the PWM module. 1: The system clock is selected and feeds the PWM module. * CGDISBASE: Clock Gating Disable Control for the Base Layer 0: Automatic Clock Gating is enabled for the Base Layer. 1: Clock is running continuously. * CGDISOVR1: Clock Gating Disable Control for the Overlay 1 Layer 0: Automatic Clock Gating is enabled for the Overlay 1 Layer. 1: Clock is running continuously. * CGDISOVR2: Clock Gating Disable Control for the Overlay 2 Layer 0: Automatic Clock Gating is enabled for the Overlay 2 Layer. 1: Clock is running continuously. * CGDISHEO: Clock Gating Disable Control for the High End Overlay 0: Automatic Clock Gating is enabled for the High End Overlay Layer. 1: Clock is running continuously. * CGDISHCR: Clock Gating Disable Control for the Hardware Cursor Layer 0: Automatic Clock Gating is enabled for the Hardware Cursor Layer. 1: Clock is running continuously. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 612 * CGDISPP: Clock Gating Disable Control for the Post Processing Layer 0: Automatic Clock Gating is enabled for the Post Processing Layer. 1: Clock is running continuously. * CLKDIV: LCD Controller Clock Divider 8-bit width clock divider for pixel clock LCD_PCLK. pixel_clock = selected_clock / (CLKDIV+2) where selected_clock is equal to system_clock when CLKSEL field is set to 0 and system_clock2x when CLKSEL is set to 1. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 613 32.7.2 LCD Controller Configuration Register 1 Name: LCDC_LCDCFG1 Address: 0xF0030004 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 28 - 20 27 - 19 13 - 5 12 - 4 11 - 3 26 - 18 25 - 17 24 - 16 10 - 2 9 - 1 8 - 0 VSPW HSPW * HSPW: Horizontal Synchronization Pulse Width Width of the LCD_HSYNC pulse, given in pixel clock cycles. Width is (HSPW+1) LCD_PCLK cycles. * VSPW: Vertical Synchronization Pulse Width Width of the LCD_VSYNC pulse, given in number of lines. Width is (VSPW+1) lines. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 614 32.7.3 LCD Controller Configuration Register 2 Name: LCDC_LCDCFG2 Address: 0xF0030008 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 28 - 20 27 - 19 13 - 5 12 - 4 11 - 3 26 - 18 25 - 17 24 - 16 10 - 2 9 - 1 8 - 0 VBPW VFPW * VFPW: Vertical Front Porch Width This field indicates the number of lines at the end of the Frame. The blanking interval is equal to (VFPW+1) lines. * VBPW: Vertical Back Porch Width This field indicates the number of lines at the beginning of the Frame. The blanking interval is equal to VBPW lines. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 615 32.7.4 LCD Controller Configuration Register 3 Name: LCDC_LCDCFG3 Address: 0xF003000C Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 - 7 14 - 6 13 - 5 12 - 4 27 - 19 26 - 18 25 - 17 24 HBPW 16 11 - 3 10 - 2 9 - 1 8 HFPW 0 HBPW HFPW * HFPW: Horizontal Front Porch Width Number of pixel clock cycles inserted at the end of the active line. The interval is equal to (HFPW+1) LCD_PCLK cycles. * HBPW: Horizontal Back Porch Width Number of pixel clock cycles inserted at the beginning of the line. The interval is equal to (HBPW+1) LCD_PCLK cycles. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 616 32.7.5 LCD Controller Configuration Register 4 Name: LCDC_LCDCFG4 Address: 0xF0030010 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 RPF 17 24 9 PPL 1 8 16 RPF 15 - 7 14 - 6 13 - 5 12 - 4 2 0 PPL * RPF: Number of Active Row Per Frame Number of active lines in the frame. The frame height is equal to (RPF+1) lines. * PPL: Number of Pixels Per Line Number of pixel in the frame. The number of active pixels in the frame is equal to (PPL+1) pixels. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 617 32.7.6 LCD Controller Configuration Register 5 Name: LCDC_LCDCFG5 Address: 0xF0030014 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 DISPDLY 30 - 22 - 14 - 6 DITHER 29 - 21 - 13 VSPHO 5 - 28 - 20 27 - 19 12 VSPSU 4 DISPPOL 11 - 3 VSPDLYE 26 - 18 GUARDTIME 10 PP 2 VSPDLYS 25 - 17 24 - 16 9 8 MODE 1 VSPOL 0 HSPOL * HSPOL: Horizontal Synchronization Pulse Polarity 0: Active High 1: Active Low * VSPOL: Vertical Synchronization Pulse Polarity 0: Active High 1: Active Low * VSPDLYS: Vertical Synchronization Pulse Start 0: The first active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. 1: The first active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. * VSPDLYE: Vertical Synchronization Pulse End 0: The second active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. 1: The second active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. * DISPPOL: Display Signal Polarity 0: Active High 1: Active Low * DITHER: LCD Controller Dithering 0: Dithering logical unit is disabled. 1: Dithering logical unit is activated. * DISPDLY: LCD Controller Display Power Signal Synchronization 0: The LCD_DISP signal is asserted synchronously with the second active edge of the horizontal pulse. 1: The LCD_DISP signal is asserted asynchronously with both edges of the horizontal pulse. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 618 * MODE: LCD Controller Output Mode Value Name Description 0 OUTPUT_12BPP LCD output mode is set to 12 bits per pixel 1 OUTPUT_16BPP LCD output mode is set to 16 bits per pixel 2 OUTPUT_18BPP LCD output mode is set to 18 bits per pixel 3 OUTPUT_24BPP LCD output mode is set to 24 bits per pixel * PP: Post Processing Enable 0: The Blended pixel is pushed into the output FIFO. 1: The Blended pixel is written back to memory, the post processing stage is enabled. * VSPSU: LCD Controller Vertical synchronization Pulse Setup Configuration 0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. 1: The vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse. * VSPHO: LCD Controller Vertical synchronization Pulse Hold Configuration 0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. 1: The vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse. * GUARDTIME: LCD DISPLAY Guard Time Number of frames inserted during start up before LCD_DISP assertion. Number of frames inserted after LCD_DISP reset. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 619 32.7.7 LCD Controller Configuration Register 6 Name: LCDC_LCDCFG6 Address: 0xF0030018 Access: Read-write Reset: 0x00000000 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 7 - 6 - 5 - 28 - 20 - 12 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 PWMCVAL 4 3 PWMPOL - 2 1 PWMPS 0 * PWMPS: PWM Clock Prescaler 3-bit value. Selects the configuration of the counter prescaler module. The PWMPS field decoding is listed below. Value Name Description 000 DIV_1 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK 001 DIV_2 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/2 010 DIV_4 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/4 011 DIV_8 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/8 100 DIV_16 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/16 101 DIV_32 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/32 110 DIV_64 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/64 * PWMPOL: LCD Controller PWM Signal Polarity This bit defines the polarity of the PWM output signal. If set to one, the output pulses are high level (the output will be high whenever the value in the counter is less than the value CVAL) If set to zero, the output pulses are low level. * PWMCVAL: LCD Controller PWM Compare Value PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 620 32.7.8 LCD Controller Enable Register Name: LCDC_LCDEN Address: 0xF0030020 Access: Write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 PWMEN 26 - 18 - 10 - 2 DISPEN 25 - 17 - 9 - 1 SYNCEN 24 - 16 - 8 - 0 CLKEN * CLKEN: LCD Controller Pixel Clock Enable 0: Writing this field to zero has no effect. 1: When set to one the pixel clock logical unit is activated. * SYNCEN: LCD Controller Horizontal and Vertical Synchronization Enable 0: Writing this field to zero has no effect. 1: When set to one, both horizontal and vertical synchronization (LCD_VSYNC and LCD_HSYNC) signals are generated. * DISPEN: LCD Controller DISP Signal Enable 0: Writing this field to zero has no effect. 1: When set to one, LCD_DISP signal is generated. * PWMEN: LCD Controller Pulse Width Modulation Enable 0: Writing this field to zero has no effect. 1: When set to one, the pwm is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 621 32.7.9 LCD Controller Disable Register Name: LCDC_LCDDIS Address: 0xF0030024 Access: Write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 PWMRST 3 PWMDIS 26 - 18 - 10 DISPRST 2 DISPDIS 25 - 17 - 9 SYNCRST 1 SYNCDIS 24 - 16 - 8 CLKRST 0 CLKDIS * CLKDIS: LCD Controller Pixel Clock Disable 0: No effect. 1: Disables the pixel clock. * SYNCDIS: LCD Controller Horizontal and Vertical Synchronization Disable 0: No effect. 1: Disables the synchronization signals after the end of the frame. * DISPDIS: LCD Controller DISP Signal Disable 0: No effect 1: Disables the DISP signal. * PWMDIS: LCD Controller Pulse Width Modulation Disable 0: No effect 1: Disables the pulse width modulation signal. * CLKRST: LCD Controller Clock Reset 0: No effect. 1: Resets the pixel clock generator module. The pixel clock duty cycle may be violated. * SYNCRST: LCD Controller Horizontal and Vertical Synchronization Reset 0: No effect. 1: Resets the timing engine. Both Horizontal and vertical pulse width are violated. * DISPRST: LCD Controller DISP Signal Reset 0: No effect. 1: Resets the DISP signal. * PWMRST: LCD Controller PWM Reset 0: No effect. 1: Resets the PWM module, the duty cycle may be violated. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 622 32.7.10 LCD Controller Status Register Name: LCDC_LCDSR Address: 0xF0030028 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 SIPSTS 27 - 19 - 11 - 3 PWMSTS 26 - 18 - 10 - 2 DISPSTS 25 - 17 - 9 - 1 LCDSTS 24 - 16 - 8 - 0 CLKSTS * CLKSTS: Clock Status 0: Pixel Clock is disabled. 1: Pixel Clock is running. * LCDSTS: LCD Controller Synchronization status 0: Timing Engine is disabled. 1: Timing Engine is running. * DISPSTS: LCD Controller DISP Signal Status 0: DISP is disabled. 1: DISP signal is activated. * PWMSTS: LCD Controller PWM Signal Status 0: PWM is disabled. 1: PWM signal is activated. * SIPSTS: Synchronization In Progress 0: Clock domain synchronization is terminated. 1: Synchronization is in progress. Access to the registers LCDC_LCDCCFG[0..6], LCDC_LCDEN and LCDC_LCDDIS has no effect. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 623 32.7.11 LCD Controller Interrupt Enable Register Name: LCDC_LCDIER Address: 0xF003002C Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 PPIE 5 - 28 - 20 - 12 HCRIE 4 FIFOERRIE 27 - 19 - 11 HEOIE 3 - 26 - 18 - 10 OVR2IE 2 DISPIE 25 - 17 - 9 OVR1IE 1 DISIE 24 - 16 - 8 BASEIE 0 SOFIE * SOFIE: Start of Frame Interrupt Enable Register 0: No effect 1: Enables the interrupt. * DISIE: LCD Disable Interrupt Enable Register 0: No effect 1: Enables the interrupt. * DISPIE: Power UP/Down Sequence Terminated Interrupt Enable Register 0: No effect 1: Enables the interrupt. * FIFOERRIE: Output FIFO Error Interrupt Enable Register 0: No effect 1: Enables the interrupt. * BASEIE: Base Layer Interrupt Enable Register 0: No effect 1: Enables the interrupt. * OVR1IE: Overlay 1 Interrupt Enable Register 0: No effect 1: Enables the interrupt. * OVR2IE: Overlay 2 Interrupt Enable Register 0: No effect 1: Enables the interrupt. * HEOIE: High End Overlay Interrupt Enable Register 0: No effect 1: Enables the interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 624 * HCRIE: Hardware Cursor Interrupt Enable Register 0: No effect 1: Enables the interrupt. * PPIE: Post Processing Interrupt Enable Register 0: No effect 1: Enables the interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 625 32.7.12 LCD Controller Interrupt Disable Register Name: LCDC_LCDIDR Address: 0xF0030030 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 PPID 5 - 28 - 20 - 12 HCRID 4 FIFOERRID 27 - 19 - 11 HEOID 3 - 26 - 18 - 10 OVR2ID 2 DISPID 25 - 17 - 9 OVR1ID 1 DISID 24 - 16 - 8 BASEID 0 SOFID * SOFID: Start of Frame Interrupt Disable Register 0: No effect 1: Disables the interrupt. * DISID: LCD Disable Interrupt Disable Register 0: No effect 1: Disables the interrupt. * DISPID: Power UP/Down Sequence Terminated Interrupt Disable Register 0: No effect 1: Disables the interrupt. * FIFOERRID: Output FIFO Error Interrupt Disable Register 0: No effect 1: Disables the interrupt. * BASEID: Base Layer Interrupt Disable Register 0: No effect 1: Disables the interrupt. * OVR1ID: Overlay 1 Interrupt Disable Register 0: No effect 1: Disables the interrupt. * OVR2ID: Overlay 2 Interrupt Disable Register 0: No effect 1: Disables the interrupt. * HEOID: High End Overlay Interrupt Disable Register 0: No effect 1: Disables the interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 626 * HCRID: Hardware Cursor Interrupt Disable Register 0: No effect 1: Disables the interrupt. * PPID: Post Processing Interrupt Disable Register 0: No effect 1: Disables the interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 627 32.7.13 LCD Controller Interrupt Mask Register Name: LCDC_LCDIMR Address: 0xF0030034 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 PPIM 5 - 28 - 20 - 12 HCRIM 4 FIFOERRIM 27 - 19 - 11 HEOIM 3 - 26 - 18 - 10 OVR2IM 2 DISPIM 25 - 17 - 9 OVR1IM 1 DISIM 24 - 16 - 8 BASEIM 0 SOFIM * SOFIM: Start of Frame Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DISIM: LCD Disable Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DISPIM: Power UP/Down Sequence Terminated Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * FIFOERRIM: Output FIFO Error Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * BASEIM: Base Layer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * OVR1IM: Overlay 1 Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * OVR2IM: Overlay 2 Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * HEOIM: High End Overlay Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 628 * HCRIM: Hardware Cursor Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * PPIM: Post Processing Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 629 32.7.14 LCD Controller Interrupt Status Register Name: LCDC_LCDISR Address: 0xF0030038 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 PP 5 - 28 - 20 - 12 HCR 4 FIFOERR 27 - 19 - 11 HEO 3 - 26 - 18 - 10 OVR2 2 DISP 25 - 17 - 9 OVR1 1 DIS 24 - 16 - 8 BASE 0 SOF * SOF: Start of Frame Interrupt Status Register When set to one, this flag indicates that a start of frame event has been detected. This flag is reset after a read operation. * DIS: LCD Disable Interrupt Status Register When set to one, this flag indicates that the horizontal and vertical timing generator has been successfully disabled. This flag is reset after a read operation. * DISP: Power-up/Power-down Sequence Terminated Interrupt Status Register When set to one, this flag indicates whether the power-up sequence or power-down sequence has terminated. This flag is reset after a read operation. * FIFOERR: Output FIFO Error When set to one, this flag indicates that an underflow occurs in the output FIFO. This flag is reset after a read operation. * BASE: Base Layer Raw Interrupt Status Register When set to one, this flag indicates that a base layer interrupt is pending. This flag is reset as soon as the BASEISR register is read. * OVR1: Overlay 1 Raw Interrupt Status Register When set to one, this flag indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the OVR1ISR register is read. * OVR2: Overlay 2 Raw Interrupt Status Register When set to one this flag indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the OVR1ISR register is read. * HEO: High End Overlay Raw Interrupt Status Register When set to one, this flag indicates that a Hi End layer interrupt is pending. This flag is reset as soon as the HEOISR register is read. * HCR: Hardware Cursor Raw Interrupt Status Register When set to one, this flag indicates that a Hardware Cursor layer interrupt is pending. This flag is reset as soon as the HCRISR register is read. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 630 * PP: Post Processing Raw Interrupt Status Register When set to one, this flag indicates that Post Processing interrupt is pending. This flag is reset as soon as the PPISR register is read. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 631 32.7.15 LCD Controller Attribute Register Name: LCDC_ATTR Address: 0xF003003C Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 PPA2Q 5 PP 28 - 20 - 12 HCRA2Q 4 HCR 27 - 19 - 11 HEOA2Q 3 HEO 26 - 18 - 10 OVR2A2Q 2 OVR2 25 - 17 - 9 OVR1A2Q 1 OVR1 24 - 16 - 8 BASEA2Q 0 BASE * BASE: Base Layer Update Attribute Register 0: No effect 1: Update the BASE window attributes. * OVR1: Overlay 1 Update Attribute Register 0: No effect 1: Update the OVR1 window attribute * OVR2: Overlay 2 Update Attribute Register 0: No effect 1: Update the OVR2 window attribute * HEO: High-End Overlay Update Attribute Register 0: No effect 1: Update the HEO window attribute * HCR: Hardware Cursor Update Attribute Register 0: No effect 1: Update the BCH window attribute * PP: Post-Processing Update Attribute Register 0: No effect 1: Update the PP window attribute * BASEA2Q: Base Layer Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the BASEHEAD register to the descriptor list. * OVR1A2Q: Overlay 1 Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the OVR1HEAD register to the descriptor list. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 632 * OVR2A2Q: Overlay 2 Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the OVR2HEAD register to the descriptor list. * HEOA2Q: High-End Overlay Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the HEOHEAD register to the descriptor list. * HCRA2Q: Hardware Cursor Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the HCRHEAD register to the descriptor list. * PPA2Q: Post-Processing Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the PPHEAD register to the descriptor list. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 633 32.7.16 Base Layer Channel Enable Register Name: LCDC_BASECHER Address: 0xF0030040 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QEN 25 - 17 - 9 - 1 UPDATEEN 24 - 16 - 8 - 0 CHEN * CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. * UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. * A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 634 32.7.17 Base Layer Channel Disable Register Name: LCDC_BASECHDR Address: 0xF0030044 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 CHRST 0 CHDIS * CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. * CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 635 32.7.18 Base Layer Channel Status Register Name: LCDC_BASECHSR Address: 0xF0030048 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QSR 25 - 17 - 9 - 1 UPDATESR 24 - 16 - 8 - 0 CHSR * CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. * UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. * A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 636 32.7.19 Base Layer Interrupt Enable Register Name: LCDC_BASEIER Address: 0xF003004C Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 637 32.7.20 Base Layer Interrupt Disable Register Name: LCDC_BASEIDR Address: 0xF0030050 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DONE: End of List Interrupt Disable Register 0: No effect. 1: interrupt source is disabled. * OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 638 32.7.21 Base Layer Interrupt Mask Register Name: LCDC_BASEIMR Address: 0xF0030054 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 639 32.7.22 Base Layer Interrupt Status Register Name: LCDC_BASEISR Address: 0xF0030058 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. * DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. * ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. * DONE: End of List Detected When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. * OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 640 32.7.23 Base Layer Head Register Name: LCDC_BASEHEAD Address: 0xF003005C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD * HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 641 32.7.24 Base Layer Address Register Name: LCDC_BASEADDR Address: 0xF0030060 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR * ADDR: DMA Transfer Start Address Frame buffer base address. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 642 32.7.25 Base Layer Control Register Name: LCDC_BASECTRL Address: 0xF0030064 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONEIEN 28 - 20 - 12 - 4 ADDIEN 27 - 19 - 11 - 3 DSCRIEN 26 - 18 - 10 - 2 DMAIEN 25 - 17 - 9 - 1 LFETCH 24 - 16 - 8 - 0 DFETCH * DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. * LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. * DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. * DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. * ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. * DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 643 32.7.26 Base Layer Next Register Name: LCDC_BASENEXT Address: 0xF0030068 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT * NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 644 32.7.27 Base Layer Configuration 0 Register Name: LCDC_BASECFG0 Address: 0xF003006C Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 28 - 20 - 12 - 4 BLEN 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 DLBO 0 SIF * SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. * BLEN: AHB Burst Length Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. * DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 645 32.7.28 Base Layer Configuration 1 Register Name: LCDC_BASECFG1 Address: 0xF0030070 Access: Read-write Reset: 0x00000000 31 - 23 - 15 30 - 22 - 14 7 6 29 - 21 - 13 28 20 - 12 5 4 - RGBMODE 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 24 - 16 - 8 CLUTMODE 1 - 0 CLUTEN * CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color lookup table is selected. * RGBMODE: RGB Input Mode Selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 * CLUTMODE: Color Lookup Table Input Mode Selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 646 32.7.29 Base Layer Configuration 2 Register Name: LCDC_BASECFG2 Address: 0xF0030074 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE * XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 647 32.7.30 Base Layer Configuration 3 Register Name: LCDC_BASECFG3 Address: 0xF0030078 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF * RDEF: Red Default Default Red color when the Base DMA channel is disabled. * GDEF: Green Default Default Green color when the Base DMA channel is disabled. * BDEF: Blue Default Default Blue color when the Base DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 648 32.7.31 Base Layer Configuration 4 Register Name: LCDC_BASECFG4 Address: 0xF003007C Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 DISCEN 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 REP 1 - 24 - 16 - 8 DMA 0 - * DMA: Use DMA Data Path 0: The default color is used on the Base Layer. 1: The DMA channel retrieves the pixels stream from the memory. * REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. * DISCEN: Discard Area Enable 0: The whole frame is retrieved from memory. 1:When set to one the DMA channel discards the area located at screen coordinate {DISCXPOS, DISCYPOS}. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 649 32.7.32 Base Layer Configuration 5 Register Name: LCDC_BASECFG5 Address: 0xF0030080 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 10 3 2 18 25 DISCYPOS 17 24 9 DISCXPOS 1 8 16 DISCYPOS 15 - 7 14 - 6 13 - 5 12 - 4 0 DISCXPOS * DISCXPOS: Discard Area horizontal coordinate Horizontal Position of the Discard Area. * DISCYPOS: Discard Area Vertical coordinate Vertical Position of the Discard Area. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 650 32.7.33 Base Layer Configuration 6 Register Name: LCDC_BASECFG6 Address: 0xF0030084 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 10 3 2 18 25 DISCYSIZE 17 24 9 DISCXSIZE 1 8 16 DISCYSIZE 15 - 7 14 - 6 13 - 5 12 - 4 0 DISCXSIZE * DISCXSIZE: Discard Area Horizontal Size Discard Horizontal size in pixels. The Discard size is set to (DISCXSIZE+1) pixels in horizontal. * DISCYSIZE: Discard Area Vertical Size Discard Vertical size in pixels. The Discard size is set to (DISCYSIZE+1) pixels in vertical. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 651 32.7.34 Overlay 1 Layer Channel Enable Register Name: LCDC_OVRCHER1 Address: 0xF0030140 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QEN 25 - 17 - 9 - 1 UPDATEEN 24 - 16 - 8 - 0 CHEN * CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. * UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates window attributes (size, alpha-blending, etc.) on the next start of frame. * A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 652 32.7.35 Overlay 1 Layer Channel Disable Register Name: LCDC_OVRCHDR1 Address: 0xF0030144 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 CHRST 0 CHDIS * CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. * CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 653 32.7.36 Overlay 1 Layer Channel Status Register Name: LCDC_OVRCHSR1 Address: 0xF0030148 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QSR 25 - 17 - 9 - 1 UPDATESR 24 - 16 - 8 - 0 CHSR * CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. * UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. * A2QSR: Add to Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 654 32.7.37 Overlay 1 Layer Interrupt Enable Register Name: LCDC_OVRIER1 Address: 0xF003014C Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 655 32.7.38 Overlay 1 Layer Interrupt Disable Register Name: LCDC_OVRIDR1 Address: 0xF0030150 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 656 32.7.39 Overlay 1 Layer Interrupt Mask Register Name: LCDC_OVRIMR1 Address: 0xF0030154 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 657 32.7.40 Overlay 1 Layer Interrupt Status Register Name: LCDC_OVRISR1 Address: 0xF0030158 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. * DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. * ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. * DONE: End of List Detected Register When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. * OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 658 32.7.41 Overlay 1 Layer Head Register Name: LCDC_OVRHEAD1 Address: 0xF003015C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD * HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 659 32.7.42 Overlay 1 Layer Address Register Name: LCDC_OVRADDR1 Address: 0xF0030160 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR * ADDR: DMA Transfer Overlay 1 Address Overlay 1 frame buffer base address. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 660 32.7.43 Overlay 1 Layer Control Register Name: LCDC_OVRCTRL1 Address: 0xF0030164 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONEIEN 28 - 20 - 12 - 4 ADDIEN 27 - 19 - 11 - 3 DSCRIEN 26 - 18 - 10 - 2 DMAIEN 25 - 17 - 9 - 1 LFETCH 24 - 16 - 8 - 0 DFETCH * DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. * LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. * DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. * DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. * ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. * DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 661 32.7.44 Overlay 1 Layer Next Register Name: LCDC_OVRNEXT1 Address: 0xF0030168 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT * NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 662 32.7.45 Overlay 1 Layer Configuration 0 Register Name: LCDC_OVR1CFG0 Address: 0xF003016C Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 LOCKDIS 5 28 - 20 - 12 ROTDIS 4 BLEN 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 DLBO 0 SIF * SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. * BLEN: AHB Burst Length Value Name Description 0 AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. AHB_BLEN_INCR16 An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. * DLBO: Defined Length Burst Only for Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). * ROTDIS: Hardware Rotation Optimization Disable 0: Rotation optimization is enabled. 1: Rotation optimization is disabled. * LOCKDIS: Hardware Rotation Lock Disable 0: AHB lock signal is asserted when a rotation is performed. 1: AHB lock signal is cleared when a rotation is performed. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 663 32.7.46 Overlay 1 Layer Configuration 1 Register Name: LCDC_OVR1CFG1 Address: 0xF0030170 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 - RGBMODE 26 - 18 - 10 - 2 - 25 - 17 - 9 24 - 16 - 8 CLUTMODE 1 - 0 CLUTEN * CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color lookup table is selected. * RGBMODE: RGB Input Mode Selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 * CLUTMODE: Color Lookup table input mode selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 664 32.7.47 Overlay 1 Layer Configuration 2 Register Name: LCDC_OVR1CFG2 Address: 0xF0030174 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XPOS * XPOS: Horizontal Window Position Overlay 1 Horizontal window position. * YPOS: Vertical Window Position Overlay 1 Vertical window position. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 665 32.7.48 Overlay 1 Layer Configuration 3 Register Name: LCDC_OVR1CFG3 Address: 0xF0030178 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XSIZE * XSIZE: Horizontal Window Size Overlay 1 window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE PPL * YSIZE: Vertical Window Size Overlay 1 window height in pixels. The window height is set to (YSIZE+1). The following constrain must be met: YPOS + YSIZE RPF SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 666 32.7.49 Overlay 1 Layer Configuration 4 Register Name: LCDC_OVR1CFG4 Address: 0xF003017C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE * XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 667 32.7.50 Overlay 1 Layer Configuration 5 Register Name: LCDC_OVR1CFG5 Address: 0xF0030180 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PSTRIDE PSTRIDE 15 14 13 12 7 6 5 4 PSTRIDE PSTRIDE * PSTRIDE: Pixel Stride PSTRIDE represents the memory offset, in bytes, between two pixels of the image. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 668 32.7.51 Overlay 1 Layer Configuration 6 Register Name: LCDC_OVR1CFG6 Address: 0xF0030184 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF * RDEF: Red Default Default Red color when the Overlay 1 DMA channel is disabled. * GDEF: Green Default Default Green color when the Overlay 1 DMA channel is disabled. * BDEF: Blue Default Default Blue color when the Overlay 1 DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 669 32.7.52 Overlay 1 Layer Configuration 7 Register Name: LCDC_OVR1CFG7 Address: 0xF0030188 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY * RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay. * GKEY: Green Color Component Chroma Key Reference Green chroma key used to match the Green color of the current overlay. * BKEY: Blue Color Component Chroma Key Reference Blue chroma key used to match the Blue color of the current overlay. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 670 32.7.53 Overlay 1 Layer Configuration 8 Register Name: LCDC_OVR1CFG8 Address: 0xF003018C Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK * RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared. * GMASK: Green Color Component Chroma Key Mask Green Mask used when the compare function is used. If a bit is set then this bit is compared. * BMASK: Blue Color Component Chroma Key Mask Blue Mask used when the compare function is used. If a bit is set then this bit is compared. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 671 32.7.54 Overlay1 Layer Configuration 9 Register Name: LCDC_OVR1CFG9 Address: 0xF0030190 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 - 7 OVR 14 - 6 LAEN 13 - 5 GAEN 12 - 4 REVALPHA 27 - 19 26 - 18 25 - 17 24 - 16 11 - 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA * CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled. * INV: Blender Inverted Blender Output Enable 0: Iterated pixel is the blended pixel. 1: Iterated pixel is the inverted pixel. * ITER2BL: Blender Iterated Color Enable 0: Final adder stage operand is set to 0. 1: Final adder stage operand is set to the iterated pixel value. * ITER: Blender Use Iterated Color 0: Pixel difference is set to 0. 1: Pixel difference is set to the iterated pixel value. * REVALPHA: Blender Reverse Alpha 0: Pixel difference is multiplied by alpha. 1: Pixel difference is multiplied by 1 - alpha. * GAEN: Blender Global Alpha Enable 0: Global alpha blending coefficient is disabled. 1: Global alpha blending coefficient is enabled. * LAEN: Blender Local Alpha Enable 0: Local alpha blending coefficient is disabled. 1: Local alpha blending coefficient is enabled. * OVR: Blender Overlay Layer Enable 0: Overlay pixel color is set to the default overlay pixel color. 1: Overlay pixel color is set to the DMA channel pixel color. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 672 * DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. * REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. * DSTKEY: Destination Chroma Keying 0: Source Chroma keying is enabled. 1: Destination Chroma keying is used. * GA: Blender Global Alpha Global alpha blender for the current layer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 673 32.7.55 Overlay 2 Layer Channel Enable Register Name: LCDC_OVRCHER2 Address: 0xF0030240 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QEN 25 - 17 - 9 - 1 UPDATEEN 24 - 16 - 8 - 0 CHEN * CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. * UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. * A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 674 32.7.56 Overlay 2 Layer Channel Disable Register Name: LCDC_OVRCHDR2 Address: 0xF0030244 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 CHRST 0 CHDIS * CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. * CHRST: Channel Reset Register When set to one this field disables the layer at the end of the current frame. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 675 32.7.57 Overlay 2 Layer Channel Status Register Name: LCDC_OVRCHSR2 Address: 0xF0030248 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QSR 25 - 17 - 9 - 1 UPDATESR 24 - 16 - 8 - 0 CHSR * CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. * UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will update on the next Frame. * A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 676 32.7.58 Overlay 2 Layer Interrupt Enable Register Name: LCDC_OVRIER2 Address: 0xF003024C Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 677 32.7.59 Overlay 2 Layer Interrupt Disable Register Name: LCDC_OVRIDR2 Address: 0xF0030250 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 678 32.7.60 Overlay 2 Layer Interrupt Mask Register Name: LCDC_OVRIMR2 Address: 0xF0030254 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 679 32.7.61 Overlay 2 Layer Interrupt Status Register Name: LCDC_OVRISR2 Address: 0xF0030258 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. * DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. * ADD: Head Descriptor Loaded Interrupt Disable Register When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. * DONE: End Of List Interrupt Disable Register When set to one this flag indicates that a End of List condition has occurred. This flag is reset after a read operation. * OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 680 32.7.62 Overlay 2 Layer Head Register Name: LCDC_OVRHEAD2 Address: 0xF003025C Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD * HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 681 32.7.63 Overlay 2 Layer Address Register Name: LCDC_OVRADDR2 Address: 0xF0030260 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR * ADDR: DMA Transfer Overlay 2 Address Overlay 2 frame buffer base address. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 682 32.7.64 Overlay 2 Layer Control Register Name: LCDC_OVRCTRL2 Address: 0xF0030264 Access: Read-Write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONEIEN 28 - 20 - 12 - 4 ADDIEN 27 - 19 - 11 - 3 DSCRIEN 26 - 18 - 10 - 2 DMAIEN 25 - 17 - 9 - 1 LFETCH 24 - 16 - 8 - 0 DFETCH * DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. * LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. * DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. * DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. * ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. * DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 683 32.7.65 Overlay 2 Layer Next Register Name: LCDC_OVRNEXT2 Address: 0xF0030268 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT * NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 684 32.7.66 Overlay 2 Layer Configuration 0 Register Name: LCDC_OVR2CFG0 Address: 0xF003026C Access: Read-Write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 LOCKDIS 5 28 - 20 - 12 ROTDIS 4 BLEN 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 DLBO 0 - * BLEN: AHB Burst Length Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. * DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for 2 and 3 beats burst. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). * ROTDIS: Hardware Rotation Optimization Disable 0: Rotation optimization is enabled. 1: Rotation optimization is disabled. * LOCKDIS: Hardware Rotation Lock Disable 0: AHB lock signal is asserted when a rotation is performed. 1: AHB lock signal is cleared when a rotation is performed. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 685 32.7.67 Overlay 2 Layer Configuration 1 Register Name: LCDC_OVR2CFG1 Address: 0xF0030270 Access: Read-Write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RGBMODE 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 24 - 16 - 8 CLUTMODE 1 - 0 CLUTEN * CLUTEN: Color Lookup Table Enable 0: RGB mode is selected 1: Color lookup table is selected * RGBMODE: RGB Input Mode Selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 * CLUTMODE: Color Lookup table input mode selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 686 32.7.68 Overlay 2 Layer Configuration 2 Register Name: LCDC_OVR2CFG2 Address: 0xF0030274 Access: Read-Write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XPOS * XPOS: Horizontal Window Position Overlay 2 Horizontal window position. * YPOS: Vertical Window Position Overlay 2 Vertical window position. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 687 32.7.69 Overlay 2 Layer Configuration 3 Register Name: LCDC_OVR2CFG3 Address: 0xF0030278 Access: Read-Write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XSIZE * XSIZE: Horizontal Window Size Overlay 2 window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE PPL * YSIZE: Vertical Window Size Overlay 2 window height in pixels. The window height is set to (YSIZE+1). The following constrain must be met: YPOS + YSIZE RPF SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 688 32.7.70 Overlay 2 Layer Configuration 4 Register Name: LCDC_OVR2CFG4 Address: 0xF003027C Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE * XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 689 32.7.71 Overlay 2 Layer Configuration 5 Register Name: LCDC_OVR2CFG5 Address: 0xF0030280 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PSTRIDE PSTRIDE 15 14 13 12 7 6 5 4 PSTRIDE PSTRIDE * PSTRIDE: Pixel Stride PSTRIDE represents the memory offset, in bytes, between two pixels of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 690 32.7.72 Overlay 2 Layer Configuration 6 Register Name: LCDC_OVR2CFG6 Address: 0xF0030284 Access: Read-Write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF * RDEF: Red Default Default Red color when the Overlay 1 DMA channel is disabled. * GDEF: Green Default Default Green color when the Overlay 1 DMA channel is disabled. * BDEF: Blue Default Default Blue color when the Overlay 1 DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 691 32.7.73 Overlay 2 Layer Configuration 7 Register Name: LCDC_OVR2CFG7 Address: 0xF0030288 Access: Read-Write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY * RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay. * GKEY: Green Color Component Chroma Key Reference Green chroma key used to match the Green color of the current overlay. * BKEY: Blue Color Component Chroma Key Reference Blue chroma key used to match the Blue color of the current overlay. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 692 32.7.74 Overlay 2 Layer Configuration 8 Register Name: LCDC_OVR2CFG8 Address: 0xF003028C Access: Read-Write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK * RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared. * GMASK: Green Color Component Chroma Key Mask Green Mask used when the compare function is used. If a bit is set then this bit is compared. * BMASK: Blue Color Component Chroma Key Mask Blue Mask used when the compare function is used. If a bit is set then this bit is compared. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 693 32.7.75 Overlay 2 Layer Configuration 9 Register Name: LCDC_OVR2CFG9 Address: 0xF0030290 Access: Read-Write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 - 7 OVR 14 - 6 LAEN 13 - 5 GAEN 12 - 4 REVALPHA 27 - 19 26 - 18 25 - 17 24 - 16 11 - 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA * CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled. * INV: Blender Inverted Blender Output Enable 0: Iterated pixel is the blended pixel. 1: Iterated pixel is the inverted pixel. * ITER2BL: Blender Iterated Color Enable 0: Final adder stage operand is set to 0. 1: Final adder stage operand is set to the iterated pixel value. * ITER: Blender Use Iterated Color 0: Pixel difference is set to 0. 1: Pixel difference is set to the iterated pixel value. * REVALPHA: Blender Reverse Alpha 0: Pixel difference is multiplied by alpha. 1: Pixel difference is multiplied by 1 - alpha. * GAEN: Blender Global Alpha Enable 0: Global alpha blending coefficient is disabled. 1: Global alpha blending coefficient is enabled. * LAEN: Blender Local Alpha Enable 0: Local alpha blending coefficient is disabled. 1: Local alpha blending coefficient is enabled. * OVR: Blender Overlay Layer Enable 0: Overlay pixel color is set to the default overlay pixel color. 1: Overlay pixel color is set to the DMA channel pixel color. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 694 * DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. * REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. * DSTKEY: Destination Chroma Keying 0: Source Chroma keying is enabled. 1: Destination Chroma keying is used. * GA: Blender Global Alpha Global alpha blender for the current layer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 695 32.7.76 High End Overlay Layer Channel Enable Register Name: LCDC_HEOCHER Address: 0xF0030340 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QEN 25 - 17 - 9 - 1 UPDATEEN 24 - 16 - 8 - 0 CHEN * CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. * UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. * A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 696 32.7.77 High End Overlay Layer Channel Disable Register Name: LCDC_HEOCHDR Address: 0xF0030344 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 CHRST 0 CHDIS * CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. * CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 697 32.7.78 High End Overlay Layer Channel Status Register Name: LCDC_HEOCHSR Address: 0xF0030348 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QSR 25 - 17 - 9 - 1 UPDATESR 24 - 16 - 8 - 0 CHSR * CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. * UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. * A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 698 32.7.79 High End Overlay Layer Interrupt Enable Register Name: LCDC_HEOIER Address: 0xF003034C Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 VOVR 14 UOVR 6 OVR 29 - 21 VDONE 13 UDONE 5 DONE 28 - 20 VADD 12 UADD 4 ADD 27 - 19 VDSCR 11 UDSCR 3 DSCR 26 - 18 VDMA 10 UDMA 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * UDMA: End of DMA Transfer for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * UDSCR: Descriptor Loaded for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * UADD: Head Descriptor Loaded for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 699 * UDONE: End of List for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * UOVR: Overflow for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * VDMA: End of DMA for V Chrominance Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * VDSCR: Descriptor Loaded for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * VADD: Head Descriptor Loaded for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * VDONE: End of List for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * VOVR: Overflow for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 700 32.7.80 High End Overlay Layer Interrupt Disable Register Name: LCDC_HEOIDR Address: 0xF0030350 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 VOVR 14 UOVR 6 OVR 29 - 21 VDONE 13 UDONE 5 DONE 28 - 20 VADD 12 UADD 4 ADD 27 - 19 VDSCR 11 UDSCR 3 DSCR 26 - 18 VDMA 10 UDMA 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * UDMA: End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * UDSCR: Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * UADD: Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 701 * UDONE: End of List Interrupt for U or UV Chrominance Component Disable Register 0: No effect. 1: Interrupt source is disabled. * UOVR: Overflow Interrupt for U or UV Chrominance Component Disable Register 0: No effect. 1: Interrupt source is disabled. * VDMA: End of DMA Transfer for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * VDSCR: Descriptor Loaded for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * VADD: Head Descriptor Loaded for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * VDONE: End of List for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * VOVR: Overflow for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 702 32.7.81 High End Overlay Layer Interrupt Mask Register Name: LCDC_HEOIMR Address: 0xF0030354 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 VOVR 14 UOVR 6 OVR 29 - 21 VDONE 13 UDONE 5 DONE 28 - 20 VADD 12 UADD 4 ADD 27 - 19 VDSCR 11 UDSCR 3 DSCR 26 - 18 VDMA 10 UDMA 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * UDMA: End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * UDSCR: Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * UADD: Head Descriptor Loaded for U or UV Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 703 * UDONE: End of List for U or UV Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * UOVR: Overflow for U Chrominance Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * VDMA: End of DMA Transfer for V Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * VDSCR: Descriptor Loaded for V Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * VADD: Head Descriptor Loaded for V Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * VDONE: End of List for V Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * VOVR: Overflow for V Chrominance Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 704 32.7.82 High End Overlay Layer Interrupt Status Register Name: LCDC_HEOISR Address: 0xF0030358 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 VOVR 14 UOVR 6 OVR 29 - 21 VDONE 13 UDONE 5 DONE 28 - 20 VADD 12 UADD 4 ADD 27 - 19 VDSCR 11 UDSCR 3 DSCR 26 - 18 VDMA 10 UDMA 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. * DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. * ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. * DONE: End of List Detected When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. * OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. * UDMA: End of DMA Transfer for U component When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. * UDSCR: DMA Descriptor Loaded for U component When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. * UADD: Head Descriptor Loaded for U component When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. * UDONE: End of List Detected for U component When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. * UOVR: Overflow Detected for U component When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. * VDMA: End of DMA Transfer for V component When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 705 * VDSCR: DMA Descriptor Loaded for V component When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. * VADD: Head Descriptor Loaded for V component When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. * VDONE: End of List Detected for V component When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. * VOVR: Overflow Detected for V component When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 706 32.7.83 High End Overlay Layer Head Register Name: LCDC_HEOHEAD Address: 0xF003035C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD * HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 707 32.7.84 High End Overlay Layer Address Register Name: LCDC_HEOADDR Address: 0xF0030360 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR * ADDR: DMA Transfer start Address Frame Buffer Base Address. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 708 32.7.85 High End Overlay Layer Control Register Name: LCDC_HEOCTRL Address: 0xF0030364 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONEIEN 28 - 20 - 12 - 4 ADDIEN 27 - 19 - 11 - 3 DSCRIEN 26 - 18 - 10 - 2 DMAIEN 25 - 17 - 9 - 1 LFETCH 24 - 16 - 8 - 0 DFETCH * DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. * LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. * DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. * DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. * ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. * DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 709 32.7.86 High End Overlay Layer Next Register Name: LCDC_HEONEXT Address: 0xF0030368 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT * NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 710 32.7.87 High End Overlay Layer U-UV Head Register Name: LCDC_HEOUHEAD Address: 0xF003036C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UHEAD UHEAD 15 14 13 12 7 6 5 4 UHEAD UHEAD * UHEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 711 32.7.88 High End Overlay Layer U-UV Address Register Name: LCDC_HEOUADDR Address: 0xF0030370 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UADDR UADDR 15 14 13 12 7 6 5 4 UADDR UADDR * UADDR: DMA Transfer Start Address for U or UV Chrominance U or UV frame buffer address. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 712 32.7.89 High End Overlay Layer U-UV Control Register Name: LCDC_HEOUCTRL Address: 0xF0030374 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 UDONEIEN 28 - 20 - 12 - 4 UADDIEN 27 - 19 - 11 - 3 UDSCRIEN 26 - 18 - 10 - 2 UDMAIEN 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 UDFETCH * UDFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. * UDMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. * UDSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. * UADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. * UDONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 713 32.7.90 High End Overlay Layer U-UV Next Register Name: LCDC_HEOUNEXT Address: 0xF0030378 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UNEXT UNEXT 15 14 13 12 7 6 5 4 UNEXT UNEXT * UNEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 714 32.7.91 High End Overlay Layer V Head Register Name: LCDC_HEOVHEAD Address: 0xF003037C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VHEAD VHEAD 15 14 13 12 7 6 5 4 VHEAD VHEAD * VHEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 715 32.7.92 High End Overlay Layer V Address Register Name: LCDC_HEOVADDR Address: 0xF0030380 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VADDR VADDR 15 14 13 12 7 6 5 4 VADDR VADDR * VADDR: DMA Transfer Start Address for V Chrominance Frame Buffer Base Address. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 716 32.7.93 High End Overlay Layer V Control Register Name: LCDC_HEOVCTRL Address: 0xF0030384 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 VDONEIEN 28 - 20 - 12 - 4 VADDIEN 27 - 19 - 11 - 3 VDSCRIEN 26 - 18 - 10 - 2 VDMAIEN 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 VDFETCH * VDFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. * VDMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. * VDSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. * VADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. * VDONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 717 32.7.94 High End Overlay Layer V Next Register Name: LCDC_HEOVNEXT Address: 0xF0030388 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VNEXT VNEXT 15 14 13 12 7 6 5 4 VNEXT VNEXT * VNEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 718 32.7.95 High End Overlay Layer Configuration 0 Register Name: LCDC_HEOCFG0 Address: 0xF003038C Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 LOCKDIS 5 BLENUV 28 - 20 - 12 ROTDIS 4 BLEN 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 DLBO 0 SIF * SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. * BLEN: AHB Burst Length Value Name Description 0 AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. AHB_BLEN_INCR16 An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. * BLENUV: AHB Burst Length for U-V channel Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 719 * DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). * ROTDIS: Hardware Rotation Optimization Disable 0: Rotation optimization is enabled. 1: Rotation optimization is disabled. * LOCKDIS: Hardware Rotation Lock Disable 0: AHB lock signal is asserted when a rotation is performed. 1: AHB lock signal is cleared when a rotation is performed. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 720 32.7.96 High End Overlay Layer Configuration 1 Register Name: LCDC_HEOCFG1 Address: 0xF0030390 Access: Read-write Reset: 0x00000000 31 - 23 - 15 30 - 22 - 14 7 6 29 - 21 - 13 28 - 20 DSCALEOPT 12 5 4 YUVMODE RGBMODE 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 24 - - 17 16 YUV422SWP YUV422ROT 9 8 CLUTMODE 1 0 YUVEN CLUTEN * CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color Lookup table is selected. * YUVEN: YUV Color Space Enable 0: Color space is RGB 1: Color Space is YUV * RGBMODE: RGB input mode selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 721 * CLUTMODE: Color Lookup table input mode selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel * YUVMODE: YUV input mode selection Value Name Description 0 32BPP_AYCBCR 32 bpp AYCbCr 444 1 16BPP_YCBCR_MODE0 16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 422 2 16BPP_YCBCR_MODE1 16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 422 3 16BPP_YCBCR_MODE2 16 bpp Cb(n)Y(+1)Cr(n)Y(n) 422 4 16BPP_YCBCR_MODE3 16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 422 5 16BPP_YCBCR_SEMIPLANAR 16 bpp Semiplanar 422 YCbCr 6 16BPP_YCBCR_PLANAR 16 bpp Planar 422 YCbCr 7 12BPP_YCBCR_SEMIPLANAR 12 bpp Semiplanar 420 YCbCr 8 12BPP_YCBCR_PLANAR 12 bpp Planar 420 YCbCr * YUV422ROT: YUV 4:2:2 Rotation When set to one, this bit indicates that the Chroma Upsampling kernel is configured to use the 4:2:2 Rotation Algorithm. This field is relevant only when a rotation angle of 90 degrees or 270 degrees is used. * YUV422SWP: YUV 4:2:2 SWAP When set to one, the Y component of the YUV 4:2:2 packed data stream are swapped. * DSCALEOPT: Down Scaling Bandwidth Optimization 0: Scaler Optimization is disabled. 1: Scaler Optimization is enabled, only relevant pixels are retrieved from memory to fill the scaler filter. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 722 32.7.97 High End Overlay Layer Configuration 2 Register Name: LCDC_HEOCFG2 Address: 0xF0030394 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XPOS * XPOS: Horizontal Window Position High End Overlay Horizontal window position. * YPOS: Vertical Window Position High End Overlay Vertical window position. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 723 32.7.98 High End Overlay Layer Configuration 3 Register Name: LCDC_HEOCFG3 Address: 0xF0030398 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XSIZE * XSIZE: Horizontal Window Size High End Overlay window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE PPL * YSIZE: Vertical Window Size High End Overlay window height in pixels. The window height is set to (YSIZE+1). The following constrain must be met: YPOS + YSIZE RPF SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 724 32.7.99 High End Overlay Layer Configuration 4 Register Name: LCDC_HEOCFG4 Address: 0xF003039C Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YMEMSIZE 17 24 9 XMEMSIZE 1 8 16 YMEMSIZE 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XMEMSIZE * XMEMSIZE: Horizontal image Size in Memory High End Overlay image width in pixels. The image width is set to (XMEMSIZE+1). * YMEMSIZE: Vertical image Size in Memory High End Overlay image height in pixels. The image height is set to (YMEMSIZE+1). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 725 32.7.100High End Overlay Layer Configuration 5 Register Name: LCDC_HEOCFG5 Address: 0xF00303A0 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE * XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 726 32.7.101High End Overlay Layer Configuration 6 Register Name: LCDC_HEOCFG6 Address: 0xF00303A4 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PSTRIDE PSTRIDE 15 14 13 12 7 6 5 4 PSTRIDE PSTRIDE * PSTRIDE: Pixel Stride PSTRIDE represents the memory offset, in bytes, between two pixels of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 727 32.7.102High End Overlay Layer Configuration 7 Register Name: LCDC_HEOCFG7 Address: 0xF00303A8 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UVXSTRIDE UVXSTRIDE 15 14 13 12 7 6 5 4 UVXSTRIDE UVXSTRIDE * UVXSTRIDE: UV Horizontal Stride UVXSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 728 32.7.103High End Overlay Layer Configuration 8 Register Name: LCDC_HEOCFG8 Address: 0xF00303AC Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UVPSTRIDE UVPSTRIDE 15 14 13 12 7 6 5 4 UVPSTRIDE UVPSTRIDE * UVPSTRIDE: UV Pixel Stride UVPSTRIDE represents the memory offset, in bytes, between two pixels of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 729 32.7.104High End Overlay Layer Configuration 9 Register Name: LCDC_HEOCFG9 Address: 0xF00303B0 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF * RDEF: Red Default Default Red color when the High End Overlay DMA channel is disabled. * GDEF: Green Default Default Green color when the High End Overlay DMA channel is disabled. * BDEF: Blue Default Default Blue color when the High End Overlay DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 730 32.7.105High End Overlay Layer Configuration 10 Register Name: LCDC_HEOCFG10 Address: 0xF00303B4 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY * RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay. * GKEY: Green Color Component Chroma Key Reference Green chroma key used to match the Green color of the current overlay. * BKEY: Blue Color Component Chroma Key Reference Blue chroma key used to match the Blue color of the current overlay. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 731 32.7.106High End Overlay Layer Configuration 11 Register Name: LCDC_HEOCFG11 Address: 0xF00303B8 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK * RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared. * GMASK: Green Color Component Chroma Key Mask Green Mask used when the compare function is used. If a bit is set then this bit is compared. * BMASK: Blue Color Component Chroma Key Mask Blue Mask used when the compare function is used. If a bit is set then this bit is compared. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 732 32.7.107High End Overlay Layer Configuration 12 Register Name: LCDC_HEOCFG12 Address: 0xF00303BC Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 - 7 OVR 14 - 6 LAEN 13 - 5 GAEN 12 VIDPRI 4 REVALPHA 27 - 19 26 - 18 25 - 17 24 - 16 11 - 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA * CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled. * INV: Blender Inverted Blender Output Enable 0: Iterated pixel is the blended pixel. 1: Iterated pixel is the inverted pixel. * ITER2BL: Blender Iterated Color Enable 0: Final adder stage operand is set to 0. 1: Final adder stage operand is set to the iterated pixel value. * ITER: Blender Use Iterated Color 0: Pixel difference is set to 0. 1: Pixel difference is set to the iterated pixel value. * REVALPHA: Blender Reverse Alpha 0: Pixel difference is multiplied by alpha. 1: Pixel difference is multiplied by 1 - alpha. * GAEN: Blender Global Alpha Enable 0: Global alpha blending coefficient is disabled. 1: Global alpha blending coefficient is enabled. * LAEN: Blender Local Alpha Enable 0: Local alpha blending coefficient is disabled. 1: Local alpha blending coefficient is enabled. * OVR: Blender Overlay Layer Enable 0: Overlay pixel color is set to the default overlay pixel color. 1: Overlay pixel color is set to the DMA channel pixel color. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 733 * DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. * REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. * DSTKEY: Destination Chroma Keying 0: Source Chroma keying is enabled. 1: Destination Chroma keying is used. * VIDPRI: Video Priority 0: OVR1 layer is above HEO layer. 1: OVR1 layer is below HEO layer. * GA: Blender Global Alpha Global alpha blender for the current layer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 734 32.7.108High End Overlay Layer Configuration 13 Register Name: LCDC_HEOCFG13 Address: 0xF00303C0 Access: Read-write Reset: 0x00000000 31 SCALEN 23 30 - 22 29 28 27 26 25 24 21 20 19 18 17 16 10 9 8 2 1 0 YFACTOR YFACTOR 15 - 7 14 - 6 13 12 11 5 4 3 XFACTOR XFACTOR * SCALEN: Hardware Scaler Enable 0: Scaler is disabled 1: Scaler is enabled. * YFACTOR: Vertical Scaling Factor Scaler Vertical Factor. * XFACTOR: Horizontal Scaling Factor Scaler Horizontal Factor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 735 32.7.109High End Overlay Layer Configuration 14 Register Name: LCDC_HEOCFG14 Address: 0xF00303C4 Access: Read-write Reset: 0x00000000 31 - 23 15 30 CSCYOFF 22 CSCRV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCRV 18 CSCRU 13 12 11 10 9 4 3 2 1 CSCRU 7 6 5 CSCRY 0 CSCRY * CSCRY: Color Space Conversion Y coefficient for Red Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCRU: Color Space Conversion U coefficient for Red Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCRV: Color Space Conversion V coefficient for Red Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCYOFF: Color Space Conversion Offset 0: Offset is set to 0 1: Offset is set to 16 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 736 32.7.110High End Overlay Layer Configuration 15 Register Name: LCDC_HEOCFG15 Address: 0xF00303C8 Access: Read-write Reset: 0x00000000 31 - 23 15 30 CSCUOFF 22 CSCGV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCGV 18 CSCGU 13 12 11 10 9 4 3 2 1 CSCGU 7 6 5 CSCGY 0 CSCGY * CSCGY: Color Space Conversion Y coefficient for Green Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCGU: Color Space Conversion U coefficient for Green Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCGV: Color Space Conversion V coefficient for Green Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCUOFF: Color Space Conversion Offset 0: Offset is set to 0 1: Offset is set to 128 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 737 32.7.111High End Overlay Layer Configuration 16 Register Name: LCDC_HEOCFG16 Address: 0xF00303CC Access: Read-write Reset: 0x00000000 31 - 23 15 30 CSCVOFF 22 CSCBV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCBV 18 CSCBU 13 12 11 10 9 4 3 2 1 CSCBU 7 6 5 CSCBY 0 CSCBY * CSCBY: Color Space Conversion Y coefficient for Blue Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCBU: Color Space Conversion U coefficient for Blue Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCBV: Color Space Conversion V coefficient for Blue Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. * CSCVOFF: Color Space Conversion Offset 0: Offset is set to 0 1: Offset is set to 128 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 738 32.7.112High End Overlay Layer Configuration 17 Register Name: LCDC_HEOCFG17 Address: 0xF00303D0 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI0COEFF3 20 19 XPHI0COEFF2 12 11 XPHI0COEFF1 4 3 XPHI0COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 * XPHI0COEFF0: Horizontal Coefficient for phase 0 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI0COEFF1: Horizontal Coefficient for phase 0 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI0COEFF2: Horizontal Coefficient for phase 0 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. * XPHI0COEFF3: Horizontal Coefficient for phase 0 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 739 32.7.113High End Overlay Layer Configuration 18 Register Name: LCDC_HEOCFG18 Address: 0xF00303D4 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 - - 4 3 XPHI0COEFF4 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * XPHI0COEFF4: Horizontal Coefficient for phase 0 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 740 32.7.114High End Overlay Layer Configuration 19 Register Name: LCDC_HEOCFG19 Address: 0xF00303D8 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI1COEFF3 20 19 XPHI1COEFF2 12 11 XPHI1COEFF1 4 3 XPHI1COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 * XPHI1COEFF0: Horizontal Coefficient for phase 1 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI1COEFF1: Horizontal Coefficient for phase 1 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI1COEFF2: Horizontal Coefficient for phase 1 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. * XPHI1COEFF3: Horizontal Coefficient for phase 1 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 741 32.7.115High End Overlay Layer Configuration 20 Register Name: LCDC_HEOCFG20 Address: 0xF00303DC Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 - - 4 3 XPHI1COEFF4 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * XPHI1COEFF4: Horizontal Coefficient for phase 1 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 742 32.7.116High End Overlay Layer Configuration 21 Register Name: LCDC_HEOCFG21 Address: 0xF00303E0 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI2COEFF3 20 19 XPHI2COEFF2 12 11 XPHI2COEFF1 4 3 XPHI2COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 * XPHI2COEFF0: Horizontal Coefficient for phase 2 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI2COEFF1: Horizontal Coefficient for phase 2 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI2COEFF2: Horizontal Coefficient for phase 2 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. * XPHI2COEFF3: Horizontal Coefficient for phase 2 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 743 32.7.117High End Overlay Layer Configuration 22 Register Name: LCDC_HEOCFG22 Address: 0xF00303E4 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 - - 4 3 XPHI2COEFF4 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * XPHI2COEFF4: Horizontal Coefficient for phase 2 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 744 32.7.118High End Overlay Layer Configuration 23 Register Name: LCDC_HEOCFG23 Address: 0xF00303E8 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI3COEFF3 20 19 XPHI3COEFF2 12 11 XPHI3COEFF1 4 3 XPHI3COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 * XPHI3COEFF0: Horizontal Coefficient for phase 3 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI3COEFF1: Horizontal Coefficient for phase 3 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI3COEFF2: Horizontal Coefficient for phase 3 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. * XPHI3COEFF3: Horizontal Coefficient for phase 3 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 745 32.7.119High End Overlay Layer Configuration 24 Register Name: LCDC_HEOCFG24 Address: 0xF00303EC Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 - - 4 3 XPHI3COEFF4 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * XPHI3COEFF4: Horizontal Coefficient for phase 3 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 746 32.7.120High End Overlay Layer Configuration 25 Register Name: LCDC_HEOCFG25 Address: 0xF00303F0 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI4COEFF3 20 19 XPHI4COEFF2 12 11 XPHI4COEFF1 4 3 XPHI4COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 * XPHI4COEFF0: Horizontal Coefficient for phase 4 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI4COEFF1: Horizontal Coefficient for phase 4 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI4COEFF2: Horizontal Coefficient for phase 4 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. * XPHI4COEFF3: Horizontal Coefficient for phase 4 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 747 32.7.121High End Overlay Layer Configuration 26 Register Name: LCDC_HEOCFG26 Address: 0xF00303F4 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 - - 4 3 XPHI4COEFF4 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * XPHI4COEFF4: Horizontal Coefficient for phase 4 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 748 32.7.122High End Overlay Layer Configuration 27 Register Name: LCDC_HEOCFG27 Address: 0xF00303F8 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI5COEFF3 20 19 XPHI5COEFF2 12 11 XPHI5COEFF1 4 3 XPHI5COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 * XPHI5COEFF0: Horizontal Coefficient for phase 5 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI5COEFF1: Horizontal Coefficient for phase 5 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI5COEFF2: Horizontal Coefficient for phase 5 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. * XPHI5COEFF3: Horizontal Coefficient for phase 5 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 749 32.7.123High End Overlay Layer Configuration 28 Register Name: LCDC_HEOCFG28 Address: 0xF00303FC Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 - - 4 3 XPHI5COEFF4 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * XPHI5COEFF4: Horizontal Coefficient for phase 5 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 750 32.7.124High End Overlay Layer Configuration 29 Register Name: LCDC_HEOCFG29 Address: 0xF0030400 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI6COEFF3 20 19 XPHI6COEFF2 12 11 XPHI6COEFF1 4 3 XPHI6COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 * XPHI6COEFF0: Horizontal Coefficient for phase 6 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI6COEFF1: Horizontal Coefficient for phase 6 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI6COEFF2: Horizontal Coefficient for phase 6 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. * XPHI6COEFF3: Horizontal Coefficient for phase 6 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 751 32.7.125High End Overlay Layer Configuration 30 Register Name: LCDC_HEOCFG30 Address: 0xF0030404 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 - - 4 3 XPHI6COEFF4 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * XPHI6COEFF4: Horizontal Coefficient for phase 6 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 752 32.7.126High End Overlay Layer Configuration 31 Register Name: LCDC_HEOCFG31 Address: 0xF0030408 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI7COEFF3 20 19 XPHI7COEFF2 12 11 XPHI7COEFF1 4 3 XPHI7COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 * XPHI7COEFF0: Horizontal Coefficient for phase 7 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI7COEFF1: Horizontal Coefficient for phase 7 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. * XPHI7COEFF2: Horizontal Coefficient for phase 7 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. * XPHI7COEFF3: Horizontal Coefficient for phase 7 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 753 32.7.127High End Overlay Layer Configuration 32 Register Name: LCDC_HEOCFG32 Address: 0xF003040C Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 - - 4 3 XPHI7COEFF4 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * XPHI7COEFF4: Horizontal Coefficient for phase 7 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 754 32.7.128High End Overlay Layer Configuration 33 Register Name: LCDC_HEOCFG33 Address: 0xF0030410 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 14 13 7 6 5 28 27 - - 20 19 YPHI0COEFF2 12 11 YPHI0COEFF1 4 3 YPHI0COEFF0 26 - 18 25 - 17 24 - 16 10 9 8 2 1 0 * YPHI0COEFF0: Vertical Coefficient for phase 0 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * YPHI0COEFF1: Vertical Coefficient for phase 0 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. * YPHI0COEFF2: Vertical Coefficient for phase 0 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 755 32.7.129High End Overlay Layer Configuration 34 Register Name: LCDC_HEOCFG34 Address: 0xF0030414 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 14 13 7 6 5 28 27 - - 20 19 YPHI1COEFF2 12 11 YPHI1COEFF1 4 3 YPHI1COEFF0 26 - 18 25 - 17 24 - 16 10 9 8 2 1 0 * YPHI1COEFF0: Vertical Coefficient for phase 1 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * YPHI1COEFF1: Vertical Coefficient for phase 1 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. * YPHI1COEFF2: Vertical Coefficient for phase 1 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 756 32.7.130High End Overlay Layer Configuration 35 Register Name: LCDC_HEOCFG35 Address: 0xF0030418 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 14 13 7 6 5 28 27 - - 20 19 YPHI2COEFF2 12 11 YPHI2COEFF1 4 3 YPHI2COEFF0 26 - 18 25 - 17 24 - 16 10 9 8 2 1 0 * YPHI2COEFF0: Vertical Coefficient for phase 2 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * YPHI2COEFF1: Vertical Coefficient for phase 2 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. * YPHI2COEFF2: Vertical Coefficient for phase 2 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 757 32.7.131High End Overlay Layer Configuration 36 Register Name: LCDC_HEOCFG36 Address: 0xF003041C Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 14 13 7 6 5 28 27 - - 20 19 YPHI3COEFF2 12 11 YPHI3COEFF1 4 3 YPHI3COEFF0 26 - 18 25 - 17 24 - 16 10 9 8 2 1 0 * YPHI3COEFF0: Vertical Coefficient for phase 3 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * YPHI3COEFF1: Vertical Coefficient for phase 3 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. * YPHI3COEFF2: Vertical Coefficient for phase 3 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 758 32.7.132High End Overlay Layer Configuration 37 Register Name: LCDC_HEOCFG37 Address: 0xF0030420 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 14 13 7 6 5 28 27 - - 20 19 YPHI4COEFF2 12 11 YPHI4COEFF1 4 3 YPHI4COEFF0 26 - 18 25 - 17 24 - 16 10 9 8 2 1 0 * YPHI4COEFF0: Vertical Coefficient for phase 4 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * YPHI4COEFF1: Vertical Coefficient for phase 4 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. * YPHI4COEFF2: Vertical Coefficient for phase 4 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 759 32.7.133High End Overlay Layer Configuration 38 Register Name: LCDC_HEOCFG38 Address: 0xF0030424 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 14 13 7 6 5 28 27 - - 20 19 YPHI5COEFF2 12 11 YPHI5COEFF1 4 3 YPHI5COEFF0 26 - 18 25 - 17 24 - 16 10 9 8 2 1 0 * YPHI5COEFF0: Vertical Coefficient for phase 5 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * YPHI5COEFF1: Vertical Coefficient for phase 5 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. * YPHI5COEFF2: Vertical Coefficient for phase 5 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 760 32.7.134High End Overlay Layer Configuration 39 Register Name: LCDC_HEOCFG39 Address: 0xF0030428 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 14 13 7 6 5 28 27 - - 20 19 YPHI6COEFF2 12 11 YPHI6COEFF1 4 3 YPHI6COEFF0 26 - 18 25 - 17 24 - 16 10 9 8 2 1 0 * YPHI6COEFF0: Vertical Coefficient for phase 6 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * YPHI6COEFF1: Vertical Coefficient for phase 6 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. * YPHI6COEFF2: Vertical Coefficient for phase 6 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 761 32.7.135High End Overlay Layer Configuration 40 Register Name: LCDC_HEOCFG40 Address: 0xF003042C Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 15 14 13 7 6 5 28 27 - - 20 19 YPHI7COEFF2 12 11 YPHI7COEFF1 4 3 YPHI7COEFF0 26 - 18 25 - 17 24 - 16 10 9 8 2 1 0 * YPHI7COEFF0: Vertical Coefficient for phase 7 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. * YPHI7COEFF1: Vertical Coefficient for phase 7 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. * YPHI7COEFF2: Vertical Coefficient for phase 7 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 762 32.7.136High End Overlay Layer Configuration 41 Register Name: LCDC_HEOCFG41 Address: 0xF0030430 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 10 - 2 25 - 17 YPHIDEF 9 - 1 XPHIDEF 24 - 16 8 - 0 * XPHIDEF: Horizontal Filter Phase Offset XPHIDEF defines the index of the first coefficient set used when the horizontal resampling operation is started. * YPHIDEF: Vertical Filter Phase Offset XPHIDEF defines the index of the first coefficient set used when the vertical resampling operation is started. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 763 32.7.137Hardware Cursor Layer Channel Enable Register Name: LCDC_HCRCHER Address: 0xF0030440 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QEN 25 - 17 - 9 - 1 UPDATEEN 24 - 16 - 8 - 0 CHEN * CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. * UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. * A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 764 32.7.138Hardware Cursor Layer Channel Disable Register Name: LCDC_HCRCHDR Address: 0xF0030444 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 CHRST 0 CHDIS * CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. * CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 765 32.7.139Hardware Cursor Layer Channel Status Register Name: LCDC_HCRCHSR Address: 0xF0030448 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QSR 25 - 17 - 9 - 1 UPDATESR 24 - 16 - 8 - 0 CHSR * CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. * UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. * A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 766 32.7.140Hardware Cursor Layer Interrupt Enable Register Name: LCDC_HCRIER Address: 0xF003044C Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 767 32.7.141Hardware Cursor Layer Interrupt Disable Register Name: LCDC_HCRIDR Address: 0xF0030450 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 768 32.7.142Hardware Cursor Layer Interrupt Mask Register Name: LCDC_HCRIMR Address: 0xF0030454 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 769 32.7.143Hardware Cursor Layer Interrupt Status Register Name: LCDC_HCRISR Address: 0xF0030458 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 OVR 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. * DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. * ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. * DONE: End of List Detected When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. * OVR: Overflow Detected When set to one this flag indicates that an Overflow has occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 770 32.7.144Hardware Cursor Layer Head Register Name: LCDC_HCRHEAD Address: 0xF003045C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD * HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 771 32.7.145Hardware Cursor Layer Address Register Name: LCDC_HCRADDR Address: 0xF0030460 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR * ADDR: DMA Transfer start address Frame buffer start address. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 772 32.7.146Hardware Cursor Layer Control Register Name: LCDC_HCRCTRL Address: 0xF0030464 Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONEIEN 28 - 20 - 12 - 4 ADDIEN 27 - 19 - 11 - 3 DSCRIEN 26 - 18 - 10 - 2 DMAIEN 25 - 17 - 9 - 1 LFETCH 24 - 16 - 8 - 0 DFETCH * DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. * LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. * DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. * DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. * ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. * DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 773 32.7.147Hardware Cursor Layer Next Register Name: LCDC_HCRNEXT Address: 0xF0030468 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT * NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 774 32.7.148Hardware Cursor Layer Configuration 0 Register Name: LCDC_HCRCFG0 Address: 0xF003046C Access: Read-write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 28 - 20 - 12 - 4 BLEN 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 DLBO 0 SIF * SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. * BLEN: AHB Burst Length Value Name Description 0 AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. AHB_BLEN_INCR16 An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. * DLBO: Defined Length Burst Only for Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 775 32.7.149Hardware Cursor Layer Configuration 1 Register Name: LCDC_HCRCFG1 Address: 0xF0030470 Access: Read-write Reset: 0x00000000 31 - 23 - 15 30 - 22 - 14 7 6 29 - 21 - 13 28 - 20 - 12 5 4 - RGBMODE 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 24 - 16 - 8 CLUTMODE 1 - 0 CLUTEN * CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color Lookup table is selected. * RGBMODE: RGB input mode selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 * CLUTMODE: Color Lookup table input mode selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 776 32.7.150Hardware Cursor Layer Configuration 2 Register Name: LCDC_HCRCFG2 Address: 0xF0030474 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XPOS * XPOS: Horizontal Window Position Hardware Cursor Horizontal window position. * YPOS: Vertical Window Position Hardware Cursor Vertical window position. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 777 32.7.151Hardware Cursor Layer Configuration 3 Register Name: LCDC_HCRCFG3 Address: 0xF0030478 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 11 - 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 - 7 14 - 6 13 - 5 12 - 4 2 0 XSIZE * XSIZE: Horizontal Window Size Hardware cursor width is limited to 128 pixels Hardware Cursor window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE PPL * YSIZE: Vertical Window Size Hardware cursor height is limited to 128 pixels Hardware Cursor window height in pixels. The window height is set to (YSIZE+1). The following constrain must be met: YPOS + YSIZE RPF SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 778 32.7.152Hardware Cursor Layer Configuration 4 Register Name: LCDC_HCRCFG4 Address: 0xF003047C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE * XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 779 32.7.153Hardware Cursor Layer Configuration 6 Register Name: LCDC_HCRCFG6 Address: 0xF0030484 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF * RDEF: Red Default Default Red color when the Hardware Cursor DMA channel is disabled. * GDEF: Green Default Default Green color when the Hardware Cursor DMA channel is disabled. * BDEF: Blue Default * Default Blue color when the Hardware Cursor DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 780 32.7.154Hardware Cursor Layer Configuration 7 Register Name: LCDC_HCRCFG7 Address: 0xF0030488 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY * RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay. * GKEY: Green Color Component Chroma Key Reference Green chroma key used to match the Green color of the current overlay. * BKEY: Blue Color Component Chroma Key Reference Blue chroma key used to match the Blue color of the current overlay. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 781 32.7.155Hardware Cursor Layer Configuration 8 Register Name: LCDC_HCRCFG8 Address: 0xF003048C Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK * RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared. * GMASK: Green Color Component Chroma Key Mask Green Mask used when the compare function is used. If a bit is set then this bit is compared. * BMASK: Blue Color Component Chroma Key Mask Blue Mask used when the compare function is used. If a bit is set then this bit is compared. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 782 32.7.156Hardware Cursor Layer Configuration 9 Register Name: LCDC_HCRCFG9 Address: 0xF0030490 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 - 7 OVR 14 - 6 LAEN 13 - 5 GAEN 12 - 4 REVALPHA 27 - 19 26 - 18 25 - 17 24 - 16 11 - 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA * CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled. * INV: Blender Inverted Blender Output Enable 0: Iterated pixel is the blended pixel. 1: Iterated pixel is the inverted pixel. * ITER2BL: Blender Iterated Color Enable 0: Final adder stage operand is set to 0. 1: Final adder stage operand is set to the iterated pixel value. * ITER: Blender Use Iterated Color 0: Pixel difference is set to 0. 1: Pixel difference is set to the iterated pixel value. * REVALPHA: Blender Reverse Alpha 0: Pixel difference is multiplied by alpha. 1: Pixel difference is multiplied by 1 - alpha. * GAEN: Blender Global Alpha Enable 0: Global alpha blending coefficient is disabled. 1: Global alpha blending coefficient is enabled. * LAEN: Blender Local Alpha Enable 0: Local alpha blending coefficient is disabled. 1: Local alpha blending coefficient is enabled. * OVR: Blender Overlay Layer Enable 0: Overlay pixel color is set to the default overlay pixel color. 1: Overlay pixel color is set to the DMA channel pixel color. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 783 * DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. * REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. * DSTKEY: Destination Chroma Keying 0: Source Chroma keying is enabled. 1: Destination Chroma keying is used. * GA: Blender Global Alpha Global alpha blender for the current layer. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 784 32.7.157Post Processing Layer Channel Enable Register Name: LCDC_PPCHER Address: 0xF0030540 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QEN 25 - 17 - 9 - 1 UPDATEEN 24 - 16 - 8 - 0 CHEN * CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. * UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. * A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 785 32.7.158Post Processing Layer Channel Disable Register Name: LCDC_PPCHDR Address: 0xF0030544 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 CHRST 0 CHDIS * CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. * CHRST: Channel Reset Register When set to one this field disables the layer at the end of the current frame. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 786 32.7.159Post Processing Layer Channel Status Register Name: LCDC_PPCHSR Address: 0xF0030548 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 A2QSR 25 - 17 - 9 - 1 UPDATESR 24 - 16 - 8 - 0 CHSR * CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. * UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will update on the next Frame. * A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 787 32.7.160Post Processing Layer Interrupt Enable Register Name: LCDC_PPIER Address: 0xF003054C Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. * DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 788 32.7.161Post Processing Layer Interrupt Disable Register Name: LCDC_PPIDR Address: 0xF0030550 Access: Write-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. * DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 789 32.7.162Post Processing Layer Interrupt Mask Register Name: LCDC_PPIMR Address: 0xF0030554 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. * DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 790 32.7.163Post Processing Layer Interrupt Status Register Name: LCDC_PPISR Address: 0xF0030558 Access: Read-only Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONE 28 - 20 - 12 - 4 ADD 27 - 19 - 11 - 3 DSCR 26 - 18 - 10 - 2 DMA 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - * DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. * DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. * ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. * DONE: End Of List Detected When set to one this flag indicates that a End of List condition has occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 791 32.7.164Post Processing Layer Head Register Name: LCDC_PPHEAD Address: 0xF003055C Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD * HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 792 32.7.165Post Processing Layer Address Register Name: LCDC_PPADDR Address: 0xF0030560 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR * ADDR: DMA Transfer start address Post Processing Destination frame buffer address. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 793 32.7.166Post Processing Layer Control Register Name: LCDC_PPCTRL Address: 0xF0030564 Access: Read-Write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 DONEIEN 28 - 20 - 12 - 4 ADDIEN 27 - 19 - 11 - 3 DSCRIEN 26 - 18 - 10 - 2 DMAIEN 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 DFETCH * DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. * DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. * DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. * ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. * DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 794 32.7.167Post Processing Layer Next Register Name: LCDC_PPNEXT Address: 0xF0030568 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT * NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 795 32.7.168Post Processing Layer Configuration 0 Register Name: LCDC_PPCFG0 Address: 0xF003056C Access: Read-Write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 28 - 20 - 12 - 4 BLEN 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 DLBO 0 SIF * SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. * BLEN: AHB Burst Length Value Name Description 0 AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. AHB_BLEN_INCR16 An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. * DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for 2 and 3 beats burst. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 796 32.7.169Post Processing Layer Configuration 1 Register Name: LCDC_PPCFG1 Address: 0xF0030570 Access: Read-Write Reset: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 ITUBT601 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 PPMODE 24 - 16 - 8 - 0 * PPMODE: Post Processing Output Format selection Table 32-55. PPMODE selection Value Name Description 0 PPMODE_RGB_16BPP RGB 16 bpp 1 PPMODE_RGB_24BPP_PACKED RGB 24 bpp PACKED 2 PPMODE_RGB_24BPP_UNPACKED RGB 24 bpp UNPACKED 3 PPMODE_YCBCR_422_MODE0 YCbCr 422 16 bpp (Mode 0) 4 PPMODE_YCBCR_422_MODE1 YCbCr 422 16 bpp (Mode 1) 5 PPMODE_YCBCR_422_MODE2 YCbCr 422 16 bpp (Mode 2) 6 PPMODE_YCBCR_422_MODE3 YCbCr 422 16 bpp (Mode 3) * ITUBT601: Color Space Conversion Luminance 0: Luminance and chrominance range is [0;255] 1: Luminance values are clamped to [16;235] range. Chrominance values are clamped to [16;240] range. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 797 32.7.170Post Processing Layer Configuration 2 Register Name: LCDC_PPCFG2 Address: 0xF0030574 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE * XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 798 32.7.171Post Processing Layer Configuration 3 Register Name: LCDC_PPCFG3 Address: 0xF0030578 Access: Read-Write Reset: 0x00000000 31 - 23 15 30 CSCYOFF 22 CSCYB 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCYB 18 CSCYG 13 12 11 10 9 4 3 2 1 CSCYG 7 6 5 CSCYR 0 CSCYR * CSCYR: Color Space Conversion R coefficient for Luminance component, signed format, step set to 1/1024 Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCYG: Color Space Conversion G coefficient for Luminance component, signed format, step set to 1/512 Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCYB: Color Space Conversion B coefficient for Luminance component, signed format, step set to 1/1024 Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCYOFF: Color Space Conversion Luminance Offset 0: The Yoff parameter value is set to 0. 1: The Yoff parameter value is set to 16. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 799 32.7.172Post Processing Layer Configuration 4 Register Name: LCDC_PPCFG4 Address: 0xF003057C Access: Read-Write Reset: 0x00000000 31 - 23 15 30 CSCUOFF 22 CSCUB 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCUB 18 CSCUG 13 12 11 10 9 4 3 2 1 CSCUG 7 6 5 CSCUR 0 CSCUR * CSCUR: Color Space Conversion R coefficient for Chrominance B component, signed format. (step 1/1024) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCUG: Color Space Conversion G coefficient for Chrominance B component, signed format. (step 1/512) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCUB: Color Space Conversion B coefficient for Chrominance B component, signed format. (step 1/512) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCUOFF: Color Space Conversion Chrominance B Offset 0: The Cboff parameter value is set to 0. 1: The Cboff parameter value is set to 128. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 800 32.7.173Post Processing Layer Configuration 5 Register Name: LCDC_PPCFG5 Address: 0xF0030580 Access: Read-Write Reset: 0x00000000 31 - 23 15 30 CSCVOFF 22 CSCVB 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCVB 18 CSCVG 13 12 11 10 9 4 3 2 1 CSCVG 7 6 5 CSCVR 0 CSCVR * CSCVR: Color Space Conversion R coefficient for Chrominance R component, signed format. (step 1/1024) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCVG: Color Space Conversion G coefficient for Chrominance R component, signed format. (step 1/512) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCVB: Color Space Conversion B coefficient for Chrominance R component, signed format. (step 1/1024) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. * CSCVOFF: Color Space Conversion Chrominance R Offset 0: The Croff parameter value is set to 0. 1: The Croff parameter value is set to 128. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 801 32.7.174Base CLUT Register x Register Name: LCDC_BASECLUTx [x=0..255] Address: 0xF0030600 Access: Read-write Reset: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 15 14 13 12 7 6 5 4 27 - 19 26 - 18 25 - 17 24 - 16 11 10 9 8 3 2 1 0 RCLUT GCLUT BCLUT * BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. * GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. * RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 802 32.7.175Overlay 1 CLUT Register x Register Name: LCDC_OVR1CLUTx [x=0..255] Address: 0xF0030A00 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT * BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. * GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. * RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. * ACLUT: Alpha Color entry This field indicates the 8-bit width Alpha channel of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 803 32.7.176Overlay 2 CLUT Register x Register Name: LCDC_OVR2CLUTx [x=0..255] Address: 0xF0030E00 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT * BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. * GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. * RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. * ACLUT: Alpha Color entry This field indicates the 8-bit width Alpha channel of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 804 32.7.177High End Overlay CLUT Register x Register Name: LCDC_HEOCLUTx [x=0..255] Address: 0xF0031200 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT * BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. * GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. * RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. * ACLUT: Alpha Color entry This field indicates the 8-bit width Alpha channel of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 805 32.7.178Hardware Cursor CLUT Register x Register Name: LCDC_HCRCLUTx [x=0..255] Address: 0xF0031600 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT * BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. * GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. * RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. * ACLUT: Alpha Color entry This field indicates the 8-bit width Alpha channel of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 806 33. Image Sensor Interface (ISI) 33.1 Description The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller. Internal FIFOs on the preview and codec paths are used to store the incoming data. The RGB output on the preview path is compatible with the LCD controller. This module outputs the data in RGB format (LCD compatible) and has scaling capabilities to make it compliant to the LCD display resolution (See Table 33-3 on page 810). Several input formats such as preprocessed RGB or YCbCr are supported through the data bus interface. It supports two modes of synchronization: The hardware with ISI_VSYNC and ISI_HSYNC signals The International Telecommunication Union Recommendation ITU-R BT.656-4 Start-of-Active-Video (SAV) and End-of-Active-Video (EAV) synchronization sequence. Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used). The polarity of the synchronization pulse is programmable to comply with the sensor signals. Table 33-1. I/O Description Signal Direction Description ISI_VSYNC IN Vertical Synchronization ISI_HSYNC IN Horizontal Synchronization ISI_DATA[11..0] IN Sensor Pixel Data ISI_MCK OUT ISI_PCK IN Master Clock Provided to the Image Sensor Pixel Clock Provided by the Image Sensor Figure 33-1. ISI Connection Example Image Sensor Image Sensor Interface data[11..0] 33.2 ISI_DATA[11..0] CLK ISI_MCK PCLK ISI_PCK VSYNC ISI_VSYNC HSYNC ISI_HSYNC Embedded Characteristics ITU-R BT. 601/656 8-bit Mode External Interface Support Supports up to 12-bit Grayscale CMOS Sensors Support for ITU-R BT.656-4 SAV and EAV Synchronization Vertical and Horizontal Resolutions up to 2048*2048 Preview Path SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 807 33.3 Up to 2048*2048 in Grayscale Mode Up to 640*480 in RGB Mode 32 Bytes FIFO on Codec Path 32 Bytes FIFO on Preview Path Support for Packed Data Formatting for YCbCr 4:2:2 Formats Preview Scaler to Generate Smaller Size image Programmable Frame Capture Rate VGA, QVGA, CIF, QCIF Formats Supported for LCD Preview Custom Formats with Horizontal and Vertical Preview Size as Multiples of 16 Also Supported for LCD Preview Block Diagram Timing Signals Interface CCIR-656 Embedded Timing Decoder(SAV/EAV) CMOS sensor Pixel input up to 12 bit YCbCr 4:2:2 8:8:8 RGB 5:6:5 CMOS sensor pixel clock input 33.4 Config Registers Camera Interrupt Controller Camera Interrupt Request Line From Rx buffers Pixel Clock Domain Preview path Frame Rate Clipping + Color Conversion YCC to RGB Pixel Sampling Module Clipping + Color Conversion RGB to YCC codec_on 2-D Image Scaler Pixel Formatter Packed Formatter APB Interface APB Clock Domain AHB Clock Domain Rx Direct Display FIFO Rx Direct Capture FIFO Core Video Arbiter Camera AHB Master Interface Scatter Mode Support AHB bus Hsync/Len Vsync/Fen APB bus Figure 33-2. Image Sensor Interface Block Diagram Codec path Functional Description The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream. The Image Sensor Interface interrupt line is connected to the Advanced Interrupt Controller and can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event. For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. When the preview DMA channel is configured and enabled, the preview path is activated and an `RGB frame' is moved to memory. The preview path frame rate is configured with the FRATE field of the ISI_CFG1 register. When the codec DMA channel is configured and enabled, the codec path is activated and a `YCbCr 4:2:2 frame' is captured as soon as the ISI_CDC bit of the ISI Control Register (ISI_CR) is set. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 808 When the FULL bit of the ISI_CFG1 register is set, both preview DMA channel and codec DMA channel can operate simultaneously. When a zero is written to the FULL bit of the ISI_CFG1 register, a hardware scheduler checks the FRATE field. If its value is zero, a preview frame is skipped and a codec frame is moved to memory instead. If its value is other than zero, at least one free frame slot is available. The scheduler postpones the codec frame to that free available frame slot. The data stream may be sent on both preview path and codec path if the value of bit ISI_CDC in the ISI_CR is one. To optimize the bandwidth, the codec path should be enabled only when a capture is required. In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CFG2 register. The codec datapath is not available when grayscale image is selected. A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames. 33.4.1 Data Timing The two data timings using horizontal and vertical synchronization and EAV/SAV sequence synchronization are shown in Figure 33-3 and Figure 33-4. In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the ISI_CR . The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface. There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one at the end of each video data block EAV(0xFF00009D). Only data sent between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. Figure 33-3. HSYNC and VSYNC Synchronization Frame ISI_VSYNC 1 line ISI_HSYNC ISI_PCK DATA[7..0] Y Cb Y Cr Y Cb Y Cr Y Cb Y Y Cr Cr Figure 33-4. SAV and EAV Sequence Synchronization ISII_PCK DATA[7..0] FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cb FF 00 00 EAV 9D 33.4.2 Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 809 All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table 33-2. Data Ordering in YCbCr Mode Mode Byte 0 Byte 1 Byte 2 Byte 3 Default Cb(i) Y(i) Cr(i) Y(i+1) Mode 1 Cr(i) Y(i) Cb(i) Y(i+1) Mode 2 Y(i) Cb(i) Y(i+1) Cr(i) Mode 3 Y(i) Cr(i) Y(i+1) Cb(i) Table 33-3. RGB Format in Default Mode, RGB_CFG = 00, No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 R7(i) R6(i) R5(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 G7(i) G6(i) G5(i) G4(i) G3(i) G2(i) G1(i) G0(i) Byte 2 B7(i) B6(i) B5(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 3 R7(i+1) R6(i+1) R5(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) Byte 0 R4(i) R3(i) R2(i) R1(i) R0(i) G5(i) G4(i) G3(i) Byte 1 G2(i) G1(i) G0(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 2 R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) G5(i+1) G4(i+1) G3(i+1) Byte 3 G2(i+1) G1(i+1) G0(i+1) B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) RGB 8:8:8 RGB 5:6:5 Table 33-4. RGB Format, RGB_CFG = 10 (Mode 2), No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 G2(i) G1(i) G0(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 B4(i) B3(i) B2(i) B1(i) B0(i) G5(i) G4(i) G3(i) Byte 2 G2(i+1) G1(i+1) G0(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) Byte 3 B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) G5(i+1) G4(i+1) G3(i+1) RGB 5:6:5 Table 33-5. RGB Format in Default Mode, RGB_CFG = 00, Swap Activated Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 R0(i) R1(i) R2(i) R3(i) R4(i) R5(i) R6(i) R7(i) Byte 1 G0(i) G1(i) G2(i) G3(i) G4(i) G5(i) G6(i) G7(i) Byte 2 B0(i) B1(i) B2(i) B3(i) B4(i) B5(i) B6(i) B7(i) Byte 3 R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1) R5(i+1) R6(i+1) R7(i+1) Byte 0 G3(i) G4(i) G5(i) R0(i) R1(i) R2(i) R3(i) R4(i) Byte 1 B0(i) B1(i) B2(i) B3(i) B4(i) G0(i) G1(i) G2(i) Byte 2 G3(i+1) G4(i+1) G5(i+1) R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1) Byte 3 B0(i+1) B1(i+1) B2(i+1) B3(i+1) B4(i+1) G0(i+1) G1(i+1) G2(i+1) RGB 8:8:8 RGB 5:6:5 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 810 The RGB 5:6:5 input format is processed to be displayed as RGB 5:6:5 format, compliant with the 16-bit mode of the LCD controller. 33.4.3 Clocks The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Management Controller (APMC) through a Programmable Clock output or by an external oscillator connected to the sensor. None of the sensors embed a power management controller, so providing the clock by the APMC is a simple and efficient way to control power consumption of the system. Care must be taken when programming the system clock. The ISI has two clock domains, the sensor master clock and the pixel clock provided by sensor. The two clock domains are not synchronized, but the sensor master clock must be faster than the pixel clock. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 811 33.4.4 Preview Path 33.4.4.1 Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16; values 0 to 15 are forbidden. Table 33-6. Decimation Factor Decimation Value 0-15 16 17 18 19 ... 124 125 126 127 Decimation Factor -- 1 1.063 1.125 1.188 ... 7.750 7.813 7.875 7.938 Table 33-7. Decimation and Scaler Offset Values OUTPUT VGA 640*480 QVGA 320*240 CIF 352*288 QCIF 176*144 INPUT 352*288 640*480 800*600 1280*1024 1600*1200 2048*1536 F -- 16 20 32 40 51 F 16 32 40 64 80 102 F 16 26 33 56 66 85 F 32 53 66 113 133 170 Example: Input 1280*1024 Output = 640*480 Hratio = 1280/640 = 2 Vratio = 1024/480 = 2.1333 The decimation factor is 2 so 32/16. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 812 Figure 33-5. Resize Examples 32/16 decimation 1280 640 1024 480 1280 56/16 decimation 352 1024 288 33.4.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: C0 0 C1 Y - Y off R G = C 0 - C 2 - C 3 x C b - C boff B C0 C4 0 C r - C roff Example of programmable value to convert YCrCb to RGB: R = 1,164 ( Y - 16 ) + 1,596 ( C r - 128 ) G = 1,164 ( Y - 16 ) - 0,813 ( C r - 128 ) - 0,392 ( C b - 128 ) B = 1,164 ( Y - 16 ) + 2,107 ( C b - 128 ) An example of programmable value to convert from YUV to RGB: R = Y + 1,596 V G = Y - 0,394 U - 0,436 V B = Y + 2,032 U SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 813 33.4.4.3 Memory Interface Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the green channel. When grayscale mode is enabled, two memory formats are supported. One mode supports two pixels per word, and the other mode supports one pixel per word. Table 33-8. Grayscale Memory Mapping Configuration for 12-bit Data GS_MODE DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] 0 P_0[11:4] P_0[3:0], 0000 P_1[11:4] P_1[3:0], 0000 1 P_0[11:4] P_0[3:0], 0000 0 0 33.4.4.4 FIFO and DMA Features Both preview and Codec datapaths contain FIFOs. These asynchronous buffers are used to safely transfer formatted pixels from the pixel clock domain to the AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB master interface. Thus, depending on the FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a series of three words. The first one defines the current frame buffer address (named DMA_X_ADDR register), the second defines control information (named DMA_X_CTRL register) and the third defines the next descriptor address (named DMA_X_DSCR). DMA transfer mode with linked list support is available for both codec and preview datapath. The data to be transferred described by an FBD requires several burst accesses. In the following example, the use of two ping-pong frame buffers is described. Example The first FBD, stored at address 0x00030000, defines the location of the first frame buffer. This address is programmed in the ISI user interface DMA_P_DSCR. To enable the descriptor fetch operation, the value 0x00000001 must be written to the DMA_P_CTRL register. LLI_0 and LLI_1 are the two descriptors of the linked list. Destination address: frame buffer ID0 0x02A000 (LLI_0.DMA_P_ADDR) Transfer 0 Control Information, fetch and writeback: 0x00000003 (LLI_0.DMA_P_CTRL) Next FBD address: 0x00030010 (LLI_0.DMA_P_DSCR) Second FBD, stored at address 0x00030010, defines the location of the second frame buffer. Destination address: frame buffer ID1 0x0003A000 (LLI_1.DMA_P_ADDR Transfer 1 Control information fetch and writeback: 0x00000003 (LLI_1.DMA_P_CTRL) Next FBD address: 0x00030000, wrapping to first FBD (LLI_1.DMA_P_DSCR) Using this technique, several frame buffers can be configured through the linked list. Figure 33-6 illustrates a typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 814 Figure 33-6. Three Frame Buffers Application and Memory Mapping Codec Done Codec Request frame n-1 frame n frame n+1 frame n+2 frame n+3 frame n+4 Memory Space Frame Buffer 3 Frame Buffer 0 LCD Frame Buffer 1 ISI config Space 4:2:2 Image Full ROI 33.4.5 Codec Path 33.4.5.1 Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: Y Cr = C0 C1 C2 Cb -C6 -C7 C8 C3 -C4 -C5 Y off R x G + Cr off B Cb off An example of coefficients is given below: Y = 0,257 R + 0,504 G + 0,098 B + 16 C = 0,439 R - 0,368 G - 0,071 B + 128 r C b = - 0,148 R - 0,291 G + 0,439 B + 128 33.4.5.2 Memory Interface Dedicated FIFOs are used to support packed memory mapping. YCrCb pixel components are sent in a single 32-bit word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not supported. 33.4.5.3 DMA Features Like preview datapath, codec datapath DMA mode uses linked list operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 815 33.5 Image Sensor Interface (ISI) User Interface Table 33-9. Register Mapping Offset Register Name Access Reset Value 0x00 ISI Configuration 1 Register ISI_CFG1 Read-write 0x00000000 0x04 ISI Configuration 2 Register ISI_CFG2 Read-write 0x00000000 0x08 ISI Preview Size Register ISI_PSIZE Read-write 0x00000000 0x0C ISI Preview Decimation Factor Register ISI_PDECF Read-write 0x00000010 0x10 ISI Color Space Conversion YCrCb To RGB Set 0 Register ISI_Y2R_SET0 Read-write 0x6832CC95 0x14 ISI Color Space Conversion YCrCb To RGB Set 1 Register ISI_Y2R_SET1 Read-write 0x00007102 0x18 ISI Color Space Conversion RGB To YCrCb Set 0 Register ISI_R2Y_SET0 Read-write 0x01324145 0x1C ISI Color Space Conversion RGB To YCrCb Set 1 Register ISI_R2Y_SET1 Read-write 0x01245E38 0x20 ISI Color Space Conversion RGB To YCrCb Set 2 Register ISI_R2Y_SET2 Read-write 0x01384A4B 0x24 ISI Control Register ISI_CR Write-only 0x00000000 0x28 ISI Status Register ISI_SR Read-only 0x00000000 0x2C ISI Interrupt Enable Register ISI_IER Write-only 0x00000000 0x30 ISI Interrupt Disable Register ISI_IDR Write-only 0x00000000 0x34 ISI Interrupt Mask Register ISI_IMR Read-only 0x00000000 0x38 DMA Channel Enable Register ISI_DMA_CHER Write-only 0x00000000 0x3C DMA Channel Disable Register ISI_DMA_CHDR Write-only 0x00000000 0x40 DMA Channel Status Register ISI_DMA_CHSR Read-only 0x00000000 0x44 DMA Preview Base Address Register ISI_DMA_P_ADDR Read-write 0x00000000 0x48 DMA Preview Control Register ISI_DMA_P_CTRL Read-write 0x00000000 0x4C DMA Preview Descriptor Address Register ISI_DMA_P_DSCR Read-write 0x00000000 0x50 DMA Codec Base Address Register ISI_DMA_C_ADDR Read-write 0x00000000 0x54 DMA Codec Control Register ISI_DMA_C_CTRL Read-write 0x00000000 0x58 DMA Codec Descriptor Address Register ISI_DMA_C_DSCR Read-write 0x00000000 0x5C-0xE0 Reserved - - - 0xE4 Write Protection Control Register ISI_WPCR Read-write 0x00000000 0xE8 Write Protection Status Register ISI_WPSR Read-only 0x00000000 0xEC-0xF8 Reserved - - - 0xFC Reserved - - - Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 816 33.5.1 ISI Configuration 1 Register Name: ISI_CFG1 Address: 0xF0034000 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 SFD 23 22 21 20 SLD 15 - 14 7 CRC_SYNC 6 EMB_SYNC 13 12 FULL 11 DISCR 10 9 FRATE 8 5 - 4 PIXCLK_POL 3 VSYNC_POL 2 HSYNC_POL 1 - 0 - THMASK * HSYNC_POL: Horizontal Synchronization Polarity 0: HSYNC active high 1: HSYNC active low * VSYNC_POL: Vertical Synchronization Polarity 0: VSYNC active high 1: VSYNC active low * PIXCLK_POL: Pixel Clock Polarity 0: Data is sampled on rising edge of pixel clock. 1: Data is sampled on falling edge of pixel clock. * EMB_SYNC: Embedded Synchronization 0: Synchronization by HSYNC, VSYNC 1: Synchronization by embedded synchronization sequence SAV/EAV * CRC_SYNC: Embedded Synchronization Correction 0: No CRC correction is performed on embedded synchronization. 1: CRC correction is performed. If the correction is not possible, the current frame is discarded and the CRC_ERR bit is set in the status register. * FRATE: Frame Rate [0..7] 0: All the frames are captured, else one frame every FRATE + 1 is captured. * DISCR: Disable Codec Request 0: Codec datapath DMA interface requires a request to restart. 1: Codec datapath DMA automatically restarts. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 817 * FULL: Full Mode is Allowed 0: The codec frame is transferred to memory when an available frame slot is detected. 1: Both preview and codec DMA channels are operating simultaneously. * THMASK: Threshold Mask Value Name Description 0 BEATS_4 Only 4 beats AHB burst allowed 1 BEATS_8 Only 4 and 8 beats AHB burst allowed 2 BEATS_16 4, 8 and 16 beats AHB burst allowed * SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. * SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 818 33.5.2 ISI Configuration 2 Register Name: ISI_CFG2 Address: 0xF0034004 Access: Read-write Reset: 0x00000000 31 30 29 RGB_CFG 23 28 YCC_SWAP 22 21 20 27 - 26 25 IM_HSIZE 24 19 18 17 16 IM_HSIZE 15 COL_SPACE 14 RGB_SWAP 13 GRAYSCALE 12 RGB_MODE 11 GS_MODE 10 9 IM_VSIZE 8 7 6 5 4 3 2 1 0 IM_VSIZE * IM_VSIZE: Vertical Size of the Image Sensor [0..2047] Vertical size = IM_VSIZE + 1 * GS_MODE: Grayscale Pixel Format Mode 0: 2 pixels per word 1: 1 pixel per word * RGB_MODE: RGB Input Mode 0: RGB 8:8:8 24 bits 1: RGB 5:6:5 16 bits * GRAYSCALE: Grayscale Mode Format Enable 0: Grayscale mode is disabled. 1: Input image is assumed to be grayscale coded. * RGB_SWAP: RGB Format Swap Mode 0: D7 -> R7 1: D0 -> R7 The RGB_SWAP has no effect when the grayscale mode is enabled. * COL_SPACE: Color Space for the Image Data 0: YCbCr 1: RGB * IM_HSIZE: Horizontal Size of the Image Sensor [0..2047] Horizontal size = IM_HSIZE + 1 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 819 * YCC_SWAP: YCrCb Format Swap Mode Defines the YCC image data Value Name Description Byte 0 Cb(i) 0 DEFAULT Byte 1 Y(i) Byte 2 Cr(i) Byte 3 Y(i+1) Byte 0 Cr(i) 1 MODE1 Byte 1 Y(i) Byte 2 Cb(i) Byte 3 Y(i+1) Byte 0 Y(i) 2 MODE2 Byte 1 Cb(i) Byte 2 Y(i+1) Byte 3 Cr(i) Byte 0 Y(i) 3 MODE3 Byte 1 Cr(i) Byte 2 Y(i+1) Byte 3 Cb(i) * RGB_CFG: RGB Pixel Mapping Configuration Defines RGB pattern when RGB_MODE is set to 1 Value Name Description Byte 0 R/G(MSB) 0 DEFAULT Byte 1 G(LSB)/B Byte 2 R/G(MSB) Byte 3 G(LSB)/B Byte 0 B/G(MSB) 1 MODE1 Byte 1 G(LSB)/R Byte 2 B/G(MSB) Byte 3 G(LSB)/R Byte 0 G(LSB)/R 2 MODE2 Byte 1 B/G(MSB) Byte 2 G(LSB)/R Byte 3 B/G(MSB) Byte 0 G(LSB)/B 3 MODE3 Byte 1 R/G(MSB) Byte 2 G(LSB)/B Byte 3 R/G(MSB) If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 820 33.5.3 ISI Preview Size Register Name: ISI_PSIZE Address: 0xF0034008 Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 19 18 17 11 - 10 - 9 3 2 1 24 PREV_HSIZE 16 PREV_HSIZE 15 - 14 - 13 - 12 - 7 6 5 4 8 PREV_VSIZE 0 PREV_VSIZE * PREV_VSIZE: Vertical Size for the Preview Path Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode) * PREV_HSIZE: Horizontal Size for the Preview Path Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 821 33.5.4 ISI Preview Decimation Factor Register Name: ISI_PDECF Address: 0xF003400C Access: Read-write Reset: 0x00000010 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 DEC_FACTOR * DEC_FACTOR: Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 822 33.5.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register Name: ISI_Y2R_SET0 Address: 0xF0034010 Access: Read-write Reset: 0x6832CC95 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 C3 23 22 21 20 C2 15 14 13 12 C1 7 6 5 4 C0 * C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/128, ranges from 0 to 1.9921875. * C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, ranges from 0 to 1.9921875. * C2: Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/128, ranges from 0 to 1.9921875. * C3: Color Space Conversion Matrix Coefficient C3 C3 element default step is 1/128, ranges from 0 to 1.9921875. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 823 33.5.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register Name: ISI_Y2R_SET1 Address: 0xF0034014 Access: Read-write Reset: 0x00007102 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 Cboff 13 Croff 12 Yoff 11 - 10 - 9 - 8 C4 7 6 5 4 3 2 1 0 C4 * C4: Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. * Yoff: Color Space Conversion Luminance Default Offset 0: No offset 1: Offset = 128 * Croff: Color Space Conversion Red Chrominance Default Offset 0: No offset 1: Offset = 16 * Cboff: Color Space Conversion Blue Chrominance Default Offset 0: No offset 1: Offset = 16 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 824 33.5.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register Name: ISI_R2Y_SET0 Address: 0xF0034018 Access: Read-write Reset: 0x01324145 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 Roff 23 - 22 21 20 19 C2 18 17 16 15 - 14 13 12 11 C1 10 9 8 7 - 6 5 4 3 C0 2 1 0 * C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. * C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875. * C2: Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/512, from 0 to 0.2480468875. * Roff: Color Space Conversion Red Component Offset 0: No offset 1: Offset = 16 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 825 33.5.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register Name: ISI_R2Y_SET1 Address: 0xF003401C Access: Read-write Reset: 0x01245E38 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 Goff 23 - 22 21 20 19 C5 18 17 16 15 - 14 13 12 11 C4 10 9 8 7 - 6 5 4 3 C3 2 1 0 * C3: Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875. * C4: Color Space Conversion Matrix Coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375. * C5: Color Space Conversion Matrix Coefficient C5 C1 element default step is 1/512, ranges from 0 to 0.2480468875. * Goff: Color Space Conversion Green Component Offset 0: No offset 1: Offset = 128 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 826 33.5.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register Name: ISI_R2Y_SET2 Address: 0xF0034020 Access: Read-write Reset: 0x01384A4B 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 Boff 23 - 22 21 20 19 C8 18 17 16 15 - 14 13 12 11 C7 10 9 8 7 - 6 5 4 3 C6 2 1 0 * C6: Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875. * C7: Color Space Conversion Matrix Coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375. * C8: Color Space Conversion Matrix Coefficient C8 C8 element default step is 1/128, ranges from 0 to 0.9921875. * Boff: Color Space Conversion Blue Component Offset 0: No offset 1: Offset = 128 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 827 33.5.10 ISI Control Register Name: ISI_CR Address: 0xF0034024 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 ISI_CDC 7 - 6 - 5 - 4 - 3 - 2 ISI_SRST 1 ISI_DIS 0 ISI_EN * ISI_EN: ISI Module Enable Request Write a one to this bit to enable the module. Software must poll ENABLE bit in the ISI_SR to verify that the command has successfully completed. * ISI_DIS: ISI Module Disable Request Write a one to this bit to disable the module. If both ISI_EN and ISI_DIS are asserted at the same time, the disable request is not taken into account. Software must poll DIS_DONE bit in the ISI_SR to verify that the command has successfully completed. * ISI_SRST: ISI Software Reset Request Write a one to this bit to request a software reset of the module. Software must poll SRST bit in the ISI_SR to verify that the software request command has terminated. * ISI_CDC: ISI Codec Request Write a one to this bit to enable the codec datapath and capture a full resolution frame. A new request cannot be taken into account while CDC_PND bit is active in the ISI_SR. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 828 33.5.11 ISI Status Register Name: ISI_SR Address: 0xF0034028 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 - 22 - 21 - 20 - 19 SIP 18 - 17 CXFR_DONE 16 PXFR_DONE 15 - 14 - 13 - 12 - 11 - 10 VSYNC 9 - 8 CDC_PND 7 - 6 - 5 - 4 - 3 - 2 SRST 1 DIS_DONE 0 ENABLE * ENABLE: Module Enable This bit is a status bit. 0: Module is disabled 1: Module is enabled * DIS_DONE: Module Disable Request has Terminated 0: Indicates that the request is not completed (if a request was issued). 1: Disable request has completed. This flag is reset after a read operation. * SRST: Module Software Reset Request has Terminated 0: Indicates that the request is not completed (if a request was issued). 1: Software reset request has completed. This flag is reset after a read operation. * CDC_PND: Pending Codec Request This bit is a status bit. 0: Indicates that no Codec request is pending 1: Indicates that the request has been taken into account but cannot be serviced within the current frame. The operation is postponed to the next frame. * VSYNC: Vertical Synchronization 0: Indicates that the vertical synchronization has not been detected since the last read of the status register. 1: Indicates that a vertical synchronization has been detected since the last read of the status register. * PXFR_DONE: Preview DMA Transfer has Terminated When set, this bit indicates that the DATA transfer on the preview channel has completed. This flag is reset after a read operation. 0: Preview transfer done not detected. 1: Preview transfer done detected. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 829 * CXFR_DONE: Codec DMA Transfer has Terminated When set, this bit indicates that the DATA transfer on the codec channel has completed. This flag is reset after a read operation. 0: Codec transfer done not detected. 1: Codec transfer done detected. * SIP: Synchronization in Progress This is a status bit. When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform the clock domain synchronization. 0: The clock domain synchronization process is terminated. 1: This bit is set when the clock domain synchronization operation occurs. No modification of the channel status is allowed when this bit is set, to guarantee data integrity. * P_OVR: Preview Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. This flag is reset after a read operation. * C_OVR: Codec Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. This flag is reset after a read operation. * CRC_ERR: CRC Synchronization Error 0: No CRC error in the embedded synchronization frame (SAV/EAV) 1: Embedded Synchronization Correction is enabled (CRC_SYNC bit is set) in the control register and an error has been detected and not corrected. The frame is discarded and the ISI waits for a new one. This flag is reset after a read operation. * FR_OVR: Frame Rate Overrun 0: No frame overrun 1: Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 830 33.5.12 ISI Interrupt Enable Register Name: ISI_IER Address: 0xF003402C Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 - 22 - 21 - 20 - 19 - 18 - 17 CXFR_DONE 16 PXFR_DONE 15 - 14 - 13 - 12 - 11 - 10 VSYNC 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 SRST 1 DIS_DONE 0 - * DIS_DONE: Disable Done Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. * SRST: Software Reset Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. * VSYNC: Vertical Synchronization Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. * PXFR_DONE: Preview DMA Transfer Done Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. * CXFR_DONE: Codec DMA Transfer Done Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. * P_OVR: Preview Datapath Overflow Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. * C_OVR: Codec Datapath Overflow Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 831 * CRC_ERR: Embedded Synchronization CRC Error Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. * FR_OVR: Frame Rate Overflow Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 832 33.5.13 ISI Interrupt Disable Register Name: ISI_IDR Address: 0xF0034030 Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 - 22 - 21 - 20 - 19 - 18 - 17 CXFR_DONE 16 PXFR_DONE 15 - 14 - 13 - 12 - 11 - 10 VSYNC 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 SRST 1 DIS_DONE 0 - * DIS_DONE: Disable Done Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. * SRST: Software Reset Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. * VSYNC: Vertical Synchronization Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. * PXFR_DONE: Preview DMA Transfer Done Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. * CXFR_DONE: Codec DMA Transfer Done Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. * P_OVR: Preview Datapath Overflow Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. * C_OVR: Codec Datapath Overflow Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 833 * CRC_ERR: Embedded Synchronization CRC Error Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. * FR_OVR: Frame Rate Overflow Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 834 33.5.14 ISI Interrupt Mask Register Name: ISI_IMR Address: 0xF0034034 Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 - 22 - 21 - 20 - 19 - 18 - 17 CXFR_DONE 16 PXFR_DONE 15 - 14 - 13 - 12 - 11 - 10 VSYNC 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 SRST 1 DIS_DONE 0 - * DIS_DONE: Module Disable Operation Completed 0: The disable completed interrupt is disabled. 1: The disable completed interrupt is enabled. * SRST: Software Reset Completed 0: The software reset completed interrupt is disabled. 1: The software reset completed interrupt is enabled. * VSYNC: Vertical Synchronization 0: The vertical synchronization interrupt is enabled. 1: The vertical synchronization interrupt is disabled. * PXFR_DONE: Preview DMA Transfer Interrupt 0: The Preview DMA transfer completed interrupt is enabled 1: The Preview DMA transfer completed interrupt is disabled * CXFR_DONE: Codec DMA Transfer Interrupt 0: The Codec DMA transfer completed interrupt is enabled 1: The Codec DMA transfer completed interrupt * P_OVR: FIFO Preview Overflow 0: The preview FIFO overflow interrupt is disabled. 1: The preview FIFO overflow interrupt is enabled. * C_OVR: FIFO Codec Overflow 0: The codec FIFO overflow interrupt is disabled. 1: The codec FIFO overflow interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 835 * CRC_ERR: CRC Synchronization Error 0: The CRC error interrupt is disabled. 1: The CRC error interrupt is enabled. * FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 836 33.5.15 DMA Channel Enable Register Name: ISI_DMA_CHER Address: 0xF0034038 Access: Write-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 C_CH_EN 0 P_CH_EN * P_CH_EN: Preview Channel Enable Write a one to this bit to enable the preview DMA channel. * C_CH_EN: Codec Channel Enable Write a one to this bit to enable the codec DMA channel. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 837 33.5.16 DMA Channel Disable Register Name: ISI_DMA_CHDR Address: 0xF003403C Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 C_CH_DIS 0 P_CH_DIS * P_CH_DIS: Preview Channel Disable Request 0: No effect 1: Disables the channel. Poll P_CH_S in DMA_CHSR to verify that the preview channel status has been successfully modified. * C_CH_DIS: Codec Channel Disable Request 0: No effect 1: Disables the channel. Poll C_CH_S in DMA_CHSR to verify that the codec channel status has been successfully modified. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 838 33.5.17 DMA Channel Status Register Name: ISI_DMA_CHSR Address: 0xF0034040 Access: Read-only Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 C_CH_S 0 P_CH_S * P_CH_S: Preview DMA Channel Status 0: Indicates that the Preview DMA channel is disabled 1: Indicates that the Preview DMA channel is enabled * C_CH_S: Code DMA Channel Status 0: Indicates that the Codec DMA channel is disabled 1: Indicates that the Codec DMA channel is enabled SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 839 33.5.18 DMA Preview Base Address Register Name: ISI_DMA_P_ADDR Address: 0xF0034044 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - P_ADDR 23 22 21 20 P_ADDR 15 14 13 12 P_ADDR 7 6 5 4 P_ADDR * P_ADDR: Preview Image Base Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 840 33.5.19 DMA Preview Control Register Name: ISI_DMA_P_CTRL Address: 0xF0034048 Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 P_DONE 2 P_IEN 1 P_WB 0 P_FETCH * P_FETCH: Descriptor Fetch Control Bit 0: Preview channel fetch operation is disabled. 1: Preview channel fetch operation is enabled. * P_WB: Descriptor Writeback Control Bit 0: Preview channel writeback operation is disabled. 1: Preview channel writeback operation is enabled. * P_IEN: Transfer Done Flag Control 0: Preview transfer done flag generation is enabled. 1: Preview transfer done flag generation is disabled. * P_DONE: Preview Transfer Done This bit is only updated in the memory. 0: The transfer related to this descriptor has not been performed. 1: The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer, when writeback operation is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 841 33.5.20 DMA Preview Descriptor Address Register Name: ISI_DMA_P_DSCR Address: 0xF003404C Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - P_DSCR 23 22 21 20 P_DSCR 15 14 13 12 P_DSCR 7 6 5 4 P_DSCR * P_DSCR: Preview Descriptor Base Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 842 33.5.21 DMA Codec Base Address Register Name: ISI_DMA_C_ADDR Address: 0xF0034050 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - C_ADDR 23 22 21 20 C_ADDR 15 14 13 12 C_ADDR 7 6 5 4 C_ADDR * C_ADDR: Codec Image Base Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 843 33.5.22 DMA Codec Control Register Name: ISI_DMA_C_CTRL Address: 0xF0034054 Access: Read-write Reset: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 C_DONE 2 C_IEN 1 C_WB 0 C_FETCH * C_FETCH: Descriptor Fetch Control Bit 0: Codec channel fetch operation is disabled. 1: Codec channel fetch operation is enabled. * C_WB: Descriptor Writeback Control Bit 0: Codec channel writeback operation is disabled. 1: Codec channel writeback operation is enabled. * C_IEN: Transfer Done Flag Control 0: Codec transfer done flag generation is enabled. 1: Codec transfer done flag generation is disabled. * C_DONE: Codec Transfer Done This bit is only updated in the memory. 0: The transfer related to this descriptor has not been performed. 1: The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer, when. writeback operation is enabled. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 844 33.5.23 DMA Codec Descriptor Address Register Name: ISI_DMA_C_DSCR Address: 0xF0034058 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 - 0 - C_DSCR 23 22 21 20 C_DSCR 15 14 13 12 C_DSCR 7 6 5 4 C_DSCR * C_DSCR: Codec Descriptor Base Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 845 33.5.24 ISI Write Protection Control Register Name: ISI_WPCR Address: 0xF00340E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 - 2 - 1 - 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 - 6 - 5 - 4 - * WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x495349 ("ISI" in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x495349 ("ISI" in ASCII). * WPKEY: Write Protection Key Password Value Name 0x495349 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 846 33.5.25 ISI Write Protection Status Register Name: ISI_WPSR Address: 0xF00340E8 Access: Read-write 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 - 24 - 19 18 17 16 11 10 9 8 3 - 2 - 1 - 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 - 6 - 5 - 4 - * WPVS: Write Protection Violation Status Value Description 0 No Write Protection Violation occurred since the last read of this register (WP_SR). 1 Write Protection detected unauthorized attempt to write a control register had occurred (since the last read). * WPVSRC: Write Protection Violation Source Value Description 0 No Write Protection Violation occurred since the last read of this register (WP_SR). 1 Write access in ISI_CFG1 while Write Protection was enabled (since the last read). 2 Write access in ISI_CFG2 while Write Protection was enabled (since the last read). 3 Write access in ISI_PSIZE while Write Protection was enabled (since the last read). 4 Write access in ISI_PDECF while Write Protection was enabled (since the last read). 5 Write access in ISI_Y2R_SET0 while Write Protection was enabled (since the last read). 6 Write access in ISI_Y2R_SET1 while Write Protection was enabled (since the last read). 7 Write access in ISI_R2Y_SET0 while Write Protection was enabled (since the last read). 8 Write access in ISI_R2Y_SET1 while Write Protection was enabled (since the last read). 9 Write access in ISI_R2Y_SET2 while Write Protection was enabled (since the last read). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 847 34. USB High Speed Device Port (UDPHS) 34.1 Description The USB High Speed Device Port (UDPHS) is compliant with the Universal Serial Bus (USB), rev 2.0 High Speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a Dual-port RAM used to store the current data payload. If two or three banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 848 34.2 34.3 Embedded Characteristics 1 Device High Speed 1 UTMI transceiver shared between Host and Device USB v2.0 High Speed Compliant, 480 Mbit/s 16 Endpoints up to 1024 bytes Embedded Dual-port RAM for Endpoints Suspend/Resume Logic (Command of UTMI) Up to Three Memory Banks for Endpoints (Not for Control Endpoint) 8 KBytes of DPRAM Block Diagram Figure 34-1. Block Diagram APB Interface APB bus ctrl status DHSDP DHSDM AHB1 AHB bus Rd/Wr/Ready DMA AHB0 AHB bus UTMI USB2.0 CORE DFSDP DP DFSDM DM AHB Switch Local AHB Slave interface EPT Alloc 32 bits DPRAM System Clock Domain 16/8 bits USB Clock Domain PMC SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 849 34.4 Typical Connection Figure 34-2. Board Schematic PIO (VBUS DETECT) 15k (1) "B" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND 1 2 3 4 DHSDM/DFSDM Shell = Shield (1) 22k CRPB CRPB:1F to 10F DHSDP/DFSDP 5K62 1% VBG 10 pF GNDUTMI Note: 34.5 The values shown on the 22 k and 15 k resistors are only valid with 3V3 supplied PIOs. Product Dependencies 34.5.1 Power Management The UDPHS is not continuously clocked. For using the UDPHS, the programmer must first enable the UDPHS Clock in the Power Management Controller Peripheral Clock Enable Register (PMC_PCER). Then enable the PLL in the PMC UTMI Clock Configuration Register (CKGR_UCKR). Finally, enable BIAS in CKGR_UCKR. However, if the application does not require UDPHS operations, the UDPHS clock can be stopped when not needed and restarted later. 34.5.2 Interrupt The UDPHS interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the UDPHS Table 34-1. Peripheral IDs Instance ID UDPHS 33 interrupt requires the Interrupt Controller to be programmed first. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 850 34.6 Functional Description 34.6.1 UTMI transceivers Sharing The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL register. Figure 34-3. USB Selection others Transceivers HS Transceiver EN_UDPHS 0 Others Ports 1 PA HS USB Host HS EHCI FS OHCI DMA HS USB Device DMA 34.6.2 USB V2.0 High Speed Device Port Introduction The USB V2.0 High Speed Device Port provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB Device through a set of communication flows. 34.6.3 USB V2.0 High Speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device. A device provides several logical communication pipes with the host. To each logical pipe is associated an endpoint. Transfer through a pipe belongs to one of the four transfer types: Control Transfers: Used to configure a device at attach time and can be used for other device-specific purposes, including control of other pipes on the device. Bulk Data Transfers: Generated or consumed in relatively large burst quantities and have wide dynamic latitude in transmission constraints. Interrupt Data Transfers: Used for timely but reliable delivery of data, for example, characters or coordinates with human-perceptible echo or feedback response characteristics. Isochronous Data Transfers: Occupy a prenegotiated amount of USB bandwidth with a prenegotiated delivery latency. (Also called streaming real time transfers.) As indicated below, transfers are sequential events carried out on the USB bus. Endpoints must be configured according to the transfer type they handle. Table 34-2. USB Communication Flow Transfer Direction Bandwidth Endpoint Size Error Detection Retrying Bidirectional Not guaranteed 8, 16, 32, 64 Yes Automatic Isochronous Unidirectional Guaranteed 8-1024 Yes No Interrupt Unidirectional Not guaranteed 8-1024 Yes Yes Bulk Unidirectional Not guaranteed 8-512 Yes Yes Control SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 851 34.6.4 USB Transfer Event Definitions A transfer is composed of one or several transactions as shown in the following table. Table 34-3. USB Transfer Events Transfer Direction Type Transaction * Setup transaction Data IN transactions Status OUT transaction CONTROL (bidirectional) * Setup transaction Data OUT transactions Status IN transaction Control Transfer (1) * Setup transaction Status IN transaction * Data IN transaction Data IN transaction Bulk IN Transfer IN (device toward host) * Data IN transaction Data IN transaction Interrupt IN Transfer Isochronous IN Transfer OUT (host toward device) (2) * Data IN transaction Data IN transaction Bulk OUT Transfer * Data OUT transaction Data OUT transaction Interrupt OUT Transfer * Data OUT transaction Data OUT transaction Isochronous OUT Transfer (2) * Data OUT transaction Data OUT transaction Notes: 1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake. 2. Isochronous transfers must use endpoints configured with two or three banks. An endpoint handles all transactions related to the type of transfer for which it has been configured. Table 34-4. UDPHS Endpoint Description Mnemonic Nb Bank DMA High Band Width Max. Endpoint Size Endpoint Type 0 EPT_0 1 N N 64 Control 1 EPT_1 3 Y Y 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 2 EPT_2 3 Y Y 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 3 EPT_3 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 4 EPT_4 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 5 EPT_5 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 6 EPT_6 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 7 EPT_7 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 8 EPT_8 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 9 EPT_9 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 10 EPT_10 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 11 EPT_11 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 12 EPT_12 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 13 EPT_13 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 14 EPT_14 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 15 EPT_15 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt Endpoint # Note: 1. In Isochronous Mode (Iso), it is preferable that High Band Width capability is available. The size of internal DPRAM is 8 KB. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 852 Suspend and resume are automatically detected by the UDPHS device, which notifies the processor by raising an interrupt. 34.6.5 USB V2.0 High Speed BUS Transactions Each transfer results in one or more transactions over the USB bus. There are five kinds of transactions flowing across the bus in packets: 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction 4. Status IN Transaction 5. Status OUT Transaction Figure 34-4. Control Read and Write Sequences Setup Stage Control Write Setup TX Data Stage Data OUT TX No Data Control Setup TX Data OUT TX Data Stage Setup Stage Control Read Status Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Status IN TX Status Stage Data IN TX Status OUT TX A status IN or OUT transaction is identical to a data IN or OUT transaction. 34.6.6 Endpoint Configuration The endpoint 0 is always a control endpoint, it must be programmed and active in order to be enabled when the End Of Reset interrupt occurs. To configure the endpoints: Fill the configuration register (UDPHS_EPTCFG) with the endpoint size, direction (IN or OUT), type (CTRL, Bulk, IT, ISO) and the number of banks. Fill the number of transactions (NB_TRANS) for isochronous endpoints. Note: For control endpoints the direction has no effect. Verify that the EPT_MAPD flag is set. This flag is set if the endpoint size and the number of banks are correct compared to the FIFO maximum capacity and the maximum number of allowed banks. Configure control flags of the endpoint and enable it in UDPHS_EPTCTLENBx according to "UDPHS Endpoint Control Disable Register (Isochronous Endpoint)" on page 897. Control endpoints can generate interrupts and use only 1 bank. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 853 All endpoints (except endpoint 0) can be configured either as Bulk, Interrupt or Isochronous. See Table 34-4. UDPHS Endpoint Description. The maximum packet size they can accept corresponds to the maximum endpoint size. Note: The endpoint size of 1024 is reserved for isochronous endpoints. The size of the DPRAM is 8 KB. The DPR is shared by all active endpoints. The memory size required by the active endpoints must not exceed the size of the DPRAM. SIZE_DPRAM = SIZE _EPT0 + NB_BANK_EPT1 x SIZE_EPT1 + NB_BANK_EPT2 x SIZE_EPT2 + NB_BANK_EPT3 x SIZE_EPT3 + NB_BANK_EPT4 x SIZE_EPT4 + NB_BANK_EPT5 x SIZE_EPT5 + NB_BANK_EPT6 x SIZE_EPT6 +... (refer to 34.7.8 UDPHS Endpoint Configuration Register) If a user tries to configure endpoints with a size the sum of which is greater than the DPRAM, then the EPT_MAPD is not set. The application has access to the physical block of DPR reserved for the endpoint through a 64 KB logical address space. The physical block of DPR allocated for the endpoint is remapped all along the 64 KB logical address space. The application can write a 64 KB buffer linearly. Figure 34-5. Logical Address Space for DPR Access DPR 8 to 64 B 1 bank Logical address 8 to 64 B 64 KB EP0 8 to1024 B 64 KB 8 to1024 B 8 to1024 B EP1 ... 64 KB EP2 8 to1024 B 8 to1024 B x banks y banks z banks 8 to1024 B 64 KB EP3 ... Configuration examples of UDPHS_EPTCTLx (UDPHS Endpoint Control Disable Register (Isochronous Endpoint)) for Bulk IN endpoint type follow below. With DMA AUTO_VALID: Automatically validate the packet and switch to the next bank. EPT_ENABL: Enable endpoint. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 854 Without DMA: TXRDY: An interrupt is generated after each transmission. EPT_ENABL: Enable endpoint. Configuration examples of Bulk OUT endpoint type follow below. With DMA AUTO_VALID: Automatically validate the packet and switch to the next bank. EPT_ENABL: Enable endpoint. Without DMA RXRDY_TXKL: An interrupt is sent after a new packet has been stored in the endpoint FIFO. EPT_ENABL: Enable endpoint. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 855 34.6.7 DPRAM Management Endpoints can only be allocated in ascending order, from the endpoint 0 to the last endpoint to be allocated. The user shall therefore configure them in the same order. The allocation of an endpoint x starts when the Number of Banks field in the UDPHS Endpoint Configuration Register (UDPHS_EPTCFGx.BK_NUMBER) is different from zero. Then, the hardware allocates a memory area in the DPRAM and inserts it between the x-1 and x+1 endpoints. The x+1 endpoint memory window slides up and its data is lost. Note that the following endpoint memory windows (from x+2) do not slide. Disabling an endpoint, by writing a one to the Endpoint Disable bit in the UDPHS Endpoint Control Disable Register (UDPHS_EPTCTLDISx.EPT_DISABL), does not reset its configuration: The Endpoint Banks (UDPHS_EPTCFGx.BK_NUMBER), The Endpoint Size (UDPHS_EPTCFGx.EPT_SIZE), The Endpoint Direction (UDPHS_EPTCFGx.EPT_DIR), and The Endpoint Type (UDPHS_EPTCFGx.EPT_TYPE). To free its memory, the user shall write a zero to the UDPHS_EPTCFGx.BK_NUMBER field. The x+1 endpoint memory window then slides down and its data is lost. Note that the following endpoint memory windows (from x+2) do not slide. Figure 34-6 on page 856 illustrates the allocation and reorganization of the DPRAM in a typical example. Figure 34-6. Allocation and Reorganization of the DPRAM Free Memory Free Memory Free Memory EPT5 EPT5 EPT5 Free Memory EPT5 Conflict EPT4 EPT4 EPT4 EPT3 EPT3 (always allocated) EPT4 EPT2 EPT2 EPT2 EPT2 EPT1 EPT1 EPT1 EPT1 EPT0 EPT0 EPT0 EPT0 Device: Device: EPT4 Lost Memory Device: Device: UDPHS_EPTCTLENBx.EPT_ENABL = 1 UDPHS_EPTCTLDIS3.EPT_DISABL = 1 UDPHS_EPTCFG3.BK_NUMBER = 0 UDPHS_EPTCFGx.BK_NUMBER <> 0 Endpoints 0..5 Activated Endpoint 3 Disabled EPT3 (larger size) UDPHS_EPTCTLENB3.EPT_ENABL = 1 UDPHS_EPTCFG3.BK_NUMBER <> 0 Endpoint 3 Memory Freed Endpoint 3 Activated 1. The endpoints 0 to 5 are enabled, configured and allocated in ascending order. Each endpoint then owns a memory area in the DPRAM. 2. The endpoint 3 is disabled, but its memory is kept allocated by the controller. 3. In order to free its memory, its UDPHS_EPTCFGx.BK_NUMBER field is written to zero. The endpoint 4 memory window slides down, but the endpoint 5 does not move. 4. If the user chooses to reconfigure the endpoint 3 with a larger size, the controller allocates a memory area after the endpoint 2 memory area and automatically slides up the endpoint 4 memory window. The endpoint 5 does not SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 856 move and a memory conflict appears as the memory windows of the endpoints 4 and 5 overlap. The data of these endpoints is potentially lost. Notes: 1. There is no way the data of the endpoint 0 can be lost (except if it is de-allocated) as the memory allocation and de-allocation may affect only higher endpoints. 2. Deactivating then reactivating the same endpoint with the same configuration only modifies temporarily the controller DPRAM pointer and size for this endpoint. Nothing changes in the DPRAM, higher endpoints seem not to have been moved and their data is preserved as far as nothing has been written or received into them while changing the allocation state of the first endpoint. 3. When the user writes a value different from zero to the UDPHS_EPTCFGx.BK_NUMBER field, the Endpoint Mapped bit (UDPHS_EPTCFGx.EPT_MAPD) is set only if the configured size and number of banks are correct as compared to the endpoint maximal allowed values and to the maximal FIFO size (i.e., the DPRAM size). The UDPHS_EPTCFGx.EPT_MAPD value does not consider memory allocation conflicts. 34.6.8 Transfer With DMA USB packets of any length may be transferred when required by the UDPHS device. These transfers always feature sequential addressing. Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not occur, or occur only once instead of several times, during a single big USB packet DMA transfer in case another AHB master addresses the memory. The locked bursts result in up to 128-word single-cycle unbroken AHB bursts for bulk endpoints and 256word single-cycle unbroken bursts for isochronous endpoints. This maximum burst length is then controlled by the lowest programmed USB endpoint size (EPT_SIZE field in the UDPHS_EPTCFGx register) and DMA Size (BUFF_LENGTH field in the UDPHS_DMACONTROLx register). The USB 2.0 device average throughput may be up to nearly 60 Mbyte/s. Its internal slave average access latency decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-state word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses need less than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz. The UDPHS DMA Channel Transfer Descriptor is described in "UDPHS DMA Channel Transfer Descriptor" on page 918. Note: In case of debug, be careful to address the DMA to an SRAM address even if a remap is done. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 857 Figure 34-7. Example of DMA Chained List Transfer Descriptor UDPHS Registers (Current Transfer Descriptor) Next Descriptor Address DMA Channel Address Transfer Descriptor UDPHS Next Descriptor DMA Channel Control Next Descriptor Address DMA Channel Address DMA Channel Address Transfer Descriptor DMA Channel Control Next Descriptor Address DMA Channel Control DMA Channel Address DMA Channel Control Null Memory Area Data Buff 1 Data Buff 2 Data Buff 3 34.6.9 Transfer Without DMA Important. If the DMA is not to be used, it is necessary that it be disabled because otherwise it can be enabled by previous versions of software without warning. If this should occur, the DMA can process data before an interrupt without knowledge of the user. The recommended means to disable DMA is as follows: // Reset IP UDPHS AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_EN_UDPHS; AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_EN_UDPHS; // With OR without DMA !!! for( i=1; i<=((AT91C_BASE_UDPHS->UDPHS_IPFEATURES & AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) { // RESET endpoint canal DMA: // DMA stop channel command AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Disable endpoint AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS |= 0XFFFFFFFF; // Reset endpoint config AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLCFG = 0; // Reset DMA channel (Buff count and Control field) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0x02; // NON STOP command // Reset DMA channel 0 (STOP) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Clear DMA channel status (read the register for clear it) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS = AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS; } SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 858 34.6.10 Handling Transactions with USB V2.0 Device Peripheral 34.6.10.1 Setup Transaction The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by the application, the UDPHS accepts the next packets sent over the device endpoint. When a valid setup packet is accepted by the UDPHS: The UDPHS device automatically acknowledges the setup packet (sends an ACK response) Payload data is written in the endpoint Sets the RX_SETUP interrupt The BYTE_COUNT field in the UDPHS_EPTSTAx register is updated An endpoint interrupt is generated while RX_SETUP in the UDPHS_EPTSTAx register is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, read the setup packet in the FIFO, then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register to acknowledge the setup stage. If STALL_SNT was set to 1, then this bit is automatically reset when a setup token is detected by the device. Then, the device still accepts the setup stage. (See Section 34.6.10.15 "STALL" on page 869). 34.6.10.2 NYET NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the PING protocol. High Speed devices must support an improved NAK mechanism for Bulk OUT and control endpoints (except setup stage). This mechanism allows the device to tell the host whether it has sufficient endpoint space for the next OUT transfer (see USB 2.0 spec 8.5.1 NAK Limiting via Ping Flow Control). The NYET/ACK response to a High Speed Bulk OUT transfer and the PING response are automatically handled by hardware in the UDPHS_EPTCTLx register (except when the user wants to force a NAK response by using the NYET_DIS bit). If the endpoint responds instead to the OUT/DATA transaction with an NYET handshake, this means that the endpoint accepted the data but does not have room for another data payload. The host controller must return to using a PING token until the endpoint indicates it has space available. Figure 34-8. NYET Example with Two Endpoint Banks data 0 ACK t=0 data 1 NYET t = 125 s Bank 1 E Bank 0 F PING ACK t = 250 s Bank 1 F Bank 1 F Bank 0 E' Bank 0 E data 0 NYET t = 375 s Bank 1 F Bank 0 E PING t = 500 s Bank 1 F Bank 0 F NACK PING t = 625 s Bank 1 E' Bank 0 F ACK E: empty E': begin to empty F: full Bank 1 E Bank 0 F 34.6.10.3 Data IN 34.6.10.4 Bulk IN or Interrupt IN Data IN packets are sent by the device during the data or the status stage of a control transfer or during an (interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. There are three ways for an application to transfer a buffer in several packets over the USB: packet by packet (see 34.6.10.5 below) 64 KB (see 34.6.10.5 below) SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 859 DMA (see 34.6.10.6 below) 34.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host) The application can write one or several banks. A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the endpoint. Algorithm Description for Each Packet: The application waits for TXRDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write access to the DPR. The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window. The application sets TXRDY flag in the UDPHS_EPTSETSTAx register. The application is notified that it is possible to write a new packet to the DPR by the TXRDY interrupt. This interrupt can be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register. Algorithm Description to Fill Several Packets: Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register. The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware. The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait that at least one bank is free. The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS. If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the TXRDY bit in the UDPHS_EPTSETSTAx register. The application is notified that all banks are free, so that it is possible to write another burst of packets by the BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers. This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate. A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register. 34.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer types except control transfer. Example DMA configuration: 1. Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred. 2. Enable the interrupt of the DMA in UDPHS_IEN 3. Program UDPHS_ DMACONTROLx: Size of buffer to send: size of the buffer to be sent to the host. END_B_EN: The endpoint can validate the packet (according to the values programmed in the AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See "UDPHS Endpoint Control Disable Register (Isochronous Endpoint)" on page 897 and Figure 34-13. Autovalid with DMA) END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0. CHANN_ENB: Run and stop at end of buffer The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 860 A transfer descriptor can be used. Instead of programming the register directly, a descriptor should be programmed and the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field (Load Next Descriptor Now) in UDPHS_DMACONTROLx register. The structure that defines this transfer descriptor must be aligned. Each buffer to be transferred must be described by a DMA Transfer descriptor (see "UDPHS DMA Channel Transfer Descriptor" on page 918). Transfer descriptors are chained. Before executing transfer of the buffer, the UDPHS may fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register. To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped. To do so, INTDIS_DMA and TXRDY may be set in the UDPHS_EPTCTLENBx register. It is also possible for the application to wait for the completion of all transfers. In this case the LDNXT_DSC field in the last transfer descriptor UDPHS_DMACONTROLx register must be set to 0 and CHANN_ENB set to 1. Then the application can chain a new transfer descriptor. The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is triggered. This can be used to stop DMA transfers in case of errors. The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the UDPHS_DMACONTROLx register). Figure 34-9. Data IN Transfer for Endpoint with One Bank Prevous Data IN TX USB Bus Packets Token IN Microcontroller Loads Data in FIFO Data IN 1 TXRDY Flag (UDPHS_EPTSTAx) Set by firmware ACK Token IN NAK Cleared by hardware Data is Sent on USB Bus Token IN Data IN 2 ACK Set by the firmware Cleared by hardware Interrupt Pending TX_COMPLT Flag (UDPHS_EPTSTAx) Payload in FIFO Set by hardware DPR access by firmware FIFO Content Interrupt Pending Data IN 1 Load in progress Cleared by firmware Cleared by firmware DPR access by hardware Data IN 2 SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 861 Figure 34-10.Data IN Transfer for Endpoint with Two Banks Microcontroller Load Data IN Bank 0 USB Bus Packets Microcontroller Load Data IN Bank 1 UDPHS Device Send Bank 0 Token IN Data IN ACK Microcontroller Load Data IN Bank 0 UDPHS Device Send Bank 1 Data IN Token IN ACK Set by Firmware, Cleared by Hardware Data Payload Written switch to next bank in FIFO Bank 0 Virtual TXRDY bank 0 (UDPHS_EPTSTAx) Cleared by Hardware Data Payload Fully Transmitted Virtual TXRDY bank 1 (UDPHS_EPTSTAx) Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending TX_COMPLT Flag (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Set by Hardware Set by Hardware Interrupt Cleared by Firmware Written by Microcontroller Read by USB Device FIFO (DPR) Bank1 Written by Microcontroller Written by Microcontroller Read by UDPHS Device Figure 34-11.Data IN Followed By Status OUT Transfer at the End of a Control Transfer Device Sends the Last Data Payload to Host USB Bus Packets Token IN Data IN Device Sends a Status OUT to Host ACK Token OUT Data OUT (ZLP) ACK Token OUT Data OUT (ZLP) ACK Interrupt Pending RXRDY (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware TX_COMPLT (UDPHS_EPTSTAx) Set by Hardware Note: Cleared by Firmware A NAK handshake is always generated at the first status stage token. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 862 Figure 34-12.Data OUT Followed by Status IN Transfer Host Sends the Last Data Payload to the Device USB Bus Packets Token OUT Data OUT Device Sends a Status IN to the Host ACK Token IN Data IN ACK Interrupt Pending RXRDY (UDPHS_EPTSTAx) Cleared by Firmware Set by Hardware TXRDY (UDPHS_EPTSTAx) Set by Firmware Note: Clear by Hardware Before proceeding to the status stage, the software should determine that there is no risk of extra data from the host (data stage). If not certain (non-predictable data stage length), then the software should wait for a NAK-IN interrupt before proceeding to the status stage. This precaution should be taken to avoid collision in the FIFO. Figure 34-13.Autovalid with DMA Bank (system) Write Bank 0 Bank 1 write bank 0 write bank 1 bank 0 is full Bank 1 Bank 0 Bank 1 write bank 0 bank 1 is full bank 0 is full Bank 0 IN data 0 Bank (usb) Bank 0 IN data 1 Bank 1 IN data 0 Bank 0 Bank 1 Virtual TXRDY Bank 0 Virtual TXRDY Bank 1 TXRDY (Virtual 0 & Virtual 1) Note: In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to DMA. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 863 34.6.10.7 Isochronous IN Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate. Isochronous transfer provides periodic, continuous communication between host and device. It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc. If the endpoint is not available (TXRDY_TRER = 0), then the device does not answer to the host. An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled, then sent to the CPU. The STALL_SNT command bit is not used for an ISO-IN endpoint. 34.6.10.8 High Bandwidth Isochronous Endpoint Handling: IN Example For high bandwidth isochronous endpoints, the DMA can be programmed with the number of transactions (BUFF_LENGTH field in UDPHS_DMACONTROLx) and the system should provide the required number of packets per microframe, otherwise, the host will notice a sequencing problem. A response should be made to the first token IN recognized inside a microframe under the following conditions: If at least one bank has been validated, the correct DATAx corresponding to the programmed Number Of Transactions per Microframe (NB_TRANS) should be answered. In case of a subsequent missed or corrupted token IN inside the microframe, the USB 2.0 Core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end. If this flush occurs, an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). If no bank is validated yet, the default DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). Then, no data bank is flushed at microframe end. If no data bank has been validated at the time when a response should be made for the second transaction of NB_TRANS = 3 transactions microframe, a DATA1 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if remaining untransmitted banks for that microframe are available at its end, they are flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). If no data bank has been validated at the time when a response should be made for the last programmed transaction of a microframe, a DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if the remaining untransmitted data bank for that microframe is available at its end, it is flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). If at the end of a microframe no valid token IN has been recognized, no data bank is flushed and no error condition is reported. At the end of a microframe in which at least one data bank has been transmitted, if less than NB_TRANS banks have been validated for that microframe, an error condition is flagged (ERR_TRANS is set in UDPHS_EPTSTAx). Cases of Error (in UDPHS_EPTSTAx) ERR_FL_ISO: There was no data to transmit inside a microframe, so a ZLP is answered by default. ERR_FLUSH: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of transactions actually validated (TXRDY_TRER) and likewise with the NB_TRANS programmed. ERR_TRANS: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of programmed NB_TRANS transactions and the packets not requested were not validated. ERR_FL_ISO + ERR_FLUSH: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN. ERR_FL_ISO + ERR_TRANS: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN and the data can be discarded at the microframe end. ERR_FLUSH + ERR_TRANS: The first token IN has been answered and it was the only one received, a second bank has been validated but not the third, whereas NB_TRANS was waiting for three transactions. ERR_FL_ISO + ERR_FLUSH + ERR_TRANS: The first token IN has been treated, the data for the second Token IN was not available in time, but the second bank has been validated before the end of the microframe. The third bank has not been validated, but three transactions have been set in NB_TRANS. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 864 34.6.10.9 Data OUT 34.6.10.10 Bulk OUT or Interrupt OUT Like data IN, data OUT packets are sent by the host during the data or the status stage of control transfer or during an interrupt/bulk/isochronous OUT transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. 34.6.10.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device) Algorithm Description for Each Packet: The application enables an interrupt on RXRDY_TXKL. When an interrupt on RXRDY_TXKL is received, the application knows that UDPHS_EPTSTAx register BYTE_COUNT bytes have been received. The application reads the BYTE_COUNT bytes from the endpoint. The application clears RXRDY_TXKL. Note: If the application does not know the size of the transfer, it may not be a good option to use AUTO_VALID. Because if a zero-length-packet is received, the RXRDY_TXKL is automatically cleared by the AUTO_VALID hardware and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the UDPHS_EPTSTAx register. Algorithm to Fill Several Packets: The application enables the interrupts of BUSY_BANK and AUTO_VALID. When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available. If the application doesn't know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RXRDY_TXKL. 34.6.10.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device) To use the DMA setting, the AUTO_VALID field is mandatory. See 34.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) for more information. DMA Configuration Example: 1. First program UDPHS_DMAADDRESSx with the address of the buffer that should be transferred. 2. Enable the interrupt of the DMA in UDPHS_IEN 3. Program the DMA Channelx Control Register: Size of buffer to be sent. END_B_EN: Can be used for OUT packet truncation (discarding of unbuffered packet data) at the end of DMA buffer. END_BUFFIT: Generate an interrupt when BUFF_COUNT in the UDPHS_DMASTATUSx register reaches 0. END_TR_EN: End of transfer enable, the UDPHS device can put an end to the current DMA transfer, in case of a short packet. END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB packet has been transferred by the DMA, if the USB transfer ended with a short packet. (Beneficial when the receive size is unknown.) CHANN_ENB: Run and stop at end of buffer. For OUT transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty). Notes: 1. When a zero-length-packet is received, RXRDY_TXKL bit in UDPHS_EPTSTAx is cleared automatically by AUTO_VALID, and the application knows of the end of buffer by the presence of the END_TR_IT. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 865 2. If the host sends a zero-length packet, and the endpoint is free, then the device sends an ACK. No data is written in the endpoint, the RXRDY_TXKL interrupt is generated, and the BYTE_COUNT field in UDPHS_EPTSTAx is null. Figure 34-14.Data OUT Transfer for Endpoint with One Bank Host Sends Data Payload USB Bus Packets Token OUT Data OUT 1 Microcontroller Transfers Data Host Sends the Next Data Payload ACK Token OUT Host Resends the Next Data Payload Data OUT 2 NAK Data OUT 2 Token OUT ACK Interrupt Pending RXRDY (UDPHS_EPTSTAx) Set by Hardware FIFO (DPR) Content Data OUT 1 Written by UDPHS Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 1 Data OUT 2 Microcontroller Read Written by UDPHS Device Figure 34-15.Data OUT Transfer for an Endpoint with Two Banks Microcontroller reads Data 1 in bank 0, Host sends second data payload Host sends first data payload USB Bus Packets Virtual RXRDY Bank 0 Token OUT Data OUT 1 ACK Token OUT Data OUT 2 Virtual RXRDY Bank 1 ACK Token OUT Data OUT 3 Cleared by Firmware Interrupt pending Set by Hardware, Data payload written in FIFO endpoint bank 0 Microcontroller reads Data 2 in bank 1, Host sends third data payload Set by Hardware Data Payload written in FIFO endpoint bank 1 Cleared by Firmware Interrupt pending RXRDY = (virtual bank 0 | virtual bank 1) (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Data OUT 1 Write by UDPHS Device FIFO (DPR) Bank 1 Data OUT 1 Data OUT 3 Read by Microcontroller Write in progress Data OUT 2 Write by Hardware Data OUT 2 Read by Microcontroller SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 866 34.6.10.13 High Bandwidth Isochronous Endpoint OUT Figure 34-16.Bank Management, Example of Three Transactions per Microframe USB bus Transactions MDATA0 MDATA1 DATA2 t = 52.5 s (40% of 125 s) t=0 RXRDY Microcontroller FIFO (DPR) Access MDATA0 Read Bank 1 Read Bank 2 MDATA1 DATA2 USB line t = 125 s RXRDY Read Bank 3 Read Bank 1 USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024 data bytes per microframe. To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average). NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe. If NB_TRANS > 1 then it is High Bandwidth. Example: If NB_TRANS = 3, the sequence should be either MData0 MData0/Data1 MData0/Data1/Data2 If NB_TRANS = 2, the sequence should be either MData0 MData0/Data1 If NB_TRANS = 1, the sequence should be Data0 34.6.10.14 Isochronous Endpoint Handling: OUT Example The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three fields as follows: TOGGLESQ_STA: PID of the data stored in the current bank CURBK: Number of the bank currently being accessed by the microcontroller. BUSY_BANK_STA: Number of busy bank This is particularly useful in case of a missing data packet. If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.) If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The ERR_CRC_NTR flag is set in UDPHS_EPTSTAx register. If the endpoint is already full, the packet is not written in the DPRAM. The ERR_FL_ISO flag is set in UDPHS_EPTSTAx. If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the task of the CPU to manage this error. The data packet is written in the endpoint (except the extra data). SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 867 If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RXRDY_TXKL flag is set, and the BYTE_COUNT field in UDPHS_EPTSTAx register is null. The FRCESTALL command bit is unused for an isochonous endpoint. Otherwise, payload data is written in the endpoint, the RXRDY_TXKL interrupt is generated and the BYTE_COUNT in UDPHS_EPTSTAx register is updated. SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 868 34.6.10.15 STALL STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a PING transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported. OUT To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register. IN Set the FRCESTALL bit in UDPHS_EPTSETSTAx register. Figure 34-17.Stall Handshake Data OUT Transfer USB Bus Packets Data OUT Token OUT Stall PID FRCESTALL Set by Firmware Cleared by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware Figure 34-18.Stall Handshake Data IN Transfer USB Bus Packets Token IN Stall PID FRCESTALL Cleared by Firmware Set by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 869 34.6.11 Speed Identification The high speed reset is managed by the hardware. At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. At the end of the reset process (full or high), the ENDRESET interrupt is generated. Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device. 34.6.12 USB V2.0 High Speed Global Interrupt Interrupts are defined in Section 34.7.3 "UDPHS Interrupt Enable Register" (UDPHS_IEN) and in Section 34.7.4 "UDPHS Interrupt Status Register" (UDPHS_INTSTA). 34.6.13 Endpoint Interrupts Interrupts are enabled in UDPHS_IEN (see Section 34.7.3 "UDPHS Interrupt Enable Register") and individually masked in UDPHS_EPTCTLENBx (see Section 34.7.9 "UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)"). Table 34-5. Endpoint Interrupt Source Masks SHRT_PCKT Short Packet Interrupt BUSY_BANK Busy Bank Interrupt NAK_OUT NAKOUT Interrupt NAK_IN/ERR_FLUSH NAKIN/Error Flush Interrupt STALL_SNT/ERR_CRC_NTR Stall Sent/CRC error/Number of Transaction Error Interrupt RX_SETUP/ERR_FL_ISO Received SETUP/Error Flow Interrupt TXRDY_TRER TX Packet Read/Transaction Error Interrupt TX_COMPLT Transmitted IN Data Complete Interrupt RXRDY_TXKL Received OUT Data Interrupt ERR_OVFLW Overflow Error Interrupt MDATA_RX MDATA Interrupt DATAX_RX DATAx Interrupt SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 870 Figure 34-19.UDPHS Interrupt Control Interface (UDPHS_IEN) Global IT mask Global IT sources DET_SUSPD MICRO_SOF USB Global IT Sources INT_SOF ENDRESET WAKE_UP ENDOFRSM UPSTR_RES (UDPHS_EPTCTLENBx) SHRT_PCKT EP mask BUSY_BANK EP sources NAK_OUT (UDPHS_IEN) EPT_0 husb2dev interrupt NAK_IN/ERR_FLUSH STALL_SNT/ER_CRC_NTR EPT0 IT Sources RX_SETUP/ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW MDATA_RX DATAX_RX (UDPHS_IEN) EPT_x EP mask EP sources (UDPHS_EPTCTLx) INTDIS_DMA EPT1-6 IT Sources disable DMA channelx request (UDPHS_DMACONTROLx) mask (UDPHS_IEN) DMA_x EN_BUFFIT mask DMA CH x END_TR_IT mask DESC_LD_IT SAMA5D3 Series [DATASHEET] 11121C-ATARM-15-Oct-13 871 34.6.14 Power Modes 34.6.14.1 Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0. Figure 34-20.UDPHS Device State Diagram Attached Hub Reset Hub or Configured Deconfigured Bus Inactive Powered Suspended Bus Activity Power Interruption Reset Bus Inactive Suspended Default Bus Activity Reset Address Assigned Bus Inactive Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Configured Suspended Bus Activity Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 A on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse