ATSAMA5D36A-CU - Atmel - Datasheet.Live

11121C–ATARM–15-Oct-13

Description

The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU

based on the ARM® Cortex®-A5 processor, achieving 536 MHz with power

consumption levels below 0.5 mW in low-power mode. The device features a floating

point unit for high-precision computing and accelerated data processing, and a high

data bandwidth architecture. It integrates advanced user interface and connectivity

peripherals and security features.

The SAMA5D3 series features an internal multi-layer bus architecture associated with

39 DMA channels to sustain the high bandwidth required by the processor and the

high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and

MLC NAND Flash memory with 24-bit ECC.

The comprehensive peripheral set includes an LCD controller with overlays for

hardware-accelerated image composition, a touchscreen interface and a CMOS

sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588,

10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism,

hardware accelerated engines for encryption (AES, TDES) and hash function (SHA),

the SAMA5D3 ensures anti-cloning, code protection and secure external data

transfers.

The SAMA5D3 series is optimized for control panel/HMI applications and applications

that require high levels of connectivity in the industrial and consumer markets. Its low-

power consumption levels make the SAMA5D3 particularly suited for battery-powered

devices.

There are five SAMA5D3 devices in this series. Table 1-1 “SAMA5D3 Device

Differences” shows the differences in the embedded features. All other features are

available on all derivatives; this includes the three USB ports as well as the encryption

engine and secure boot features.

ARM-based Embedded MPU

SAMA5D3 Series

DATASHEET

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

1. Features

Core

ARM® Cortex®-A5 Processor with ARM v7-A Thumb2® Instruction Set

CPU Frequency up to 536 MHz

32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA)

Fully Integrated MMU and Floating Point Unit (VFPv4)

Memories

One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loa der: Boot on 8-bit

NAND Flash, SDCard, eMMC, serial DataFlash®, selectable Order

One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed

High Bandwidth 32-bit Multi-port Dynamic RAM Controller supporting 512 Mbyte 8 bank

DDR2/LPDDR/LPDDR2 with datapath scrambling

Independent Static Memory Controller with datapath scrambling and SLC/MLC NAND Support with up to

24-bit Error Correcting Code (PMECC)

System running up to 166 MHz

Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock

Boot Mode Select Option, Remap Command

Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator

Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator

One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed

39 DMA Channels including two 8-channel 64-bit Central DMA Controllers

64-bit Advanced Interrupt Controller

Three Programmable External Clock Signals

Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer

Low Power Management

Shut Down Controller

Battery Backup Registers

Clock Generator and Power Management Controller

Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities

Peripherals

LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion

ITU-R BT. 601/656 Image Sensor Interface

Three HS/FS/LS USB Ports with On-Chip Transceivers

One Device Controller

One Host Controller with Integrated Root Hub (3 Downstream Ports)

One 10/100/1000 Mbps Gigabit Ethernet MAC Controller (GMAC) with IEEE1588 support

One 10/100 Mbps Ethernet MAC Controller (EMAC)

Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B

Softmodem Interface

Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0)

Two Master/Slave Serial Peripheral Interfaces

Two Synchronous Serial Controllers

Three Two-wire Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS

Four USARTs, two UARTs, one DBGU

Two Three-channel 32-bit Timer/Counters

One 4-channel 16-bit PWM Controller

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function

Safety

Power-on Reset Cells

Independent Watchdog

Main Crystal Clock Failure Detection

Write Protection Registers

SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512)

Memory Management Unit

Security

TRNG: True Random Number Generator

Encryption Engine

AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications

TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications

Atmel® Secure Boot Solution

I/O

Five 32-bit Parallel Input/Output Controllers

160 I/Os

Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input

Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering

Slew Rate Control on High Speed I/Os

Impedance Control on DDR I/Os

Package

324-ball LFBGA, 15 x 15 x 1.4 mm, pitch 0.8 mm

324-ball TFBGA, 12 x 12 x 1.2 mm, pitch 0.5 mm

Table 1-1. SAMA5D3 Device Differences

Peripherals SAMA5D31 SAMA5D33 SAMA5D34 SAMA5D35 SAMA5D36

CAN0, CAN1 — — X X X

EMAC X — — X X

GMAC —XXXX

HSMCI2 X—XXX

LCDC X X X — X

TC1 ———X X

UART0, UAR T 1 X — — X X

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

2. Block Diagram

Figure 2-1. SAMA5D3 Block Diagram

Note: 1. Per ipheral Bridge 0 (APB0) connects HSMCI0 , SPI0, USART0, USART1, TWI0, TWI1, UART0, SSC0, SMD.

Peripheral Bridge 1 (APB1) connects HSMCI1, HSMCI2, ADC, SSC1, UART1, USART2, USART3, TWI2, DBGU,

SPI1, SHA, AES, TDES.

AIC

PLLA

SysC

PMC

PLLUTMI

PIT

WDT

OSC 32K

SHDC

RSTC

POR

DBGU

GPBR

EBI

Reduced

Static

Memory

Controller

TWI0

TWI1

TWI2

USART0

USART1

USART2

USART3

4-CH

PWM

Osc12 MHz

POR

RTC

Trans

Trans HS

Trans

DDR2

LPDDR2

512 MB

12-CH

12-bit ADC

TouchScreen

SSC0

SSC1

PIO

NAND Flash

Controller

MCL/SLC

ECC

(4 KB SRAM)

HS EHCI

USB HOST

Cortex-A5

Multi-Layer Matrix

JTAG / SWD

In-Circuit Emulator

MMU

BIU

I/D

ICache

32 KB DCache

32 KB

SRAM0

64 KB

LCD

DMA DMA

ISI

DMADMADMA

GMAC

10/100/1000

8-CH

DMA0

PB PA

VFP PC

CAN0

CAN1

8-CH

DMA1 Peripheral

Bridges

TRNG SHA

AES

TDES

PIO

MCI0/MCI1/MCI2

SD/SDIO

eMMC

HS USB

Device

PIO

DMA

EMAC

10/100

UART0

UART1

DDR_D0-DDR_D31

DDR_A0-DDR_A13

DDR_CS

DDR_CKE

DDR_RAS, DDR_CAS

DDR_CLK,DDR_CLKN

DDR_DQSN[3..0]

DDR_DQM[3..0]

DDR_WE

DDR_BA[2..0]

A0/NBS0

NCS0,NCS1,NCS2

NWR1/NBS1

A1-A20

NWAIT

NCS3/NANDCS

MCI1_DA[3..0]

MCI2_DA[3..0]

MCI0_CK

MCI0_DA[7..0]

MCI0_CDA

MCI1_CDA

MCI2_CDA

MCI1_CK

MCI2_CK

A21/NANDALE

A22/NANDCLE

VBG

DHSDM/HHSDMA

HHSDMB

HHSDMC

HHSDPC

LCD-DAT0-LCD_DAT23

LCD_VSYNC, LCD_HSYNC

LCD_PCK, LCD_DISP

LCD_DEN,LCD_PWM

ISI_PCK

ISI_DO-ISI_D11

ISI_HSYNC, ISI_VSYNC

GTXCK-GRXCK

GTXEN-GTXER

GCRS, GCOL

GRXER-GRXDV

GRX0-GRX7

GTX0-GTX7

GMDC, GMDIO

EREFCK

ETXEN

ECRSDV, ERXER

ERX0-ERX1

ETX0-ETX1

EMDC, EMDIO

TDI

TDO

TMS/SWDIO

TCK/SWCLK

JTAGSEL

NTRST

FIQ

IRQ

DRXD

DTXD

PCK0-PCK2

VDDBU

SHDN

WKUP

XIN

NRST

XOUT

XIN32

XOUT32

TST

TWCK0-TWCK2

TWD0-TWD2

PWMH0-PWMH3

TIOA0-TIOA5

TIOB0-TIOB5

TCLK0-TCLK5

NPCS1,NPCS2,NPCS3

SPCK

MOSI

MISO

NPCS0

SPI0_, SPI1_

TK0-TK1

TF0-TF1

TD0-TD1

RD0-RD1

RF0-RF1

RK0-RK1

CANTX0-CANTX1

CANRX0-CANRX1

RTS0-3

SCK0-3

TXD0-3

RDX0-3

CTS0-3

UTXD0-UTXD1

URDX0-URDX1

TSADTRIG

TSADVREF

GPAD5-GPAD11

AD0UL

AD1UR

AD2LL

AD3LR

AD4PI

12 MHZ

RC Osc

HHSDPB

DHSDP/HHSDPA

DIBN

DIBP

SRAM1

64 KB

DDR_DQS[3..0]

BMS

NANDRDY

PWML0-PWML3

PWMFI0-PWMFI3

A23-A25

NRD/NANDOE

NWE/NWR0/NANDWE

D0-D15

G125CK-G125CKO

DDR_CALN

DDR_CALP

DDR_VREF

SMD

TC0, TC1

TC2, TC3

TC4, TC5

SPI0

SPI1

ROM

160 KB

PIOA

PIOC

PIOB

PIOD

PIOE

Real-time

Events

DMA

DMA DMA DMA DMA DMA

DMA

(1)

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

3. Signal Description

Table 3-1 gives details on the signal names classified by peripheral.

Table 3-1. Sign al Description List

Signal Name Function Type Active Level

Clocks, Oscillators and PLLs

XIN Main Oscillator Input Input —

XOUT Main Oscillator Output Output —

XIN32 Slow Clock Oscillator Input Input —

XOUT32 Slow Clock Oscillator Output Output —

VBG Bias Voltage Reference for USB Analog —

PCK0–PCK2 Programmable Clock Output Output —

Shutdown, Wake-up Logic

SHDN Shut-Down Control Output —

WKUP Wake-Up Input Input —

ICE and JTAG

TCK/SWCLK Test Clock/Serial Wire Clock Input —

TDI Test Data In Input —

TDO Test Data Out Output —

TMS/SWDIO Test Mode Select/Serial Wire Input/Output I/O —

JTAGSEL JTAG Selection Input —

Reset/Test

NRST Microcontroller Reset I/O Low

TST Test Mode Select Input —

NTRST Test Reset Signal Input —

BMS Boot Mode Select Input —

Debug Unit - DBGU

DRXD Debug Receive Data Input —

DTXD Debug Tr ansmit Data Output —

Advanced Interrupt Controller - AIC

IRQ External Interrupt Input Input —

FIQ Fast Interrupt Input Input —

PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE

PA0–PAxx Parallel IO Controller A I/O —

PB0–PBxx Parallel IO Controller B I/O —

PC0–PCxx Parallel IO Controller C I/O —

PD0–PDxx Parallel IO Controller D I/O —

PE0–PExx Parallel IO Controller E I/O —

External Bus Interface - EBI

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

D0–D15 Data Bus I/O —

A0–A25 Address Bus Output —

NWAIT External Wait Signal Input Low

Static Memory Controller - HSMC

NCS0–NCS3 Chip Select Lines Output Low

NWR0–NWR1 Write Signal Output Low

NRD Read Signal Output Low

NWE Write Enable Output Low

NBS0–NBS1 Byte Mask Signal Output Low

NANDOE NAND Flash Output Enable Output Low

NANDWE NAND Flash Write Enable Output Low

DDR2/LPD DR Co ntroller

DDR_VREF Reference Voltage Input —

DDR_CALP Positive Calibration Reference Input —

DDR_CALN Negative Calibration Reference Input —

DDR_CK, DDR_CKN DDR2 differential clock Output —

DDR_CKE DDR2 Clock Enable Output High

DDR_CS DDR2 Controller Chip Select Output Low

DDR_BA[2..0] Bank Select Output Low

DDR_WE DDR2 Write Enable Output Low

DDR_RAS, DDR_CAS Row and Column Signal Output Low

DDR_A[13..0] DDR2 Address Bus Output —

DDR_D[31..0] DDR2 Data Bus I/O —

DQS[3..0] Differential Data Strobe I/O —

DQSN[3..0] DQSN must be connected to DDR_VREF for DDR2 memories I/O —

DQM[3..0] Write Data Mask Output —

High Speed Multimedia Card Interface - HSMCI0–2

MCI0_CK, MCI1_CK, MCI2_CK Multimedia Card Clock I/O —

MCI0_CDA, MCI1_CDA, MCI2_CDA Multimedia Card Command I/O —

MCI0_DA[7..0] Multimedia Card 0 Data I/O —

MCI1_DA[3..0] Multimedia Card 1 Data I/O —

MCI2_DA[3..0) Multimedia Card 2 Data I/O —

Table 3-1. Sign al Description List (Continued)

Signal Name Function Type Active Level

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

Universal Synchronou s Asynchronous Receiver Transmitter - USART0–3

SCKx USARTx Serial Clock I/O —

TXDx USARTx Transmit Data Output —

RXDx USARTx Receive Data Input —

RTSx USARTx Request To Send Output —

CTSx USARTx Clear To Send Input —

Universal Asynchronous Receiver Transmitter - UARTx [1..0]

UTXDx UARTx Transmit Data Output —

URXDx UARTx Receive Data Input —

Synchronous Seri al Controller - SSCx [1..0]

TDx SSC Transmit Data Output —

RDx SSC Receive Data Input —

TKx SSC Transmit Clock I/O —

RKx SSC Receive Clock I/O —

TFx SSC Transmit Frame Sync I/O —

RFx SSC Receive Frame Sync I/O —

Timer/Counter - TCx [5..0]

TCLKx TC Channel x External Clock Input Input —

TIOAx TC Channel x I/O Line A I/O —

TIOBx TC Channel x I/O Line B I/O —

Serial Peripheral Interface - SPIx [1..0]

SPIx_MISO Master In Slave Out I/O —

SPIx_MOSI Master Out Slave In I/O —

SPIx_SPCK SPI Serial Clock I/O —

SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low

SPIx_NPCS[3..1] SPI Peripheral Chip Select Output Low

Two-Wire Interface - TWIx [2..0]

TWDx Two-wire Serial Data I/O —

TWCKx Two-wire Serial Clock I/O —

CAN controller - CANx

CANRXx CAN input Input —

CANTXx CAN output Output —

Soft Modem - SMD

DIBN Soft Modem Signal I/O —

DIBP Soft Modem Signal I/O —

Pulse Width Modulation Controller - PWMC

PWMH[3..0] PWM Waveform Output High Output —

Table 3-1. Sign al Description List (Continued)

Signal Name Function Type Active Level

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

PWML[3..0] PWM Waveform Output Low Output —

PWMFIx PWM Fault Input Input —

USB Host High Speed Port - UHPHS

HHSDPA USB Host Port A High Speed Data + Analog —

HHSDMA USB Host Port A High Speed Dat a - Analog —

HHSDPB USB Host Port B High Speed Data + Analog —

HHSDMB USB Host Port B High Speed Dat a - Analog —

HHSDPC USB Host Port C High Speed Data + Analog —

HHSDMC USB Host Port C High Speed Data - Analog —

USB Device High Speed Port - UDPHS

DHSDP USB Device High Speed Data + Analog —

DHSDM USB Device High Speed Data - Analo g —

GIgabit Ethernet 10/100/1000 - GMAC

GTXCK Transmit Clock or Reference Clock Input —

G125CK 125 MHz input Clock Input —

G125CKO 125 MHz output Clock Output —

GTXEN Transmit Enable Output —

GTX[7..0] Transmit Data Output —

GTXER Transmit Coding Error Outp ut —

GRXCK Receive Clock Input —

GRXDV Rece ive Data Valid Input —

GRX[7..0] Receive Data Input —

GRXER Receive Error Input —

GCRS Carrier Sense and Data Valid Input —

GCOL Collision Detect Input —

GMDC Management Data Clock Output —

GMDIO Management Data Input/Output I/O —

RMII Ethernet 10/100 - EMAC

EREFCK Transmit Clock or Reference Clock Input —

ETXEN Transmit Enable Output —

ETX[1..0] Transmit Data Output —

ECRSDV Carrier Sense/Data Valid Input —

ERX[1..0] Receive Data Input —

ERXER Receive Error Input —

EMDC Management Data Clock Output —

EMDIO Management Data Input/Output I/O —

LCD Controller - LCDC

Table 3-1. Sign al Description List (Continued)

Signal Name Function Type Active Level

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

LCDDAT[23..0] LCD Data Bus Output —

LCDVSYNC LCD Vertical Synchronization Output —

LCDHSYNC LCD Horizontal Synchronization Output —

LCDPCK LCD pixel Clock Output —

LCDDEN LCD Data Enable Output —

LCDPWM LCDPWM for Contrast Control Outp ut —

LCDDISP LCD Display ON/OFF Output —

Image Sensor Interface - ISI

ISI_D[11..0] Image Sensor Data Input —

ISI_HSYNC Image Sensor Horizontal Synchro i nput —

ISI_VSYNC Image Sensor Vertical Synchro input —

ISI_PCK Image Sensor Data clock input —

Touch Screen Analog-to-Digital Converter - ADC

AD0UL Upper Left Touch Panel Analog —

AD1UR Upper Right Touch Panel Analog —

AD2LL Lower Left Touch Panel Analog —

AD3LR Lower Right Touch Panel Analog —

AD4PI Panel Input Analog —

AD5–AD11 7 Analog Inputs Analog —

ADTRG ADC Trigger Input —

ADVREF ADC Reference Analog —

Table 3-1. Sign al Description List (Continued)

Signal Name Function Type Active Level

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

4. Package and Pinout

The SAMA5D3 product is available in two packages:

324-ball LFBGA (15 x 15 x 1.4 mm, pitch 0.8 mm)

324-ball TFBGA (12 x 12 x 1.2 mm, pitch 0.5 mm)

4.1 324-ball LFBGA Package (15 x 15 x 1.4 mm, pitch 0.8 mm)

Figure 4-1 shows the ball map of the 324-ball LFBGA package.

Figure 4-1. 324-ball LFBGA Ball Map

1 3 4 5 6 7 8 9 101112131415 1617218

Bottom VIEW

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

4.2 324-ball LFBGA Package Pinout

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package

Pin Power Rail I/O Type

Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State

Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir

Signal, Dir,

PU, PD, HiZ,

E3 VDDIOP0 GPIO PA0 I/O — — LCDDAT0 O — — — — PIO, I, PU, ST

F5 VDDIOP0 GPIO PA1 I/O — — LCDDAT1 O — — — — PIO, I, PU, ST

D2 VDDIOP0 GPIO PA2 I/O — — LCDDAT2 O — — — — PIO, I, PU, ST

F4 VDDIOP0 GPIO PA3 I/O — — LCDDAT3 O — — — — PIO, I, PU, ST

D1 VDDIOP0 GPIO PA4 I/O — — LCDDAT4 O — — — — PIO, I, PU, ST

J10 VDDIOP0 GPIO PA5 I/O — — LCDDAT5 O — — — — PIO, I, PU, ST

G4 VDDIOP0 GPIO PA6 I/O — — LCDDAT6 O — — — — PIO, I, PU, ST

J9 VDDIOP0 GPIO PA7 I/O — — LCDDAT7 O — — — — PIO, I, PU, ST

F3 VDDIOP0 GPIO PA8 I/O — — LCDDAT8 O — — — — PIO, I, PU, ST

J8 VDDIOP0 GPIO PA9 I/O — — LCDDAT9 O — — — — PIO, I, PU, ST

E2 VDDIOP0 GPIO PA10 I/O — — LCDDAT10 O — — — — PIO, I, PU, ST

K8 VDDIOP 0 GPIO PA11 I/O — — LCDDAT11 O — — — — PIO, I, PU, ST

F2 VDDIOP0 GPIO PA12 I/O — — LCDDAT12 O — — — — PIO, I, PU, ST

G6 VDDIOP0 GPIO PA13 I/O — — LCDDAT13 O — — — — PIO, I, PU, ST

E1 VDDIOP0 GPIO PA14 I/O — — LCDDAT14 O — — — — PIO, I, PU, ST

H5 VDDIOP0 GPIO PA15 I/O — — LCDDAT15 O — — — — PIO, I, PU, ST

H3 VDDIOP0 GPIO PA16 I/O — — LCDDAT16 O — — ISI_D0 IPIO, I, PU, ST

H6 VDDIOP0 GPIO PA17 I/O — — LCDDAT17 O — — ISI_D1 I PIO, I, PU, ST

H4 VDDIOP0 GPIO PA18 I/O — — LCDDAT18 OTWD2 I/O ISI_D2 IPIO, I, PU, ST

H7 VDDIOP0 GPIO PA19 I/O — — L CDDAT19 O TWCK2 O ISI_D3 I PIO, I, PU, ST

H2 VDDIOP0 GPIO PA20 I/O — — LCDDAT20 OPWMH0 OISI_D4 IPIO, I, PU, ST

J6 VDDIOP0 GPIO PA21 I/O — — LCDDAT21 O PWML0 O ISI_D5 I PIO, I, PU, ST

G2 VDDIOP0 GPIO PA22 I/O — — LCDDAT22 OPWMH1 OISI_D6 IPIO, I, PU, ST

J5 VDDIOP0 GPIO PA23 I/O — — LCDDAT23 O PWML1 O ISI_D7 I PIO, I, PU, ST

F1 VDDIOP0 GPIO PA24 I/O — — LCDPWM O — — — — PIO, I, PU, ST

J4 VDDIOP0 GPIO PA25 I/O — — LCDDISP O — — — — PIO, I, PU, ST

G3 VDDIOP0 GPIO PA26 I/O — — LCDVSYNC O — — — — PIO, I, PU, ST

J3 VDDIOP0 GPIO PA27 I/O — — LCDHSYNC O — — — — PIO, I, PU, ST

G1 VDDIOP0 GPIO_CLK2 PA28 I/O — — LCDPCK O — — — — PIO, I, PU, ST

K4 VDDIOP0 GPIO PA29 I/O — — LCDDEN O — — — — P IO, I, PU, ST

H1 VDDIOP0 GPIO PA30 I/O — — TWD0 I/O URXD1 IISI_VSYNC IPIO, I, PU, ST

K3 VDDIOP0 GPIO PA31 I/O — — TWCK0 O UTXD1 O ISI_HSYNC I PIO, I, PU, ST

T2 VDDIOP1 GMAC PB0 I/O — — GTX0 OPWMH0 O — — PIO, I, PU, ST

N7 VDDIOP1 GMAC PB1 I/O — — GTX1 O PWML0 O — — PIO, I, PU, ST

T3 VDDIOP1 GMAC PB2 I/O — — GTX2 OTK1 I/O — — PIO, I, PU, ST

N6 VDDIOP1 GMAC PB3 I/O — — GTX3 O TF1 I/O — — PIO, I, PU, ST

P5 VDDIOP1 GMAC PB4 I/O — — GRX0 IPWMH1 O — — PIO, I, PU, ST

T4 VDDIOP1 GMAC PB5 I/O — — GRX1 I PWML1 O — — PIO, I, PU, ST

R4 VDDIOP1 GMAC PB6 I/O — — GRX2 ITD1 O — — PIO, I, PU, ST

U1 VDDIOP1 GMAC PB7 I/O — — GRX3 I RK1 I — — PIO, I, PU, ST

R5 VDDIOP1 GMAC PB8 I/O — — GTXCK IPWMH2 O — — PIO, I, PU, ST

P3 VDDIOP1 GMAC PB9 I/O — — GTXEN O PWML2 O — — PIO, I, PU, ST

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

R6 VDDIOP1 GMAC PB10 I/O — — GTXER ORF1 I/O — — PIO, I, PU, ST

V3 VDDIOP1 GMAC PB11 I/O — — GRXCK I RD1 I — — PIO, I, PU, ST

P6 VDDIOP1 GMAC PB12 I/O — — GRXDV IPWMH3 O — — PIO, I, PU, ST

V1 VDDIOP1 GMAC PB13 I/O — — GRXER I PWML3 O — — PIO, I, PU, ST

R7 VDDIOP1 GMAC PB14 I/O — — GCRS ICANRX1 I — — PIO, I, PU, ST

U3 VDDIOP1 GMAC PB15 I/O — — GCOL I CANTX1 O — — PIO, I, PU, ST

P7 VDDIOP1 GMAC PB16 I/O — — GMDC O — — — — PIO, I, PU, ST

V2 VDDIOP 1 GMAC PB17 I/O — — GMDIO I/O — — — — PIO, I, PU, ST

V5 VDDIOP1 GMAC PB18 I/O — — G125CK I — — — — PIO, I, PU, ST

T6 VDDIOP1 GMAC PB19 I/O — — MCI1_CDA I/O GTX4 O — — PIO, I, PU, ST

N8 VDDIOP1 GMAC PB20 I/O — — MCI1_DA0 I/O GTX5 O — — PIO, I, PU, ST

U4 VDDIOP1 GMAC PB21 I/O — — MCI1_DA1 I/O GTX6 O — — PIO, I, PU, ST

M7 VDDIOP1 GMAC PB22 I/O — — MCI1_DA2 I/O GTX7 O — — PIO, I, PU, ST

U5 VDDIOP1 GMAC PB23 I/O — — MCI1_DA3 I/O GRX4 I — — PIO, I, PU, ST

M8 VDDIOP1 GMAC PB24 I/O — — MCI1_CK I/O GRX5 I — — PIO, I, PU, ST

T5 VDDIOP1 GMAC PB25 I/O — — SCK1 I/O GRX6 I — — PIO, I, PU, ST

N9 VDDIOP1 GMAC PB26 I/O — — CTS1 IGRX7 I — — PIO, I, PU, ST

V4 VDDIOP1 GPIO PB27 I/O — — RTS1 O G125CKO O — — PIO, I, PU, ST

M9 VDDIOP1 GPIO PB28 I/O — — RXD1 I — — — — PIO, I, PU, ST

P8 VDDIOP1 G PIO PB29 I/O — — TXD1 O — — — — PIO, I, PU, ST

M10 VDDIOP0 GPIO PB30 I/O — — DRXD I — — — — PIO, I, PU, ST

R9 VDDIOP0 GPIO PB31 I/O — — DTXD O — — — — PIO, I, PU, ST

D8 VDDIOP0 GPIO PC0 I/O — — ETX0 OTIOA3 I/O — — PIO, I, PU, ST

A4 VDDIOP 0 GPIO PC1 I/O — — ETX1 O TIOB3 I/O — — PIO, I, PU, ST

E8 VDDIOP0 GPIO PC2 I/O — — ERX0 ITCLK3 I — — PIO, I, PU, ST

A3 VDDIOP 0 GPIO PC3 I/O — — ERX1 I TIOA4 I/O — — PIO, I, PU, ST

A2 VDDIOP0 GPIO PC4 I/O — — ETXEN OTIOB4 I/O — — PIO, I, PU, ST

F8 VDDIOP0 GPIO PC5 I/O — — ECRSDV I TCLK4 I — — PIO, I, PU, ST

B3 VDDIOP0 GPIO PC6 I/O — — ERXER ITIOA5 I/O — — PIO, I, PU, ST

G8 VDDIOP0 GPIO PC7 I/O — — EREFCK I TIOB5 I/O — — PIO, I, PU, ST

B4 VDDIOP0 GPIO PC8 I/O — — EMDC OTCLK5 I — — PIO, I, PU, ST

F7 VDDIOP0 GPIO PC9 I/O — — EMDIO I/O — — — — PIO, I, PU, ST

A1 VDDIOP0 GPIO PC10 I/O — — MCI2_CDA I/O — — LCDDAT20 OPIO, I, PU, ST

D7 VDDIOP0 GPIO PC11 I/O — — M CI2_ DA 0 I/O — — LCDDAT19 O PIO, I, PU, ST

C6 VDDIOP0 GPIO PC12 I/O — — MCI2_DA1 I/O TIOA1 I/O LCDDAT18 OPIO, I, PU, ST

E7 VDDIOP0 GPIO PC13 I/O — — MCI2_DA2 I/O TIOB1 I/O LCDDAT17 O PIO, I, PU, ST

B2 VDDIOP0 GPIO PC14 I/O — — MCI2_DA3 I/O TCLK1 ILCDDAT16 OPIO, I, PU, ST

F6 VDDIOP0 MCI_CLK PC15 I/O — — MCI2_CK I/O PCK2 O LCDDAT21 O PIO, I, PU, ST

B1 VDDIOP0 GPIO PC16 I/O — — TK0 I/O — — — — PIO, I, PU, ST

E6 VDDIOP0 GPIO PC17 I/O — — TF0 I/O — — — — PIO, I, PU, ST

C3 VDDIOP0 GPIO PC18 I/O — — TD0 O — — — — PIO, I, PU, ST

D6 VDDIOP0 GPIO PC19 I/O — — RK0 I/O — — — — PIO, I, PU, ST

C4 VDDIOP0 GPIO PC20 I/O — — RF0 I/O — — — — PIO, I, PU, ST

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Pin Power Rail I/O Type

Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State

Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir

Signal, Dir,

PU, PD, HiZ,

SAMA5D3 Series [DATASHEET]

11121C–ATARM–15-Oct-13

D5 VDDIOP0 GPIO PC21 I/O — — RD0 I — — — — PIO, I, PU, ST

C2 VDDIOP0 GPIO PC22 I/O — — SPI1_MISO I/O — — — — PIO, I, PU, ST

G9 VDDIOP0 GPIO PC23 I/O — — SPI1_MOSI I/O — — — — PIO, I, PU, ST

C1 VDDIOP0 GPIO_CLK PC24 I/O — — SPI1_SPCK I/O — — — — PIO, I, PU, ST

H10 VDDIOP0 GPIO PC25 I/O — — SPI1_NPCS0 I/O — — — — PIO, I, PU, ST

H9 VDDIOP0 GPIO PC26 I/O — — SPI1_NPCS1 OTWD1 I/O ISI_D11 IPIO, I, PU, ST

D4 VDDIOP0 GPIO PC27 I/O — — SPI1_NPCS2 O TWCK1 O ISI_D10 I PIO, I, PU, ST

H8 VDDIOP0 GPIO PC28 I/O — — SPI1_NPCS3 OPWMFI0 IISI_D9 IPIO, I, PU, ST

G5 VDDIOP0 GPIO PC29 I/O — — URXD0 I PWMFI2 I ISI_D8 I PIO, I, PU, ST

D3 VDDIOP0 GPIO PC30 I/O — — UTXD0 O — — ISI_PCK OPIO, I, PU, ST

E4 VDDIOP0 GPIO PC31 I/O — — FIQ I PWMFI1 I — — PIO, I, PU, ST

K5 VDDIOP1 GPIO PD0 I/O — — MCI0_CDA I/O — — — — PIO, I, PU, ST

P1 VDDIOP1 GPIO PD1 I/O — — MCI0_DA0 I/O — — — — PIO, I, PU, ST

K6 VDDIOP1 GPIO PD2 I/O — — MCI0_DA1 I/O — — — — PIO, I, PU, ST

R1 VDDIOP1 GPIO PD3 I/O — — MCI0_DA2 I/O — — — — PIO, I, PU, ST

L7 VDDIOP1 GPIO PD4 I/O — — MCI0_DA3 I/O — — — — PIO, I, PU, ST

P2 VDDIOP 1 GPIO PD5 I/O — — MCI0_DA4 I/O TIOA0 I/O PWMH2 O PIO, I, PU, ST

L8 VDDIOP1 GPIO PD6 I/O — — MCI0_DA5 I/O TIOB0 I/O PWML2 OPIO, I, PU, ST

R2 VDDIOP1 GPIO PD7 I/O — — MCI0_DA6 I/O TCLK0 I PWMH3 O PIO, I, PU, ST

K7 VDDIOP1 GPIO PD8 I/O — — MCI0_DA7 I/O — — PWML3 OPIO, I, PU, ST

U2 VDDIOP1 MCI_CLK PD9 I/O — — MCI0_CK I/O — — — — PIO, I, PU, ST

K9 VDDIOP1 GPIO PD10 I/O — — SPI0_MISO I/O — — — — PIO, I, PU, ST

M5 VDDIOP1 GPIO PD11 I/O — — SPI0_MOSI I/O — — — — PIO, I, PU, ST

K10 VDDIOP1 GPIO_CLK PD12 I/O — — SPI0_SPCK I/O — — — — PIO, I, PU, ST

N4 VDDIOP1 GPIO PD13 I/O — — SPI0_NPCS0 I/O — — — — PIO, I, PU, ST

L9 VDDIOP1 GPIO PD14 I/O — — SCK0 I/O SPI0_NPCS1 OCANRX0 IPIO, I, PU, ST

N3 VDDIOP1 GPIO PD15 I/O — — CTS0 I SPI0_NPCS2 O CANTX0 O PIO, I, PU, ST

L10 VDDIOP1 GPIO PD16 I/O — — RTS0 OSPI0_NPCS3 OPWMFI3 IPIO, I, PU, ST

N5 VDDIOP1 GPIO PD17 I/O — — RXD0 I — — — — PIO, I, PU, ST

M6 VDDIOP1 GPIO PD18 I/O — — TXD0 O — — — — PIO, I, PU, ST

T1 VDDIOP1 GPIO PD19 I/O — — ADTRG I — — — — PIO, I, PU, ST

N2 VDDANA GPIO_ANA PD20 I/O — — AD0 I — — — — PIO, I, PU, ST

M3 VDDANA GPIO_ANA PD21 I/O — — AD1 I — — — — PIO, I, PU, ST

M2 VDDANA GPIO_ANA PD22 I/O — — AD2 I — — — — PIO, I, PU, ST

L3 VDDANA GPIO_ANA PD23 I/O — — AD3 I — — — — PIO, I, PU, ST

M1 VDDANA GPIO_ANA PD24 I/O — — AD4 I — — — — PIO, I, PU, ST

N1 VDDANA GPIO_ANA PD25 I/O — — AD5 I — — — — PIO, I, PU, ST

L1 VDDANA GPIO_ANA PD26 I/O — — AD6 I — — — — PIO, I, PU, ST

L2 VDDANA GPIO_ANA PD27 I/O — — AD7 I — — — — PIO, I, PU, ST

K1 VDDANA GPIO_ANA PD28 I/O — — AD8 I — — — — PIO, I, PU, ST

K2 VDDANA GPIO_ANA PD29 I/O — — AD9 I — — — — PIO, I, PU, ST

J1 VDDANA GPIO_ANA PD30 I/O — — AD10 IPCK0 O — — PIO, I, PU, ST

J2 VDDANA GPIO_ANA PD31 I/O — — AD11 I PCK1 O — — PIO, I, PU, ST

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Pin Power Rail I/O Type

Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State

Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir

Signal, Dir,

PU, PD, HiZ,