DM54165J/883 - NATIONAL SEMICONDUCTOR

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TL/F/9782

54165/DM74165 8-Bit Parallel-to-Serial Converter

August 1989

54165/DM74165

8-Bit Parallel-to-Serial Converter

General Description

The ’165 is an 8-bit parallel load or serial-in register with

complementary outputs available from the last stage. Paral-

lel inputting occurs asynchronously when the Parallel Load

(PL) input is LOW. With PL HIGH, serial shifting occurs on

the rising edge of the clock; new data enters via the Serial

Data (DS) input. The 2-input OR clock can be used to com-

bine two independent clock sources, or one input can act as

an active LOW clock enable.

Connection Diagram

Dual-In-Line-Package

TL/F/9782–1

Order Number 54165DMQB, 54165FMQB or DM74165N

See NS Package Number J16A, N16E or W16A

Logic Symbol

TL/F/9782–2

VCC ePin 16

GND ePin 8

Pin Names Description

CP1, CP2 Clock Pulse Inputs (Active Rising Edge)

DSSerial Data Input

PL Asynchronous Parallel Load Input

(Active LOW)

P0– P7 Parallel Data Inputs

Q7 Serial Output from Last Stage

Q7 Complementary Output

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

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Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range

54 b55§Ctoa

125§C

DM74 0§Ctoa

70§C

Storage Temperature Range b65§Ctoa

150§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter 54165 DM74165 Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.8 0.8 V

IOH High Level Output Current b0.8 b0.8 mA

IOL Low Level Output Current 16 16 mA

TAFree Air Operating Temperature b55 125 0 70 §C

ts(H) Setup Time HIGH or LOW 10 10 ns

ts(L) Pnto PL 10 10

th(H) Hold Time HIGH or LOW 10 0 ns

th(L) Pnto PL 10 0

ts(H) Setup Time HIGH or LOW 20 20 ns

ts(L) DSto CPn20 20

th(H) Hold Time HIGH or LOW 0 0 ns

th(L) DSto CPn00

(H) Setup Time HIGH 30 30 ns

CP1 to CP2 or CP2 to CP1

tw(H) CPnPulse Width HIGH 25 25 ns

tw(L) PL Pulse Width LOW 15 15 ns

trec Recovery Time, PL to CPn45 45 ns

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

12 mA b1.5 V

VOH High Level Output Voltage VCC eMin, IOH eMax, VIL eMax 2.4 3.4 V

VOL Low Level Output Voltage VCC eMin, VIH eMin 0.2 0.4 V

IIInput Current @Max VCC eMax, VIe5.5V 1mA

Input Voltage

IIH High Level Input Current VCC eMax, VIe2.4V PL 80 mA

Inputs 40

IIL Low Level Input Current VCC eMax, VIe0.4V PL b3.2 mA

Inputs b1.6

IOS Short Circuit VCC eMax 54 b20 b55 mA

Output Current (Note 2) DM74 b18 b55

ICC Supply Current VCC eMax, PL eß63 mA

PneK,CP

,CP

2e4.5V

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Switching Characteristics

VCC ea

5.0V, TAea

25§C (See Section 1 for waveforms and load configurations)

CLe15 pF

Symbol Parameter RLe400XUnits

Min Max

fmax Maximum Clock Frequency 20 MHz

tPLH Propagation Delay 31 ns

tPHL PL to Q7 or Q740

PLH Propagation Delay 24 ns

tPHL CP1 to Q7 or Q731

PLH Propagation Delay 17 ns

tPHL P7 to Q7 36

tPLH Propagation Delay 27 ns

tPHL P7 to Q727

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time.

Functional Description

The ’165 contains eight clocked master/slave RS flip-flops

connected as a shift register with auxiliary gating to provide

overriding asynchronous parallel entry. Parallel data enters

when the PL signal is LOW. The parallel data can change

while PL is LOW provided that the recommended setup and

hold times are observed.

For clocked operation, PL must be HIGH. The two clock

inputs perform identically; one can be used as a clock inhibit

by applying a HIGH signal. To avoid double clocking, how-

ever, the inhibit signal should only go HIGH while the clock

is HIGH. Otherwise, the rising inhibit signal will cause the

same response as a rising clock edge. The flip-flops are

edge-triggered for serial operations. The serial input data

can change at any time, provided only that the recommend-

ed setup and hold times are observed, with respect to the

rising edge of the clock.

Truth Table

PL CP Contents Response

1 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

L X X P0 P1 P2 P3 P4 P5 P6 P7 Parallel Entry

HLLD

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Right Shift

HHLQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 No Change

HLLD

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Right Shift

HLH Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 No Change

HeHIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

LePositive Rising Edge

Logic Diagram

TL/F/9782–3

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Physical Dimensions inches (millimeters)

16-Lead Ceramic Dual-In-Line Package (J)

Order Number 54165DMQB

NS Package Number J16A

16-Lead Molded Dual-In-Line Package (N)

Order Number DM74165N

NS Package Number N16E

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54165/DM74165 8-Bit Parallel-to-Serial Converter

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (W)

Order Number 54165FMQB

NS Package Number W16A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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