1
FEATURES DESCRIPTION
APPLICATIONS
75W
75W
75W
75W
RGB
Channel0
75W
75W
75W
RGB
Channel1
75W
75W
RGB
Out
+5V
-5V EN
Channel
Select
OPA3875
(Patented)
RGBSwitching
OPA3875
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............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
Triple 2:1 High-Speed Video Multiplexer
2
•700MHz SMALL-SIGNAL BANDWIDTH
The OPA3875 offers a very wideband, 3-channel, 2:1(A
V
= +2)
multiplexer in a small SSOP-16 package. Using only11mA/ch, the OPA3875 provides three, gain of +2,•425MHz, 4V
PP
BANDWIDTH
video amplifier channels with greater than 400MHz•0.1dB GAIN FLATNESS to 150MHz
large-signal bandwidth (4V
PP
). Gain accuracy and•4ns CHANNEL SWITCHING TIME
switching glitch are improved over earlier solutionsusing a new (patented) input stage switching•LOW SWITCHING GLITCH: 40mV
PP
approach. This technique uses current steering as the•3100V/ µs SLEW RATE
input switch while maintaining an overall closed-loop•0.025%/0.025 ° DIFFERENTIAL GAIN, PHASE
design. Gain matching between each of the3-channel pairs is also significantly improved using•HIGH GAIN ACCURACY: 2.0V/V ± 0.4%
this technique ( < 0.2% gain mismatch). With greaterthan 700MHz small-signal bandwidth at a gain of 2,the OPA3875 gives a typical 0.1dB gain flatness to•RGB SWITCHING
greater than 150MHz.•LCD PROJECTOR INPUT SELECT
System power may be reduced using the chip enable•WORKSTATION GRAPHICS
feature for the OPA3875. Taking the chip enable line•TRIPLE ADC INPUT MUX
high powers down the OPA3875 to less than 900 µA•DROP-IN UPGRADE TO LT1675
total supply current. Muxing multiple OPA3875outputs together, then using the chip enable to selectwhich channels are active, increases the number ofpossible inputs to the 3-channel outputs.
Where a single channel of the OPA3875 is required,consider the OPA875 .
OPA3875
SELECT ENABLE RED OUT GREEN OUT BLUE OUT
1 0 R0 G0 B00 0 R1 G1 B1X 1 Off Off Off
OPA3875 RELATED PRODUCTS
DESCRIPTION
OPA875 Single-Channel OPA3875OPA4872 Quad 510MHz 4:1 MultiplexerOPA3693 Triple 650MHz Video Buffer
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V+
OUT_R
OUT_G
OUT_B
V-
V-
SEL
EN
R0
G0
B0
GND
GND
R1
G1
B1
SSOP-16
x2
x2
x2
OPA3875
TopView SSOP
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORTPRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
OPA3875IDBQ Rails, 75OPA3875 SSOP-16 DBQ – 45 ° C to +85 ° C OP3875
OPA3875IDBQR Tape and Reel, 2500
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
Over operating temperature range, unless otherwise noted.
OPA3875 UNIT
Power Supply ± 6.5 VInternal Power Dissipation See Thermal AnalysisInput Voltage Range ± V
S
VStorage Temperature Range – 65 to +125 ° CLead Temperature (soldering, 10s) +260 ° COperating Junction Temperature +150 ° CContinuous Operating Junction Temperature +140 ° CESD Rating:
Human Body Model (HBM) 2000 VCharge Device Model (CDM) 1500 VMachine Model (MM) 200 V
PIN CONFIGURATION
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ELECTRICAL CHARACTERISTICS: V
S
= ± 5V
OPA3875
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............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
At G = +2, R
L
= 150 Ω, unless otherwise noted.
OPA3875
MIN/MAX OVERTYP TEMPERATURE
0 ° C to – 40 ° C to MIN/ TESTPARAMETER CONDITIONS +25 ° C +25 ° C
(2)
70 ° C
(3)
+85 ° C
(3)
UNITS MAX LEVEL
(1)
AC PERFORMANCE See Figure 1
Small-Signal Bandwidth V
O
= 200mV
PP
, R
L
= 150 Ω700 525 515 505 MHz min B
Large-Signal Bandwidth V
O
= 4V
PP
, R
L
= 150 Ω425 390 380 370 MHz min B
Bandwidth for 0.1dB Gain Flatness V
O
= 200mV
PP
150 MHz typ C
Maximum Small-Signal Gain V
O
= 200mV
PP
, R
L
= 150 Ω, f = 5MHz 2.0 2.02 2.03 2.05 V/V max B
Minimum Small-Signal Gain V
O
= 200mV
PP
, R
L
= 150 Ω, f = 5MHz 2.0 1.98 1.97 1.95 V/V min B
SFDR 10MHz, V
O
= 2V
PP
, R
L
= 150 Ω– 68 – 65 – 64 – 63 dBc max B
Input Voltage Noise f > 100kHz 6.7 7.0 7.2 7.4 nV/ √Hz max B
Input Current Noise f > 100kHz 3.8 4.2 4.6 4.9 pA/ √Hz max B
NTSC Differential Gain R
L
= 150 Ω0.025 % typ C
NTSC Differential Phase R
L
= 150 Ω0.025 ° typ C
Slew Rate V
O
= ± 2V 3100 2800 2700 2600 V/ µs min B
Rise Time and Fall Time V
O
= 0.5V Step 460 ps typ C
V
O
= 1.4V Step 600 ps typ C
CHANNEL-TO-CHANNEL PERFORMANCE
Gain Match Channel to Channel, R
L
= 150 Ω± 0.05 ± 0.25 ± 0.3 ± 0.35 % max A
All inputs, R
L
= 150 Ω± 0.1 ± 0.5 ± 0.6 ± 0.7 % max A
Output Offset Voltage Mismatch All three outputs ± 3 ± 9 ± 10 ± 12 mV max A
All Hostile Crosstalk f = 50MHz, R
L
= 150 Ω– 50 dB typ C
Channel-to-Channel Crosstalk f = 50MHz, R
L
= 150 Ω– 58 dB typ C
CHANNEL AND CHIP-SELECT PERFORMANCE
SEL (Channel Select) Swtiching Time R
L
= 150 Ω4 ns typ C
EN (Chip Select) Switching Time Turn On 9 ns typ C
Turn Off 60 ns typ C
SEL (Channel Select) Switching Glitch All Inputs to Ground, At Matched Load 40 mV
PP
typ C
EN (Chip-Select) Switching Glitch All Inputs to Ground, At Matched Load 15 mV
PP
typ C
All Hostile Disable Feedthrough 50MHz, Chip Disabled ( EN = High) – 68 dB typ C
Maximum Logic 0 EN, SEL 0.8 0.8 0.8 V max B
Minimum Logic 1 EN, SEL 2.0 2.0 2.0 V min B
EN Logic Input Current 0V to 4.5V 75 100 125 150 µA max A
SEL Logic Input Current 0V to 4.5V 160 200 250 300 µA max A
DC PERFORMANCE
Output Offset Voltage R
IN
= 0 Ω, G = +2V/V ± 2.5 ± 14 ± 15.8 ± 17 mV max A
Average Output Offset Voltage Drift R
IN
= 0 Ω, G = +2V/V ± 50 ± 50 µV/ ° C max B
Input Bias Current ± 5 ± 18 ± 19.5 ± 20.5 µA max A
Average Input Bias Current Drift ± 40 ± 40 nA/ ° C max B
Gain Error (from 2V/V) V
O
= ± 2V 0.4 1.4 1.5 1.6 % max A
INPUT
Input Voltage Range ± 2.8 V typ C
Input Resistance 1.75 M Ωtyp C
Input Capacitance Channel Selected 0.9 pF typ C
Channel Deselected 0.9 pF typ C
Chip Disabled 0.9 pF typ C
(1) Test levels: (A) 100% tested at +25 ° C. Over temperature limits set by characterization and simulation. (B) Limits set by characterizationand simulation. (C) Typical value only for information.(2) Junction temperature = ambient for +25 ° C tested specifications.(3) Junction temperature = ambient at low temperature limit; junction temperature = ambient +36 ° C at high temperature limit for overtemperature specifications.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
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OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
= ± 5V (continued)At G = +2, R
L
= 150 Ω, unless otherwise noted.
OPA3875
MIN/MAX OVERTYP TEMPERATURE
0 ° C to – 40 ° C to MIN/ TESTPARAMETER CONDITIONS +25 ° C +25 ° C
(2)
70 ° C
(3)
+85 ° C
(3)
UNITS MAX LEVEL
(1)
OUTPUT
Output Voltage Range ± 3.5 ± 3.4 ± 3.35 ± 3.3 V min A
Output Current V
O
= 0V, Linear Operation ± 70 ± 50 ± 45 ± 40 mA min A
Output Resistance Chip enabled 0.3 Ωtyp C
Chip Disabled, Maximum 800 912 915 918 Ωmax A
Chip Disabled, Minumum 800 688 685 682 Ωmin A
Output Capacitance Chip Disabled 2 pF typ C
POWER SUPPLY
Specified Operating Voltage ± 5 V typ C
Minimum Operating Voltage ± 3.0 ± 3.0 ± 3.0 V min B
Maximum Operating Voltage ± 6.3 ± 6.3 ± 6.3 V max A
Maximum Quiescent Current Chip Selected, V
S
= ± 5V 33 34 35 36 mA max A
Minimum Quiescent Current Chip Selected, V
S
= ± 5V 33 31 30 27 mA min A
Maximum Quiescent Current Chip Deselected 0.9 1.2 1.4 1.5 mA max A
Power-Supply Rejection Ratio (+PSRR) Input-Referred 56 50 48 47 dB min A
( – PSRR) Input-Referred 55 51 49 48 dB min A
THERMAL CHARACTERISTICS
Specified Operating Range D Package – 40 to +85 ° C typ C
Thermal Resistance θ
JA
Junction-to-Ambient
DBQ SSOP-16 85 ° C/W typ C
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TYPICAL CHARACTERISTICS: V
S
= ± 5V
7
6
1
4
3
2
1
0
Gain(dB)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
NormalizedGainFlatness(dB)
Frequency(Hz)
1M 10M 100M 1G
VO PP
=500mV
RW
L=150
G=+2V/V
GainFlatness
RightScale
FrequencyResponse
LeftScale
8
7
6
5
4
3
2
1
0
-1
-2
-3
Gain(dB)
Frequency(100MHz/div)
0 100 200 300 400 500 600 700 800 900 1000
R =150W
L
G=+2V/V
V =4V
O PP
V =5V
O PP V =2V
O PP
V =1V
O PP
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
Small-SignalOutputVoltage(V)
Large-SignalOutputVoltage(V)
Time(1ns/div)
Large-Signal4VPP
RightScale
Small-Signal0.4VPP
LeftScale
R =150W
L
G=+2V/V
100MHzSquare-WaveInput
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
Isolation(dB)
Frequency(Hz)
1M 10M 100M 1G
Input-Referred
=+5V
EN
80
70
60
50
40
30
20
10
0
R )W(
S
CapacitiveLoad(pF)
1 10 100 1000
8
7
6
5
4
3
2
1
0
-1
-2
-3
GaintoCapacitiveLoad(dB)
Frequency(MHz)
1 10 100 400
0.1dBPeakingTargeted
C =47pF
L
C =100pF
L
C =10pF
L
C =22pF
L
RS
75W
1kW(1)
CL
75W
NOTE:(1)1k isoptional.W
x2
OPA3875
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............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
At G = +2 and R
L
= 150 Ω, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE
Figure 1. Figure 2.
NONINVERTING PULSE RESPONSE ALL INPUT DISABLE FEEDTHROUGH vs FREQUENCY
Figure 3. Figure 4.
RECOMMENDED R
S
vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD
Figure 5. Figure 6.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
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-60
-65
-70
-75
-80
-85
-90
HarmonicDistortion(dBc)
Resistance( )W
100 1k
V =2V
O PP
f=10MHz
2nd-Harmonic
3rd-Harmonic
dBc=dBBelowCarrier
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
HarmonicDistortion(dBc)
SupplyVoltage( V)±
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V =2V
O PP
R =150W
L
f=10MHz
3rd-Harmonic
2nd-Harmonic
dBc=dBBelowCarrier
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
HarmonicDistortion(dBc)
Frequency(MHz)
1 10 100
V =2V
O PP
R =150
LW
2nd-Harmonic
3rd-Harmonic
dBc=dBBelowCarrier
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
HarmonicDistortion(dBc)
OutputVoltageSwing(V )
PP
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.0
R =150
LW
f=10MHz
dBc=dBBelowCarrier
2nd-Harmonic
3rd-Harmonic
-50
-60
-70
-80
-90
-100
Third-OrderSpuriousLevel(dBc)
Single-ToneLoadPower(dBm)
-6-4-2 0 2 4 6 8 10
R =100W
L
LoadPoweratMatched50 LoadW
dBc=dBBelowCarrier
50MHz
20MHz 10MHz
5
4
3
2
1
0
-1
-2
-3
-4
-5
V (V)
OUT
I (mA)
O
-200 -150 -100 -50 0 50 100 150 200
1WInternal
PowerLimit
1WInternal
PowerLimit
50 LoadLineW
100 LoadLineW
25 LoadLineW
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At G = +2 and R
L
= 150 Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs SUPPLY VOLTAGE
Figure 7. Figure 8.
HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE
Figure 9. Figure 10.
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS OUTPUT VOLTAGE AND CURRENT LIMITIATIONS
Figure 11. Figure 12.
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1.5
1.0
0.5
0
-0.5
-1.0
-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
OutputVoltage(V)
ChannelSelect(V)
Time(5ns/div)
OutputVoltage
VSEL
RL=150W
V Ch1=400MHz,1V
IN_ PP
V Ch0=0V
IN_ DC
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
OutputVoltage(V)
ChannelSelect(V)
Time(5ns/div)
OutputVoltage
VSEL
VIN_ DC
Ch0=+0.5V
V Ch1= 0.5V-
IN_ DC
6
4
2
0
-2
OutputVoltage(mV)
ChannelSelect(V)
Time(10ns/div)
AtMatchedLoad
(0Vinputbothchannels)
VSEL
40
30
20
10
0
-10
-20
6
4
2
0
-2
OutputVoltage(V)
EnableVoltage(V)
Time(100ns/div)
AtMatchedLoad
VEN
20
15
10
5
0
-5
-10
-20
-30
-40
-50
-60
-70
-80
-90
Crosstalk(dB)
Frequency(Hz)
1M 10M 100M 1G
Input-Referred
B0Selected
B1Driven
R1Selected
R0Driven
OPA3875
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............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At G = +2 and R
L
= 150 Ω, unless otherwise noted.
CHANNEL SWITCHING CHANNEL-TO-CHANNEL SWITCHING TIME
Figure 13. Figure 14.
CHANNEL SWITCHING GLITCH DISABLE/ENABLE TIME
Figure 15. Figure 16.
DISABLE/ENABLE SWITCHING GLITCH CHANNEL-TO-CHANNEL CROSSTALK
Figure 17. Figure 18.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): OPA3875
0
-10
-20
-30
-40
-50
-60
-70
-80
Crosstalk(dB)
Frequency(Hz)
1M 10M 100M 1G
AdjacentChannelCrosstalk
AllHostileCrosstalk
Input-Referred
10k
1k
100
10
1
0.1
OutputImpedance( )W
Frequency(Hz)
100k 1M 10M 100M 1G
Disabled
Enabled
10M
1M
100k
10k
1k
100
InputImpedance( )
W
Frequency(Hz)
100k 1M 10M 100M 1G
60
50
40
30
20
10
0
Power-SupplyRejectionRatio(dB)
Frequency(Hz)
100 1k 10k 100k 1M 10M 100M 1G
-PSRR
+PSRR
40
38
36
34
32
30
28
26
24
22
20
SupplyCurrent(mA)
AmbientTemperature( C)°
-50 -25 0 25 50 75 100 125
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
OutputOffsetVoltage(mV)
InputBiasCurrent( A)m
AmbientTemperature( C)°
-50 -25 0 25 50 75 100 125
InputBiasCurrent(I )
B
RightScale
OutputOffsetVoltage(V )
OS
LeftScale
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At G = +2 and R
L
= 150 Ω, unless otherwise noted.
ALL HOSTILE AND ADJACENT-CHANNEL CROSSTALK vsFREQUENCY CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Figure 19. Figure 20.
INPUT IMPEDANCE vs FREQUENCY PSRR vs FREQUENCY
Figure 21. Figure 22.
SUPPLY CURRENT vs TEMPERATURE TYPICAL DC DRIFT OVER TEMPERATURE
Figure 23. Figure 24.
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Product Folder Link(s): OPA3875
100
10
1
VoltageNoise(nV/ )ÖHz
Currentnoise(pA/ )ÖHz
Frequency(Hz)
10 100 1k 10k 100k 1M 10M 100M
VoltageNoise(6.7nV/ )ÖHz
InputCurrentNoise(3.8pA/ )ÖHz
OPA3875
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............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At G = +2 and R
L
= 150 Ω, unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE
Figure 25.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
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APPLICATIONS INFORMATION
2:1 HIGH-SPEED VIDEO MULTIPLEXER
LOGO INSERTER
RGB VIDEO INVERTER
75W
75W
75W
+5V
-5V EN
Channel
Select
1/3OPA3875
x1
x1
VIN_1
VOUT
VIN_2
402W
402W
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
www.ti.com
that the 75 Ωinput matching impedance is set here bythe parallel combination of 92 Ωand 402 Ω. In ordernot to disturb the sync, color burst, and blanking ifOPERATION
present, the inverting amplifiers are only switched onThe OPA3875 can be used as a triple 2:1 high-speed
during active video.video multiplexer, as illustrated in the front pageschematic for an RGB signal. Figure 26 shows asimplified version of the front page schematic inwhich one output is shown with its input and output Figure 28 illustrates the principle of overlaying aimpedance matching resistors. picture in a picture. The picture comes through U1;the signal to be overlayed comes through U2. Herewe have a reference voltage of 0.714V in channel 2indicating that we will highlight a section of the pictureFigure 27 illustrates an extension of the previously
with white (for NTSC-related RGB video). How muchshown RGB switching circuit with a noninverting
white comes through depends on the combination ofsignal going through channel 1 and an inverted signal
select 1 and select 2 pins as well as the series outputgoing through channel two. Here, the output
resistance of each OPA3875. To match the 75 Ωimpedance of the OPA3875 is set to 75 Ω. Looking at
output impedance of the video cable, the parallelthe input part of this circuit, we see that the RGB
combination of the series output resistance (R andsignal is inverted with an OPA3693 fixed gain set in
nR) needs to be 75 Ω. The two select pins gives us 2an inverting configuration with a reference voltage on
bits of control. By selecting n = 2, you have thethe noninverting node. The reference voltage, set
capability of a 0% highlight (full original video signal),here at 0.714V, has a gain of 1 at the output of the
33% highlight, 66% highlight, and 100% highlight (allOPA3691 as the input signal is AC-coupled (not
white). By selecting n = 3, you have 0%, 25%, 75%,represented here). This bias voltage is required to
and 100% highlight capabilities, etc.prevent the video from swinging negative. Note also
Figure 26. Triple 2:1 High-Speed Video Multiplexer
10 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3875
92W75W
+5V
-5V EN
Channel
Select
OPA3875
x1
RIN
ROUT
75W
GOUT
75W
BOUT
92W
x1
GIN
92W
x1
BIN
VREF
VREF
VREF
x1
300W
300W
1/3
OPA3693
x1
300W
300W
1/3
OPA3693
x1
300W
300W
1/3
OPA3693
V =0.749V
REF
402W
402W
402W
402W
402W
402W
OPA3875
www.ti.com
............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
Figure 27. RGB Video Inverter
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): OPA3875
75W
RO
+5V
-5V EN
OPA3875
x1
RIN
ROUT
RO
GOUT
RO
BOUT
75W
x1
GIN
75W
x1
Select1
Select2
x1
x1
x1
VREF
nRO
-5V EN
OPA3875
x1
nRO
nRO
x1
x1
x1
x1
x1
VREF
V =0.714V
R ||nR =75
REF
O O W
BIN
U2
U1
402W
402W
402W
402W
402W
402W
402W
402W
402W
402W
402W
402W
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
www.ti.com
Figure 28. Logo Inserter
12 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3875
ADC INPUT MUX
250W
250W
1/2
ADS5232
VCC
+3.3V
250W
250W
+5V
-5V Channel
Select
EN
OPA3875
x1
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
x1
x1
x1
x1
x1
IN
IN
250W
250W
1/2
ADS5232
VCC
+3.3V
250W
250W
IN
IN
250W
250W
1/2
ADS5232
VCC
+3.3V
250W
250W
IN
IN
VCM
VCM
VCM
402W
402W
402W
402W
402W
402W
OPA3875
www.ti.com
............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
Figure 29 shows the OPA3875 used as a multiplexer in a high-speed data acquisition signal chain.
Figure 29. ADC Input Multiplexer
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): OPA3875
DESIGN-IN TOOLS
DEMONSTRATION FIXTURE
MACROMODELS AND APPLICATIONS
DC ACCURACY
V =V +(R I )xG 5 (V ) x10±| |
OSO_envelope OSO S b S+
-·-PSRR+
20
PSRR-
20
CMRR
20
±| |5 (V ) x10 +V x10
S+
- - CM
- -
OPERATING SUGGESTIONS
DRIVING CAPACITIVE LOADS
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
www.ti.com
problem have been suggested. When the primaryconsiderations are frequency response flatness,pulse response fidelity, and/or distortion, the simplestand most effective solution is to isolate the capacitiveload from the feedback loop by inserting a seriesA printed circuit board (PCB) is available to assist in
isolation resistor between the amplifier output and thethe initial evaluation of circuit performance using the
capacitive load. This isolation resistor does notOPA3875. The fixture is offered free of charge as an
eliminate the pole from the loop response, but ratherunpopulated PCB, delivered with a user's guide. The
shifts it and adds a zero at a higher frequency. Thesummary information for this fixture is shown in
additional zero acts to cancel the phase lag from theTable 1 .
capacitive load pole, thus increasing the phasemargin and improving stability.Table 1. OPA3875 Demonstration Fixture
LITERATURE
The Typical Characteristics show the recommendedPRODUCT PACKAGE ORDERING NUMBER NUMBER
R
S
versus capacitive load and the resulting frequencyOPA3875IDBQ SSOP-16 DEM-OPA-SSOP-3E SBOU043
response at the load; see Figure 5 and Figure 6 ,respectively. Parasitic capacitive loads greater thanThe demonstration fixture can be requested at the
2pF can begin to degrade the performance of theTexas Instruments web site at (www.ti.com ) through
OPA3875. Long PCB traces, unmatched cables, andthe OPA3875 product folder.
connections to multiple devices can easily cause thisvalue to be exceeded. Always consider this effectcarefully, and add the recommended series resistoras close as possible to the OPA3875 output pin (seethe Board Layout Guidelines section).SUPPORT
Computer simulation of circuit performance usingSPICE is often useful when analyzing the
The OPA3875 offers excellent DC signal accuracy.performance of analog circuits and systems. This is
Parameters that influence the output DC offsetparticularly true for video and RF amplifier circuits
voltage are:where parasitic capacitance and inductance can havea major effect on circuit performance. A SPICE model •Output offset voltagefor the OPA875 is available through the Texas
•Input bias currentInstruments web site at www.ti.com . Use three of
•Gain errorthese models to simulate the OPA3875. These
•Power-supply rejection ratiomodels do a good job of predicting small-signal AC
•Temperatureand transient performance under a wide variety ofoperating conditions. They do not do as well in
Leaving both temperature and gain error parameterspredicting the harmonic distortion or dG/dP
aside, the output offset voltage envelope can becharacteristics. These models do not attempt to
described as shown in Equation 1 :distinguish between the package types in theirsmall-signal AC performance nor do they predictchannel-to-channel effects.
(1)
With:
V
OSO
:Output offset voltageR
S
:Input resistance seen by R0, R1, G0, G1, B0,or B1.One of the most demanding, yet very common loadconditions is capacitive loading. Often, the capacitive
I
b
:Input bias currentload is the input of an ADC — including additional
G: Gainexternal capacitance that may be recommended to
V
S+
:Positive supply voltageimprove ADC linearity. A high-speed device such as
V
S –
:Negative supply voltagethe OPA3875 can be very susceptible to decreasedstability and closed-loop response peaking when a
PSRR+: Positive supply PSRRcapacitive load is placed directly on the output pin.
PSRR – : Negative supply PSRRWhen the device open-loop output resistance isconsidered, this capacitive load introduces anadditional pole in the signal path that can decreasethe phase margin. Several external solutions to this
14 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3875
NOISE PERFORMANCE
± ±14mV+75 xW18 Ax2m ± | |5 6 x10-
50
20
-
51
20
-
± -5 ( 6) x10| |- -
=±22.7mV
(2)
DISTORTION PERFORMANCE
+5V
-5V Channel
Select
EN
1/3OPA3875
x1
x1
en
ib
RS
eRS
eo
4kTRS
402W
402W
e =2
oe +(i R ) +4kTR
n b S S
2 2
(3)
e =
ne +(i R ) +4kTR
n Sb S
2 2
(4)
OPA3875
www.ti.com
............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
Evaluating the front-page schematic, using aworst-case, +25 ° C offset voltage, bias current and
The OPA3875 offers an excellent balance betweenPSRR specifications and operating at ± 6V, gives a
voltage and current noise terms to achieve low outputworst-case output equal to Equation 2 :
noise. As long as the AC source impedance lookingout of the noninverting node is less than 100 Ω, thiscurrent noise will not contribute significantly to thetotal output noise. Figure 30 shows this device noiseanalysis model with all the noise terms included. Inthis model, all noise terms are taken to be noisevoltage or current density terms in either nV/ √Hz orpA/ √Hz.
The OPA3875 provides good distortion performanceinto a 100 Ωload on ± 5V supplies. Relative toalternative solutions, it provides exceptionalperformance into lighter loads. Generally, until thefundamental signal reaches very high frequency orpower levels, the 2nd-harmonic dominates thedistortion with a negligible 3rd-harmonic component.Focusing then on the 2nd-harmonic, increasing theload impedance improves distortion directly. Also,providing an additional supply decoupling capacitor(0.01 µF) between the supply pins (for bipolaroperation) improves the 2nd-order distortion slightly(3dB to 6dB).
In most op amps, increasing the output voltage swingincreases harmonic distortion directly. The Typical
Figure 30. Noise ModelCharacteristics show the 2nd-harmonic increasing ata little less than the expected 2X rate while the3rd-harmonic increases at a little less than the
The total output spot noise voltage can be computedexpected 3X rate. Where the test power doubles, the
as the square root of the sum of all squared output2nd-harmonic increases only by less than the
noise voltage contributors. Equation 3 shows theexpected 6dB, whereas the 3rd-harmonic increases
general form for the output noise voltage using theby less than the expected 12dB. This also shows up
terms shown in Figure 30 .in the two-tone, 3rd-order intermodulation spurious(IM3) response curves. The 3rd-order spurious levelsare extremely low at low output power levels. The
Dividing this expression by the device gain (2V/V)output stage continues to hold them low even as the
gives the equivalent input-referred spot noise voltagefundamental power reaches very high levels. As the
at the noninverting input as shown in Equation 4 .Typical Characteristics show, the spuriousintermodulation powers do not increase as predictedby a traditional intercept model. As the fundamentalpower level increases, the dynamic range does not
Evaluating these two equations for the OPA3875decrease significantly. For two tones centered at
circuit and component values shown in Figure 2620MHz, with 4dBm/tone into a matched 50 Ωload
gives a total output spot noise voltage of 13.6nV/ √Hz(that is, 1V
PP
for each tone at the load, which requires
and a total equivalent input spot noise voltage of4V
PP
for the overall 2-tone envelope at the output
6.8nV/ √Hz. This total input-referred spot noisepin), the Typical Characteristics show a 82dBc
voltage is higher than the 6.7nV/ √Hz specification fordifference between the test-tone power and the
the mux voltage noise alone. This number reflects the3rd-order intermodulation spurious levels.
noise added to the output by the bias current noisetimes the source resistor.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): OPA3875
THERMAL ANALYSIS
P =10V 36mA+3(5 /4 (100 ||804 ))=571mW´ W W
D´2
MaximumT =+85 C+(0.57W 85 C/W)=133 C°
J´ ° °
BOARD LAYOUT GUIDELINES
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
www.ti.com
b) Minimize the distance ( < 0.25") from thepower-supply pins to high frequency 0.1 µFHeatsinking or forced airflow may be required under
decoupling capacitors. At the device pins, theextreme operating conditions. Maximum desired
ground and power plane layout should not be in closejunction temperature will set the maximum allowed
proximity to the signal I/O pins. Avoid narrow powerinternal power dissipation as discussed in this
and ground traces to minimize inductance betweendocument. In no case should the maximum junction
the pins and the decoupling capacitors. Thetemperature be allowed to exceed +150 ° C.
power-supply connections (on pins 9, 11, 13, and 15)should always be decoupled with these capacitors.Operating junction temperature (T
J
) is given by T
A
+
An optional supply decoupling capacitor across theP
D
×θ
JA
. The total internal power dissipation (P
D
) is
two power supplies (for bipolar operation) will improvethe sum of quiescent power (P
DQ
) and additional
2nd-harmonic distortion performance. Larger (2.2 µFpower dissipated in the output stage (P
DL
) to deliver
to 6.8 µF) decoupling capacitors, effective at lowerload power. Quiescent power is simply the specified
frequency, should also be used on the main supplyno-load supply current times the total supply voltage
pins. These may be placed somewhat farther fromacross the part. P
DL
depends on the required output
the device and may be shared among severalsignal and load but, for a grounded resistive load, is
devices in the same area of the PCB.at a maximum when the output is fixed at a voltageequal to 1/2 of either supply voltage (for equal bipolar
c) Careful selection and placement of externalsupplies). Under this condition P
DL
= V
S
2
/(4 × R
L
),
components will preserve the high-frequencywhere R
L
includes feedback network loading.
performance of the OPA3875. Resistors should bea very low reactance type. Surface-mount resistorsNote that it is the power in the output stage and not in
work best and allow a tighter overall layout. Metal-filmthe load that determines internal power dissipation.
and carbon composition, axially leaded resistors canAs a worst-case example, compute the maximum T
J
also provide good high-frequency performance.using an OPA3875 in the circuit of Figure 26
Again, keep their leads and PCB trace length as shortoperating at the maximum specified ambient
as possible. Never use wirewound type resistors in atemperature of +85 ° C with all three outputs driving a
high-frequency application. Other networkgrounded 100 Ωload to +2.5V:
components, such as noninverting input terminationresistors, should also be placed close to the package.
d) Connections to other wideband devices on theboard may be made with short direct traces orThis worst-case condition is approaching the
through onboard transmission lines. For shortmaximum +150 ° C junction temperature. Normally,
connections, consider the trace and the input to thethis extreme case is not encountered. Careful
next device as a lumped capacitive load. Relativelyattention to internal power dissipation is required.
wide traces (50mils to 100mils) should be used,preferably with ground and power planes opened uparound them. Estimate the total capacitive load andset R
S
from the plot of Figure 5 . Low parasiticAchieving optimum performance with a high
capacitive loads ( < 5pF) may not need an R
Sfrequency amplifier such as the OPA3875 requires
because the OPA3875 is nominally compensated tocareful attention to board layout parasitics and
operate with a 2pF parasitic load. If a long trace isexternal component types. Recommendations that
required, and the 6dB signal loss intrinsic to awill optimize performance include:
doubly-terminated transmission line is acceptable,a) Minimize parasitic capacitance to any AC implement a matched impedance transmission lineground for all of the signal I/O pins. Parasitic using microstrip or stripline techniques (consult ancapacitance on the output pin can cause instability: ECL design handbook for microstrip and striplineon the noninverting input, it can react with the source layout techniques). A 50 Ωenvironment is normallyimpedance to cause unintentional bandlimiting. To not necessary on board, and in fact, a higherreduce unwanted capacitance, a window around the impedance environment will improve distortion assignal I/O pins should be opened in all of the ground shown in the Distortion versus Load plots.and power planes around those pins. Otherwise,ground and power planes should be unbrokenelsewhere on the board.
16 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3875
INPUT AND ESD PROTECTION
External
Pin
+VCC
-VCC
Internal
Circuitry
OPA3875
www.ti.com
............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
With a characteristic board trace impedance definedbased on board material and trace dimensions, a
The OPA3875 is built using a very high-speedmatching series resistor into the trace from the output
complementary bipolar process. The internal junctionof the OPA3875 is used as well as a terminating
breakdown voltages are relatively low for these veryshunt resistor at the input of the destination device.
small geometry devices. These breakdowns areRemember also that the terminating impedance will
reflected in the Absolute Maximum Ratings table. Allbe the parallel combination of the shunt resistor and
device pins have limited ESD protection using internalthe input impedance of the destination device; this
diodes to the power supplies as shown in Figure 31 .total effective impedance should be set to match thetrace impedance. The high output voltage and currentcapability of the OPA3875 allows multiple destinationdevices to be handled as separate transmission lines,each with their own series and shunt terminations. Ifthe 6dB attenuation of a doubly-terminatedtransmission line is unacceptable, a long trace can beseries-terminated at the source end only. Treat thetrace as a capacitive load in this case and set theseries resistor value as shown in Figure 5 . This willnot preserve signal integrity as well as a
Figure 31. Internal ESD Protectiondoubly-terminated line. If the input impedance of thedestination device is low, there will be some signal
These diodes provide moderate protection to inputattenuation due to the voltage divider formed by the
overdrive voltages above the supplies as well. Theseries output into the terminating impedance.
protection diodes can typically support 30mAe) Socketing a high-speed part like the OPA3875 continuous current. Where higher currents areis not recommended. The additional lead length and possible (for example, in systems with ± 15V supplypin-to-pin capacitance introduced by the socket can parts driving into the OPA3875), current-limitingcreate an extremely troublesome parasitic network series resistors should be added into the two inputs.which can make it almost impossible to achieve a Keep these resistor values as low as possiblesmooth, stable frequency response. Best results are because high values degrade both noise performanceobtained by soldering the OPA3875 onto the board. and frequency response.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): OPA3875
OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................
www.ti.com
Revision History
Changes from Revision C (September 2007) to Revision D .......................................................................................... Page
•Changed storage temperature range rating in Absolute Maximum Ratings table from – 40 ° C to +125 ° C to – 65 ° C to+125 ° C ................................................................................................................................................................................... 2
Changes from Revision B (December 2006) to Revision C ........................................................................................... Page
•Changed the ordering number column in Table 1 ............................................................................................................... 14
18 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3875
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA3875IDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA3875IDBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA3875IDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA3875IDBQRG4 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA3875IDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA3875IDBQR SSOP DBQ 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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