VSP5620
VSP5621
VSP5622
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SBES022 –JULY 2011
16-Bit, 4-Channel, CCD/CMOS Sensor
Analog Front-End with LED Driver
Check for Samples: VSP5620,VSP5621,VSP5622
1FEATURES
23•Four-Channel CCD/CMOS Signal: 2-Channel, •Power (at 4-channel, LVDS, 3.3 V, without LED
3-Channel, and 4-Channel Selectable Driver):
•Power Supply: 3.3 V Only, Typ –VSP5620: 320 mW at 35 MSPS
(Built-in LDO, 3.3 V to 1.8 V) –VSP5621: 406 mW at 50 MSPS
•Maximum Conversion Rate: –VSP5622: 523 mW at 70 MSPS
–VSP5620: 35 MSPS
–VSP5621: 50 MSPS APPLICATIONS
–VSP5622: 70 MSPS •Copiers
•16-Bit Resolution •Facsimile Machines
•CDS/SH Selectable •Scanners
•Maximum Input Signal Range: 2.0 V
•Analog and Digital Hybrid Gain: DESCRIPTION
–Analog Gain: 0.5 V/V to 3.5 V/V in The VSP5620/21/22 are high-speed,
3/64-V/V Steps high-performance, 16-bit analog-to-digital-converters
(ADCs) that have four independent sampling circuit
–Digital Gain: 1 V/V to 2 V/V in channels for multi-output charge-coupled device
1/256-V/V Steps (CCD) and complementary metal oxide
•Offset Correction DAC: ±250 mV, 8-Bit semiconductor (CMOS) line sensors. Pixel data from
•Standard LVDS/CMOS Selectable Output: the sensor are sampled by the sample/hold (SH) or
–LVDS: correlated double sampler (CDS) circuit, and are then
converted to digital data by an ADC. Data output is
–Data Channel: 2-Channel selectable in low-voltage differential signaling (LVDS)
–Clock Channel: 1-Channel or CMOS modes.
–8-Bit/7-Bit Serializer Selectable The VSP5620/21/22 include a programmable gain to
–CMOS: 4 Bits ×4support the pixel level inflection caused by luminance
•Timing Generator and a built-in light-emitting diode (LED) driver to
–Fast Transfer Clock: One Signal adjust the brightness. The integrated
–Slow Transfer Clock: One Signal digital-to-analog-converter (DAC) can be used to
adjust the offset level for the analog input signal.
•LED Driver: Three Channels Furthermore, the timing generator (TG) is integrated
–Current: 60-mA/Channel Max, in these devices for the control of sensor operation.
16-Steps/Channel
•Timing Adjustment Resolution: tMCLK/48 The VSP5620/21/22 use 1.65 V to 1.95 V for the core
voltage and 3.0 V to 3.6 V for I/Os. The core voltage
•Input Clamp/Input Reference Level is supplied by a built-in low-dropout regulator (LDO).
Internal/External Selectable
•Reference DAC: 0.5 V, 1.1 V, 1.5 V, 2 V
•SPI™: Three-Wire Serial
•GPIO: Four-Port
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI is a trademark of Motorola.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VSP5620
VSP5621
VSP5622
SBES022 –JULY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA,
PRODUCT LEAD DESIGNATOR RANGE MARKING NUMBER QUANTITY
VSP5620 QFN-48 RSL 0°C to +85°C VSP5620 VSP5620RSLR Tape and Reel, 2500
VSP5621 QFN-48 RSL 0°C to +85°C VSP5621 VSP5621RSLR Tape and Reel, 2500
VSP5622 QFN-48 RSL 0°C to +85°C VSP5622 VSP5622RSLR Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over free-air temperature range, unless otherwise noted. VSP5620, VSP5621, VSP5622 UNIT
Supply voltage: VDD, DVDD_IO, LVDD 4.0 V
Supply voltage difference: VDD, DVDD_IO, LVDD ±0.6 V
Ground voltage difference: VSS, DVSS, LVSS, LEDVSS ±0.1 V
Digital voltage input –0.3 to DVDD_IO + 0.3 V
Analog voltage input –0.3 to VDD + 0.3 V
Digital input current ±10 mA
LED driver voltage: LED1, LED2, LED3 7.0 V
Analog input current ±10 mA
Ambient temperature under bias –40 to +125 °C
Storage temperature –55 to +150 °C
Junction temperature +150 °C
Package temperature (IR reflow, peak) +260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
LDO and analog I/O power-supply voltage VDD 3.0 3.3 3.6 V
Digital power-supply voltage DVDD_IO 3.0 3.3 3.6 V
LVDS/CMOS power-supply voltage LVDD 3.0 3.3 3.6 V
Supply voltage difference VDD, DVDD_IO, LVDD –0.3 0.3 V
Digital input logic family Low-voltage CMOS
VSP5620 1 11.66 MHz
Master clock frequency (MCLK) VSP5621 1 16.66 MHz
VSP5622 1 23.33 MHz
Serial I/O clock frequency (SCLK) 10 MHz
Operating free-air temperature 0 +85 °C
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ELECTRICAL CHARACTERISTICS: VSP5620
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 8.75 MHz, and four-channel mode, unless
otherwise noted. VSP5620
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Allowable input voltage 0 VDD V
Full-scale range Gain = 1 V/V 1 VPP
Input capacitor 5 pF
DIGITAL INPUT
Positive-going threshold VT+ DVDD_IO ×0.7 V
Negative-going threshold VT–DVDD_IO ×0.3 V
Hysteresis (VT+ –VT–)ΔVTDVDD_IO ×0.13 V
Input current IIN ±1µA
Input capacitor 5 pF
DIGITAL OUTPUT
IOH =–2 mA DVDD_IO –0.45 V
High-level output voltage VOH IOH =–4 mA DVDD_IO –0.50 V
IOH =–8 mA DVDD_IO –0.50 V
IOL = 2 mA 0.35 V
Low-level output voltage VOL IOL = 4 mA 0.50 V
IOL = 8 mA 0.65 V
CMOS data output bit rate 80 MHz
LVDS DRIVER (TA, TB, TCLK)
Differential steady-state output |VOD| RL= 100 Ω300 350 400 mV
voltage adjustment range
Differential steady-state output |VOD| 3 Steps
adjustment step
Differential steady-state output |VOD|–30 30 %
voltage tolerance
Change in the steady-state
differential output voltage magnitude Δ|VOD| 35 mV
between opposite binary states
Steady-state common-mode output VOC(SS) RL= 100 Ω1.125 1.375 V
voltage
Peak-to-peak common-mode output VOC(PP) 80 150 mV
voltage
Short-circuit output current IOS VO= 0 V (VO= TA, TB, TCLK) –6±24 mA
VO= 0 V to LVDD
Hi-Z output current IOZ ±10 µA
(VO= TA, TB, TCLK)
Transition time, differential output tLR/tLF 0.75 1.5 ns
voltage
TCLK clock rate 8 35 MHz
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ELECTRICAL CHARACTERISTICS: VSP5620 (continued)
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 8.75 MHz, and four-channel mode, unless
otherwise noted. VSP5620
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LED DRIVER
Output current ILD 60 mA/ch
Off-state leak current 50 µA
Output current tolerance –10 10 %
Total output current(1) All channels 132 mA
Channel mismatch –5 5 %
Current step 16 steps/ch
0.7 4.5 V
Drive voltage VLD LED turns off, ILD = 0 mA 6 V
Temperature drift TA= 0°C to +85°C, design ensured –2 2 %
POWER SUPPLY
LDO and analog I/O supply voltage VDD 3.0 3.3 3.6 V
Digital I/O supply voltage DVDD_IO 3.0 3.3 3.6 V
LVDS/CMOS supply voltage LVDD 3.0 3.3 3.6 V
LDO and analog I/O current VDD 74.9 mA
Digital I/O current DVDD_IO Load = 10 pF 3.8 mA
CMOS current LVDD 10 mA
LVDS current LVDD Two-pair data, one-pair clock 18 mA
LVDS, two-pair 320 mW
Power consumption CMOS output 293 mW
Standby mode (MCLK = 0 MHz) 15 mW
TEMPERATURE RANGE
Operation temperature TA0 +85 °C
DLL, PLL
MCLK input frequency fMCLK 1 11.66 MHz
MCLK modulated frequency MCLK >5 MHz 35 kHz
MCLK modulated amplitude –3.5 0 %
DLL tap number 48 Taps
Maximum DLL and PLL lock-up time MCLK = 1 MHz 10 ms
(1) The total current limitation circuitry is not included.
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VSP5622
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SBES022 –JULY 2011
ELECTRICAL CHARACTERISTICS: VSP5620 (continued)
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 8.75 MHz, and four-channel mode, unless
otherwise noted. VSP5620
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TRANSFER CHARACTERISTICS
Channels 2 4 Channels
Resolution 16 Bits
LVDS, two- and three-channel mode 1 11.66 MHz/Ch
LVDS, four-channel mode 1 8.75 MHz/Ch
CMOS 4-bit ×4, two-channel mode 1 10 MHz/Ch
Conversion rate CMOS 4-bit ×4, three-channel 1 6.7 MHz/Ch
mode
CMOS 4-bit ×4, four-channel mode 1 5 MHz/Ch
Maximum differential nonlinearity Gain = 1 V/V, 12-bit ±0.5 LSB
Maximum integral nonlinearity Gain = 1 V/V, 12-bit ±2 LSB
No missing codes Specified
Signal-to-noise ratio SNR Gain = 1 V/V 72(2) 76 dB
Analog channel crosstalk Gain = 1 V/V, 12-bit, full-scale step ±3 LSB
Total absolute gain error –10 10 %
ANALOG PROGRAMMABLE GAIN (APG)
Gain range APG_x 0.5 3.5 V/V
Gain step 63 Steps
Gain relative error Basis gain = 1 V/V –10 10 %
Gain monotonicity Only APG_x Specified
DIGITAL PROGRAMMABLE GAIN (DPG)
Gain range DPG_x 1.0 2.0 V/V
Gain step 255 Steps
Gain monotonicity Only DPG_x Specified
AIN REFERENCE LEVEL (REF_AIN)
Setting code = 0 0.5 V
Setting code = 1 1.1 V
Internal DAC output VRINT Setting code = 2 (default) 1.5 V
Setting code = 3 2.0 V
Internal DAC output tolerance VRINT –10 10 %
Internal DAC output temperature VRINT TA= 0°C to +85°C(2) –2 2 %
drift
External reference range VREXT 0.5 VDD –0.9 V
INPUT CLAMP
Internal reference level clamp VRINT V
Clamp level VCLP External reference level clamp VREXT V
Fixed level clamp 2.2 V
Clamp-on resistance RCLP 500 Ω
OFFSET DAC
Resolution 8 Bits
Output range ±250 mV
Setting tolerance –10 10 %
Temperature drift TA= 0°C to +85°C(2) –2 2 %
(2) Specified by design.
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ELECTRICAL CHARACTERISTICS: VSP5621
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 12.5 MHz, and four-channel mode, unless
otherwise noted. VSP5621
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Allowable input voltage 0 VDD V
Full-scale range Gain = 1 V/V 1 VPP
Input capacitor 5 pF
DIGITAL INPUT
Positive-going threshold VT+ DVDD_IO ×0.7 V
Negative-going threshold VT–DVDD_IO ×0.3 V
Hysteresis (VT+ –VT–)ΔVTDVDD_IO ×0.13 V
Input current IIN ±1µA
Input capacitor 5 pF
DIGITAL OUTPUT
IOH =–2 mA DVDD_IO –0.45 V
High-level output voltage VOH IOH =–4 mA DVDD_IO –0.50 V
IOH =–8 mA DVDD_IO –0.50 V
IOL = 2 mA 0.35 V
Low-level output voltage VOL IOL = 4 mA 0.50 V
IOL = 8 mA 0.65 V
CMOS data output bit rate 80 MHz
LVDS DRIVER (TA, TB, TCLK)
Differential steady-state output |VOD| RL= 100 Ω300 350 400 mV
voltage adjustment range
Differential steady-state output |VOD| 3 Steps
adjustment step
Differential steady-state output |VOD|–30 30 %
voltage tolerance
Change in the steady-state
differential output voltage magnitude Δ|VOD| 35 mV
between opposite binary states
Steady-state common-mode output VOC(SS) RL= 100 Ω1.125 1.375 V
voltage
Peak-to-peak common-mode output VOC(PP) 80 150 mV
voltage
Short-circuit output current IOS VO= 0 V (VO= TA, TB, TCLK) –6±24 mA
VO= 0 V to LVDD
Hi-Z output current IOZ ±10 µA
(VO= TA, TB, TCLK)
Transition time, differential output tLR/tLF 0.75 1.5 ns
voltage
TCLK clock rate 8 50 MHz
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SBES022 –JULY 2011
ELECTRICAL CHARACTERISTICS: VSP5621 (continued)
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 12.5 MHz, and four-channel mode, unless
otherwise noted. VSP5621
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LED DRIVER
Output current ILD 60 mA/ch
Off-state leak current 50 µA
Output current tolerance –10 10 %
Total output current(1) All channels 132 mA
Channel mismatch –5 5 %
Current step 16 steps/ch
0.7 4.5 V
Drive voltage VLD LED turns off, ILD = 0 mA 6 V
Temperature drift TA= 0°C to +85°C, design ensured –2 2 %
POWER SUPPLY
LDO and analog I/O supply voltage VDD 3.0 3.3 3.6 V
Digital I/O supply voltage DVDD_IO 3.0 3.3 3.6 V
LVDS/CMOS supply voltage LVDD 3.0 3.3 3.6 V
LDO and analog I/O current VDD 99.6 mA
Digital I/O current DVDD_IO Load = 10 pF 5.4 mA
CMOS current LVDD 10 mA
LVDS current LVDD Two-pair data, one-pair clock 18 mA
LVDS, two-pair 406 mW
Power consumption CMOS output 380 mW
Standby mode (MCLK = 0 MHz) 15 mW
TEMPERATURE RANGE
Operation temperature TA0 +85 °C
DLL, PLL
MCLK input frequency fMCLK 1 16.66 MHz
MCLK modulated frequency MCLK >5 MHz 35 kHz
MCLK modulated amplitude –3.5 0 %
DLL tap number 48 Taps
Maximum DLL and PLL lock-up time MCLK = 1 MHz 10 ms
(1) The total current limitation circuitry is not included.
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ELECTRICAL CHARACTERISTICS: VSP5621 (continued)
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 12.5 MHz, and four-channel mode, unless
otherwise noted. VSP5621
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TRANSFER CHARACTERISTICS
Channel 2 4 Channels
Resolution 16 Bits
LVDS, two- and three-channel mode 1 16.66 MHz/Ch
LVDS, four-channel mode 1 12.5 MHz/Ch
CMOS 4-bit ×4, two-channel mode 1 10 MHz/Ch
Conversion rate CMOS 4-bit ×4, three-channel 1 6.7 MHz/Ch
mode
CMOS 4-bit ×4, four-channel mode 1 5 MHz/Ch
Maximum differential nonlinearity Gain = 1 V/V, 12-bit ±0.5 LSB
Maximum integral nonlinearity Gain = 1 V/V, 12-bit ±2 LSB
No missing codes Specified
Signal-to-noise ratio SNR Gain = 1 V/V 72(2) 76 dB
Analog channel crosstalk Gain = 1 V/V, 12-bit, full-scale step ±6.5 LSB
Total absolute gain error –10 10 %
ANALOG PROGRAMMABLE GAIN (APG)
Gain range APG_x 0.5 3.5 V/V
Gain step 63 Steps
Gain relative error Basis gain = 1 V/V –10 10 %
Gain monotonicity Only APG_x Specified
DIGITAL PROGRAMMABLE GAIN (DPG)
Gain range DPG_x 1.0 2.0 V/V
Gain step 255 Steps
Gain monotonicity Only DPG_x Specified
AIN REFERENCE LEVEL (REF_AIN)
Setting code = 0 0.5 V
Setting code = 1 1.1 V
Internal DAC output VRINT Setting code = 2 (default) 1.5 V
Setting code = 3 2.0 V
Internal DAC output tolerance VRINT –10 10 %
Internal DAC output temperature VRINT TA= 0°C to +85°C(2) –2 2 %
drift
External reference range VREXT 0.5 VDD –0.9 V
INPUT CLAMP
Internal reference level clamp VRINT V
Clamp level VCLP External reference level clamp VREXT V
Fixed level clamp 2.2 V
Clamp-on resistance RCLP 500 Ω
OFFSET DAC
Resolution 8 Bits
Output range ±250 mV
Setting tolerance –10 10 %
Temperature drift TA= 0°C to +85°C(2) –2 2 %
(2) Specified by design.
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SBES022 –JULY 2011
ELECTRICAL CHARACTERISTICS: VSP5622
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless
otherwise noted. VSP5622
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Allowable input voltage 0 VDD V
Full-scale range Gain = 1 V/V 1 VPP
Input capacitor 5 pF
DIGITAL INPUT
Positive-going threshold VT+ DVDD_IO ×0.7 V
Negative-going threshold VT–DVDD_IO ×0.3 V
Hysteresis (VT+ –VT–)ΔVTDVDD_IO ×0.13 V
Input current IIN ±1µA
Input capacitor 5 pF
DIGITAL OUTPUT
IOH =–2 mA DVDD_IO –0.45 V
High-level output voltage VOH IOH =–4 mA DVDD_IO –0.50 V
IOH =–8 mA DVDD_IO –0.50 V
IOL = 2 mA 0.35 V
Low-level output voltage VOL IOL = 4 mA 0.50 V
IOL = 8 mA 0.65 V
CMOS data output bit rate 80 MHz
LVDS DRIVER (TA, TB, TCLK)
Differential steady-state output |VOD| RL= 100 Ω300 350 400 mV
voltage adjustment range
Differential steady-state output |VOD| 3 Steps
adjustment step
Differential steady-state output |VOD|–30 30 %
voltage tolerance
Change in the steady-state
differential output voltage magnitude Δ|VOD| 35 mV
between opposite binary states
Steady-state common-mode output VOC(SS) RL= 100 Ω1.125 1.375 V
voltage
Peak-to-peak common-mode output VOC(PP) 80 150 mV
voltage
Short-circuit output current IOS VO= 0 V (VO= TA, TB, TCLK) –6±24 mA
VO= 0 V to LVDD
Hi-Z output current IOZ ±10 µA
(VO= TA, TB, TCLK)
Transition time, differential output tLR/tLF 0.75 1.5 ns
voltage
TCLK clock rate 8 70 MHz
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ELECTRICAL CHARACTERISTICS: VSP5622 (continued)
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless
otherwise noted. VSP5622
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LED DRIVER
Output current ILD 60 mA/ch
Off-state leak current 50 µA
Output current tolerance –10 10 %
Total output current(1) All channels 132 mA
Channel mismatch –5 5 %
Current step 16 steps/ch
0.7 4.5 V
Drive voltage VLD LED turns off, ILD = 0 mA 6 V
Temperature drift TA= 0°C to +85°C, design ensured –2 2 %
POWER SUPPLY
LDO and analog I/O supply voltage VDD 3.0 3.3 3.6 V
Digital I/O supply voltage DVDD_IO 3.0 3.3 3.6 V
LVDS/CMOS supply voltage LVDD 3.0 3.3 3.6 V
LDO and analog I/O current VDD 133 mA
Digital I/O current DVDD_IO Load = 10 pF 7.5 mA
CMOS current LVDD 10 mA
LVDS current LVDD Two-pair data, one-pair clock 18 mA
LVDS, two-pair 523 mW
Power consumption CMOS output 497 mW
Standby mode (MCLK = 0 MHz) 15 mW
TEMPERATURE RANGE
Operation temperature TA0 +85 °C
DLL, PLL
MCLK input frequency fMCLK 1 23.33 MHz
MCLK modulated frequency MCLK >5 MHz 35 kHz
MCLK modulated amplitude –3.5 0 %
DLL tap number 32 Taps
Maximum DLL and PLL lock-up time MCLK = 1 MHz 22 ms
(1) The total current limitation circuitry is not included.
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SBES022 –JULY 2011
ELECTRICAL CHARACTERISTICS: VSP5622 (continued)
All specifications at TA= +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless
otherwise noted. VSP5622
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TRANSFER CHARACTERISTICS
Channel 2 4 Channels
Resolution 16 Bits
LVDS, two- and three-channel mode 1 23.33 MHz/Ch
LVDS, four-channel mode 1 17.5 MHz/Ch
CMOS 4-bit ×4, two-channel mode 1 10 MHz/Ch
Conversion rate CMOS 4-bit ×4, three-channel 1 6.7 MHz/Ch
mode
CMOS 4-bit ×4, four-channel mode 1 5 MHz/Ch
Maximum differential nonlinearity Gain = 1 V/V, 12-bit ±0.5 LSB
Maximum integral nonlinearity Gain = 1 V/V, 12-bit ±2 LSB
No missing codes Specified
Signal-to-noise ratio SNR Gain = 1 V/V 72(2) 75 dB
Analog channel crosstalk Gain = 1 V/V, 12-bit, full-scale step ±15 LSB
Total absolute gain error –10 10 %
ANALOG PROGRAMMABLE GAIN (APG)
Gain range APG_x 0.5 3.5 V/V
Gain step 63 Steps
Gain relative error Basis gain = 1 V/V –10 10 %
Gain monotonicity Only APG_x Specified
DIGITAL PROGRAMMABLE GAIN (DPG)
Gain range DPG_x 1.0 2.0 V/V
Gain step 255 Steps
Gain monotonicity Only DPG_x Specified
AIN REFERENCE LEVEL (REF_AIN)
Setting code = 0 0.5 V
Setting code = 1 1.1 V
Internal DAC output VRINT Setting code = 2 (default) 1.5 V
Setting code = 3 2.0 V
Internal DAC output tolerance VRINT –10 10 %
Internal DAC output temperature VRINT TA= 0°C to +85°C(2) –2 2 %
drift
External reference range VREXT 0.5 VDD –0.9 V
INPUT CLAMP
Internal reference level clamp VRINT V
Clamp level VCLP External reference level clamp VREXT V
Fixed level clamp 2.2 V
Clamp-on resistance RCLP 500 Ω
OFFSET DAC
Resolution 8 Bits
Output range ±250 mV
Setting tolerance –10 10 %
Temperature drift TA= 0°C to +85°C(2) –2 2 %
(2) Specified by design.
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VDD
VSS
a)NegativeSignalInput(AINx_POL =0)
(1) b)PositiveSignalInput(AINx_POL =1)
(1)
VDD
VSS
1/fPIX
VSIG
VOFFSET
VRST
VOFFSET
VSIG
1/fPIX
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VSP5621
VSP5622
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THERMAL INFORMATION VSP562xRSL
THERMAL METRIC(1) RSL UNITS
48 PINS
θJA Junction-to-ambient thermal resistance 25.8
θJCtop Junction-to-case (top) thermal resistance 13.2
θJB Junction-to-board thermal resistance 3.5 °C/W
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 3.5
θJCbot Junction-to-case (bottom) thermal resistance 0.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
PARAMETERIC MEASUREMENT INFORMATION
Analog Input Specification (AIN1, AIN2, AIN3, AIN4)
The analog input specification has two signal inputs: negative and positive. These inputs are shown in Figure 1a
and Figure 1b, respectively.
Figure 1. Analog Input Definition
Table 1. Timing Characteristics for Figure 1
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSP5620 1 11.66 MHz/Ch
Input pixel rate fPIX VSP5621 1 16.66 MHz/Ch
VSP5622 1 23.33 MHz/Ch
Negative (AINx_POL(1) = 0) VOFFSET V
Signal range VSIG Positive (AINx_POL(1) = 1) VDD –VOFFSET V
Maximum full-scale range VSIG Gain = 0.5 V/V 1.8 2 2.2 V
Reset field through noise VRST –VOFFSET VDD –VOFFSET V
range Fixed level clamp mode (REF_SEL = 0) 2.2 V
Internal reference level clamp mode VRINT V
Offset level VOFFSET (REF_SEL = 1)
External reference level clamp mode VREXT V
(REF_SEL = 2)
(1) AINx_POL = Analog input polarity setting register (x = 1, 2, 3, and 4).
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R /2(1)
L
R /2(1)
L
Tx+
Tx-
VOD
VOC
VOD(H)
VOD(L)
tLF tLR
100%
80%
0V
20%
0%
VOC(PP)
0V
VOC(SS) VOC(SS)
VSP5620
VSP5621
VSP5622
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SBES022 –JULY 2011
LVDS Output Voltage Specification
The test load and voltage definition for the LVDS outputs are shown in Figure 2.
(1) RL/2 = 49.9 Ω ± 1%
Figure 2. Test Load and Voltage Definition for LVDS Outputs
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VSS
AIN1
AINGND1
AIN2
AINGND2
AIN3
AINGND3
AIN4
AINGND4
VSS
REF_AIN
ISET
LVSS
LVDD
TA+/D0
TA /D1-
TB+/D2
TB /D3-
TCLK+/CK0
TCLK /CK1-
SCLK
SDI
SEN
MCLK
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
AVDD_LDO
48
REFP 13
TEST
47
REFN 14
VSS
46
VSS 15
DVSS
45
VDD 16
XP1
44
LED1_EN 17
XSH1
43
LED2_EN 18
XST/GPIO3
42
LED3_EN 19
SDO/GPIO1
41
LEDVSS 20
XLSYNC
40
LED1 21
DVSS
39
LED2 22
DVDD_IO
38
LED3 23
DVSS
37
LEDVSS 24
VSP5620
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VSP5622
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PIN CONFIGURATION
RSL PACKAGE
QFN-56
(TOP VIEW)
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PIN ASSIGNMENTS
PIN
NUMBER PIN NAME TYPE(1) DESCRIPTION
1 VSS AGND LDO and analog I/O ground
2 AIN1 AI3.3 First channel analog signal input(2)
3 AINGND1 AI3.3 First channel analog signal ground(2)
4 AIN2 AI3.3 Second channel analog signal input(2)
5 AINGND2 AI3.3 Second channel analog signal ground(2)
6 AIN3 AI3.3 Third channel analog signal input(2)
7 AINGND3 AI3.3 Third channel analog signal ground(2)
8 AIN4 AI3.3 Fourth channel analog signal input(2)
9 AINGND4 AI3.3 Fourth channel analog signal ground(2)
10 VSS AGND LDO and analog I/O ground
REF_DAC_IN
11 REF_AIN AI3.3/AO3.3 0 = Analog signal reference output (default)
1 = Analog signal reference input
12 ISET LVO1.8 Internal reference voltage output; bypass to ground with a 10-kΩ ± 1% resister
13 REFP AO1.8 Positive reference; bypass to AGND with a 0.1-μF capacitor
14 REFN AO1.8 Negative reference; bypass to AGND with a 0.1-μF capacitor
15 VSS AGND LDO and analog I/O ground
16 VDD AP3.3 LDO and analog I/O power supply
LED driver 1 enable (with an internal pull-down resistor)
17 LED1_EN DI3.3 Polarity is set with the LED_EN_POL register (default = active high)
LED driver 2 enable (with an internal pull-down resistor)
18 LED2_EN DI3.3 Polarity is set with the LED_EN_POL register (default = active high)
LED driver 3 enable (with an internal pull-down resistor)
19 LED3_EN DI3.3 Polarity is set with the LED_EN_POL register (default = active high)
20 LEDVSS LDGND LED driver ground
21 LED1 LDO5.0 LED driver 1
22 LED2 LDO5.0 LED driver 2
23 LED3 LDO5.0 LED driver 3
24 LEDVSS LDGND LED driver ground
25 MCLK DI3.3 Master clock input
26 SEN DI3.3 Serial I/F enable; active low (with an internal pull-up resistor)
SDI_BUFF_CTRL
27 SDI DIO3.3 0 = Serial I/F data input
1 = Serial I/F data input/output (with an internal pull-down resistor)
28 SCLK DI3.3 Serial I/F clock (with an internal pull-down resistor)
29 TCLK–/CK1 LVO3.3 LVDS clock output–/clock output 1
30 TCLK+/CK0 LVO3.3 LVDS clock output+/clock output 0
31 TB–/D3 LVO3.3 TB channel LVDS data output–/data output bit 3
32 TB+/D2 LVO3.3 TB channel LVDS data output+/data output bit 2
33 TA–/D1 LVO3.3 TA channel LVDS data output–/data output bit 1
34 TA+/D0 LVO3.3 TA channel LVDS data output+/data output bit 0
35 LVDD LVP3.3 LVDS/CMOS output power supply
36 LVSS LVGND LVDS/CMOS output ground
37 DVSS DGND Digital ground
(1) AP3.3 = 3.3-V analog power supply; AP1.8 = 1.8-V analog power supply; AGND = analog ground; GND = ground; AO3.3 = 3.3-V analog
output; AO1.8 = 1.8-V analog output; AI3.3 = 3.3-V analog input; DP3.3 = 3.3-V digital power supply; DP1.8 = 1.8-V digital power
supply; DGND = digital ground; DO3.3 = 3.3-V digital output; DI3.3 = 3.3-V digital input; DIO3.3 = 3.3-V digital I/O; LVP3.3 = 3.3-V
LVDS power supply; LVGND = LVDS ground; LVO3.3 = 3.3-V LVDS output; LVI3.3 = 3.3-V LVDS input; LVO = 3.3-V LVDS output;
LDO5.0 = 5.0-V LED driver output; and LDGND = LED driver GND.
(2) If these pins are unused, they can be opened or decoupled to GND with a decoupling capacitor.
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PIN ASSIGNMENTS (continued)
PIN
NUMBER PIN NAME TYPE(1) DESCRIPTION
38 DVDD_IO DP3.3 Digital I/O power supply
39 DVSS DGND Digital ground
XLSYNC_SEL
0 = Internal line synchronous signal output (default)
40 XLSYNC DIO3.3 When used as an input, the bit requires an internal pull-down resistor.
1 = External line synchronous signal input
Polarity is set by the XLSYNC_POL register (default = active high)
GPIO1_SDO_SEL
0 = GPI1; general-purpose input port 1 (default)
When used as an input, the bit requires an internal pull-down resistor.
41 SDO/GPIO1 DIO3.3 1 = GPO1; general-purpose output port 1
2 = Reserved; internal test input
3 = SDO; serial I/F data output
GPIO3_XST_SEL
0 = GPI3; general-purpose input port 3 (default)
When used as an input, the bit requires an internal pull-down resistor.
42 XST/GPIO3 DIO3.3 1 = GPO3; general-purpose output port 3
2 = Reserved; internal test input
3 = XST; storage pulse output
43 XSH1 DO3.3 Sensor shift gate output 1
44 XP1 DO3.3 Fast transfer clock output φ1
45 DVSS DGND Digital ground
46 VSS AGND LDO and analog I/O ground
47 TEST DI3.3 Internal test pin; connect to DGND
48 AVDD_LDO AP1.8 Analog core power voltage output; not connected, open
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DVSS
DVDD_IO
3.3 V
16-Bit
ADC
16
4:1
MU
X
CDS
/SH
Clamp
Internal
Reference
REFP
REFN
8-Bit
DAC
SEN
SDI
SCLK
Serial Interface/Register
AINGND1
AVDD_LDO
VDD
DLL Tap Selector
Line
Sync
XLSYNC
MCLK
DPG
LDO
3.3 V to 1.8 V
VSS
3.3 V
LVSS
LVDD
AIN4
DLL
48 Taps
+
Ref
DAC
CDS
/SH
Clamp 8-Bit
DAC
AIN3 +
CDS
/SH
Clamp 8-Bit
DAC
AIN2 +
APG
CDS
/SH
Clamp 8-Bit
DAC
AIN1 +
REF_AIN
APG
APG
APG
XP1
Timing Generator
XST/GPIO3
AINGND2
AINGND3
AINGND4
SHD_A,
SHD_B,
SHP_A,
SHP_B
PLL
XSH1
LED Control
LED2
LED1
LED3
LEDVDD
LEDVSS
LEDVSS
TA /D1
TA+/D0
LVDS
4
Serializer
Parallel Load
7-or 8-BIt
Shift Register
Serializer
Parallel Load
7-or 8-BIt
Shift Register
LVDS
TCLK /CK1
TCLK+/CK0
MUX
TB /D3
TB+/D2
3.3 V
SDO/GPIO1
LED2_EN
LED1_EN
LED3_EN
ADCK
LVCK
ISET
10 kΩ
±1%
LVDS
VSP5620
VSP5621
VSP5622
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FUNCTIONAL BLOCK DIAGRAM
Figure 3. VSP5620/21/22 Block Diagram
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SYSTEM OVERVIEW
INTRODUCTION
The VSP5620/21/22 are analog front-end (AFE) devices for CCD and CMOS line image sensor applications such
as copiers, facsimile machines, etc. The VSP5620/21/22 each provide four independent data processing
channels.
The data from each image sensor channel are sampled and held by either the SH or CDS circuit and are then
converted into digital data by an ADC. The digital data for each channel are later converted into serial data that
can be output in either LVDS mode or CMOS mode.
AFE BLOCK
ANALOG SIGNAL INPUT
These devices have four channels that can be used as analog input ports for an image sensor. In addition to the
four-channel input, this AFE device also supports three-channel and two-channel inputs. Each channel mode can
be selected with internal register settings. Table 2 shows the register settings required to select the different
channel modes.
Table 2. Analog Input Channel Mode Selection
MODE AIN_CH_SEL AIN1 AIN2 AIN3 AIN4
Two-channel 2 Active Standby Active Standby
Three-channel 1 Active Active Active Standby
Four-channel 0 Active Active Active Active
Each analog input supports CDS and simple SH circuits to accommodate CCD and CMOS image sensors. The
sampling mode can be selected independently for each channel by configuring the internal registers. As shown in
Table 3, if AINx_SH_CDS is set to '0', then the corresponding channel operates in CDS mode.
Table 3. CDS/SH Mode Selection
AINx_SH_CDS(1) SH/CDS
0 CDS
1 SH
(1) AINx_POL = Analog input polarity setting register (x = 1, 2, 3, and 4).
In addition, these devices also support independent selection of the input signal polarity for each channel. Input
signal polarity can be set using the AINx_POL register, where x = 1, 2, 3, or 4. The input signal range and
polarity are defined in the Analog Input Specification section.
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CFBx
CFBx
VP
VN
SHP
/SHD
SHP
CSx
CSx
AINx(1)
AINGNDx(1)
+
AINx_POL
VCLP
RCLP
CSx
CSx
Offset
DAC
OFDAC_x[7:0]
SH_REFx_EN
CLP_y
CLPDM
CLP_y
SHP_y
VSP5620
VSP5621
VSP5622
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Correlated Double Sampler (CDS) Mode (AINx_SH_CDS = 0)
CDS mode is designed to accommodate inputs from the CCD sensor. The output signal of a CCD image sensor
is sampled twice during one pixel period. First, the reference interval is sampled by the SHP pulse, then the data
interval is sampled by the SHD pulse. Subtracting these two samples provides the video information of the pixel
as well as removes any noise common to both intervals. Thus, CDS plays an important role in reducing the reset
noise and other low-frequency noises that are present on the CCD output signal. Figure 4 shows a diagram of
CDS mode.
Figure 4. CDS Mode Input Circuit for CCD Signal
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CFBx
CFBx
VP
VN
SHD
SHD
CSx
CSx
AINx(1)
AINGNDx(1)
+
AINx_POL
VCLP
RCLP
CSx
CSx
Offset
DAC
OFDAC_x[7:0]
SH_REFx_EN
CLP_y
CLPDM
CLP_y
SHP_y
VSP5620
VSP5621
VSP5622
SBES022 –JULY 2011
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Sample Hold (SH) Mode (AINx_SH_CDS = 1)
SH mode supports CCD and CMOS sensors. For the CCD sensor, the sensor signal pedestal level is clamped to
the VCLP level using an internal clamp circuit. SH samples only once during a pixel period. The SHD pulse is
used to sample the CCD signal data interval. After sampling, the SH circuit takes the difference of the data and
VCLP levels to extract the video information.
For the CMOS input, the input clamp function should be set according to the requirements. If the sensor output is
within the allowable input range, an ac-coupling capacitor for analog input may not be needed. When the sensor
signal is directly input to the AFE, the SH circuit requires a reference voltage to set the black level. To use VCLP
as a reference, SH_REFx_EN should be enabled and AINGNDx then opened or coupled to GND with a
capacitor. To use an external reference, it can be input to AINGNDx with sensor signals connected to AINx.
Figure 5 shows a diagram of the SH mode.
(1) Under some conditions, the sensor signal can be directly input to the AFE without requiring an external capacitor.
(2) In SH mode, the SHP clock should be programmed so that it does not overlap the SHD clock.
Figure 5. SH Mode Input Circuit for CCD or CMOS Signal
INPUT CLAMP AND SENSOR REFERENCE
The CCD output signal has a large dc offset that may exceed the input range of the AFE input circuit. Therefore,
this output signal is ac-coupled to the AFE through a capacitor, and the internal dc level is set to the clamp
voltage (VCLP) by an internal clamp circuit. The VSP5620/21/22 provide three modes for clamp operation: pixel
clamp, line clamp, and not clamped. These modes are shown in Table 4. The clamp mode can be set
independently for each channel by configuring the AINx_CLP_SEL register.
Table 4. Clamp Mode Selection
MODE SETTING CLAMP ACTIVE CONDITION AND SETTING
CLAMP MODE CLPDM AND
AINx_CLP_SEL(1) CDS/SH CLP_y(2) SH_REF_EN
SHP_y(2)
Pixel clamp 0 (default) CDS/SH Active Active Off
Line clamp 1 CDS/SH —Active Off
2 Only SH — — On
Not clamped 3 Only SH — — Off
(1) AINx_CLP_SEL (x = 1, 2, 3, and 4).
(2) y = A and B.
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MCLK
AINx(1)
CLP_y(2)
SHP_y(2)
SHD_y(2)
MCLK
AINx(1)
SHP_y(2)
SHD_y(2)
tFC_y
tCW_y
tRP_y tPW_y tRP_y tPW_y
a)PixelClamp b)ClampDuringCLPDMActive
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In pixel clamp mode, CLP_A/B is used for clamping. The input signal is clamped to VCLP via the CLP_A/B pulse
during each pixel period, as shown in Figure 6a. Because the ac-coupling capacitor is charged on a pixel-to-pixel
basis, the clamp level droop can be controlled by the clamp pulse width.
In line clamp mode, SHP_A/B is used for clamping when CLPDM is active, as shown in Figure 6b. The input
signal is clamped only in the CLPDM period within one line cycle of the sensor. The signal is clamped in this
method because the charge leaks the least from the coupling capacitor during the CLPDM period. Accordingly,
because there may be a large droop in the clamp level, this device does not support line clamp in the SH mode.
The not-clamped mode is mainly used in for a CMOS sensor input. If the sensor signal is directly connected to
the AFE, this mode should be configured without an ac-coupling capacitor at the input port. This mode has two
options to select a reference for the sensor black level: internal reference and external input. In the internal
reference option, the internal reference (VCLP) is used with AINx_CLP_SEL = 2. In the external input option, the
external input is used from AINGNDx with AINx_CLP_SEL = 3.
(1) x = AIN channel number, x = 1, 2, 3, and 4.
(2) y = Group code of sample pulse signals. When x = 1 or 2, y = A. When x = 3 or 4, y = B.
Figure 6. Input Clamp Function
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As shown in Figure 7, the internal VCLP node provides the clamp reference voltage. As for the clamp level, it is
possible to select three reference voltage modes by setting the AINx_REF_SEL register. The first mode provides
a fixed 2.2 V, the second mode provides selectable outputs (0.5 V, 1.1 V, 1.5 V, and 2.0 V) of an internal DAC,
and the third mode allows an external input from the REF_AIN pin to be used as the clamp reference. This
REF_AIN pin is bidirectional and also acts as an output of the internal DAC. Table 5 shows the relationship
between the register and clamp level. Table 6 shows the DAC configuration.
(1) If the sensor signal is directly input to the AFE, the enternal capacitor should not be connected.
Figure 7. VCLP Block Diagram
Table 5. Clamp Level Selection
MODE SETTING
AINx_REF_SEL[1:0](1) CLAMP LEVEL
0 2.2 V Reference DAC (0.5 V, 1.1 V, 1.5 V, and
1 VRINT 2.0 V)
2 VREXT REF_AIN external input
(1) AINx_CLP_SEL (x = 1, 2, 3, and 4).
Table 6. VRINT Voltage Selection
SETTING CODE VRINT_SEL REF DAC VRINT (V)
2 0.5
3 1.1
0 1.5 (default)
1 2.0
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AINx
(External)
LS
(Internal)
CLPDM
(Internal)
DummyPixels OpticalBlack ActivePixels
LineClampPeriod
DM_END+1
DM_STR +1
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If line clamp mode is used, the CLPDM period should be configured by the internal registers. The CLPDM period
is determined with reference to the line cycle signal for the sensor (LS). Thus, the start and end of CLPDM are
each defined as the number of pixels from the LS falling edge. Because CLPDM is used as the clamp period, it
should be assigned for the interval of any dummy or optical black pixels. Figure 8 shows the relationship
between LS and CLPDM.
Figure 8. Line Clamp Period Setting
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36 0 120362412
48 48
DLLSetting
Number
SHP_y
CLP_y
SHP_y_TR
t =t /2
CW_y PW_Y
tPW_Y
SHP_y_TF
36 0 120362412
48 48
DLLSetting
Number
SHP_y
CLP_y
SHP_y_TR
SHP_y_TF
CLP_y_TF
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Pixel Clamp Period Setting
In pixel clamp mode, without CLPDM, the sensor signal is clamped with CLP_A and CLP_B pulses. CLP_A
corresponds to AIN1 and AIN2; CLP_B corresponds to AIN3 and AIN4. The start of these pulses is synchronized
with the SHP_y rising edge (where y = A or B). There are two options to configure the end position: first, to
automatically set the pulse width to 50% that of SHP_y; and second, to manually configure the end position
using an internal register. Figure 9 and Figure 10 illustrate the details of the clamp pulse function in automatic
and manual mode, respectively.
Automatic Mode (CLP_TF_AT_DIS = 0)
Figure 9 shows the automatic mode when CLP_TF_AT_DIS is '0'.
Figure 9. Automatic Mode
Manual Mode (CLP_TF_AT_DIS = 1)
Figure 10 shows the manual mode when CLP_TF_AT_DIS is '1'.
Figure 10. Manual Mode
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In pixel clamp mode when CLPDM is active, the sensor signal is clamped with SHP_y. Therefore, the pixel clamp
operation is closely related with the status of CLPDM. The condition of CLPDM should be properly defined with
the internal registers. Because CLPDM is always high during a default condition after reset or power up, the
status of CLPDM should be defined according to this sequence. Furthermore, the CLPDM status should be
defined in the second step of the flowchart shown in Figure 11 for either configuration. All other user-dependent
settings, except XLSYNC_SEL and EN_OUT of the software reset sequence, are described in Figure 11.
(1) Internal registers: AINx_CLP_SEL = addresses 16 and 17; LINT = address 7; DM_STR = address 8; DM_END = address 9; and
EN_CLPDM = address 399, bit 1.
Figure 11. Configuration Sequence for Pixel Clamp
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3.5
3
2.5
2
1.5
1
0.5
0
064
InputCodeforAnalogGainControl(0LSBto63LSBs)
Gain(V/V)
8 403224 48 5616
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
064
InputCodeforAnalogGainControl(0LSBto63LSBs)
InputRange(V)
8 403224 48 5616
DPG(V/V)= ´Code+1 (Code=0LSBto255LSB)
1
256
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0256
InputCodeforDigitalGainControl(0LSBto255LSBs)
DigitalGain(V/V)
32 16012896 192 22464
VSP5620
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ANALOG PROGRAMMABLE GAIN (APG)
The SH output can be amplified using programmable analog gain. This gain can be set from 0.5 V/V to 3.5 V/V
with a step size of 3/64 V/V.
The gain setting can be controlled by an internal register (APG_x). Equation 1 shows the relationship between
the setting code and gain. The gain of each of the four channels can be set independently using different
registers. Note that the black pixel level may possibly change as a result of the change in the gain; therefore, the
appropriate timing of the gain change should be used to avoid degradation in image quality. Figure 12 shows
analog gain as a function of gain control code in terms of V/V. Figure 13 shows the maximum allowed input
signal as a function of gain control code.
(1)
Figure 12. Analog Gain vs Setting Code Figure 13. Input Range vs Analog Gain Setting
Code
DIGITAL PROGRAMMABLE GAIN (DPG)
The VSP5620/21/22 provides a maximum digital gain of 2 V/V. The total gain is fixed by the combination of
CDS/SH analog gain (APG) and digital gain (DPG). DPG is controlled by an 8-bit internal register (DPG_x) that
can set the gain from 1 V/V to 2 V/V, as defined by Equation 2. This register is included in each of the four
channels, so the gain of each channel can be set independently.
Figure 14 shows the relationship between the digital gain and register code. Note that the default value is 1 V/V.
(2)
Figure 14. Digital Gain Setting Code
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DACOutput(mV)= ´OFDAC_x[7:0]
250
128
300
200
100
0
100
200
300
-
-
-
-128 128
8-BitDACCode(LSB)
DACOutput(mV)
-96 320-32 64 96-64
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ADC
The ADC output format is selectable as twos complement or offset binary by configuring a register. Table 7
shows the relationship between register setting and condition.
Table 7. ADC Data Format Configuration
ADC_DAT_FRM MODE
0 (default) Twos complement
1 Offset binary
OFFSET DAC
The VSP5620/21/22 have an independent DAC in each channel for offset level correction of the input signal. The
correction range is ±250 mV and resolution is 8 bits. The DAC output voltage can be set by register settings.
Table 8 and Figure 15 show the relationship between the output and setting codes. The setting code is defined in
twos complement format. The DAC output offset voltage in millivolts as a function of the register setting is given
in Equation 3.
Table 8. Offset DAC Setting Code
SETTING CODE
OFDAC_x[7:0](1) OUTPUT (mV)
7Fh 248.05
7Eh 246.09
… …
01h 1.95
00h 0
FFh –1.95
… …
81h –248.05
80h –250.00
(1) ×= 1, 2, 3, and 4.
where:
x = 1, 2, 3, and 4 (3)
Figure 15. Offset DAC Setting Code vs Output Voltage
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): VSP5620 VSP5621 VSP5622
MCLK
(External) ・・・・・
MCK
(Internal)
・・・・・
LS_INT
(Internal)
LS
(Internal)
3
・・・・・ LINT-3 0 1LINT-2 LINT-1 LINT
PIX_CNT[19:0]
(Internal) 1 2LINT-3 LINT-1 LINT 0LINT-2
tLINE
tXLS_ACT
XLSYNC
(External)
More Than3Clocks
XLSYNC_POL =0(ActiveHigh)
tXLS_H tXLS_S tXLS_H tXLS_S
MCLK
(External)
・・・・・
MCK
(Internal)
・・・・・
XLSYNCMaskPeriod XLSYNCUnmaskPeriod
LS_MSK
(Internal)
LS
(Internal)
PIX_CNT[19:0]
(Internal)
10LINT +1LINT 1-LINT
XLSYNCMaskPeriod
VSP5620
VSP5621
VSP5622
SBES022 –JULY 2011
www.ti.com
TIMING GENERATOR (TG)
The image sensor timing generator (TG) is incorporated into these devices. The TG provides two signals that
function as slow transfer clocks and one signal that function as a fast transfer clock. The TG signals are
synchronized with LS (which is the image sensor line cycle) and are completely controlled by the internal
registers. Because the TG output is locked under the default setting, EN_OUT (address 2, bit 10) should be set
to '1' to enable the outputs.
LINE SYNCHRONOUS FUNCTION
The VSP5620/21/22 have two modes for synchronizing the sensor line cycle: internal line (Figure 16) and
external line syncronous mode (Figure 17). In internal line synchronous mode, the line cycle signal (LS) is
generated after a certain number of MCLK cycles that are counted by an internal counter (PIX_CNT). The
number of MCLK cycles is determined by the LINT[19:0] register; the counter clears after LS is generated. The
active LS period is equal to one MCLK cycle period.
Figure 16. Internal Line Synchronous Mode (XLSYNC_SEL = 1)
Figure 17. External Line Synchronous Mode (XLSYNC_SEL = 0, default)
Table 9. Timing Requirements for Figure 16 and Figure 17
PARAMETER TEST CONDITION MIN TYP MAX UNIT
tLINE Line cycle period setting XLSYNC = 1 3 LINT + 1 220 –1 Clocks
tXLS_ACT XLSYNC active period XLSYNC = 0 3 Clocks
tXLS_S XLSYNC setup to MCLK XLSYNC = 0 10 ns
tXLS_H XLSYNC hold to MCLK XLSYNC = 0 10 ns
28 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5620 VSP5621 VSP5622
VSP5620
VSP5621
VSP5622
www.ti.com
SBES022 –JULY 2011
The other mode is the external line synchronous mode which requires an external signal (XLSYNC). In this
mode, if the logic circuit detects an active XLSYNC period for more than three MCLK cycles, the internal line
synchronous signal (LS) is generated. This mode has a function that mask XLSYNC in order to avoid noise
interference. The duration of the XLSYNC mask can be set by the LINT[19:0] register, which is also used in the
internal line synchronous mode.
The two line synchronous modes and the polarity can be selected by the XLSYNC_SEL and XLSYNC_POL
registers, respectively. The default settings are external mode and active high polarity. XLSYNC can be used to
output some internal signals. Table 10 shows the register settings required to select the desired output signals.
PIX_CNT can be automatically reset by LS_CNT_RST (which is an internal register). Before performing this
function, a software reset must be executed in order set RST_ALL to '1'. If LS_CNT_RST is set to '1' after a
software reset, the pixel counter is then held at '0'. To make the counter active, LS_CNT_RST should return to
'0'.
Table 10. XLSYNC Output Signal (XLSYNC_SEL = 1)
REGISTER SETTING
XLSYNC_OUT OUTPUT SIGNAL
0 LS
1 CLPDM
2 Reserved
3 Reserved
SLOW TRANSFER CLOCK SETTING (XST, XSH1)
XST and XSH1 are slow transfer clocks that can be configured by setting the initial polarity and toggle points. As
shown in Table 11, the predetermined number of toggle points is different for each signal. Because the two
toggles generate one pulse, the number of pulses is half the number of toggles.
Table 11. Toggle Number and Generated Pulse
SIGNAL TOGGLE PULSE
XST 8 4
XSH1 16 8
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): VSP5620 VSP5621 VSP5622
LS
(Internal)
XSTConfiguration
Toggle
Setting
XST_P =0(InitialPolarity=Low)
XST
(Output)
・・・
XST_P =1(InitialPolarity=High)
XST
(Output)
・・・
XSH1Configuration
Toggle
Setting
XSH1_P =0(InitialPolarity=Low)
XSH1
(Output)
・・・
XSH1_P =1(InitialPolarity=High)
XSH1
(Output) ・・・
XST_T7+1
XST_T6+1
・・
XST_T1+1
XST_T0+1
XSH1_T15+1
・・
XSH1_T2+1
XSH1_T1+1
XSH1_T0+1
1LineCycle(Max=MCLK 2 )´20
VSP5620
VSP5621
VSP5622
SBES022 –JULY 2011
www.ti.com
Each toggle position is defined by a register that is exclusive for each signal. The toggle position is synchronized
with LS and the gap between the toggle position and the LS falling edge. The LS falling edge is defined in terms
of tMCLK, the cycle period of MCLK. This gap is set by register settings and is defined by Equation 4:
t = (Xn_T(k) + 1) ×tMCLK
where:
n = ST, SH1
k = 0 to 7 (XST); k = 0 to 15 (XSH1)
Xn_T(k) is less than LINT and is the register value of the toggle setting (4)
The toggle for each signal can be disabled with register settings. To make the toggle active, Xn_TGL_EN should
be set to '1'. However, because XST shares a pin with GPIO3, pin function should be configured with the
GPIO3_XST_SEL register. Figure 18 shows the configuration regarding the slow transfer clock.
(1) If Xn_Tn is set to '0', the toggle position is ignored (except for Xn_T0).
(2) The period between the toggle position and LS falling edge = (Xn_T(k) + 1) ×tMCLK.
(3) The following requirement must be satisfied: Xn_T(k) <Xn_T(k + 1).
(4) The signal is set to the desired polarity settings at the falling edge of LS.
Figure 18. Slow Transfer Gate Signal Setting for XST and XSH1
30 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5620 VSP5621 VSP5622
MCLK
(External)
tMCKD
MCK
(Internal)
x1Mode tTR_P1_x1
tTF_P1_x1
XP1
(Output)
x2Mode tTR_P1_x2
tTF_P1_x2
XP1
(Output)
tMCLK
tP1
tW_P1
tP1
tW_P1
VSP5620
VSP5621
VSP5622
www.ti.com
SBES022 –JULY 2011
FAST TRANSFER CLOCK PULSE SETTING
XP1 is a fast transfer clock signal with rising and falling edges that are configurable via register settings. The DLL
Tap Selector is used to select both the rising and falling edges of each signal from among 48 tap positions.
In addition, it is possible to change the clock rate with register settings. The clock rate is based on the frequency
of MCLK. XP1 can select between the x1 and x2 rate settings.
Note that two independent sets of registers are available to set the clock rate, the clock rising edge, and the
clock falling edge for operation in x1-mode and x2-mode.
Figure 19 describes the timing of the fast transfer clock pulse for XP1.
Figure 19. XP1 Fast Transfer Clock Pulse Setting
Table 12. Timing Requirements for Figure 19
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSP5620 1 11.66 MHz
fMCLK MCLK frequency VSP5621 1 16.66 MHz
VSP5622 1 23.33 MHz
tMCLK MCLK period 1/fMCLK ns
tMCKD MCLK to MCK delay 2 ns
x1 mode tMCLK ns
tP1 XP1 period x2 mode tMCLK ×1/2 ns
tTR_P1_x1 x1 mode 0 tMCLK ×47/48 ns
XP1 rising edge delay from MCK
tTR_P1_x2 x2 mode 0 tMCLK ×23/24 ns
tTF_P1_x1 x1 mode 0 tMCLK ×47/48 ns
XP1 falling edge delay from MCK
tTF_P1_x2 x2 mode 0 tMCLK ×23/24 ns
x1 mode 2 tMCLK –2 ns
tW_P1 XP1 pulse width x2 mode 2 tMCLK ×1/2 –2 ns
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): VSP5620 VSP5621 VSP5622
LEDVDD
VLD
Vf
LEDn
LEDVSS
ILD
RR x ILD
・・・ ・
Coarse Current Cell
4 mA x 14
4mA4mA4mA
Fine Current Cell
1 mA x 4
1mA1mA1mA 1mA
LEDn_EN
(Register)
EN_LED
LEDn_EN
VSP5620
VSP5621
VSP5622
SBES022 –JULY 2011
www.ti.com
LED DRIVER
These devices have three constant-current sink LED driver channels. The output current for each channel can be
independently set via register settings within a 0 mA to 60 mA range in 4-mA steps. The maximum allowable
total constant-current value for all three channel drivers is 120 mA. Because the circuitry that limits the total
constant-current is not incorporated, the current value should be carefully set when multiple channels are
concurrently active.
Figure 20 shows an LED driver block diagram and the connection with the external LED device. This driver
supports VLD (driver voltage) within a range of 0.7 V to 4.5 V. VLD depends on the VF(LED forward voltage)
because this driver is a constant-current source. The LED driver power consumption, defined as VLD ×ILD (LED
current), affects package temperature. Therefore, when VFis small, it is recommended to insert an external
resister between LEDn (the LED driver pin) and LEDVDD (the LED power supply) to reduce thermal affects
caused by high-power consumption.
Figure 20. LED Driver Block Diagram
This driver can be turned on or off with a combination of logic circuitry driven by internal register settings and
external pins, as shown in Table 13. Note that the internal EN_LED register should be set to '1' to enable the
logic circuit.
Table 13. LED Driver Control Register and Pin Setting(1)
EN_LED REGISTER LEDN_EN PIN SETTING LEDN_EN REGISTER LED DRIVER STATE
0 X X Disabled
Low 0 Disabled
Low 1 Enabled
1High 0 Enabled
High 1 Disabled
(1) n = 1, 2, and 3.
32 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5620 VSP5621 VSP5622
A9 A8 ¼A1 A0 D19 D18 ¼D1 D0
MSB LSB
10-BitAddress 20-BitData
XX A[9:0] D[19:0] XX A[9:0]
SEN
SCLK
SDI
VSP5620
VSP5621
VSP5622
www.ti.com
SBES022 –JULY 2011
SERIAL INTERFACE
All device functions and settings are controlled through the serial interface. The serial interface consists of three
signals (SCLK, SEN, and SDI) for register writing, and a fourth signal (SDO) for readback. SDO shares the
terminal with the GPIO signal; thus, a register setting is required to activate the SDO function. Other signals are
assigned to individual terminals.
Serial data are composed of 30 bits total, as shown in Figure 21. 10 bits are assigned for the register address
and 20 bits for register data. The input serial data at SDI are sequentially stored in a shift register at the SCLK
rising edge. Data shift operation is performed at the SCLK rising edges with SEN low. All 30 input data bits are
loaded to a parallel latch in an internal register at the rising edge of SEN.
This device has two modes: read and write. The mode selection can be made via the SPL_RW internal register,
located at bit 0 of address 0. SPL_RW = 0 implies a write mode and SPL_RW = 1 implies read mode.
Figure 21. Serial I/F Data Format
WRITE MODE (SPI_RW = 0, Default)
Normally, one serial interface command is sent by one address and data combination. The address should be
sent MSB first. Data are stored into the respective register, as indicated by the address. If the serial data at the
end of the data stream are less than 30 bits, the last incomplete serial data are discarded. Figure 22 shows the
SPI signal flow while in write mode.
Figure 22. SPI Signal Flow of Write Mode
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): VSP5620 VSP5621 VSP5622
SEN
SCLK SCLK
SDI
SDI
SDO
SDO
SEN
SDO_EN
Device ASIC/CPU
a)Four-WireConnection
SDIInputPort:SDI_BUFF_CTRL=0
SEN
SCLK SCLK
SDI
SDIO
SEN
SDO_EN
Device ASIC/CPU
b)Three-WireConnection
SDIBidirectionalPort:SDI_BUFF_CTRL=1
SDO
XX A[9:0],Input D[19:0],Input XX A[9:0],Input
D[19:0],Output
Hi-Z Hi-Z
20SCLKCycles
for20-BitData
SEN
SCLK
SDI
SDO
SDO_EN
(Internal)
XX A[9:0],Input D[19:0],Input XX A[9:0],Input
20SCLKCycles
for20-BitData
SEN
SCLK
SDI/SDO
SDO_EN
(Internal)
VSP5620
VSP5621
VSP5622
SBES022 –JULY 2011
www.ti.com
READ MODE (SPI_RW = 1)
In read mode, two types of connections are possible between the AFE and external systems such as an ASIC or
CPU. One connection is the four-wire connection in which the SDI and SDO pins are separately connected to the
system as shown in Figure 23a.
The other connection is a three-wire connection in which only the SDI pin is connected to the bidirectional I/O
port of the external system, as shown in Figure 23b. In this case, SDI_BUFF_CTRL should be set to '1' to create
an SPI bidirectional port. The bit flow of the four-wire connection is shown in Figure 24. The bit flow of the
three-wire connection is shown in Figure 25. As shown in Figure 25, SDI changes from an input to an output at
the SCLK falling edge after the end of the A[9:0] input. Because the SDI port is always in pull down mode, the
external pull down resistance is unnecessary.
Figure 23. SPI Connection Between AFE and System
Figure 24. SPI Signal Flow of Read Mode for Four-Wire Connection
Figure 25. SPI Signal Flow of Read Mode for Three-Wire Connection
34 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5620 VSP5621 VSP5622
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
VSP5620RSLR ACTIVE VQFN RSL 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
VSP5621RSLR ACTIVE VQFN RSL 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
VSP5622RSLR ACTIVE VQFN RSL 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
VSP5620RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
VSP5621RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
VSP5620RSLR VQFN RSL 48 2500 367.0 367.0 38.0
VSP5621RSLR VQFN RSL 48 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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