High Speed SRAM
32K-Word By 8 Bit CS18HS02565
1 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date Remark
1.3
1.4
1.5
1.6
1.7
1.8
Add green code in part no.
Add in 28L TSOP 1-8x13.4mm
Remove 28L TSOP 1-8x13.4mm
Revise speed option and DC/AC Characteristics.
Remove 28L PDIP 300mil
Increase version description in Order Information
Jul. 22, 2005
Mar. 10,2006
Jun. 12,2006
Mar. 05,2007
Apr. 24,2007
Sep, 05, 2008
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
2 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
DESCRIPTION
The CS18HS02565 series products are 32,768-words by 8-bits static RAMs fabricated with
advanced 8" wafer submicron CMOS technology. Using unique CMOS peripheral circuits and special
poly-load 4-transistor memory cells, the CS18HS02565 series products exhibit very high-speed
performance with single +5-volt power supply while requiring low power and no clock or refreshing to
operate. The CS18HS02565 is packed in 28-pin SOP-330mil and 28-pin SOJ-300mil.
FEATURES
1. 32,768-word x 8-bit organization
2. Operation voltage: 4.5 ~ 5.5V
3. Fully static operation: no clock or refreshing required
4. LVTTL-compatible inputs and outputs
5. Common I/O capability
6. Low power consumption
Active: 45/35 mA（Max.）
Standby: 350μA
7. Very high speed access: 10/12 ns
8. Output Enable ( OE ) available for very fast access
Product Family
Part No. Operating
Temp
Vcc.
Range Speed (ns) Supply Current
mA (Max.) Package Type
10 45
CS18HS02565 0~70oC 4.5~5.5V
12 35
28 SOP-330mil
28 SOJ-300mil
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
3 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
PIN CONFIGURATIONS
BLOCK DIAGRAM
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
4 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
PIN DESCRIPTIONS
Symbols Functions
A0〜A14 Address Inputs
I/O1〜I/O8 Data Inputs / Outputs
CS Chip Select Input
WE Write Enable Input
OE Output Enable Input
VCC Power Supply
VSS Ground
TRUTH TABLE
CS OE WE Mode I/O1〜I/O8 VCC Current
H X X Not Selected High Z ISB, ISB1
L H H Output Disable High Z IDD
L L H Read Data Out IDD
L X L Write Data In IDD
ABSOLUTE MAXIMUM RATINGS
Parameters Rating Unit
Supply Voltage to Vss -0.5 to +7.0 V
Input/Output to Vss -0.5 to VCC +0.5 V
Allowable Power Dissipation 1.5 W
Storage Temperature -65 to +150 ℃
Operating Temperature 0 to +70 ℃
OPERATING RANGE
Range Ambient Temperature Vcc
Commercial 0~70oC 5.0V±5%
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
5 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V, Vss = 0V, Ta = 0 to 70℃)
Parameters Symbols Test Conditions Min. Typ. Max Unit
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.2 - VCC+0.5 V
Input Leakage Current ILI V
IN = VSS to VCC -1 - +1
μA
Output Leakage Current ILO VI/O = VSS to VCC, CS = VIH
or OE = VIH or WE = VIL
-1 - +1
μA
Output Low Voltage VOL I
OL = +8.0mA - - 0.4 V
Output High Voltage VOH I
OH = -4.0mA 2.4 - - V
10 - - 45 mA
Operating Power
Supply Current
IDD CS = VIL, I/O = 0 mA
Cycle = MIN
Duty = 100%
12 - - 35 mA
ISB CS = VIH, Cycle = MIN
Duty = 100%
- - 1 mA
Standby Power Supply
Current
ISB1 CS≧ V
CC -0.2V - - 350
μA
Note: Typical characteristics are measured at VCC = 5 V, Ta = 25℃
AC Characteristics:
Capacitances
(VCC = 5V, Ta = 25℃, f = 1 MHz)
Parameters Symbols Conditions Max. Unit
Input Capacitance CIN V
IN = 0V 8 pF
Input/Output Capacitance CI/O V
OUT = 0V 10 pF
Note: These parameters are sampled but not 100% tested.
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
6 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
AC Test Conditions
Parameters Conditions
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3 ns
Input and Output Timing Reference Level 1.5V
Output Load CL = 30 pF, IOH/IOL = -4 mA / 8 mA
AC Test Loads and Waveforms
30 pF
Including
Jig and
Scope
5V
OUTPUT
R2 = 255 ohm
••
R1 = 480 ohm
5 pF
Including
Jig and
Scope
5V
OUTPUT
R2 = 255 ohm
••
R1 = 480 ohm
(For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW)
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
7 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
AC Performances:
(VCC = 5V, VSS = 0V, Ta = 0 to 70℃)
(1) Read Cycle
CS18HS02565-10 CS18HS02565-12
Parameters Symbols
Min. Max. Min. Max.
Unit
Read Cycle Time TRC 10 - 12 - ns
Address Access Time TAA - 10 - 12 ns
Chip Select Access Time TACS - 10 - 12 ns
Output Enable to Output Valid TAOE - 6 - 6 ns
Chip Selection to Output in Low Z TCLZ* 2 - 3 - ns
Output Enable to Output in Low Z TOLZ* 0 - 0 - ns
Chip Deselection to Output in High Z TCHZ* - 5 - 6 ns
Output Disable to Output in High Z TOHZ* - 5 - 7 ns
Output Hold from Address Change TOH 2 - 2 - ns
These parameters are sampled but not 100% tested
(2) Write Cycle
CS18HS02565-10 CS18HS02565-12
Parameters Symbols
Min. Max. Min. Max.
Unit
Write Cycle Time TWC 10 - 12 - ns
Chip Selection to End of Write TCW 9 - 10 - ns
Address Valid to End of Write TAW 9 - 10 - ns
Address Setup Time TAS 0 - 0 - ns
Write Pulse Width TWP 9 - 9 - ns
Write Recovery Time TWR 0 - 0 - ns
Data Valid to End of Write TDW 7 - 7 - ns
Data Hold from End of Write TDH 0 - 0 - ns
Write to Output in High Z TWHZ* - 6 - 6 ns
Output Disable to Output in High Z TOHZ* - 6 - 6 ns
Output Active from End of Write TOW 0 - 0 - ns
These parameters are sampled but not 100% tested
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
8 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
Timing Waveforms
Read Cycle 1
(Address Controlled)
TRC
T
OH
T
AA T
OH
Address
DOUT
Read Cycle 2
(Chip Select Controlled)
TACS
TCLZ
TCHZ
CS
DOUT
Read Cycle 3
(Output Enable Controlled)
TRC
TAOE
TAA
Address
DOUT
OLZ
T
ACS
TCLZ
TOH
TOHZ
TCHZ
CS
OE
T
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
9 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
Write Cycle 1
(OE Clock)
TWC
TWP
TCW
Address
DOUT
AS
TAW
CS
T
TWR
TOHZ (1,4)
TDW TDH
WE
DIN
OE
Write Cycle 2
(OE = VIL Fixed)
TWC
TWP
TCW
Address
DOUT
AS
TAW
CS
T
TDW TDH
WE
DIN
TWR
TWHZ
(1,4)
TOH
TOW
(2) (3)
High Speed SRAM
32K-Word By 8 Bit CS18HS02565
10 Rev. 1.8
Chiplus reserves the right to change product or specification without notice.
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the
outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is
guaranteed but not 100% tested.
ORDER INFORMATION
Note: Package material code “R” meets ROHS
