High Speed SRAM 32K-Word By 8 Bit CS18HS02565 Revision History Rev. No. History Issue Date 1.3 Add green code in part no. Jul. 22, 2005 1.4 Add in 28L TSOP 1-8x13.4mm Mar. 10,2006 1.5 Remove 28L TSOP 1-8x13.4mm Jun. 12,2006 1.6 Revise speed option and DC/AC Characteristics. Mar. 05,2007 1.7 Remove 28L PDIP 300mil Apr. 24,2007 1.8 Increase version description in Order Information Sep, 05, 2008 Remark 1 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM CS18HS02565 32K-Word By 8 Bit DESCRIPTION The CS18HS02565 series products are 32,768-words by 8-bits static RAMs fabricated with advanced 8" wafer submicron CMOS technology. Using unique CMOS peripheral circuits and special poly-load 4-transistor memory cells, the CS18HS02565 series products exhibit very high-speed performance with single +5-volt power supply while requiring low power and no clock or refreshing to operate. The CS18HS02565 is packed in 28-pin SOP-330mil and 28-pin SOJ-300mil. FEATURES 1. 32,768-word x 8-bit organization 2. Operation voltage: 4.5 ~ 5.5V 3. Fully static operation: no clock or refreshing required 4. LVTTL-compatible inputs and outputs 5. Common I/O capability 6. Low power consumption Active: 45/35 mAMax. Standby: 350A 7. Very high speed access: 10/12 ns 8. Output Enable ( OE ) available for very fast access Product Family Part No. Operating Vcc. Temp Range Speed (ns) 10 CS18HS02565 0~70oC Supply Current mA (Max.) Package Type 45 28 SOP-330mil 4.5~5.5V 28 SOJ-300mil 12 35 2 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM 32K-Word By 8 Bit CS18HS02565 PIN CONFIGURATIONS BLOCK DIAGRAM 3 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM CS18HS02565 32K-Word By 8 Bit PIN DESCRIPTIONS Symbols Functions A0A14 Address Inputs I/O1I/O8 Data Inputs / Outputs CS WE OE Chip Select Input Output Enable Input VCC Power Supply VSS Ground Write Enable Input TRUTH TABLE CS OE WE Mode I/O1I/O8 VCC Current H X X Not Selected High Z ISB, ISB1 L H H Output Disable High Z IDD L L H Read Data Out IDD L X L Write Data In IDD ABSOLUTE MAXIMUM RATINGS Parameters Rating Unit -0.5 to +7.0 V -0.5 to VCC +0.5 V 1.5 W -65 to +150 0 to +70 Range Ambient Temperature Vcc Commercial 0~70oC 5.0V5% Supply Voltage to Vss Input/Output to Vss Allowable Power Dissipation Storage Temperature Operating Temperature OPERATING RANGE 4 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM CS18HS02565 32K-Word By 8 Bit DC ELECTRICAL CHARACTERISTICS (VCC = 5V, Vss = 0V, Ta = 0 to 70) Parameters Symbols Test Conditions Min. Typ. Max Unit Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.2 - VCC+0.5 V Input Leakage Current ILI -1 - +1 A Output Leakage Current ILO -1 - +1 A VIN = VSS to VCC VI/O = VSS to VCC, CS = VIH or OE = VIH or WE = VIL Output Low Voltage VOL IOL = +8.0mA - - 0.4 V Output High Voltage VOH IOH = -4.0mA 2.4 - - V Operating Power IDD - - 45 mA - - 35 mA - - 1 mA - - 350 A CS = VIL, I/O = 0 mA Supply Current 10 Cycle = MIN 12 Duty = 100% Standby Power Supply ISB Current CS = VIH, Cycle = MIN Duty = 100% ISB1 CS VCC -0.2V Note: Typical characteristics are measured at VCC = 5 V, Ta = 25 AC Characteristics: Capacitances (VCC = 5V, Ta = 25, f = 1 MHz) Parameters Symbols Conditions Max. Unit Input Capacitance CIN VIN = 0V 8 pF Input/Output Capacitance CI/O VOUT = 0V 10 pF Note: These parameters are sampled but not 100% tested. 5 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM CS18HS02565 32K-Word By 8 Bit AC Test Conditions Parameters Conditions Input Pulse Levels 0V to 3V Input Rise and Fall Times 3 ns Input and Output Timing Reference Level 1.5V Output Load CL = 30 pF, IOH/IOL = -4 mA / 8 mA AC Test Loads and Waveforms R1 = 480 ohm 5V OUTPUT R1 = 480 ohm 5V * * 30 pF Including Jig and Scope R2 = 255 ohm OUTPUT * * 5 pF Including Jig and Scope R2 = 255 ohm (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW) 6 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM CS18HS02565 32K-Word By 8 Bit AC Performances: (VCC = 5V, VSS = 0V, Ta = 0 to 70) (1) Read Cycle Parameters Symbols CS18HS02565-10 CS18HS02565-12 Min. Max. Min. Max. Unit Read Cycle Time TRC 10 - 12 - ns Address Access Time TAA - 10 - 12 ns Chip Select Access Time TACS - 10 - 12 ns Output Enable to Output Valid TAOE - 6 - 6 ns Chip Selection to Output in Low Z TCLZ* 2 - 3 - ns Output Enable to Output in Low Z TOLZ* 0 - 0 - ns Chip Deselection to Output in High Z TCHZ* - 5 - 6 ns Output Disable to Output in High Z TOHZ* - 5 - 7 ns Output Hold from Address Change TOH 2 - 2 - ns These parameters are sampled but not 100% tested (2) Write Cycle Parameters Symbols CS18HS02565-10 CS18HS02565-12 Min. Max. Min. Max. Unit Write Cycle Time TWC 10 - 12 - ns Chip Selection to End of Write TCW 9 - 10 - ns Address Valid to End of Write TAW 9 - 10 - ns Address Setup Time TAS 0 - 0 - ns Write Pulse Width TWP 9 - 9 - ns Write Recovery Time TWR 0 - 0 - ns Data Valid to End of Write TDW 7 - 7 - ns Data Hold from End of Write TDH 0 - 0 - ns Write to Output in High Z TWHZ* - 6 - 6 ns Output Disable to Output in High Z TOHZ* - 6 - 6 ns TOW 0 - 0 - ns Output Active from End of Write These parameters are sampled but not 100% tested 7 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM CS18HS02565 32K-Word By 8 Bit Timing Waveforms Read Cycle 1 (Address Controlled) TRC Address TOH TAA TOH DOUT Read Cycle 2 (Chip Select Controlled) CS DOUT TACS TCHZ TCLZ Read Cycle 3 (Output Enable Controlled) TRC Address TAA OE TAOE CS TOLZ TACS DOUT TOH TCLZ TOHZ TCHZ 8 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM CS18HS02565 32K-Word By 8 Bit Write Cycle 1 ( OE Clock) TWC Address TWR OE TCW CS WE DOUT TAW TWP TAS TOHZ (1,4) TDW TDH DIN Write Cycle 2 ( OE = VIL Fixed) TWC Address TWR TCW CS TAW WE TAS TWP TWHZ DOUT (1,4) TDW TOH TOW (2) (3) TDH DIN 9 Rev. 1.8 Chiplus reserves the right to change product or specification without notice. High Speed SRAM 32K-Word By 8 Bit CS18HS02565 Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500mV from steady state with CL = 5pF. This parameter is guaranteed but not 100% tested. ORDER INFORMATION Note: Package material code "R" meets ROHS 10 Rev. 1.8 Chiplus reserves the right to change product or specification without notice.