FEB 42 1991 National February 1990 Low Power 9-Bit Buffer General Description Features: The F100322 is a monolithic 9-bit buffer. The device con- & 30% power reduction of the F100122 tains nine non-inverting buffer gates with single input and = 2000V ESD protection output. All inputs have 50 k0Q pull-down resistors and all = Pin/function compatible with F100122 outputs are buffered. @ Voltage compensated operating range = 4.2V to 5.7V Logic Symbol Dy _}> O1 Pin Names Description Ds > Oo Dy, Dg Data Inputs O01, Og Data Outputs % >or >o TL/F/10608-1 Connection Diagrams 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak C7 Ds DgVocaVersO4 O5 Og Dg Og VocaYer D7 Dg Yoo, 4! 244-0, ADAM Lj) | ji 0,42 23D, O 24 23 22 24 20 19 0-43 22D, anh 18F Ds 44 2k, Do 42 17D, os 20, O;-43 16 F Very Yoo 6 19} Veca Yeca 4 157% Veud? 7 0;-45 141-06, 0,-46 13-0 0,48 17 2 6 8 ; Le 7 8 9 10 11:12 6 (9) 2 Bl 2 a rTTtrrt Og. 10 15}Ds, Dy Do Ds VegsVoca0s 02 91 09 Voc Yorn 0g 97 Osa 4D, TL/F/106084 TL/F/10608-3 O,-q12 13PVecy TL/F/10608 -2 1990 National Semiconductor Corporation TL/F/ 10608 i RRAD-B20M20/ Printed in U. S.A 49}jNG WG-6 JOMOd MO] 2Z2E0014Absolute Maximum Ratings Above which the useful life may be impaired. (Note 1) if Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Output Current (DC Output HIGH) ESD (Note 2) 50 mA 2 2000V Recommended Operating Office/Distributors for availability and specifications. Conditions Storage Temperature (Tstq) 68C to + 150C Case Temperature (Tc) Maximum Junction Temperature (Ty) Commercial O to + 85C Ceramic +175C Military 55C to + 125C Plastic + 150C Supply Voltage (VEE) Vee Pin Potential to Ground Pin 7.0V to +0.5V Commercial 5,7V to 4.2V Input Voltage (DC) Ver to +0.5V Military 5.7V to 4.2V Commercial Version DC Electrical Characteristics VeE = 4.2V to 5.7V, Voc = Voca = GND, Tc = 0C to + 85C (Note 3) Symbol Parameter Min Max Units Conditions Von Output HIGH Voltage 1025 955 870 mV Vin = Vin (Max) Loading with VoL Output LOW Voltage 1830 | -1705 | 1620 or Vit (Min) 502 to 2.0V VoHc Output HIGH Voltage 1035 mV Vin = Vipin) Loading with VoLc Output LOW Voltage 1610 or ViL (Max) S00 to 2.0V Vin Input HIGH Voltage 4165 870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage 1830 1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 pA Vin = Vit (in) NH Input HIGH Current 240 pA Vin = VIH (Max) lEE Power Supply Current 65 30 mA Inputs Open Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the worst case vaiue for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = 4.2V to 5.7V, Voc = Veca = GND n = 2 = +4 o Symbol Parameter Te = oC Te = + 25C Te B5C Units Conditions Min Max Min Max Max tPLH Propagation Delay Figures 1 and 2 ton Data to Output 0.45 1.45 0.45 1.45 1.55 ns (Note 1) tTLH Transition Time Figures 1 and 2 tH 20% to 80%, 80% to 20% 0.35 1.20 0.35 1.20 1.20 ns Note 1: The propagation delay specified is for single output switching. Delays may vary up to 200 ps with muttipie outputs switching. PCC and Cerpak AC Electrical Characteristics Vee = 4.2V to 5.7V, Voc = Voca = GND =? = +25 = +85 Symbol Parameter Te = oC Te 25' Te 85C | units| Conditions Min Max Min Max Min Max 'PLH Propagation Delay Figures f and 2 - 25 4 . . . teu Data to Output 0.45 1 0.45 1.25 0.45 1.35 ns (Note 2) tly Transition Time . tH 20% to 80%, 80% to 20% 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures f and 2 tsG-G__| Skew, Gate to Gate TBD TBD TBD ps | PCC Only (Note 1) Note 1: Gate to gate skew is defined as the difference in propagation delays between each of the outputs. Note 2: The propagation delay specified is for single output switching. Delays may vary up to 200 ps with multiple outputs switching. 2Military VersionPreliminary DC Electrical Characteristics Vee = 4.2V to 5.7V, Voc = Vocoa = GND, To = OC to + 85C Symbol Parameter Min Max | Units Te Conditions Notes Vou Output HIGH Voltage | 1025 | 870 mV OC to + 126C 1085 | 870 mV 8C Vin =ViH (Max | Loading with 123 VoL Output LOW Voltage | 1830] 1620| mv | orCto +125_ | OF ViL min) 500 to 2.0V ~1830 | 1555 mV 55C VoHc Output HIGH Voltage | 1035 mv OC to + 125C 1085 mV 5C Vin = Vin (Max) | Loading with 1.24 Voic | Output LOW Voltage -1610| mv | oto +126C | % VIL (Min) 50 to 2.0V 71555 mV 55C ViH Input HIGH Voltage 1165 | 870 mV 55C to +125C Guaranteed HIGH Signal 1234 for All Inputs VIL Input HIGH Voltage 1830 | 1475 | mv 55C to + 125C Guaranteed LOW Signal 12.34 for All inputs Ne Input LOW Current 0.50 yA 55C to + 125 Vee = 4.2V 12.3 Vin = Vit (Min) tH Input HIGH Current 240 pA OC to + 125C Vee = 5.7V 1293 340 pA 55C VIN = Vind (Max) _ lee Power Supply Current 70 25 mA | 55C to + 125C | Inputs Open 1,2,3 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction ternperature equals 55C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at 55C, + 25C, and + 125C, Subgroups 1, 2, 3, 7, and 8. Note 3: Sample tested (Method 5005, Table 1) on each manufactured lot at 55C, + 25C, and + 125C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing Vou/ Vor. Ceramic Dual-In-Line Package AC Electrical Characteristics Veg = 4.2V to 5.7V, Voc = Voca = GND Symbol Parameter To = ~ 55C To ~ + 25C To ~ + 125C units} Conditions | Notes Min Max Min Max Min Max Pu Fropagation neey 030 180 | 040 160 | 040 180 | ns 1,2,3,5 PHL a P Figures ft and 2 tTLH Transition Time rit | 5006 to 80%. 80% to 20% | 290 120 | 090 120 | 030 1.20 | ns 4 Cerpak AC Electrical Characteristics Veg = 4.2V to 5.7V, Voc = Voca = GND Symbol Parameter To = ~ 55C Te = + 25C To = + 128C | units| Conditions | Notes Min Max Min Max Min Max Pld Propagation ney 030 180 | 040 14.60 | 040 # 1.80 | ns 1,2,3,5 PHL Pp Figures 1 and 2 ttLH Transition Time in |ao%e 10.80%. 80% to20%| 290 120 | 030 120 | 030 1.20 | ns 4 Note 1: FIQO0K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immediately after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at + 25C, only Subgroup A9. Note 3: Sample tested (Method 5005, Table I} on each manufactured lot at + 25C, Subgroup A9, and at + 125C and 55C temperatures, Subgroups At0 and All. Note 4: Not tested at + 25C, + 125C, and 55C temperature (design characterization data). Note 5: The propagation delay specified is for single output switching. Delays may vary up to 200 ps with multiple outputs switching. 3Test Circuit fi SCOPE V Nd CHAN A CC 04 AF Notes: $4 L Rr Voc. Voca = +2, Veg = 2,5V L1 and L2 = equal length 5029 impedance lines + + Ry = 502 terminator internal to scope ~ ~ Decoupling 0.1 wF from GND to Veg and Veg L2 All unused outputs are loaded with 509 to GND PULSE ry CIRCUIT] 7, SCOPE Cy = Fixture and stray capacitance < 3 pF GENERATOR]; ileal + CHAN B Lt L Ry 0.1,F = vee T" TL/F/10608-5 FIGURE 1. AC Test Circuit Switching Waveforms 0.7 +0.1 ~~ re ns +105 V 80% INPUT 50% 20% mo te 50% 20% wat al le FIGURE 2. Propagation Delay and Transition Times Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: OUTPUT TL/F/10608-6 100322 D C QR Device Type (basic) Special Variations QR = Commercial grade device Package Code with burn-in. D = Ceramic DIP QB = Military grade grade device F = Quad Cerpak with environmental and burn- Q = Plastic Leaded Chip Carrier (PCC) in processing. Temperature Range C = Commercial (0C to + 85C) M = Military (55C to + 126C)Physical Dimensions inches (millimeters) _ 1.215 _ (30.86) "| 0.025 MAX 0,030 0.055 (0.635) (0.762 1.397) RAD Pal [2a] Jez} jes) feo) [rs] [ve] [v7] fie) fxs) fia] fa RAD TYP 0.390 0.370 (9.906) ) (9.398) MAX GLASS + | Wiz] Lay tat is Ley Ley Led ed bo i 0.037 + 0.005 ~~ +0.127) 0.005. GLASS 0.055 +0.005 (0.9400. 0.400 0.430 0.180 {0.127} SEALANT {1.397 + 0.127} * 0.020- 0.070 (10.16 10.92) (4.572) MIN (0.508 1.778) ' MAX 1 N | 2 ) 0.225 J A A (5.715) H\ mr. h a ttt 95 +5 | sex ans TP J uu TYP * ig 203 0.305) 0.425 TyP 0.055 | 0.100+0.010 0.013 +0.003 (3.175) 0.485 + 0.050 (1.397) (2.540 + 0.254} (0.457 +0.076) MIN (12.3241.270) MAX TYP TYP BOTH ENDS J24E (REV G) 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) NS Package Number J24E t > 0.370 - 0.004 0.006_ ~~ g250-0360 | (9398) sg 2800360 + (0.102 0.152) (6.350 9.144) MIN SQUARE (6.350 - 9.144) TYP Tye PINND. 1 \ Lt 1) rf , 24 23:22 21 20 19, 1 ___J? tI 0 _ Ss F. a 4 ba o eee 5 _ o _______""J5 bBo 3 a 7 8 9 101112 0.075 (1.905) 8 PLCS 0.016 -0.018 _ | MAX _ 0.035 0.050 (0.4050.457} | 0.050 + 0.005 rr (0.889 1.270) TYP (1.2702 0.127) 0.085 0.406 TYP (2.159) * (10.16) MAX SQUARE MAX GLASS W24B (REV Cr 24-Lead Ceramic Flatpak (F) NS Package Number W24BF100322 Low Power 9-Bit Buffer Physical Dimensions inches (millimeters) (Continued) Lit. # 114907 6 SPACES AT VIEW A-A 005 | (143) x a& 0.4100.430 (10.41 10.82) SQUARE (CONTACT DIMENSICN) 0.020 0.0130.018 0.032 - 0.040 (0.508) 7 0.3300.457) 0.165 -0.180 (0.813 1.016) MIN TYP (4.191 ~ 4.572) tf wh pol rm 0.005 0.015 (0.127 - 0.381) S pwns f TI ooeeo02 Fo rou oe (DENT (0.660 0.813) (2.642 2.997) 0.450 TYP *~ 111.43) REF SQ 0.485 0.495 (12.32 12.57) SQUARE V2BA (REV G) 28-Lead Plastic Chip Carrier (Q) NS Package Number V28A LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. to the user. Semi NS Japan Ltd. Semb Semi Ni d Corporation GmbH Sanseido Bldg. SF Hong Kong Ltd. Do Grasil Lida. (AustraHa) PTY, Ltd. 2900 Semiconductor Drive Industrestrasse 10 4-15 Nishi Shinjuku Suite 513, 5th Floor Av. Brig. Faria Lima, 1383 1st Floor, 441 St. Kilda Rd. P.O. Box 58090 0-8080 Furstenfaldbruck Shinjuku-Ku, Chinachem Golden Plaza, 6.0 Andor-Conj. 62 Melbourne, 3004 Santa Clara, CA 95052-6090 West Germany Tokyo 160, Japan 77 Mody Road, Tsimshatsui East, 01451 Sao Paulo, SP, Brasil Victory, Australia Tel: (408) 721-5000 Tal: (0-81-41) 103-0 Tel: 2-299-7001 Kowloon, Hong Kong Tel: (65/11) 242-5066 Tel: (03) 267-5000 TWX: (910) 339-9240 Talex: 527-649 FAX: 3-299-7000 Tel: 3-7231290 Fax; (55/11) 211-1181 NSBR BR Fax: 61-3-2677458 Fax: (08141) 103554 Telex: 52996 NSSEA HX Fax: 3-3112596 National does not assume any responsibility for use of any citcuiry described, no circuit patant licenses are implied and National resarves the right at any time without notice to change said circuitry and specifications. &