MTC-20285 - AMI Semiconductor, Inc.

Data Sheet

Rev. 0.1 - March 2000

MTC-20285

ISDN / IDSL Terminal

Controller with USB

1. ISDN / IDSL Terminal Controller with USB

MTC-20285 240300 [1]

The MTC-20285 is a fully integrated

controller for ISDN/IDSL terminal

equipment applications with advanced

data communications features, offering

integrated USB interfaces. It has been

specifically designed for control and

interface functions between ISDN

access devices, such as the MTC-

20276/77 Integrated NT and other

terminal functions, such as analog

interfaces, for example by means of

the MTK-40130 Short-Haul POTS

chipset.

It incorporates an ARM7TDMI RISC

core, which can perform all of the

terminal control and data flow

management functions required in

software. It can thus form the core

of an Intelligent NT, or ‘NTplus’ unit,

as well as being the core of router /

multiplexer equipment for data

applications. In addition, the GCI

port for analog peripherals supports

the x8 multiplex mode, allowing up

to 16 analog ports to be accessed.

It can also form the core of a small

ISDN based PABX. The register map

is a functional superset of the MTC-

20280 ISDN terminal controller, so

is upward software compatible. The

on-board USB controller offers data

connectivity to PCs for high-speed

data applications, or for specialist

products for CTI, dealer-desk or call-

center applications.

Key Features Key Applications

• Integrated 32 MHz ARM7TDMI

RISC processor core

• Integrated USB controller

• 16 or 8-bit memory bus

• 4 kByte, 32-bit zero wait-state

RAM on board

• 5 full-duplex HDLC formatters

with deep FIFO’s (transparent

mode via FIFO’s)

• 3-way GCI interface and

router

• 239.4 kBaud UART with full-

duplex 16-byte FIFO’s

• 24-bit user parallel I/O ports

• ISDN and application software

available

• 144 pin PQFP package style

• ISDN NT + with high speed

USB data features

• USB based ISDN TAs

• ISDN / IDSL routers / multi-

plexers

• ISDN PABX

ISDN Line

Connection

mains

USB PORT

S - bus

POTS 1

POTS 2

MTC-30132

SH-LIC

MTK-40131

SH-POTS chipset

Power

Supply

GCI

MTC-

20232

CODSP

'NT1+' Box

MTC-20276/7

INT S

MTC-20285

Controller for

ISDN

Terminal

Adapters with

USB

PHY

RS-232 PORT V.24

PHY

DIAGNOSTIC PORT V.24

PHY MTC-30132

SH-LIC

Fig.1: ISDN/IDSL Terminal Controller - Typical Application

MTC-20285

MTC-20285 240300 [2]

External

Memory

Interface

USB

Protocol

Engine

1kB

RAM

UART+BRG

1024 x 32

fast RAM

UART +

BRG Parallel I/O

Timer1

Timer2

Watchdog

ARM7

TDMI

core

HDLC1

HDLC2

HDLC3

HDLC4

HDLC5

GCI

and

HDLC

router

GCI S

GCI A

GCI U

Clock

Generator

xtal USB

xtal

APB

bridge

USB transceiver Serial Data Port Power / Ground

USB status LEDS

External memory bus

Telecom device interfaces

Parallel I/O, diagnostic UART and

Timer interfaces

IT JTAG debug

& test port

CKOUT

Fig.2: MTC-20285 - IDSN/IDSL with USB Controller - Block Diagram

MTC-20285

Clock Generation and Control

A master clock oscillator is provided,

based on an external crystal of 15.36

Mhz. This provides an output at the

crystal frequency for the ISDN chip

(INTT or INTQ). It therefore offers

accuracy of better than 100ppm.

The CPU clock frequency is software

selectable, allowing the power

consumption to be reduced at times

when full processing speed is not

required. An on-board DPLL doubles

clock frequency to allow the CPU and

all peripherals to operate at higher

clock speeds. (The default condition

emulates the timing of the MTC-

20280 for software compatibility).

Memory Bus

The external memory bus supports

either 8-bit (for low cost) or 16-bit

(high-speed) memory systems. It allows

read / write access to off-chip memory

and I/O resources, and includes a

simple to use on-chip memory decoding

scheme to minimize external logic.

In most cases, the external memory

interfaces requires no glue-logic

whatsoever. A maximum of 12 MBytes

external memory can be accessed in

automatically decoded pages of 2

MBytes. It is designed to interface to

standard FLASH EEPROM and (pseudo)

static RAMs. The bus interface logic

includes a programmable WAIT STATE

generator, to allow access to slow

external devices. 4 kBytes of fast

(zero wait-state with 32-bit access)

on-chip static RAM is included.

A programmable Chip-Select (CS)

decoder defines the external memory

map. The default map ensures that

the CPU can start up from reset by

enabling ROM at address 0. It allows

6 external memory ranges to be

individually decoded. With regard

to EMC requirements, the slope of the

memory bus transitions is controlled

in a manner consistent with achieving

the required bus transfer speed. Each

CS memory range has programmable

wait-states.

General Description

is the ability to set fixed routes of

the B channels from a source to any

destination without the need for further

intervention by the CPU, thus relieving

the CPU of much of the real-time

processing. Up to 8 GCI time slots are

supported on each GCI port indepen-

dently, where external GCI clocks

are available. The internal GCI clock

supports 1 time slot or 8 time slots.

The clock source which determines the

number of time slots supported by the

channel is independently selectable

for each GCI port. Using an external

clock therefore allows the GCI ports to

interface to all commonly used ISDN

devices.

With regard to EMC requirements, the

slope of the GCI data output pins are

controlled in a manner consistent with

achieving the required bus transfer

speed.

HDLC Controllers

The 5 integrated HDLC controllers can

be routed to/from any B or D channel

of any port. In addition, they each

have full-duplex 64 byte FIFO’s, which

allow a large timing latency and thus

easy software timing constraints. The

HDLC controller protocol may be

disabled under software control, thus

allowing the FIFO’s to be used to

buffer real-time data. For example, for

the processing of voice-band signals on

B-channels (DTMF decoding, modem

emulation and pre-recorded voice

announcements etc). In this mode, the

data order (MSB first or LSB first) may

be user selected for compatibility with

various applications (for example,

when using the FIFO’s to buffer PCM

data from an analog GCI terminal

requires bit-reversal).

Generally, HDLC1 will be used to

manage the ISDN D-channel. D-channel

conflicts between the S bus and the

HDLC1 controller of the device are

handled by forcing a D-channel busy

condition on the S-bus by means of the

appropriate command to the S inter-

face of the INT, via the appropriate

3-way GCI Interface

The terminology ‘Downstream’ refers

to the transfer of data coming from the

U interface towards the S or analog

interfaces. ‘Upstream’ is the direction

from the S or analog interfaces

towards the U.

The device provides 3 fully independent

CGI interfaces normally allocated as

follows:

• U interface of MTC-20276 /

20277 INT, GCI-U.

• S interface of MTC-20276 /

20277 INT, GCI-S.

• Interface to analog devices

such as MTK-40130 short-haul

POTS chipset, GCI-A.

In reality, all three GCI ports are

identical - the allocation to U, S and

A (analog) is arbitrary and shown

for clarity only.

The U interface section of the INT will

always provide the GCI clocks (master)

when active. (This can be achieved by

issuing the AWAKE command on the

GCI C/I bits to the U interface, which

activates the timing generator of the

U interface without actually initiating

transmission). All other GCI buses will

generally be slaved to this one. In

applications where the use of the U

interface is not mandatory (e.g. in

a micro-PABX system which allows

internal calling without U activation),

an internal GCI clock source can be

selected. An integrated PLL system

may be enabled to allow the internally

generated GCI clocks to track and

lock to the U GCI clock, should this

become active in the course of

operation.

All bytes of the GCI frames of all three

GCI interfaces are accessible to the

processor read and write. A sophisti-

cated router allows for any of the GCI

fields (B channel, D channel, C/I bits,

Monitor channel) to be routed to the

corresponding field of any destination

channel (bytes can also be ‘disabled’,

in which case they remain at the idle

logic ‘1’ state). Particularly powerful

MTC-20285 240300 [3]

MTC-20285

M-channel commands. This is done

only after the microprocessor has

verified that the BUSY bit in the ‘S’-bus

interface circuit (SIC) control registers

is clear (i.e. D-channel not in use).

HDLC controllers 2 and 3 are gene-

rally used to handle packetized data

transport over the B channels (including

balanced applications such as LAPB).

However, in specific applications

such as internal call transfer support

or PABX, the D-channel to/ from the

S-bus requires independent manage-

ment (while still monitoring the D

channel to/from the U interface).

HDLC 2 to 5 can be used for this

purpose. Additional HDLC controllers

can be used to buffer speech

information, as required.

DTMF Decoding

Low-cost, external analog DTMF

decoder circuits can be used to

perform this function. These can be

connected to the CPU via an on-chip

8-bit parallel I/O port (programmable

bit directions). Alternatively, software

algorithms on the ARM7TDMI

processor may be used. The zero

wait-state, on-chip RAM facilitates this.

Serial I/O

A UART with selectable Baud rate

and full duplex 64-byte buffering is

provided. The Baud rate is program-

mable to standard rates up to 230.4

kbps. The external UART interface

pins are 5V compatible. A second,

simplified UART without buffering is

also provided, intended for product

configuration or diagnostics.

Parallel I/O Ports

A number of parallel I/O ports are

provided, totaling 24-bits when in 16-

bit memory bus mode (an additional 8

I/O pins are available when the 8-bit

bus mode is used). These ports are

primarily to allow an interface to

to provide either system reset (normal

use) or routed to an interrupt pin for

system debug.

CPU

The ARM7TDMI CPU is integrated

and will generally use the 16-bit data

bus mode ‘Thumb’. The external bus

interface supports 16 or 32-bit trans-

fers multiplexed to 16 or 8-bits, while

access to the on-chip SRAM can take

place as 8, 16 or 32-bit transfers (it

thus supports the full performance of

the ARM7TDMI CPU). The CPU will

generally run at the clock frequency

set by the crystal oscillator (15.36

MHz) multiplied by 2 to give 31 MHz.

However, a programmable divider is

provided to allow software control of

the processor speed, and therefore

the power consumption.

USB Controller

The on-board Revision 1.1 compliant

USB controller, supports up to 12 end-

points (6 bi-directional endpoints). In

addition to memory mapped control

registers, a dual-port RAM implemen-

tation of user definable FIFO’s for each

endpoint ensures that USB data trans-

fers do not interfere with CPU activity,

with resulting loss of CPU throughput.

Full support of USB Plug&Play features

is offered, and the execution of all

standard USB commands is automatic

(that is not require CPU intervention).

The USB controller block remains in a

reset state until the user software has

properly initialized the block. The USB

controller communicates to an off-chip

physical USB driver / receiver device

via an interface as defined by the

USB Implementers Forum, and is thus

compatible with industry standard

devices. The use of an off-chip physical

device facilitates system design for EMC

and the stringent isolation requirements

of the telecommunications industry. 7

status indication outputs are provided,

which can be used to drive indicator

LEDs showing USB status and activity

on each endpoint pair.

external DTMF decoder chips and

other application dependent hard-

ware. The ports are addressable by

the CPU as a latched output, an

unlatched input, and a data direction

direction (input at reset) of each bit.

External port pins may also request

an interrupt to the CPU (maskable)

when selected as an input.

Interrupt Control

The device contains several interrupt

sources, which can be masked by

setting a bit in a control register.

Priority is resolved in software and all

‘interrupt request’ bits from the various

sources are readable in a register. This

writing a 1 clears the corresponding

request bit, but writing a 0 has no

effect. Individual interrupt control

registers also exist within each of the

functional blocks (HDLC controller,

UART etc). The registers described

here provide a centralized and thus

fast means of handling priorities. The

various interrupt sources are perma-

nently routed to the nIRQ (normal

interrupts) and to the FIRQ (fast

response) of the AMR7TDMI CPU.

An external interrupt request pin

allows external peripheral devices

to communicate asynchronously with

the CPU. In addition, most of the

available parallel I/O pins can

function as interrupt sources when

programmed as inputs.

Timers / Watchdog

Two 16-bit timer / counters and a

(7 second maximum) Watchdog timer

are included. The timers support auto

pre-load timer interrupt generation,

thus allowing interrupts to be generated

at regular, programmable intervals.

Timer 2 also supports timer capture

functions (the source of which is

selectable), to allow the timing of

external events to be simplified. The

watchdog output can be connected,

MTC-20285 240300 [4]

MTC-20285

The next sections describe in detail the

pin functions and I/O type, in normal

and test modes. The following figures

show the pin-out names and package

orientations in top view.

MTC-20285 240300 [5]

MECHANICAL DATA, PIN FUNCTIONS AND EXTERNAL COMPONENTS

Package and Pin-out

The device is delivered in a 144 pin

PQFP package. For detailed

mechanical data, please refer to the

Alcatel Microelectronics Packaging

Handbook, specification number

16505 for production packages.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ12

DQ13

DQ14

DQ15

VDD

VSS

PD0

PD1

PD2

PD3

MC6

MC7

VSS

VDD

VSS

PG0

PG1

PG2

PG3

PH0

PH1

PH2

PH3

A10

A11

A12

A13

A14

VDD

MM1

MM0

VSS

A15

A16

A17

A18

A19

A20

A21

VDD

VSS

MC5

MC4

MC3

MC2

MC1

MC0

VSS

BASECLK

NOE

NWR

RXD

TXD

PF3

PF2

PF1

PF0

VDD

VSS

CTS

RTS

PC0

PC1

PC2

PC3

FSCA

DCLA

DOA

DIA

VDD

VSS

FSCS

DCLS

DOS

DIS

VDD

VSS

FSCU

DCLU

DOU

DIU

CKOUT

WDALARM

VDD

USB1_RXTX

USB_CFG

VSS

USB_PULL

USB2_RXTX

USB3_RXTX

USB4_RXTX

USB5_RXTX

USB6_RXTX

(T1I)

RXD2

100

101

102

103

104

105

106

107

108

TXD2

CTS2

RTS2

USB_VP

USB_SUSPND

USB_OEN

USB_VMO

USB_VPO

VSS

VDD

USB_RCV

USB_VM

USB_VBUS

VDD

USB_XTAL1

USB_XTAL2

VSS

PE0

PE1

PE2

PE3

PB0

PB1

PB2

PB3

PA0

PA1

PA2

PA3

VDD

XTAL1

XTAL2

VSS

NRST

TDO

TDI

TCK

TMS

NTRST

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

DCD/OUT2

127

RI/OUT1

128

DSR

129

DTR

130

T2O

131

T2I

132

T1O

133

T1I

134

135

136

137

138

139

140

141

142

143

MTC-20285

(144 PQFP)

Fig.3: MTC-20285 pin-out names (Top View)

MTC-20285

MTC-20285 240300 [6]

Package Orientation

144 PQFP

DQ0

Fig.4: Package Orientation

(top view)

Marking on the Package

The marking described below is used

on production devices, according to

the ‘Standard Marking Specification

for Alcatel Microelectronics’,

specification number 16020.

Topside Marking (PQFP)

Standard Marking Layout

ARM

LOGO

2840

YYWW

MTC-20285 PQ-C

C285 - MMM

ZZZZZZZZZ

Fig.5: Topside Marking

LOGO (Alcatel Microelectronics LOGO) Y ALCATEL 2840

CUST. BRAND (Customer LOGO) Y ARM Logo (1)

YYWW (Assembly year and week code) Y Standard

GGGG (Product name) Y ARM

CUST_PART_NR (Product code) Y MTC-20285PQ-C

MMMM_MMM (Product name) Y C285-xxx (2)

ZZZZZZ (Wafer Lot Number) Y Standard

SS (Assembly source) Y Standard

Special Feature N

NOTE:

(1) The ARM logo is optional (not needed because the name ‘ARM’ is on the

package)

(2) xxx corresponds to the mask / process code used for the device

Reverse Side Marking

Standard, i.e. no marking

MTC-20285

Devices can be delivered in tubes as

defined in specification 15830 and

9200, or trays for QFP as defined in

specification 9200 with optional dry

packing as defined in specification

16650. Tape on Reel as defined in

specification 16665 is available on

request.

Delivery

Important Notes on 5 V

Tolerant Pins

NOTE 1:

This means that these cells accept

5V INPUT signals, but they do not

generate 5V OUTPUT signals. That

is for outputs, only tri-state cells can

be used, for example tri-state (cells

of type ‘*5z’):

• required for driving bus structures in

open drain configuration (e.g. GCI

data out)

• requires an external pull-up resistor

to either 3.3V or 5V depending on

which high output level is requested

by the application and system.

NOTE 2:

Also when using a 5V interface, the

system should be designed such that

no 5V inputs are applied when the

3.3V power supply is not present as

this limits the lifetime of the device

(see section 5.2).

Table 1 Pin Assignment, enumerates

the pins and their type, as well as

which pins are used in which mode

of operation (either normal or test

mode). The type of pin is encoded

with a letter code, such as ‘DId’ for a

Digital Input with internal pull down.

The first letter differentiates between:

D = Digital

A = Analog

P = Power

The second letter differentiates between:

I = Input

O = Output

B = Bi-directional

The next letter differentiates between:

d = pin with internal pull-down

u = pin with internal pull-up

The next letter indicates whether

the I/O is:

s = pin with Schmitt trigger input

The next letter indicates whether

the I/O is:

5 = 5 Volt tolerant input/output

The next letter indicates whether

the I/O is:

z = pin with tri-state output

If some pins are not used in certain

modes, then they are shown either

connected to power (VDD) or ground

(GND), or must remain unconnected

(DNC).

MTC-20285 240300 [7]

Pin Description and Assignment

MTC-20285

Nmb Name Type Function

95 DIU DIs5

94 DOU DO5z

93 DCLU DBs5

92 FSCU DBs5

89 DIS DIs5

88 DOS DO5z TTL GCI

87 DCLS DBs5 6mA INTERFACE

86 FSCS DBs5

83 DIA DIs5

82 DOA DO5z

81 DCLA DBs5

80 FSCA DBs5

1 DQ0 DBs

2 DQ1 DBs

3 DQ2 DBs

4 DQ3 DBs

5 DQ4 DBs

6 DQ5 DBs

7 DQ6 DBs

8 DQ7 DBs CMOS

11 DQ8 DBs 4mA

12 DQ9 DBs

13 DQ10 DBs

14 DQ11 DBs

15 DQ12 DBs

16 DQ13 DBs

17 DQ14 DBs

18 DQ15 DBs

26 MC7 DOz RAM

29 A1 DO INTERFACE

30 A2 DO

31 A3 DO

32 A4 DO

33 A5 DO

34 A6 DO

35 A7 DO

36 A8 DO

37 A9 DO

38 A10 DO CMOS

39 A11 DO 4mA

40 A12 DO

41 A13 DO

42 A14 DO

47 A15 DO

48 A16 DO

49 A17 DO

50 A18 DO

51 A19 DO

52 A20 DO

53 A21 DO

Table 1: Pin Assignment

MTC-20285 240300 [8]

MTC-20285

Nmb Name Type Function

61 MC0 DO

60 MC1 DO

59 MC2 DO

58 MC3 DO CMOS

57 MC4 DO 4mA

56 MC5 DO

25 MC6 DO

65 NWR DO

64 NOE DO

44 MM1 DI CMOS

45 MM0 DI 4mA

66 RXD DIs5

67 TXD DO5 TTL UART1

74 CTS DIs5 6mA

75 RTS DO5

144 NTRST Did

143 TMS Diu CMOS JTAG

142 TCK Diu 4mA

141 TDI Diu

140 TDO DO

136 XTAL1 Dis

137 XTAL2 Dis CMOS Oscillator

120 USB_XTAL1 Dis 4mA Inputs

121 USB_XTAL2 Dis

96 CKOUT DO clock

139 NRST Dis5 TTL reset

97 IT Dis5 6mA Irq

98 WDALARM DO5z watchdog

63 BASECLK DI CMOS, 4 mA Clock select

108 USB_PULL DO

109 USB_SUSPND DO

110 USB_OEN DO

111 USB_VMO DO

112 USB_VPO DO

115 USB_RCV DI

116 USB_VP DI

117 USB_VM DI CMOS USB

118 USB_VBUS Dis5 4mA Interface

106 USB_CFG DO

105 USB1_RXTX DO

104 USB2_RXTX DO

103 USB3_RXTX DO

102 USB4_RXTX DO

101 USB5_RXTX DO

100 USB6_RXTX DO

131 PA0 DBs5

132 PA1 DBs5 TTL Parallel

133 PA2 DBs5 6mA I/O

134 PA3 DBs5

MTC-20285 240300 [9]

MTC-20285

Nmb Name Type Function

127 PB0 DBs5

128 PB1 DBs5 TTL

129 PB2 DBs5 6mA

130 PB3 DBs5

76 PC0 DBs5

77 PC1 DBs5 TTL

78 PC2 DBs5 6mA

79 PC3 DBs5

21 PD0 DBs5

22 PD1 DBs5 TTL Parallel

23 PD2 DBs5 6mA I/O

24 PD3 DBs5

123 PE0 DBs5

124 PE1 DBs5 TTL

125 PE2 DBs5 6mA

126 PE3 DBs5

71 PF0 DBs5

70 PF1 DBs5 TTL

69 PF2 DBs5 6mA

68 PF3 DBs5

9 VDD PI

19 VDD PI

27 VDD PI

43 VDD PI

54 VDD PI

72 VDD PI Power

84 VDD PI

90 VDD PI

99 VDD PI

114 VDD PI

119 VDD PI

135 VDD PI

10 VSS PI

20 VSS PI

28 VSS PI

46 VSS PI

55 VSS PI

62 VSS PI

73 VSS PI Ground

85 VSS PI

91 VSS PI

107 VSS PI

113 VSS PI

122 VSS PI

138 VSS PI

MTC-20285 240300 [10]

MTC-20285

MTC-20285 240300 [11]

Table 2 gives a summary of all MTC-

20285 pins and their functions in

normal (i.e. non-test) mode. Note that

the allocation of GCI ports to U,S,A

(shown with an *) is for convenience

only. All 3 GCI ports are functionally

identical and can be interchanged.

Pin Function in Normal (Non-test) Mode

Note also that depending on the

configuration in which the MTC-

20285 is used, then:

▼the MSB byte of the data bus can

be re-used as parallel I/O. This is

the case when the WordAccess

Mode is disabled for the memory

interface (see section 3.12 - case

a, and Fig.3, the multiple functions

of several device pins are listed,

along with PG[3..0] and PH[3..0]).

▼the parallel I/O port PA[3..0] can

be used to access one input and/or

one output control signal for each

Timer module. The input allows a

count based on externally applied

positive edge events. The output

shows a toggling signal, based

on the timer interrupt events, which

can be used as a clock. The connec-

tion to either the general purpose

Parallel I/O function or a Timer

function, is programmed on a bit-

basis by setting the corresponding

CHIP_CFG[i] bit (see section 3.13

and Fig.3, the functions T1I, T1O,

T2I, T2O). RXD can also be

connected to a timer, instead of

PA[3].

▼the parallel I/O port PB[3..0] can

be used to access input/output

control signals of the UART1

module for implementing a modem

communication protocol. This

happens as soon as the Pb2Uart

mode is selected (see section 3.11

and Fig.3, functions DTR, DSR,

RI/OUT1, DCD/OUT2).

▼the parallel I/O port PC[3..0] can

be used to access the RTS, CTS,

TXD, RXD signals of the UART2

(see section 3.12).

MTC-20285

Pin Fnc Description of Pin Function

DCLU GCI-U* GCI Data clock associated with the U-GCI interface

FSCU INT. GCI Frame clock associated with the U-GCI interface

DIU GCI Data from the U-GCI interface

DOU GCI Data to the U-GCI interface

DCLS GCI-S* GCI Data clock associated with the S-GCI interface

FSCS INT. GCI Frame clock associated with the S-GCI interface

DIS GCI Data from the S-GCI interface

DOS GCI Data to the S-GCI interface

DCLA GCI-A* GCI Data clock associated with the A-GCI interface

FSCA INT. GCI Frame clock associated with the A-GCI interface

DIA GCI Data from the A-GCI interface

DOA GCI Data to the A-GCI interface

DQ15..0 RAM Bi-directional data bus. DQ0:Isb, DQ15:MSB. MSB byte used as P i/O ports

PG, PH if singleByte access mode is chosen

A21..1 INT. Address bus: A1:LSB, A21:MSB

(note: LSB = MC7 depending on interface mode)

MC7..0 Memory control outputs (meaning dependent on interface mode),

e.g. chip select signals (active low), LSB/MSB byte selection, address LSB

See section 3.8 for functionality, depending on MM1..0

MM1..0 MemoryAccess mode selection (see section 3.8)

NWR Write enable signal, active low

NOE Output enable signal, active low

RXD UART1 Serial data input

TXD Serial data output

CTS Modem control signal: Clear to Send input

RTS Modem control signal: Request to Send output

NTRST JTAG JTAG reset signal, active low

TMS JTAG mode select signal

TCK JTAG clock (max 10 MHz)

TDI JTAG data input

TDO JTAG data output

XTAL1 Clocks Pins to connect an external parallel mode crystal for the on-chip oscillator.

Nominal frequency: 15.36 MHz ±50ppm

XTAL2 Note: XTAL1 may be used as an input for an external master clock source. In

which case XTAL2 must be connected to GND

USB_XTAL1 Pins to connect an external parallel mode crystal for the on-chip oscillator for

the USB core. Nominal frequency: 48 MHz ±2500ppm

USB_XTAL2 Note: USB_XTAL1 may be used as an input for an external master clock

source. In which case USB_XTAL2 must be connected to GND

CKOUT Programmable output clock (typically 15.36 MHz for U-interface clock)

NRST Hardware reset, active low. Schmitt-trigger input with threshold at 1.65 V

(CMOS LEVEL). Connect an external (RC) circuit with timing > 1 ms

WDALARM Watchdog alarm output signal

BASECLK Enable/disable PLL (30.72 MHz or 15.36 MHz)

IT External interrupt source (pos/neg-edge or level triggered)

Table 2: Pin Function and Description

MTC-20285 240300 [12]

MTC-20285

Pin Fnc Description of Pin Function

PA3..0 Parallel I/O Bitwise controlled Input or Output, or potential connection to Timer modules

T1 or T2, (PA3/RXD = T1I, PA2 = T1O, PA1 = T2I, PA0 = T2O) depending

on CHIP_CFG[6..3] and CHIP_CFG2[2]

PB3..0 Bitwise controlled Input or Output, or potential extra connection to UART1

for modem communication with:

PB3 = = DTR output

PB2 = = DSR input

PB1 = = RI input / OUT1 output

PB0 = = DCD input / OUT2 output

Depending on CHIP_CFG[0] and CHIP_CFG2[0]

PC3..0 Bitwise controlled Input or Output, or potential connection to UART2 with:

PC3 = = RTS output

PC2 = = CTS input

PC1 = = TXD output

PC0 = = RXD input

Depending on CHIP_CFG2[1]

PD3..0 Bitwise controlled Input or Output

PE3..0

PF3..0

USB_VBUS USB USB bus power (serves as USB cable attachment detection)

USB_VP D+ signal from USB, passed through Physical Transceiver buffer

USB_VM D- signal from USB, passed through Physical Transceiver buffer

USB_RCV Differential USB input, coming from the Physical Transceiver

USB_VPO NRZI formatted D+ data going to the Physical Transceiver

USB_VMO NRZI formatted D- data going to the Physical Transceiver

USB_NOE Active Low Output enable for the Physical Transceiver

USB_SUSPND USB Suspend indication going to the Physical Transceiver

USB_PULL Used to selectively connect the device termination pull-up resistor

USB_CFG Output is high when USB device is configured by the USB host

USB1..6_RXTX Output pulses high during USB traffic through endpoint 1..6

VDD Power 3.3 V power supply

VSS Ground 0 V ground

MTC-20285 240300 [13]

MTC-20285

The device can be placed in test

mode by means of the JTAG interface,

as described in section 4.2. When in

test mode the functions of the pins can

be redefined.

Pin Functions in Test Mode

Figure 6 shows the connections of the

external components.

Application Schematic and External Components

MTC-20285 240300 [14]

RgciDOU

RgciDOS

RgciDOA

VDD VDD

VSS

VDD

MTC-20285

XTAL

USB_XTAL

CX1,2 CXU1,2

Cd(a...x)

Fig.6: External Component

MTC-20285

The following external components

may be needed depending on the

application environment.

MTC-20285 240300 [15]

Table 3: GCI Related Components

Name Description Value Tolerance

RGCIDOU Pull-up for GCI data-up output towards U interface 1 kOhm 10%

(either to 5V or 3.3V, depending on application)

RGCIDOS Pull-up for GCI data-down output towards S interface 1 kOhm 10%

(either to 5V or 3.3V, depending on application)

RGCIDOA Pull-up for GCI data-down output towards A interface 1 kOhm 10%

(either to 5V or 3.3V, depending on application)

Table 4: XTAL Input Related Components

Name Description Value Tolerance

XTAL An external crystal is used to control the on-chip 15.36 MHz ±50 ppm

oscillator via the XTAL1 and XTAL2 pins (The alternative

is to control the XTAL1 pin by an external master clock

source and connect XTAL2 to GND)

CX1, CX2 Capacitors for external crystal 30 pF ±10%

Table 5: USB XTAL Input Related Components

Name Description Value Tolerance

USB_XTAL External xtal to control on-chip oscillator via the 48 MHz ±2500 ppm

USB_XTAL1 and USB_XTAL2 pins (The alternative is

to control the USB_XTAL1 pin by an external master

clock source and connect USB_XTAL2 to GND)

CXU1, CXU2 Capacitors for external crystal 30 pF ±10%

Table 6: Power Supply Decoupling Related Components

Name Description Value Tolerance

Cd[a..l] Decoupling capacitance to be placed in between 100 nF 10%

(12 X) each VDD-VSS pair of MTC-20285

Cd[m..x] Decoupling capacitance to be placed in between 10 µF 10%

(12 X) each VDD-VSS pair of MTC-20285

Table 7: Hardware Reset Related Components

Name Description Value Tolerance

Rr.Cr Power Reset circuitry > = 1ms 10%

According to Alcatel Microelectronics

convention, upstream is from the

subscriber to the exchange and

downstream is from the exchange to

the subscriber. See Fig.7, the corres-

ponding input and output pin names

of the MTC-20285 are also shown.

Convention Upstream / Downstream

MTC-20285

MTC-20285 240300 [16]

Interface

MTC-20285 downstream

upstream

Down -

stream

Up -

stream

DOU

DOA

DIA

Down -

stream

Up -

stream

DIS DOS

Exchange

To User (S)

To User (Z)

Interface

downstream

upstream

RS232

USB

DIU

Interface

Fig.7: Upstream and Downstream Convention

GENERAL ASPECTS

MTC-20285

1. The contents of one GCI frame is

different depending on whether it is

an ISDN interface (U or S) or an

analog interface (SHPOTS). ISDN

connections use 2 D-channel bits,

which are used as normal signaling /

control bits for SHPOTS. The MTC-

20285 however will always handle

the U,S,A interfaces in the same way.

They are functionally identical and can

be interchanged, the names U,S,A

being used for convenience only.

Therefore the 2 D and 4 C/I bits are

always considered separately as for

an ISDN connection. The software is

responsible for making the right inter-

pretation of the 2 formats, i.e. consider

the 2 D bits as 2 more CI bits.

GCI Frame Formats

MTC-20285 240300 [17]

GCI B1 channel B2 channel Monitor channel C/I channel

VERSION (1 byte) (1 byte) (1 byte) (1 byte)

Signaling and Monitor

control bits handshake bits

ISDN B1 (8) B2 (8) M (8) D (2) C/I (4) A/E (2)

ANALOG B1 (8) B2 (8) M (8) C/I (6) A/E (2)

Table 8: GCI Frame Formats

2. The serial communication is MSB

first, therefore the MSB of the data

in the parallel registers of the MTC-

20285 that are related to GCI, will

be sent / received as the first bit. In

order to cope with the difference in

convention between GCI and HDLC

(LSB first) formats, the HDLC modules

are capable of bit-reversal on the

parallel data, (in case the data is

non-hdlc formatted GCI data).

3. The MTC-20285 also supports

multiplexed GCI channels. For example,

an 8-channel multiplexed mode, in

which the frame contents as described

above, are sent 8 times faster over the

bit-serial I/O. According to the GCI

specification, the first transmitted

channel is called Channel0, the last

one Channel7. In this sequence, such

channels are referred to as Burst0 up

to Burst7. GCI frames of up to 3088

kbps (8 bursts x 32bit + 130 spare

bits, all at 8kHz) are accepted if

generated by an external GCI master.

An external GCI master may also

apply less than 8 bursts, e.g. a 768

kbps GCI frame of 3 bursts of 32-bits.

MTC-20285

Parameter Updating, Timing

and Initial Values

The following sections describe the

functional building blocks and their

parameters, stored in registers. The

registers can be addressed by the

ARM to modify the parameter values.

The default rule is that all parameters

can be read or written at any time,

and the new value that is written is

immediately used. However, some

exceptions are made to this default

rule. They relate to USB and GCI as

follows:

1. USB RAM Related Exception

to Default Rule

Changed USB core configuration

values (residing in the USB internal

RAM) are only taken into account

after a reset of the USB interface, by

burst in the GCI frame (see Fig.8).

The value that is read is the value

that is used in the current GCI frame

I, therefore the read value can be

different from the last written value

(i.e. if no update was done since it

was last written).

• HDxTX registers (see section 3.4.3)

are read only and show the value,

which is being transferred in the

current GCI frame (see Fig.8).

• RX registers (i.e. all registers named

‘_RX’ in section 3.2) are read only

and show the value, which was

received during the previous GCI

frame (see Fig.8).

either doing a write ‘1’ access to the

USB_START bit (USB_DCMD register,

bit[0]), or by plugging the USB cable

in the device.

2. GCI Registers Related

Exception to Default Rule

• Source, CPU and Swap registers of

the GCI router (i.e. all registers

named ‘_SRC’, ‘_CPU’ and ‘_SWP’

in section 3.2) can be written to at

any time, but will only be updated /

used based on the rate at which the

RAM open / closed space will be

switched (see section 3.2.1 GCI

Router - Architecture). The rate is

equivalent to the GCI frame rate,

but the moment of switching coin-

cides with the last byte of the last

MTC-20285 240300 [18]

. . . . . .

Gci FSC

Gci Bursts (2 Mbps)

Gci B1,B2,M,CI bytes

Update of read value

(swap RAM access space: open/closed) Update of read value

(swap RAM access space: open/closed)

. . .

Gci Frame I+1

Gci Frame I

Gci Frame I-1

RX registers (read only), except RXlast

HDxTX registers (read only)

Read - RX reg - received in GCI Frame i-1

Read - HDxTX reg - transmitted in GCI Frame i

SRC, CPU and SWP registers

(read mode)

(writing a new value can be done at any moment)

Read - SRC,CPU,SWP reg -

= value written in RAM Frame i-1, used in GCI Frame i

RAM access

Frame I+1

RAM access

Frame I

RAM access

Frame I-1

Well-defined read value Well-defined read

value

RXlast reg (read only),

= last byte of last burst of U,S,A

Read - RXlast reg - received in GCI Frame i-1

. . . . . . Gci bits (256 kbps)

. . .

ca (GCI period)/32

Fig.8: Timing of Register Updating

MTC-20285

MTC-20285 240300 [19]

• For the RX register corresponding to

the last byte of the last burst in the

GCI frame, an exception must be

made, as shown in Fig.8. The value

should not be read during the time

window, starting the moment the

RAM space is swapped until the

start of a new GCI frame.

Notice that after power reset, no write

operations will be issued before the

first GCI frame FSC is generated. This

is to allow a correct initialization of

the MTC-20285.

Notice also that after power reset, the

default GCI clocks selected for U,S,A

is the ‘power down’ mode (see section

3.3). This means the FSC/DCL remains

inactive low (‘0’), but also the output

GCI data stream remains inactive high

(‘1’: idle). So none of the uninitialized

output stream, unless under software

control. The software has to do the

appropriate initialization before

selecting it as source register.

When the GCI clocks are switched

from one to another source (e.g.

between Umaster and crystal based

clocks on A interface), the data will

be unpredictable during the switching

because a re-synchronization must

take place. This will take at most 2

GCI frames.

In order to limit the side effects, the

user may specify to use temporarily

the IDLE source or CPU (with for

example, ‘zero’ a-law code) source

during the switching period.

3. Handling D Channel Collisions

The GCI router and MTC-20285

architecture / parameters control

whether the D-channel from S to U

upstream is busy or not. It uses the

output of an HDLC block as D-channel

U-up when S is inactive.

4. Reset Behaviour

The MTC-20285 has two reset pins,

NRST (Functional reset) and NTRST

(JTAG reset). Both active low reset

inputs are independent and do not

interact:

• NRST: Resets the integrated ARM

processor (i.e. disables the ARM

clock) and the functional MTC-

20285 blocks, without affecting

the JTAG related memories. For

example the test configuration

interface is not reset if set in a

specific test mode, this mode will

remain selected while resetting the

ARM and functional blocks.

• NTRST: Resets the JTAG interface

logic, including the test configuration

in non-test functional mode. Note

that the NTRST input cell has an

integrated pull-down, such that the

JTAG logic is reset by default

without any required connection

at PCB level.

The watchdog alarm output pin

WDALARM will typically be externally

connected to the NRST input, and

possibly used to reset inputs of other

chips on the board.

MTC-20285

Architecture

GCI Router

This architecture accepts receive and

send up to 8 bursts per GCI interface

(max 8x3x4 bytes).

In case any GCI interface works faster

than 2048 kbps (e.g. 3088 kbps, the

highest GCI rate accepted by MTC-

20285), the extra spare bits received

by the MTC-20285 will not be stored

in the RAM. The corresponding output

stream generated by the MTC-20285

will contain idle spare bits (i.e. value

= ‘1’ according to GCI).

The core of GCI Router is made of a

dual port ram. One port is dedicated

to the GCI interfaces, the other one to

the processor access. The ram is split

into 2 spaces:

• Open: space where the data can

be modified, used to store the

incoming GCI frames

• Closed: space where the data is

held for 1 GCI frame, used to store

the GCI frames to be sent

MTC-20285 240300 [20]

diU

diS

diA

Open

Closed

doU

doS

doA

Shift register

Update at byte frequency

Shift register updated at byte

frequency

Direct access from diU/diS/diA when compatible

ARM

RAM access control

Address coder/decoder

RAM

Fig.9: GCI Router Architecture

Multiplexer

The CPU can program an automatic

routing of any channel from any burst

through the GCI buses, from the CPU

addressable registers or from one of

the 5 HDLC formatters. The source of

each channel output is controlled via

the value stored in the source control

registers, as shown in Table 9. The

ARM can write the SRC registers. If

a new value is written to the register,

it will only be used from the next GCI

frame onwards (see section 3).

The ARM can read the SRC registers.

The burst to which the data corresponds

must be set by first writing the required

burst number into the GCI_BUR_SRC

sources can be stored in a SRC

(see section 3.2.3). Swapping can

also be programmed between the

channels B1 and B2 via the SWP

registers.

MTC-20285

Table 9: SCR Register Table

Name Address (byte) Function

GCI_SRC_BUR 7F (1FC) Burst selection for reading Source control registers:

[2:0] = target burst (0 to 7)

U_B1_SRC 80 (200) Source control of B1 U-up channels routing:

[2:0] = target burst (0 to 7)

[4:3] = source line

0 = U-down channel

1 = S-up channel

2 = A-up channel

3 = Extension

[7:5] = if source line = U or S or A: source burst (0 to 7)

if source line = Extension, then one of following possible sources is:

0 = IDLE

1 = CPU register

2 = HDLC1

3 = HDLC2

4 = HDLC3

5 = HDLC4

6 = HDLC5

U_B2_SRC 81 (204) Source control of B2 U-up channels routing description:

the same as for B1 U-up

U_D_SRC 82 (208) Source control of D U-up channels routing description:

idem

U_CI_SRC (*) 83 (20C) Source control of C/I U-up channels routing description:

the same as for B1 U-up, except for HDLC source (*)

U_M_SRC (*) 84 (210) Source control of M U-up channels routing description:

the same as for B1 U-up, except for HDLC source (*)

U_AE_SRC(*) 85 (214) Source control of A/E U-up channels routing description:

the same as for B1 U-up, except for HDLC source (*)

S_B1_SRC 86 (218) Source control of B1 S-down channels routing description:

idem

S_B2_SRC 87 (21C) Source control of B2 S-down channels routing description:

the same as for B1 U-up

S_D_SRC 88 (220) Source control of D S-down channels routing description:

the same as for B1 U-up

S_CI_SRC (*) 89 (224) Source control of C/I S-down channels routing description:

the same as for B1 U-up, except for HDLC source (*)

S_M_SRC (*) 8A (228) Source control of M S-down channels routing description:

the same as for B1 U-up, except for HDLC source (*)

S_AE_SRC(*) 8B (22C) Source control of A/E S-down channels routing description:

idem, except for HDLC source (*)

A_B1_SRC 8C (230) Source control of B1 A-down channels routing description:

the same as for B1 U-up

A_B2_SRC 8D (234) Source control of B2 A-down channels routing description:

the same as for B1 U-up

A_D_SRC 8E (238) Source control of D A-down channels routing description:

the same as for B1 U-up

A_CI_SRC (*) 8F (23C) Source control of C/I A-down channels routing description:

the same as for B1 U-up, except for HDLC source (*)

MTC-20285 240300 [21]

MTC-20285

Name Address (byte) Function

A_M_SRC (*) B0 (2C0) Source control of M A-down channels routingdescription:

the same as for B1 U-up, except for HDLC source (*)

A_AE_SRC(*) B1 (2C4) Source control of A/E A-down channels routing description:

the same as for B1 U-up, except for HDLC source (*)

U_B1_SWP B2 (2C8) bit[ i ] = 0: no swap B1-burst i U-up channel will be routed with the

B1 channel of the selected source (U,S,A only)

bit[ i ] = 1: swap B1-burst i U-up channel will be routed with the

B2 channel of the selected source (U,S,A only)

U_B2_SWP B3 (2CC) bit[ i ] = 0: no swap B2-burst i U-up channel will be routed with the

B2 channel of the selected source (U,S,A only)

bit[ i ] = 1: swap B2-burst i U-up channel will be routed with the

B1 channel of the selected source (U,S,A only)

S_B1_SWP B4 (2D0) bit[ i ] = 0: no swap B1-burst i S-down channel will be routed with the

B1 channel of the selected source (U,S,A only)

bit[ i ] = 1: swap B1-burst i S-down channel will be routed with the

B2 channel of the selected source (U,S,A only)

S_B2_SWP B5 (2D4) bit[ i ] = 0: no swap B2-burst i S-down channel will be routed with the

B2 channel of the selected source (U,S,A only)

bit[ i ] = 1: swap B2-burst i S-down channel will be routed with the

B1 channel of the selected source (U,S,A only)

A_B1_SWP B6 (2D8) bit[ i ] = 0: no swap B1-burst i A-down channel will be routed with the

B1 channel of the selected source (U,S,A only)

bit[ i ] = 1: swap B1-burst i A-down channel will be routed with the

B2 channel of the selected source (U,S,A only)

A_B2_SWP B7 (2DC) bit[ i ] = 0: no swap B2-burst i A-down channel will be routed with the

B2 channel of the selected source (U,S,A only)

bit[ i ] = 1: swap B2-burst i A-down channel will be routed with the

B1 channel of the selected source (U,S,A only)

NOTES:

• All the above registers are undefined after reset, which means that the multiplexer is undefined after reset. The software

must initialize the register values before using them. Note however that the default clock configuration of all GCI channels

is the IDLE state (see section 3.3), such that the output stream will be continuously ‘1’ (idle).

• All SRC and SWP registers can be read and written to but ‘what you read is not what you write’:

- write operation: new value that will be effective from the next GCI frame

- read operation: value used for the current GCI frame

• The HDLC source selections are not applicable for the CI, M and AE channels (see registers marked (*)). The bits are

unspecified if the HDLC is selected as source, therefore it is not recommended.

• For an analog GCI frame, the D and CI channels form one entity but the MTC-20285 handles them separately. Therefore,

the software must use the same selection for both D and CI channels.

• Whenever data is routed from one GCI interface to another one, a single GCI frame delay is always inserted. Whenever

a register access is involved, a double GCI frame delay is involved (e.g. from the ARM or the HDLC module). No direct

connection without delay is possible.

• If the target burst number is set higher than the number of bursts to be transmitted on a GCI output stream, this will be

neglected. However for a source burst number higher than the number of bursts in the GCI input stream, the byte will

be unspecified.

• In case of a non-multiplexed GCI stream, target and source burst numbers must be set to ‘0’.

MTC-20285

Examples:

If you need to connect the destination U / burst3 / B1 with the source S / burst7 / B1, then make:

• U_B1_SRC[7..0] = ‘111 01 011’ (source burst = 7; source = S; target burst = 3), and

• U_B1_SWP[7..0] = ‘xxxx 0xxx’ (bit3 set to ‘0’ in order not to swap the source of U/B1: B1)

If you need to connect the destination U / burst3 / B1 with the source S / burst7 / B2, then make:

• U_B1_SRC[7..0] = ‘111 01 011’ (source burst = 7; source = S; target burst = 3), and

• U_B1_SWP[7..0] = ‘xxxx 1xxx’ (bit3 set to ‘1’ in order to swap the source of U/B1: B2)

Note that the SWP register values are only used, if the corresponding source is either U, S or A.

Reading the SRC value shows the connection that is selected for the current GCI Frame (see section 3). Because 8 values

can be specified at the same time for each SRC register (e.g. U_B1_SRC, one value per target burst), reading U_B1_SRC

necessitates first writing to register GCI_SRC_BUR to choose one target burst:

Write U_B1_SRC[7..0] = ‘110 01 011’ (source burst = 6; source = S; target burst = 3)

Write U_B1_SRC[7..0] = ‘111 00 010’ (source burst = 7; source = U; target burst = 2)

Write U_B1_SRC[7..0] = ‘101 10 001’ (source burst = 5; source = A; target burst = 1)

Write GCI_SRC_BUR[2..0] = ‘010’ (specify target burst = 2 for reading)

Read U_B1_SRC[7..0] returns ‘111 00 010’ (source burst = 7; source = U; target burst = 2)

Write GCI_SRC_BUR[2..0] = ‘011’ (specify target burst = 3 for reading)

Read U_B1_SRC[7..0] returns ‘110 01 011’ (source burst = 6; source = S; target burst = 3)

MTC-20285

CPU Registers (ARM > GCI)

Through the CPU registers, the ARM

can directly send data to any GCI

channel.

Name Address (byte) Function

Ui_B1_CPU 60 (180) CPU source value register for U-up / B1, burst i,

where i is defined by the register GCI_CPU_RX

Ui_B2_CPU 61 (184) CPU source value register for U-up / B2, burst i

where i is defined by the register GCI_CPU_RX

Ui_M_CPU 62 (188) CPU source value register for U-up / M, burst i

where i is defined by the register GCI_CPU_RX

Ui_E_CPU 63 (18C) CPU source value register for

[7:6] = U-up / D, burst i

[5:2] = U-up / CI, burst i

[1:0] = U-up / AE, burst I

where i is defined by the register GCI_CPU_RX

Si_B1_CPU 64 (190) CPU source value register for S-down / B1, burst i

where i is defined by the register GCI_CPU_RX

Si_B2_CPU 65 (194) CPU source value register for S-down / B2, burst i

where i is defined by the register GCI_CPU_RX

Si_M_CPU 66 (198) CPU source value register for S-down / M, burst i

where i is defined by the register GCI_CPU_RX

Si_E_CPU 67 (19C) CPU source value register for

[7:6] = S-down / D, burst i

[5:2] = S-down / CI, burst i

[1:0] = S-down / AE, burst I

where i is defined by the register GCI_CPU_RX

Ai_B1_CPU 68 (1A0) CPU source value register for A-down / B1, burst i

where i is defined by the register GCI_CPU_RX

Ai_B2_CPU 69 (1A4) CPU source value register for A-down / B2, burst i

where i is defined by the register GCI_CPU_RX

Ai_M_CPU 6A (1A8) CPU source value register for A-down / M, burst i

where i is defined by the register GCI_CPU_RX

Ai_E_CPU 6B (1AC) CPU source value register for

[7:6] = A-down / D, burst i

[5:2] = A-down / CI, burst i

[1:0] = A-down / AE, burst i

where i is defined by the register GCI_CPU_RX

GCI_CPU_RX 78 (1E0) Specifies the target burst for line U, S or A used when accessing the CPU

and RX registers:

[1:0] = target line; 0 = U

1 = S

2 = A

[4:2] = CPU target burst (0 to 7)

[7:5] = RX target burst (0 to 7)

where i is defined by the register GCI_CPU_RX

MTC-20285 240300 [24]

Table 10: CPU Register Table

MTC-20285

NOTES:

• All CPU registers are undefined after reset (the same as for GCI multiplexing registers)

• The register GCI_CPU_RX can define and store 3 commands in parallel, one for each interface (U,S,A). The latest stored

command for each interface will be used to select the corresponding CPU and RX register of that source. (For RX

registers detail, see section 3.2.5)

Example:

- initialisation: select for S and U:

GCI_CPU_RX = ‘ 000 010 01 ‘; S: cpu-burst = 2, rx-burst = 0

GCI_CPU_RX = ‘ 011 110 00 ‘; U: cpu-burst = 6, rx-burst = 3

- use CPU and RX registers:

Si_B2_CPU = Ui_B1_RX; means CPU/S_B2/burst2 gets data from RX/U_B1/burst3

- re-select for S:

GCI_CPU_RX = ‘ 000 101 01 ‘; S: cpu-burst = 5, rx-burst = 0

- use CPU and RX registers:

Si_B2_CPU = Ui_B1_RX; means CPU/S_B2/burst5 gets data from RX/U_B1/burst3

• All CPU registers can be read and written to but ‘what you read is not what you write’:

- write operation: new value that will be effective from the next GCI frame

- read operation: value used for the current GCI frame

• When a constant value needs to be used from a CPU register, the value should be written during two consecutive GCI

frames into the CPU register. This is due to the architecture with 2 parallel RAM spaces.

MTC-20285 240300 [25]

MTC-20285

MTC-20285 240300 [26]

RX Registers (GCI > ARM)

The ARM can read at any time the GCI

content on each interface (U, S, A) with

a delay of one frame (see section 3).

Name Address (byte) Function

Ui_B1_RX 6C (1B0) First byte of the U downstream GCI frame, burst i (1)

Ui_B2_RX 6D (1B4) Second byte of the U downstream GCI frame, burst i (1)

Ui_M_RX 6E (1B8) Third byte of the U downstream GCI frame, burst i (1)

Ui_E_RX 6F (1BC) Fourth byte of the U downstream GCI frame, burst i (1)

Si_B1_RX 70 (1C0) First byte of the S upstream GCI frame, burst i (1)

Si_B2_RX 71 (1C4) Second byte of the S upstream GCI frame, burst i (1)

Si_M_RX 72 (1C8) Third byte of the S upstream GCI frame, burst i (1)

Si_E_RX 73 (1CC) Fourth byte of the S upstream GCI frame, burst i (1)

Ai_B1_RX 74 (1D0) First byte of the A upstream GCI frame, burst i (1)

Ai_B2_RX 75 (1D4) Second byte of the A upstream GCI frame, burst i (1)

Ai_M_RX 76 (1D8) Third byte of the A upstream GCI frame, burst i (1)

Ai_E_RX 77 (1DC) Fourth byte of the A upstream GCI frame, burst i (1)

GCI_CPU_RX 78 (1E0) Specify the burst targeted by the ARM when writing to the CPU and RX

registers:

[1:0] = target line; 0 = U

1 = S

2 = A

[4:2] = CPU target burst (0 to 7)

[7:5] = RX target burst (0 to 7)

Table 11: RX Register Table

(1) Where i is defined by the register GCI_CPU_RX

NOTES:

• All RX registers can only be read (see section 3).

- read operation: value received during the previous GCI frame is read

MTC-20285

The value of each bit of the 6 D/CI

bits of one GCI burst, is compared to

its value during the previously received

GCI frame (6 exors per burst). If

at least one of the 6-bits of burst k

changed, the corresponding burst

bit k = 0..7 is set in the CI-activity-

detection register, unless it is masked

(by setting the corresponding ‘mask

bit’ to 1). There are 3 D/CI-activity

detection registers, one for each inter-

face (U,S,A), each 8-bits wide (for the

8 possible bursts per interface). There

is one mask register per D/CI-activity

detection register. After reset, the

mask registers are set to 0xFF, all

activity detection being masked.

If less than 8 bursts are present on a

certain GCI interface, the activity bits

corresponding to the non-existing

bursts will remain inactive ‘0’, so

no masking is required to prevent

an incorrect activity detection.

From the moment that one of the 3x8

CI-activity bits is active an interrupt is

generated. The interrupts stay active

until they are explicitly cleared by

writing to the GCI_ITx registers. The

interrupt source itCI goes as well to

the interrupt handler (i.e. the raw, un-

masked interrupt bit, see section 3.9).

For the capture signal of Timer1 (see

section 3.13.1).

D/CI Activity Detection

D bits. A control byte is provided for

each GCI interface. Every bit in these

control bytes corresponds to one burst.

When a bit is set to ‘1’, it will block

the D bits activity detection for a

particular burst / GCI interface.

Note that no debouncing is done on

the activity detection. If necessary, this

must be done in software.

An additional mask is foreseen to

suppress the activity detection for the

MTC-20285 240300 [27]

Mask

U1_DCI

Activity

U-D/CI, frame i

U-D/CI, frame i -1

itCl

Fig.10: D/CI Activity Detection

GCI_MSKU[i] and

GCI_GCI_MSKUD([i]

1 - D activity detection on U, burst i: masked

CI activity detection on U, burst i: masked

0 1 D activity detection on U, burst i: masked

CI activity detection on U, burst i: enabled

0 0 D activity detection on U, burst i: enabled

CI activity detection on U, burst i: enabled

MTC-20285

MTC-20285 240300 [28]

Name Address (byte) Function

GCI_ITU 79 (1E4) READ access:

bit[i] = 1: D-CI activity detected on U-downstream, burst i

WRITE access:

bit[i] = 1: reset the interrupt detection on U-downstream, burst i

GCI_ITS 7A (1E8) READ access:

bit[i] = 1: D-CI activity detected on S-upstream, burst i

WRITE access:

bit[i] = 1: reset the interrupt detection on S-upstream, burst i

GCI_ITA 7B (1EC) READ access:

bit[i] = 1: D-CI activity detected on A-upstream, burst i

WRITE access:

bit[i] = 1: reset the interrupt detection on A-upstream, burst i

GCI_MSKU 7C (1F0) bit[i] = 1: mask D-CI activity detection on U, burst i

GCI_MSKS 7D (1F4) bit[i] = 1: mask D-CI activity detection on S, burst i

GCI_MSKA 7E (1F8) bit[i] = 1: mask D-CI activity detection on A, burst i

GCI_MSKUD B8 (2E0) bit[i] = 1: mask D bits activity detection on U, burst i

GCI_MSKSD B9 (2E4) bit[i] = 1: mask D bits activity detection on S, burst i

GCI_MSKAD BA (2E8) bit[i] = 1: mask D bits activity detection on A, burst i

Table 12: GCI Register Table

Asynchronous Pull-up/Pull-down

APPLICATION:

When the U line is defined as master and the U device is in power down (i.e no GCI clock present), the ARM must be able

to pull the GCI line down toward the U device to wake it up.

Name Address (byte) Function

GCI_PULL BB (2EC) bit[1:0]: for line U

bit[3:2]: for line S

bit[5:4]: for line A

0: inactive

1: pull GCI data line up

2: pull GCI data line down

3: /

Table 13: GCI_PULL Register Table

In order to force the GCI data output

line to zero when no clock is present

at the corresponding GCI interface,

an asynchronous pull-up/pull-down is

provided.

MTC-20285

Each GCI interface can work at a

different speed (= clock domain

fsc/dcl), however each U,S,A is

synchronized (via its FSC signal) on

one and only one GCI Master FSC

(fscMstr). The selection of fscMstr as

well as the clock domain to be used

for U,S,A is under software control.

As each interface can be selected

as GCI master, and at most one inter-

face can work as master and the

others as slave, all FSC/DCL pins are

bi-directional. After reset, all 3 pairs

of pins are in input mode such that no

conflict occurs on any of the interfaces

with a possible external master device.

The Master FSC (fscMstr) can be

selected from 4 different sources,

and the corresponding DCL clock

will also be used as an input to the

MTC-20285:

GCI Clocks Generation

b) master: (dclMstr/fscMstr): the

dcl/fsc clocks of that interface will

follow the dclMstr/fscMstr of the

interface which is selected as master

interface.

c) 512k: (dcl512/fsc512). The

dcl/fsc clocks are derived from the

crystal, but synchronized(1) with

the master frame clock (fscMstr).

Dcl = 512 kHz, 1 burst per frame.

d) 4096k: (dcl4096 / fsc4096).

The dcl/fsc clocks are derived from

the crystal, but synchronized(1) with

the master frame clock (fscMstr).

Dcl = 4096 kHz, 8 bursts per frame.

NOTE:

(1) In case the crystal is selected as

master, fsc is synchronized with a

free-running, internally generated,

crystal based 8kHz FSC signal.

Two (positive-edge triggered)

interrupts are generated on:

• the Master Frame Clock, fscMstr

• the internal frame clock, always

running. See section 3.9 on

Interrupts.

When the Master domain is chosen

from one of the three external GCI

interfaces, the source clock selection

must be made appropriately to avoid

clock conflicts as shown below:

• if GCI-U must be master, you have

to write CLK_GCI = 01 xx xx 01

• if GCI-S must be master, you have

to write CLK_GCI = 10 xx 01 xx

• if GCI-A must be master, you have

to write CLK_GCI = 11 01 xx xx

With a crystal based master (the

MTC-20285 being GCI master), the

MTC-20285 can only generate either

non-multiplexed or 8-burst multiplexed

GCI frame formats. However, when

an external master is specified, the

MTC-20285 will follow the format of

the external master. For example, a

5-burst mode or an 8-burst mode with

extra spare bits. Therefore the MTC-

20285 is fully GCI compatible when

used in slave mode bit-rates of up to

1. Crystal clocks = dcl512/fsc512

2. U GCI interface = DCLU/FSCU

3. S GCI interface = DCLS/FSCS

4. A GCI interface = DCLA/FSCA

The default source after reset is the

crystal, because this source will

always be present.

For each clock domain fsc/dcl of

U,S,A, you can choose between 4

possible sources:

a) non-active: this is the default after

reset, and means dcl/fsc of that

interface remains inactive low and

the GCI data output stream remains

inactive high (idle code). Selection

of the non-active source for the

interface, will overrule any other

source selected for the data stream

(e.g U_B1_SRC = HDLC1 will be

overruled).

MTC-20285 240300 [29]

pdown

XTAL

15.36MHz

dcl512

fcs512

dcl4096

fcs4096

dclMstr

fcsMstr

fcsMstr dcl512 / fcs512

DCLU

FCSU

DIU

DOU

DCLS

FCSS

DIS

DOS

DCLA

FCSA

DIA

DOA

Clock

Gen

PLL

Fig.11: GCI Clock Generation

MTC-20285

3088 kbps may be applied as master;

this corresponds to a maximum of 8

bursts of 32-bits, followed by 130

spare bits (see GCI specification).

Notice that in case spare bits occur

in the input data stream, these spare

bits will not be stored for possible

processing, nor be routed through to

another GCI output data stream (e.g.

from DIU to DOS). Incoming spare

bits are neglected, and outgoing

spare bits are always set idle ‘1’.

In case the Master is chosen from one

of the 3 GCI interfaces, the dcl/fsc

clocks derived from the crystal will

be synchronized on the Master frame.

A Digital PLL is used to track the frame

with a maximum correction of 2 ms

per frame. Therefore:

• the amount of dcl transitions per

frame is not affected.

• the bit 0 of the CLK_3 register

reports if the PLL is locked. If the

master clock stops, then bit 0 of

CLK_3 goes immediately to 0.

• the generated dfr signals (dfr512

and dfr4096) are slaved to the dfr

signal chosen as master.

• the dpll can make a correction

of maximum +/- 1.7% per frame;

so a maximum of 30 frames

(= 50%/1.7%) may be needed

when changing dfr master.

• the frequencies of the data clocks

(dlc512 and dcl4096) are adapted

in the same way

• the dpll adds or subtracts a

maximum of 32 pulses of the 15.36

MHz clock per frame (32/1920 =

1.7%) (15.36 MHz = ± 65 ns).

• the dpll works with an hysteresis of

65 ns; a phase shift of +/-65 ns or

more will cause a correction.

• if no frame clock is present on the

selected dfr master, no tracking will

be applied and the generated dfr

clocks will be free running.

APPLICATION EXAMPLE:

for the S channel, use the internal

clocks (dfr512/dcl512) and, as dfr

master, the frame clock coming from

the U channel. As soon as no activity

is seen on the U frame clock (e.g.

U interface deactivated), the S frame

is a free-running clock based on the

crystal frequency. As soon as the

U activates, the dpll begins to track,

to recover any frame phase delay

between the U and S GCI channels.

Hardware Implementation

of the Multiplexing

MTC-20285 240300 [30]

dcl 512 (Xtal)

dcl FromU

dcl FromS

dcl FromA

CLK_GCI [7:6]

powerDown

dcl 512

dcl 4096

CLK_GCI [1:0]

dfr U

dfr 512 (Xtal)

dfr FromU

dfr FromS

dfr FromA dfr 512

dfr 4096

dcl U

Fig.12: Multiplexing for the U-GCI Clocks

• the control of the multiplexers comes

directly (asynchronously) from the

CPU register CLK_GCI. It is the

application software that has to

take care when it modifies the multi-

plexing, but typically, the control

will be set once (forever) because it

is mainly dependent on the devices

connected to the GCI lines.

• the dcl and dfr signals have the

same source

MTC-20285

Name Address (byte) Function

CLK_GCI 90 (240) bit[5:0]: GCI DCL clock selection per interface U,S,A:

bit[1:0] = for the U GCI router

bit[3:2 ] = for the S GCI router

bit[5:4] = for the A GCI router

0 = non-active (default at reset)

1 = master: dclMstr / fscMstr

2 = 512k: dcl512 / fsc512

3 = 4096k: dcl4096 / fsc4096

bit[7:6]: GCI Master FSC selection (fscMstr)

0 = Xtal (default at reset)

1 = U

2 = S

3 = A

CLK_3 93 (24C) bit[0]: DPLL status (read only)

0 = internal GCI clocks not synchronized with the external

reference or the external reference is not active, DPLL is tracking

1 = internal GCI clocks synchronized

CHIP_GCI_L 02 (008) Bits per GCI Frame on GCI master interface (Read only):

CHIP_GCI_M 03 (00C) result of auto-detection of the mode of the GCI master interface this 16-bit

word stored in upper (_M) and lower byte (_L) value corresponds to the

number of bits detected in one GCI frame:

e.g. 8-burst 2048 kbps: CHIP_GCI_[M/L] = 256 = ox 01 00 = [1/0]

3-burst mode: CHIP_GCI_[M/L] = 96 = ox 00 60 = [0/96]

8-burst 3088 kbps: CHIP_GCI_[M/L] = 386 = ox 01 82 = [0/130]

Table 14: CLK_GCI Register Table

MTC-20285 240300 [31]

NOTE:

The 4096 kHz clock generated from the crystal, does not produce a perfect 50% duty cycle.

MTC-20285

Description

5 identical HDLC formatters are

provided. They can be routed to any

B1, B2 or D channels for any burst of

any U, S or A interface.

Each HDLC formatter works as a single

channel HDLC controller with send and

receive FIFO pools. It is designed to

work in OSI Layer2 (Data Link layer)

applications, such as a LAP-D or LAP-B

processor.

FEATURES INCLUDE:

• HDLC processor

+ flag generation and detection

+ abort generation and checking

+ CRC generation and checking

+ zero insertion and deletion

• Receive address comparison

+ 1 broadcast TEI register

+ 2 programmable address

matching registers

+ 2 programmable ‘wildcard’

registers

• Transmit address of packets can be

set from register or data stream

• 64 byte FIFO’s in both directions

• Transparent mode at which the

FIFO’s (Rx and Tx) can be used to

buffer data transfers without HDLC

formatting.

• Data bit-reversal possible (LSB <->

MSB) in order to cope with the

different formatting between HDLC

formatted (LSB first) and non-HDLC,

GCI formatted data (MSB first).

• Interrupt generation

HDLC Formatter

HDLC Protocol

HDLC (High Level Data Link Control)

is a bit-oriented, synchronous serial

protocol used in data communication

systems. Both LAPD (Link Access

Protocol on D-channel) and LAPB

(Link Access Protocol Balanced) are

descended from HDLC, but differ

slightly in frame format.

The HDLC block transmits and

receives data in frames. The start

and end of frames are marked by a

unique bit pattern called a flag. The

data between the start and end flags

consists of an address field, control

field, information field and a Frame

Check Sequence (FCS) field. Fig.13

shows the HDLC frame format

MTC-20285 240300 [32]

Flag Flag

01111110 Address Control Information FCS 01111110

in LAPD

Nmax=260 (optional)

1 - 2 Octets 1 - 2 Octets 0 -N Octets 2/4 Octets

Passed between Receive/Transmit FIFO’s

Fig.13: HDLC Frame Format

MTC-20285

1. Framing

A flag is the unique bit-pattern

‘01111110’ (7E hex), and marks

both the start and the end of the

frame. Flags are generated internally,

and the HDLC block automatically

appends start and end flags on frame

transmission. Flags are searched

for on a bit-by-bit basis, and can be

recognised at any point in the receive

bit stream. Flags are not transferred

to or from the HDLC block.

2. Addressing

The frame address is contained in

the first field following the start flag.

This can be either 1 or 2 octets long,

and is used to distinguish the various

network devices from one another.

Together with optional address

matching circuitry, the HDLC block

can search the complete address field

of incoming frames, selecting only

those frames addressed to it. The

address field is transferred to and

from the HDLC block.

3. Control

A control field follows the address field.

This can be either 1 or 2 octets long,

and is used to transfer commands and

responses between Layer 2 entities and

the network. The HDLC block does not

operate on this field, transferring it

transparently.

4. Information

The information field contains the

data to be transmitted, and may be

null. This field may not be an integer

number of octets. If the last few bits of

the information field do not completely

fill the last octet, then that octet is

padded with zeros before being

transferred to the Receive FIFO as a

complete byte. The device will only

transmit frames with an integer number

of octets (before zero insertion).

5. Error Checking

The Frame Check Sequence (FCS)

field is contained in the last two

octets before the end flag in a frame.

The field is computed using a Cyclic

Redundancy Check (CRC) polynomial.

This is used to perform error detection

binary 1’s in the LAPD protocol. The

number of 1’s can be less than a full

octet. The LAPB protocol, on the other

hand, specifies flag characters to be

inserted between frames.

8. Frame Abort

Transmission of data frames can

be prematurely cancelled by use of

an abort character. The transmitter

aborts a frame by sending the abort

character ‘11111110’ (FE hex). The

receiver interprets this character as

an abort, and begins the search for

a new frame.

How to generate a Tx Frame Abort.

This can be done in one of the

following 3 ways:

• disable the TX before the ‘end-of-

frame’ (indicated by writing the

‘last-byte-indication’ to the TX-FIFO)

• clear the TX-FIFO before the ‘end-of-

frame’

• let the TX-FIFO run empty before the

‘end-of-frame’

on the address, control and information

fields. The standard CRC-CCITT poly-

nomial is used in both the receive and

transmit directions:

X16 + X12 + X5 + 1

The HDLC block also provides support

for a non-standard 32-bit CRC (CRC-

32), which may be used instead of the

standard CCITT-CRC. The polynomial

for this is:

X32 + X26 + X23 + X22 + X16 +

X12 + X11 + X10 + X8+ X7 + X5 +

X4 + X2 + X + 1

CRC generation and checking is

performed automatically by the HDLC

block. On transmit, the CRC generator

is initialized with FFFF hex. The CRC

is computed serially on the address,

control and information fields, and is

then complemented before being

transmitted MSB first.

In the receive direction the CRC checker

is initialized with FFFF hex on receipt of

a valid start flag. A CRC is performed

on all bits between the start and end

flags, including the transmitted CRC

field, and the end result is compared

to 1D0F hex (or C704DD7B hex for

CRC-32), hex numbers written MSB

first. The frame is transferred to the

receive FIFO, regardless of whether

the CRC checker detected an error or

not. The CRC field can also be trans-

ferred to the receive FIFO if required.

6. Zero Insertion/Deletion

Zero insertion and deletion is

performed by the HDLC block to

prevent the start and end flags from

being imitated by the data. The

transmit section inserts a zero after

any succession of five 1’s within a

frame (between start and end flags).

The receive section deletes all 0’s

inserted by the transmitter.

7. Inter-frame Time Fill

An inter-frame time fill condition

occurs when the HDLC block has no

frames to transmit. The device can be

configured to transmit either an idle

stream or flag characters during this

period. The idle stream consists of

MTC-20285 240300 [33]

MTC-20285

Control Registers

This section details the programmable

registers accessible to the CPU. These

registers either control the operation

of the HDLC formatter, or report its

status. HDx parameters in Table 15

refer to 5 parameters, x referring to

any of the 5 HDLC formatters.

Name Address (byte) Function

HDx-SRC Source data for the receive path:

x = 1 40 (100) [1:0]: line selection

x = 2 41 (104) 0 = U

x = 3 42 (108) 1 = S

x = 4 47 (11C) 2 = A

x = 5 48 (120) 3 = / (unspecified; not to be used)

[4:2]: burst selection (0 to 7)

[6:5]: channel selection

0 = B1

1 = B2

2 = D

3 = / (unspecified; not to be used)

HD_BREV 43 (10C) Bit-reverse data byte (LSB <-> MSB) read/written from/to the HDLC FIFO’s

bit[0] = 1: bit-reverse data for HDLC1 formatter

bit[1] = 1: bit-reverse data for HDLC2 formatter

bit[2] = 1: bit-reverse data for HDLC3 formatter

bit[3] = 1: bit reverse data for HDLC4 formatter

bit[4] = 1: bit reversed per block of 2 for D channel transmission through

HDLC1 in transparent mode

bit[5] = 1: bit reversed per block of 2 for D channel transmission through

HDLC2 in transparent mode

bit[6] = 1: bit reversed per block of 2 for D channel transmission through

HDLC3 in transparent mode

bit[7] = 1: bit reversed per block of 2 for D channel transmission through

HDLC4 in transparent mode

Note: No bit-reverse support is foreseen for HDLC5.

HDx-TX HDLC packet ready to be transmitted in the current frame (read only

x = 1 44 (110) register - the register is updated by and when the HDLC TX-FIFO is active,

x = 2 45 (114) transmitting data)

x = 3 46 (118)

x = 4 49 (124)

x = 5 4A (128)

HDx-MODE HDLC Mode Register (MODE)

x = 1 10 (040) This register controls the formatter configuration

x = 2 20 (080) = [0, HEN, TXE, RXE, CR32, ITF, FLS, TIC]

x = 3 30 (0C0) HEN: HDLC Protocol Enable

x = 4 D0 (340) - 1: HDLC protocol enabled (data sent LSB first)

MTC-20285 240300 [34]

Table 15: Control Registers

MTC-20285

x = 5 E0 (380) - 0: HDLC protocol disabled (data sent LSB first)

TXE: Transmitter Enable

- 1: Transmitter activated

- 0: Transmitter deactivated

RXE: Receiver Enable

- 1: Receiver activated

- 0: Receiver deactivated

CR32: 32-bit CRC Enable

- 1: Enable 32-bit CRC (non-standard)

- 0: Disable 32-bit CRC

ITF: Inter-frame Time Fill

- 1: Continuous 1’s between frames

- 0: Flag characters between frames

FLS: Flag sharing

- 1: Transmit one flag between frames

- 0: Transmit two flags between frames

TIC: Transmit Incorrect CRC

- 1: Transmit an incorrect CRC field value

- 0: Transmit correct CRC field value

HDx-EMODE HDLC Extended Mode Register (EMODE)

x = 1 11 (044) This register controls the configuration of the extended HDLC modes.

x = 2 21 (084) = [LPB, CPT, TAIE, RAF1, RAF0, MFLE, MFL1, MFL0]

x = 3 31 (0C4) LPB: Loop-back (at parallel ARM-I/O side, NOT at bit-serial GCI side)

x = 4 D1 (344) - 1: Transmit - receive looped back

x = 5 E1 (384) - 0: Transmit - receive not looped back

CPT: CRC Pass Through

- 1: Pass CRC bytes into the data stream

- 0: Do not pass CRC bytes into data stream

TAIE: Transmit Address Insertion Enable

- 1: Transmit address octets sourced from TA1/2

- 0: Transmit address octets sourced from data

RAF[1:0]: Receive Address Filter

- 00: No filter on receive addresses

- 01: Frame accepted if first address octet corresponds to either

RA1/RAW1 or RA2/RAW2

- 10: Frame accepted if second address octet corresponds to either

RA1/RAW1 or RA2/RAW2

- 11: Frame accepted if: first address octet corresponds to RA1/RAW1

and second address octet corresponds to RA2/RAW2

MFLE: Minimum Frame Length Check Enable

- 1: Minimum frame length check enabled

- 0: Minimum frame length check disabled

MFL[1:0]: Minimum Frame Length Check

- 00: Only receive frames of 3 bytes or more

- 01: Only receive frames of 4 bytes or more

- 10: Only receive frames of 5 bytes or more

- 11: Only receive frames of 6 bytes or more

HDx-CMD HDLC Command Register (CMD)

x = 1 12 (048) Commands for the formatter are written to this register. Writing a ‘1’ to any

x = 2 22 (088)) of the bit locations will cause the appropriate action to take place.

x = 3 32 (OC8) = [0, 0, 0, 0, TFT, TFC, RFC, RFB]

x = 4 D2 (348) TFT: Transmit Frame Terminator

MTC-20285 240300 [35]

MTC-20285

MTC-20285 240300 [36]

x = 5 E2 (388) - 1: The next byte to be written to the Transmit FIFO is the last of the frame

TFC: Transmit FIFO Clear

- 1: Transmit FIFO is cleared

RFC: Receive FIFO Clear

- 1: Receive FIFO is cleared

RFB: Receive Frame Abort

- 1: Abort the receive frame

HDx-SSTAT HDLC Serial Status Register (SSTAT)

x = 1 13 (O4C) This register contains the current status of the Formatter receive and transmit

x = 2 23 (08C) serial functions.

x = 3 33 (0CC) = [0, 0, 0, 0, SPG, RID, RFL, TIF]

x = 4 D3 (34C) SPG: Serial Port Grant: this bit will have no influence when reset, because

x = 5 E3 (38C) it is always granted by hardware construction:

- 1: Serial port granted

- 0: Serial port has not been granted

RID: Receive Line Idle

- 1: Receiving idle characters

- 0: Frames or starting flags are being received

RFL: Receiving Flag Characters

- 1: Receiving flag characters

- 0: Idle/frame data being received

TIF: Transmit in Frame

- 1: Transmitting frame data characters

- 0: Transmitting idle/flag characters

HDx-FSTAT HDLC FIFO Status Register (FSTAT)

x = 1 14 (050) This register contains the current status of the Formatter.

x = 2 24 (090) = [0, RSB, TLL, TFE, TOU, RLH, RFE, ROU]

x = 3 34 (0D0) reset value = 32 hex

x = 4 D4 (350) RSB: Receive Status Byte

x = 5 E4 (390) - 1: Next byte on receive FIFO is a status byte

- 0: Next byte on receive FIFO is a data byte

TLL: Transmit FIFO Level is Low

- 1: Transmit FIFO level is less than its threshold level

- 0: Transmit FIFO level is greater than or equal to its threshold level

TFE: Transmit FIFO is Full/Empty

- 1: Transmit FIFO full if TLL = 0, empty if TLL = 1

- 0: Transmit FIFO is neither full nor empty

TOU: Transmit FIFO has Overrun/Underrun

- 1: Transmit FIFO overrun if TLL = 0, underrun if TLL = 1

- 0: Transmit FIFO has neither overrun nor underrun

RLH: Receive FIFO Level is High

- 1: Receive FIFO level is greater than or equal to its threshold level

- 0: Receive FIFO level is less than its threshold level

RFE: Receive FIFO is Full/Empty

- 1: Receive FIFO full if RLH = 1, empty if RLH = 0

- 0: The receive FIFO is neither full nor empty

ROU: Receive FIFO has Overrun/Underrun

- 1: Receive FIFO overrun if RLH = 1, underrun if RLH = 0

- 0: Receive FIFO has neither overrun nor underrun

Threshold level = 25% / 75% of the FIFO depth

MTC-20285

MTC-20285 240300 [37]

HDx-ISTAT HDLC Interrupt Status Register (ISTAT)

x = 1 15 (054) = [TXOK, TXERR, RXOK, RXERR, TXFL, TXFU, RXFH, RXFO]

x = 2 25 (094) (see HDLC Interrupt Mask Register (HDx_IMASK))

x = 3 35 (0D4) Holds the current interrupt status, reading this register returns the same

x = 4 D5 (354) value that was read during the last read of HDx_ISERV.

x = 5 E5 (594)

HDx-ISRV HDLC Interrupt Service Register (ISRV)

x = 1 16 (058) = [TXOK, TXERR, RXOK, RXERR, TXFL, TXFU, RXFH, RXFO]

x = 2 26 (098) (see HDLC Interrupt Mask Register (IMASK))

x = 3 36 (0D8) Reading this register:

x = 4 D6 (358) - 1. stores the value indicating all pending interrupts in HDx_ISTAT

x = 5 E6 (398) - 2. clears the interrupts (ISRV reset to 00hex);

Note: the read value can not be used, read ISTAT

HDx-IMASK HDLC Interrupt Mask Register (IMASK)

x = 1 17 (05C) = [TXOK, TXERR, RXOK, RXERR, TXFL, TXFU, RXFH, RXFO]

x = 2 27 (09C) TXOK: Transmit Frame OK

x = 3 37 (0DC) - 1: Frame transmitted OK

x = 4 D7 (35C) - 0: No interrupt

x = 5 E7 (39C) TXERR: Transmit Frame Aborted

- 1: Transmit frame aborted

- 0: No interrupt

RXOK: Receive Frame OK

- 1: Frame received OK

- 0: No interrupt

RXERR: Receive Frame Error

- 1: Frame aborted/received with CRC error

- 0: No interrupt

TXFL: Transmit FIFO low

- 1: Transmit FIFO level has fallen below threshold

- 0: No interrupt

TXFU: Transmit FIFO Underrun

- 1: Transmit FIFO has underrun

- 0: No interrupt

RXFH: Receive FIFO High

- 1: Receive FIFO level has risen above threshold

- 0: No interrupt

RXFO: Receive FIFO Overrun

- 1: Receive FIFO has overrun

- 0: No interrupt

Threshold level = 25% / 75% of the FIFO depth

HDx-FIFO TX / RX Data

x = 1 18 (060) Reading this register pops data off the Receive FIFO, from the current read

x = 2 28 (0A0) address, and writing this register pushes data onto the Transmit FIFO.

x = 3 38 (0E0) Note that writing a ‘1’ to the TFT bit in the HDx_CMD register before writing

x = 4 D8 (360) the last byte to this register will terminate the last byte in the HDLC frame.

x = 5 E8 (3A0) Note that when changing to transparent mode either from reset, or during

normal operation, the first received byte in the RX FIFO should be ignored.

= [D7, D6, D5, D4, D3, D2, D1, D0]

HDx-RFBC Receive Frame Byte Count (RFBC)

x = 1 19 (064) The contents of this register are valid after an RXOK/RXERR interrupt.

x = 2 29 (0A4) The value in this register corresponds to the number of receive frame bytes

MTC-20285

MTC-20285 240300 [38]

x = 3 39 (0E4) placed into the Receive FIFO. This value includes CRC bytes if CPT = 1,

x = 4 D9 (364) but does not include the Receive Status Byte placed into the Receive FIFO

x = 5 E9 (3A4) immediately following the frame data.

= [C7, C6, C5, C4, C3, C2, C1, C0] (modulo 256)

HDx-TA1 Transmit Address 1 (TA1)

x = 1 1A (068) This register contains the first address octet for outgoing HDLC frames.

x = 2 2A (0A8) This register value will only be used as the first address octet if the TAIE

x = 3 3A (0E8) bit in the HDx_EMODE register is set to ‘1’.

x = 4 DA (368) = [T17, T16, T15, T14, T13, T12, T11, T10]

x = 5 EA (3A8)

HDx-TA2 Transmit Address 2 (TA2)

x = 1 1B (06C) This register contains the second address octet for outgoing HDLC frames.

x = 2 2B (0AC) This register value will only be used as the second address octet if the TAIE

x = 3 3B (0EC) bit in the HDx_EMODE register is set to ‘1’.

x = 4 DB (36C) = [T27, T26, T25, T24, T23, T22, T21, T20]

x = 5 EB (3AC)

HDx-RAW1 Receive Address Wildcard 1 (RAW1)

x = 1 1C (070) This register contains a ‘wildcard’ pattern for use by receive address

x = 2 2C (0B0) register RA1. Any bits set to ‘1’ in this register will not be used in the

x = 3 3C (0F0) comparison with an address octet.

x = 4 DC (370) = [RW17, RW16, RW15, RW14, RW13, RW12, RW11, RW10]

x = 5 DE (378)

HDx-RAW2 Receive Address Wildcard 2 (RAW2)

x = 1 1D (074) This register contains a ‘wildcard’ pattern for use by receive address

x = 2 2D (0B4) register RA2. Any bits set to ‘1’ in this register will not be used in the

x = 3 3D (0F4) comparison with an address octet.

x = 4 DD (374) = [RW27, RW26, RW25, RW24, RW23, RW22, RW21, RW20]

x = 5 DE (378)

HDx-RA1 Receive Address 1 (RA1)

x = 1 1E (078) This register contains a value to be used in the address matching circuitry

x = 2 2E (0B8) for received HDLC frames. The RAF bits in the HDx_EMODE register control

x = 3 3E (0F8) the operation of the address matching circuitry.

x = 4 DE (378) = [RA17, RA16, RA15, RA14, RA13, RA12, RA11, RA10]

x = 5 EE (3B8)

HDx-RA2 Receive Address 2 (RA2)

x = 1 1F (07C) This register contains a value to be used in the address matching circuitry

x = 2 2F (0BC) for received HDLC frames. The RAF bits in the HDx_EMODE register control

x = 3 3F (0FC) the operation of the address matching circuitry.

x = 4 DF (37C) = [RA27, RA26, RA25, RA24, RA23, RA22, RA21, RA20]

x = 5 EF (3BC)

MTC-20285

NOTES:

On receiving a frame, a receive status byte is appended to the frame data in the FIFO. This status byte indicates how

successfully the frame was received. The status byte can be identified in the receive data stream either by examining the

RSB status bit of the HDx_FSTAT register, or by examining the RFBC register value after an RXOK/RXERR interrupt has

occurred.

Receive Status Byte = [0, 0, 0, RAB, CRC/ERR, PAD2, PAD1, PAD0]

RAB: Receive Abort

- 1: Receive frame aborted

- 0: Receive frame not aborted

CRC/ERR: Receive CRC Error

- 1: Receive CRC Error

- 0: No receive CRC Error

PAD[2:0]: 3-bit number indicating the number of padding bits added to the final receive character in the case of non octet

aligned data.

MTC-20285 240300 [39]

MTC-20285

Description

An integrated USB Device Controller

revision 1.1 compliant, is provided for

interfacing with a personal computer.

Apart from the mandatory bi-

directional USB control pipe (Control

Endpoint 0), it can handle a maximum

of 6 bi-directional data streams using

6 shared (bi-directional) endpoints

1..6. These streams are buffered in

configurable size FIFO’s and use

either USB Isochronous, Bulk or Inter-

rupt Endpoints. They can for example,

be used to send/receive the B1, B2

and D channels of any burst to/from

two GCI interfaces (U, S, A).

The USB interface consists of hard-

ware and some ARM software.

It is fully software configurable as

follows:

• The ISDN USB logical architecture

(type of endpoints, USB descriptors,

USB FIFO sizes etc) is selectable

through configuration data in the USB

RAM (mapped in the APB space).

• Reading/writing USB FIFO’s is done

in ARM software, for example,

using interrupt routines.

• ISDN layer 2 and 3 processing

can optionally be provided in ARM

software, reducing the CPU load

of the USB host (PC).

USB Interface

FEATURES INCLUDE:

• Full-speed USB device

• Interface to external USB driver,

according to the USB Implementers

Forum recommendations.

• Device powered (does not receive

power via USB cable)

• Soft-configurable (see above)

• A 48 MHz (2,500ppm) clock for

USB bus clock recovery

• Most of the interface is clocked at

12 MHz (obtained by dividing the

48 MHz clock)

• The entire Standard USB command

handling (e.g. GET_STATUS,

GET_DESCRIPTOR, etc) is an

exclusive hardware responsibility.

No overhead in the ARM software

• USB FIFO. Their handling is an

ARM Software responsibility for

example, Reset USB, Get info on

ISDN handling parameters, etc.

• Indication signals are provided to

monitor the traffic over Channels

1..6 (typically D, B1 and B2

channels of 2 ISDN streams) and

USB connectivity (device configured

by USB host). They can optionally

be used to drive 7 LEDs -

USB1_RXTX to USB6_RXTX and

USB_CFG pins.

MTC-20285 240300 [40]

1 USB Configuration

4 USB Interfaces:

• Interface 0:

Control Endpoint 0 (always enabled)

• Interface 1:

- Alternate Setting 0: Endpoints 1 and 4 disabled (default reset value)

- Alternate Setting 1: Bi-directional Endpoint 1 enabled

- Alternate Setting 2: Bi-directional Endpoint 4 enabled

- Alternate Setting 3: Bi-directional Endpoints 1 and 4 enabled

• Interface 2:

- Alternate Setting 0: Endpoints 2 and 5 disabled (default reset value)

- Alternate Setting 1: Bi-directional Endpoint 2 enabled

- Alternate Setting 2: Bi-directional Endpoint 5 enabled

- Alternate Setting 3: Bi-directional Endpoints 2 and 5 enabled

• Interface 3:

- Alternate Setting 0: Endpoints 3 and 6 disabled (default reset value)

- Alternate Setting 1: Bi-directional Endpoint 3 enabled

- Alternate Setting 2: Bi-directional Endpoint 6 enabled

- Alternate Setting 3: Bi-directional Endpoints 3 and 6 enabled

4 USB Strings:

• String 0: Language ID (support for 1 language)

• String 1: Manufacturer

• String 2: Product

• String 3: Serial Number

USB Disabled

If the USB function is not used in the

application, the following device pins

must be connected to VSS, and all

other USB related pins left open.

Name Pin Nr.

USB_XTAL2 121

USB_RCV 115

USB_VP 116

USB_VM 117

USB_VBUS 118

USB Logical Architecture

The device supports:

MTC-20285

The number of logical endpoints

(visible to the USB host) equals 7.

Endpoint 0: Control endpoint.

Endpoint 1..6: shared (bi-directional)

endpoints.

The total number of physical end-

points equals 25, taking into account

all endpoints in all configurations and

for all alternate settings.

Typically, this logical architecture

will be used to implement the ISDN

Multi-Channel model.

• USB Control Endpoint 0 is located

in Interface 0, the communication

class interface.

• Interfaces 1,2 and 3 are data class

interfaces for transferring D, B1 and

B2 basic rate ISDN channel data.

• Endpoints 1,2 and 3 are used for

1 basic rate ISDN line, while end-

points 4,5 and 6 can optionally be

used for a second line, or for some

other application specific information

exchange.

• Endpoints 1..6 can be configured

as Bulk-, Isochronous or Interrupt

endpoints.

Architecture

The interface is built around a Phoenix

(Sand) USB Device Controller (UDC)

synthesizable core. It also contains an

APB - mapped 1 kByte RAM, that holds

USB FIFO data for all channels, and

configuration data (USB descriptors

and UDC buffer values).

USB RAM Memory

A bi-directional multi-channel FIFO

serves as buffer space between the

Sand Application Bus and the ARM-

APB bus. Buffering is needed because

the UDC initiates all data transfers on

the Sand Application Bus, and the

application has to accept / provide

data within 4 cycles after the UDC

request.

UDC buffer values configure the UDC

(ISDN USB logical architecture) and

select the sizes of all channel 1..6

FIFO blocks. The USB descriptors

contain information that has to be

sent to the USB host, on its request.

This part of the RAM is called USB

CONFIG.

The size of the RAM is 1024 Bytes.

In each direction (USB towards ARM,

and ARM towards USB), 7 separate

bi-directional FIFO blocks are provided,

corresponding to Channels 0 to 6.

Channel 0 is always used for the

mandatory bi-directional USB control

pipe (Endpoint 0). Channels 1…6

correspond to the shared (bi-directional)

endpoints 1…6. The 7 FIFO blocks

in the USB towards the ARM direction

are called USB RX FIFO, the 7 blocks in

the opposite direction are called USB

TX FIFO. Each Channel corresponds

to a USB RX FIFO block and a USB

TX FIFO block.

The size of the channel 0 FIFO block is

fixed to 8 bytes in each direction. The

size of each FIFO block for channel

1..6 is soft-configurable. (The base

address of each block is contained

in the UDC buffer values, and RX/TX

blocks for the same endpoint are

adjacent (no gap). This information

is extracted during the configuration

phase of the Sand core (UDC buffer

values download).

Note that 7 bi-directional channels is an

upper bound. Certain configurations

could use less, e.g. ISDN/CAPI or a

‘download’ mode where the personal

computer can download USB confi-

guration information + descriptors

and ARM software into the device.

The FIFO is built around one dual-

port RAM. Using one single RAM

is possible because each side (USB,

ARM) will only access one channel

at once, for either reading or writing.

Synchronization mechanisms are

provided between the Sand USB Core

(Sand Application Bus), that runs on

a 12MHz clock, and the rest of the

USB interface (APB access mechanism

including accessible registers).

This USB RAM not only serves as

FIFO, but also holds UDC buffer

values and all USB descriptors. They

have to be loaded, by the ARM soft-

ware, from external memory into the

USB RAM at device power-up. The

MTC-20285 240300 [41]

MTC-20285

Each channel 1..6 RX FIFO block has

a configurable base address, that is

contained in the UDC buffer values.

The RAM address range of each block

extends from its base address to the

base address of the next block minus

one. Although the USB RX FIFO is

entirely memory mapped, the software

will only directly access these

addresses for test purposes.

Software reads data from a RX FIFO

block, by doing read accesses to its

corresponding Channel register

address, USBxFIFO (x = 0..6). The

hardware maintains a circular read

pointer to physically access the RAM.

While doing a write transfer to a USB

RX FIFO block, the least significant

10-bits of the UDC address bus

contain the base address of that

particular block. A hardware circular

Write Pointer is maintained to

generate the RAM write address.

Upon completion of a (multi-Byte)

write transaction, the UDC indicates

whether or not the transaction was

successful, using Acknowledge /

Not-Acknowledge signals. In case

the transaction was unsuccessful, the

received data is ignored. Unsuccessful

transactions are caused by data errors

on the USB (e.g. bitstuff error, CRC

error, host sends more bytes than the

Endpoints MaxPktSize).

A second circular Write Pointer, the

ACKed Write Pointer, is used for this

accept/ignore mechanism. When data

is received, it is written in the RAM,

and the Write pointer is updated.

When the transfer has successfully

completed, the ACKed Write pointer

gets the value of the Write pointer.

For unsuccessful transfers, the ACKed

Write pointer is not updated, causing

the received data to be ignored.

Each time the software accesses a

RX FIFO block, a circular Read Pointer

is updated in hardware. This pointer

is used together with the ACKed

Write Pointer to determine the RX

FIFO High/Low level, Full/ Empty

and Overrun/Underrun indications

for that particular RX FIFO block.

If an RX FIFO block is Full, and UDC

issues a Write request, the data is

ignored and a NAK handshake is

sent towards the host.

MTC-20285 240300 [42]

Base Address

Write Pointer

Acked Write Pointer

Read Pointer USBx-FIFO

USB Side

(Sand Application Bus) ISDN Side

(AMBA APB Bus)

Read Access

Fig.14: USB RX FIFO Block Organisation

USB RX FIFO

MTC-20285

MTC-20285 240300 [43]

Each TX FIFO block has a configurable

base address, which is contained

in the UDC buffer values. The RAM

address range of each block extends

from its base address to the base

address of the next block minus one.

Although the USB TX FIFO is entirely

memory mapped, the software will

only directly access these addresses

for test purposes.

Software writes data to a RX FIFO

block, by doing write accesses to

its corresponding Channel register

address, USBxFIFO (x = 0..6). The

hardware maintains a circular write

pointer to physically access the

RAM.

While doing a read transfer from a

USB TX FIFO block, the UDC address

bus contains the base address of

that particular block. A hardware

circular Read Pointer is maintained to

generate the RAM read address.

Upon completion of a (multi-Byte)

read transaction, the UDC indicates

whether or not the transaction was

successful, using the Acknowledge /

Not-Acknowledge signals. In case the

transaction was unsuccessful, the

transmitted data must be retained in

the TX FIFO block. Unsuccessful trans-

actions are caused by data errors on

USB (e.g. no ACK received from Host).

A second circular Read Pointer, the

ACKed Read Pointer, is used for this

accept/ignore mechanism. Each time

a data Byte is read from the RAM and

put on the Application Bus, the Read

Pointer is updated. When the transfer

has successfully completed, the ACKed

Read Pointer gets the value of the Read

Pointer. For unsuccessful transfers, the

Base Address

Read Pointer

Acked Read Pointer

Write Pointer

USBx-FIFO

USB Side

(Sand Application Bus) ISDN Side

(AMBA APB Bus)

Write Access

Fig.15: USB TX FIFO Block Organisation

USB TX FIFO

ACKed Read Pointer is not updated,

causing the transmitted data to be

available for retransmission.

Each time the software accesses

a TX FIFO block, a Write Pointer is

updated in hardware. This pointer is

used together with the ACKed Read

Pointer to determine the TX FIFO

High/Low level, Full/Empty and

Overrun/Underrun indications for that

particular TX FIFO block.

If a TX FIFO block is Full, and UDC

issues a Read request, the reaction

depends on the Endpoint type. For

a Bulk or Interrupt Endpoint, either a

NAK handshake or a Short Packet

and an ACK handshake is sent to the

host. For an Isochronous Endpoint, a

Zero Byte Data Packet is sent to the

host.

MTC-20285

USB CONFIG

The UDC can address each location

of the USB CONFIG block. It contains

static data (UDC buffer values and

USB descriptors) that are loaded

during device start-up. On the USB

side, the UDC generates addresses for

this part of the RAM. On the ARM

side, the software can access all

locations over the APB-bus.

USB Error Indication

When any problem is encountered

sending/receiving a USB packet (due

to USB error conditions ‘cf. Supra’ or

FIFO overrun/underrun conditions)*,

this is indicated by setting the NACK

(Not Acknowledged Packet) bit of that

particular USB channel (= bi-

directional endpoint). This bit is

located in USBx-FSTAT[6], x = 0..6.

This bit is only cleared when the ARM

reads the USBx-FSTAT register.

* A Standard USB command (always

handled by the UDC) will also make

the Channel 0 NACK bit = ‘1’.

handshake is sent to the host. (When

flushing / no threshold, a Short Packet

and an ACK handshake is sent to the

host). In case of an Isochronous End-

point, a Zero Byte Data Packet is sent

to the host.

6. Write to a full USB TX FIFO, USB

TX FIFO Overrun interrupt (use USB

RX FIFO Low / High interrupt driven

actions to avoid this).

7. Read from an empty HDLC RX FIFO,

HDLC RX FIFO Underrun (use HDLC

RX FIFO High driven actions to avoid

this).

8. Write to a full HDLC RX FIFO,

HDLC RX FIFO Overrun interrupt.

USB FIFO Overrun / Underrun inter-

rupts can be avoided by writing /

reading FIFO data in chunks that are

smaller than half the FIFO channel

size, triggered by the USB FIFO

Low / High Level interrupts.

When the HDLC RX FIFO level is

getting too high, software can use

external or internal RAM memory

storage (Back Pressure).

Figure 12 shows an example of the

data flow mechanism between ISDN

and USB. A single FIFO channel is

shown for each data direction.

Underrun / Overrun behaviour is

discussed for each numbered item

in the figure.

Note that interrupts can of course be

masked.

1. A Write request to a USB RX FIFO,

which has less space free than its

threshold, produces a USB RX FIFO

Overrun interrupt, the data written is

ignored, and a NAK is sent to the

host, which will either re-transmit bulk

data or discard isochronous data.

2. Read from an empty USB RX FIFO,

USB RX FIFO Underrun interrupt (use

USB TX FIFO Low / High interrupt

driven actions to avoid this).

3. Write to a full HDLC TX FIFO, HDLC

TX FIFO Overrun (use HDLC TX FIFO

Low driven actions to avoid this).

4. Read from an empty HDLC TX

FIFO, Inter-frame Time Fill (D-channel:

’1’ bits, B-channels: 0x7E Flag

characters) are inserted on GCI inter-

face.

5. Read request to a USB TX FIFO,

which contains less bytes than its

threshold (and not flushing), USB TX

FIFO Underrun interrupt. In case of a

Bulk (or Interrupt) Endpoint, a NAK

MTC-20285 240300 [44]

USB RX FIFO

USB TX FIFO HDLC RX FIFO

HDLC TX FIFO

USB

(Sand Application Bus)

ARM

(AMBA-APB Bus)

ISDN

(GCI)

2 3 4

5 6 7 8

Fig.16: ISDN <->USB Data Flow Mechanism

ISDN <-> USB Data Flow Mechanism

MTC-20285

USB Control/Status Registers

Registers related to the USB device

as a whole reside in APB page 0x17.

Registers related to a particular

channel (0..6) reside in APB pages

0x10..0x16.

USB_DIMASK is an interrupt mask

triggered) interrupt generation. It has

no shadowed status register, status

can be found in USB_DSTAT and

USB_ALTSET registers.

The channel interrupts are level

triggered (USBx-ISTAT, -ISRV, -IMASK

mechanism) and can be cleared

locally, by reading USBx-ISRV.

Name Address (byte) Function

USB_DCMD 170 (5C0) USB Device Command:

bit[0]: USB_START: USB Start-up

Doing a write ‘1’ access to this bit generates a reset pulse for the USB

interface (reset and restart). It also triggers the hardware to load the UDC

buffer values from the USB RAM, into the Sand USB Core. After this, the

USB interface will become activated (UDC_CFG becomes ’1’).

bit[1]: USB_PULL: enable pull-up resistor on D+

- 1 = enable pull-up resistor on D+, provided that UDC_CFG = ‘1’

- 0 = disable pull-up resistor on D+, regardless the value of UDC_CFG

bit[2]: UDC_FORCECLK: Force UDC clocking (all 48 MHz and 12 MHz

clocks) during USB suspend

- 1 = UDC is clocked, even if USB_SUSPEND = ‘1’

- 0 = UDC is not clocked, provided that USB_SUSPND =’1’

bit[3]: UDC_DISABLECLK: Disable UDC clocking (all 48 MHz and 12 MHz

clocks) at all times

- 1 = all UDC clocking is disabled (USB power-down mode)

- 0 = all UDC clocking is enabled

To bring the USB interface into power-down mode, it is recommended to first

make USB_PULL = ‘1’, and only thereafter UDC_DISABLECLK = ‘1’.

After resuming the USB interface from power-down (UDC_DISABLECLK = ‘0’),

a new USB_START is required.

When a USB Suspend has happened while UDC_DISABLECLK was ‘1’

(effectively disabling the USB clocks), the software needs to clear all USB

FIFO’s when Suspend is resumed.

USB_DSTAT 171 (5C4) USB Device Status:

bit[0]: USB_PHCON: Device Physically Connected

- 1 = Device is physically connected to the USB

- 0 = Device is not physically connected to the USB

bit[2:1]: UDC_CFG: Sand Core Configured

- 00 = Sand Core unconfigured

- 01 = Configuring Sand core (loading UDC buffer values)

- 10 = Sand core configured (successfully received its UDC buffer values)

bit[3]: USB_CFG: Device configured by Host

- 0 = USB device not configured by USB Host

- 1 = USB device configured by USB Host

bit[4]: USB_SUSPND: USB Suspend State

- 0 = USB is not Suspended

- 1 = USB is Suspended

MTC-20285 240300 [45]

MTC-20285

USB_ALTSET 172 (5C8) USB Alternate Setting (per Interface, as set by the USB Host):

bit[1:0]: Alternate Setting of USB Interface 1

bit[3:2]: Alternate Setting of USB Interface 2

bit[5:4]: Alternate Setting of USB Interface 3

USB_DIMASK 174 (5D0) USB Device Interrupt Mask Register

bit[0] = USB_PHCON Event (USB cable connect/disconnect)

bit[1] = USB_CFG Event (USB SET_CONFIGURATION)

bit[2] = USB_INTF Event (USB SET_INTERFACE: Alt. Settings/Interfaces)

bit[3] = USB_SUSPND Event (USB into suspend or resume from suspend)

USBx-FIFO TX / RX Data for USB channel x

x = 0 105 (414) Reading this register pops data off the USB RX FIFO, from the current read

x = 1 115 (454) address, and writing this register pushes data onto the USB TX FIFO.

x = 2 125 (494)

x = 3 135 (4D4)

x = 4 145 (514)

x = 5 155 (554)

x = 6 165 (594)

USBx-SET USB FIFO Settings

x = 1 116 (458) bit[2:0] = USB_THR: USB FIFO Threshold level towards USB bus

x = 2 126 (498) 000 = No Threshold

x = 3 136 (4D8) 001 = 8 Bytes Threshold (default)

x = 4 146 (518) 010 = 16 Bytes Threshold

x = 5 156 (558) 011 = 32 Bytes Threshold

x = 6 166 (598) 100 = 64 Bytes Threshold

101 = 128 Bytes Threshold

110 = 256 Bytes Threshold

111 = 512 Bytes Threshold

Typically, the threshold of an endpoint will be chosen to be equal to the USB

Packet size for that particular endpoint, to avoid abundant short packet

generation.

These threshold values can be written at device start-up, and should not be

modified during USB operation.

The threshold of RX0 / TX0 FIFO is fixed to 8 Bytes. Endpoint 0 Packet size

should be configured to be 8 Bytes. All data phases of control 0 Vendor/Class

specific commands should be integer multiples of 8 Bytes.

USBx-CMD USB Command Register (CMD)

x = 0 100 (400) Commands for the formatter are written to this register. Writing a ‘1’ to

x = 1 110 (440) any of the bit locations StatusOK, TFFL, TFC, RFC will cause the appropriate

x = 2 120 (480) action to take place. The bits TFEN, RFEN, TSTL, RSTL can hold either a ‘1’

x = 3 130 (4C0) or a ‘0’ value, enabling or disabling the corresponding feature.

x = 4 140 (5000 = [StatusOK, TFFL, TFEN, RFEN, TFC, RFC, TSTL, RSTL]

x = 5 150 (540)

x = 6 160 (580) SatusOK: Endpoint 0 Class/Vendor Command handled OK

- 1: Endpoint 0 command status is OK

TFFL: Transmit FIFO Flush

- 1: Transmit FIFO is flushed

TFEN: Transmit FIFO Enable

- 1: Transmit FIFO is enabled

- 0: Transmit FIFO is disabled

(mimics an empty FIFO towards USB)

MTC-20285 240300 [46]

MTC-20285

RFEN: Receive FIFO Enable

- 1: Receive FIFO is enabled

- 0: Receive FIFO is disabled

(mimics an empty FIFO towards USB)

TFC: Transmit FIFO Clear

- 1: Transmit FIFO is cleared

RFC: Receive FIFO Clear

- 1: Receive FIFO is cleared

TSTL: Transmit Endpoint Stall

- 1: Transmit Endpoint is stalled

- 0: Transmit Endpoint is unstalled

RSTL: Receive Endpoint Stall

- 1: Receive Endpoint is stalled

- 0: Receive Endpoint is unstalled

Transmit FIFO Flush can for example, be used to force a short packet at the

end of a data stream.

StatusOK bit exists for Endpoint 0 only.

TFFL, TFEN, RFEN bits exist for Endpoints 1…6 only.

TFC, RFC, TSTL, RSTL bits exist for all Endpoints (0 …6).

USBx-FSTAT USB FIFO Status Register (FSTAT)

x = 0 101 (404) This register contains the current status of the USB FIFO.

x = 1 111 (444) - Bit[7..0] = [SETUP, NACK, TLL, TFE, TO, RLH, RFE, RU]

x = 2 121 (484) - Reset value = 32 hex

x = 3 131 (4C4)

x = 4 141 (504) NACK: Not Acknowledged Packet

x = 5 151 (544) - 1: USB transmission error occurred

x = 6 161 (584) - 0: no USB transmission error occurred since last read of USBx-FSTAT

(this bit is cleared on Read)

TLL: Transmit FIFO Level is Low

- 1: Transmit FIFO level is less than its threshold level

- 0: Transmit FIFO level is greater than or equal to its threshold level

TFE: Transmit FIFO is Full/Empty

- 1: Transmit FIFO full if TLL = 0, empty if TLL = 1

- 0: Transmit FIFO is neither full nor empty

TO: Transmit FIFO has Overrun

- 1: Transmit FIFO overrun

- 0: Transmit FIFO has no overrun

RLH: Receive FIFO Level is High

- 1: Receive FIFO level is greater than or equal to its threshold level

- 0: Receive FIFO level is less than its threshold level

RFE: Receive FIFO is Full/Empty

- 1: Receive FIFO full if RLH = 1, empty if RLH = 0

- 0: The receive FIFO is neither full nor empty

RU: Receive FIFO has Underrun

- 1: Receive FIFO has underrun

- 0: Receive FIFO has no underrun

Threshold level (towards APB bus) = half of the FIFO depth

For x = 0, an extra bit is defined in USB0-FSTAT: USB0-FSTAT[7] = SETUP:

SETUP Packet

- 1: Receiving / Received 8 byte SETUP Packet in RX0 FIFO

MTC-20285 240300 [47]

MTC-20285

MTC-20285 240300 [48]

(When a SETUP packet arrives, both RX0 and TX0 FIFO’s are

unconditionally cleared*, before the receiving of data will start)

- 0: Received non SETUP Packet in RX0 FIFO

USBx-ISTAT USB Interrupt Status Register

x = 0 102 (408) Bit[7..0] = [TXFH, TXFO, RXFL, RXFU, TXFL, TXFU, RXFH, RXFO]

x = 1 112 (448) (see USB Interrupt Mask Register (USBx-IMASK))

x = 2 122 (488) Holds the current interrupt status, reading this register returns the same

x = 3 132 (4C8) value that was read during the last read of USBx-ISERV.

x = 4 142 (508)

x = 5 152 (548)

x = 6 162 (588)

USBx-ISRV USB Interrupt Service Register

x = 0 103 (40C) Bit[7..0] = [TXFH, TXFO, RXFL, RXFU, TXFL, TXFU, RXFH, RXFO]

x = 1 113 (44C) (see USB Interrupt Mask Register (USBx-IMASK))

x = 2 123 (48C) Reading this register:

x = 3 133 (4CC) 1. returns a value indicating all pending interrupts, and

x = 4 143 (50C) 2. clears the interrupts (ISRV reset to 00hex).

x = 5 153 (54C) The returned value is stored in USBx-ISTAT for further reading

x = 6 163 (58C)

USBx-IMASK USB Interrupt Mask Register

x = 0 104 (410) Bit[7..0] = [TXFH, TXFO, RXFL, RXFU, TXFL, TXFU, RXFH, RXFO]

x = 1 114 (450) TXFH: Transmit FIFO High

x = 2 124 (490) - 1: Transmit FIFO level has risen above threshold

x = 3 134 (4D0) - 0: No interrupt

x = 4 144 (510) TXFO: Transmit FIFO Overrun

x = 5 154 (550) - 1: Transmit FIFO has overrun

x = 6 164 (590) - 0: No interrupt

RXFL: Receive FIFO Low

- 1: Receive FIFO level has fallen below threshold

- 0: No interrupt

RXFU: Receive FIFO Underrun

- 1: Receive FIFO has underrun

- 0: No interrupt

TXFL: Transmit FIFO low

- 1: Transmit FIFO level has fallen below threshold

- 0: No interrupt

TXFU: Transmit FIFO Underrun

- 1: Transmit FIFO has underrun

- 0: No interrupt

RXFH: Receive FIFO High

- 1: Receive FIFO level has risen above threshold

- 0: No interrupt

RXFO: Receive FIFO Overrun

- 1: Receive FIFO has overrun

- 0: No interrupt

Threshold level (towards APB bus) = half of the FIFO depth

* Reception of any SETUP packet will clear the RX0 / TX0 FIFO’s: both those corresponding to Class/Vendor Specific USB

commands (which are handled by the Software, and will make it into the RX FIFO) and Standard USB commands (which

are handled by the UDC, will not make it into the RX0 FIFO and will be NACKed).

MTC-20285

MTC-20285 240300 [49]

Start-up Sequence

1. After a system reset, the USB core

is in reset as long as the USB cable is

not connected to the device.

2. ARM Software (start-up code) reads

UDC buffer values and USB descriptors

from the external memory, and writes

them into the internal USB RAM.

3. When these values are in the RAM,

software will test the USB_PHCON bit /

interrupt. If an active USB cable is con-

nected, ARM Software will do a write

‘1’ access to the USB_START register.

4. Triggered by the write ‘1’ access to

the USB_START register, MTC-20285

Hardware resets USB core and loads

UDC buffer values from the internal

USB RAM into the UDC.

5. When UDC_CFG becomes ‘1’,

ARM Software will write a ‘1’ in the

USB_PULL bit. This will make the

device visible to the host, as a valid

full speed USB device.

6. Normal operation is now entered.

The USB host will configure the device

(SET_CONFIGURATION), causing

USB_CFG to become ‘1’, and will

issue a SET_INTERFACE, after which

USB data transfers can take place.

USB RAM Accesses

The entire APB-memory mapped USB

internal RAM contains:

• all bi-directional USB FIFO channel

data

• USB_CONFIG, UDC buffer values

and USB descriptors

All FIFO channel data is accessed using

Control/Status Registers (1 single re-

gister per channel, for both Rx and Tx,

USBx-FIFO). Since the entire USB RAM

is memory mapped, the FIFO channel

data can also be directly accessed for

test purposes (non ’FIFO’-access will

not update Read/Write pointers).

During normal operation, the software

does not perform such accesses.

1 Device descriptor: 18 Bytes

1 Configuration descriptor: 9 Bytes

13 Interface descriptors: 13 * 9 Bytes

24 Endpoint descriptors: 24 * 7 Bytes

String descriptors: String 0: 4 Bytes

String 1: C[1] + 2 Bytes

String 2: C[2] + 2 Bytes

String 3: C[3] + 2 Bytes

TOTAL: C[1] + C[2] + C[3] + 322 Bytes

Device Configuration

1. USB Descriptors

(C[i] = number of characters in String i)

2. UDC Buffer Values

EndPtBufn[15:12], for each logical

endpoint should contain the FIFO

index.

FIFO Index = (2 * EndPoint number),

for an RX FIFO (OUT Endpoint)

FIFO Index = (2 * EndPoint number)

+ 1, for a TX FIFO (IN Endpoint)

EndPtBufn[9:0], for each logical

endpoint should contain the FIFO

base address.

FIFO’s are ordered as follows: EP0

RX, EP0 TX, EP1 RX, EP2 RX, etc

(no gaps in between)

The descriptor space starts right after

the last position of EP 6 TX.

1 ConfigBuf: 4 Bytes

4 StringBufs: 4 * 3 Bytes

25 EndPtBufs: 25 * 5 Bytes

TOTAL: 141 Bytes to be loaded into Sand core Flip-flops

NOTE:

The USB descriptors and the UDC buffer values combined consume about half of

the USB RAM space.

MTC-20285

A master clock oscillator is included,

based on an external crystal of 15.36

MHz. This can provide an output at

the crystal frequency for the ISDN

chip (INTT or INTQ). It therefore offers

better than 100 ppm accuracy, the

external crystal is specified to 50 ppm

accuracy.

NOTE:

The oscillator pins may also be con-

trolled from an external master clock.

In which case the external master

clock is connected to the pin XTAL1,

whereas pin XTAL2 is connected to

GND. An internal PLL is provided to

multiply the crystal frequency by two.

The BASECLK input pin is used to

enable/disable this internal PLL:

• when BASECLK is tied ‘0’,

the internal PLL is disabled,

so internal clock = 15.36 MHz.

• when BASECLK is tied ‘1’,

the internal PLL is enabled,

so internal clock = 30.72 MHz.

This internal clock is used as the input

clock to generate the ASB clock (used

for ARM), APB clock and CKOUT.

Note that the UART and GCI clock

frequencies are independent of

BASECLK.

When the BASECLK is ‘0’, the ASB-,

APB- and CKOUT clocks have the

same frequency as in the MTC-20280

device, for equal values of the clock

division registers CLK_3[3:2],

CLK_2[3:0] and CLK_1[3..0].

When the BASECLK is ‘1’, these

clocks have a frequency that is twice

that in the MTC-20280 device, for

equal clock division register values.

A second clock oscillator, based on

an external crystal of 48 MHz is

provided. It needs to be 2,500 ppm

(0.25%) accuracy. It is used for clock

recovery in the USB interface and to

derive a 12 MHz clock that clocks all

other parts of the USB interface.

NOTE:

The oscillator pins may also be

controlled from an external master

Clock Generation

clock. In which case the external

master clock is connected to the pin

USB_XTAL1, whereas pin USB_XTAL2

is connected to GND.

One clock output (CKOUT) with a

programmable division ratio from the

internal clock, is provided for use by

any external peripheral function. It is

user-programmable via the control

also be disabled. When the clock is

disabled, it remains constant high.

Typically CKOUT can be used to drive

the 15.36MHz input clock of the

INTT/INTQ. The duty cycle is 50%.

Table 16: CKOUT Frequency

MTC-20285 240300 [50]

The ASB clock (ARM clock) is also a

programmable clock derived from the

internal clock. It is user-programmable

via the control register CLK_2. The

duty cycle is 50%.

Table 17: ASB Clock Frequency

BASECLK = '0' BASECLK = '1'

CLK_1[3..0] = 0 15.36 MHz 30.72 MHz

CLK_1[3..0] = 1 15.36 MHz / 2 30.72 MHz / 2

CLK_1[3..0] = 2 15.36 MHz / 4 30.72 MHz / 4

CLK_1[3..0] = 3 15.36 MHz / 6 30.72 MHz / 6

CLK_1[3..0] = x 15.36 MHz / (2*x) 30.72 MHz / (2*x)

BASECLK = '0' BASECLK = '1'

CLK_2[3..0] = 0 15.36 MHz 30.72 MHz

CLK_2[3..0] = 1 15.36 MHz / 2 30.72 MHz / 2

CLK_2[3..0] = 2 15.36 MHz / 4 30.72 MHz / 4

CLK_2[3..0] = 3 15.36 MHz / 6 30.72 MHz / 6

CLK_2[3..0] = x 15.36 MHz / (2*x) 30.72 MHz / (2*x)

MTC-20285

Also the ASB clock can be completely

disabled, bringing the ARM into

power-down mode.

NOTE:

• the modification of the ASB clock

(write to APB address 0x92) can

not be done with the multiple-store

instruction but only with a simple

store instruction

• the ASB clock can not be disabled

and its frequency modified

simultaneously. Two separate

instructions have to be used

In order to avoid accidental disabling

of the clocks, a 4-bit word must be

written in specific register fields

(CLK_1[7..4] and CLK_2[7..4]).

a) CKOUT must be enabled by the

software by writing any value different

from ‘1001’ to CLK_1[7..4], at the

same time the value written in

CLK_1[3..0] defines the start-up

frequency.

b) For the ASB clock, this is slightly

different. It is disabled under software

control by writing the appropriate

value to register CLK_2. This also

defines the start-up frequency.

However, enabling must be done by

a hardware activity detection circuit,

triggering the ARM interrupt (FIQ or

IRQ). Therefore before going into

power-down, the software must take

care that the appropriate interrupt

input source is enabled (not masked),

otherwise only a power reset will

allow start-up of the ARM again.

The bits CLK_2[7..4] will be reset

automatically by the hardware

activity detection.

Notice that during ARM power-down,

all other hardware units (HDLCs,

UARTs, etc) and the GCI interfaces

will keep running.

The peripheral clock, the APB clock,

is derived from the ASB clock by a

programmable division factor.

NOTE:

In the MTC-20280, the APB clock

does not depend of the ASB clock.

Table 18: APB Clock Frequency

MTC-20285 240300 [51]

BASECLK = '0' BASECLK = '1'

CKOUT 15.36 MHz 30.72 MHz CLK_1 = 0

ASB clock 15.36 MHz 30.72 MHz CLK_2 = 0

CLK_3[3..2] = 0 ASB clock

CLK_3[3..2] = 1 ASB clock / 4

CLK_3[3..2] = 2 ASB clock / 8

CLK_3[3..2] = 3 ASB clock / 32

The clock generator also generates

clocks for the 2 integrated UART

blocks. The frequency is fixed to

3.6864 MHz. For power reduction,

the clocks can be disabled separately

(see Table 18, register CLK_3).

After reset, the clock CKOUT and the

ASB clock are not disabled and set to:

MTC-20285

Table 19: Clock Register Table

MTC-20285 240300 [52]

Name Address (byte) Function

CLK_1 [3..0] 91(244) Integer representing the CKOUT output clock frequency

CLK_1 [7..4] Notes:

a) the maximum division factor is CLK_1[3..1] = 15

b) CKOUT can be disabled by setting bits CLK_1[7..4] = = ‘1001’

c) bit[7..4]: write only

CLK_2 [3..0] 92(248) Integer representing the ASB clock frequency

CLK_2 [7..4] Notes:

a) the max division factor is CLK_2[3..0] = 15

b) ASB clock can be disabled by setting bits CLK_2[7..4] = = ‘1001’

c) bit[7..4]: write only

CLK_3 93(24C) bit[0]: DPLL status (read only)

- 0 = internal GCI clocks not synchronized with the external reference or

the external reference is not active, DPLL is tracking

- 1 = internal GCI clocks synchronized

bit[1]: UART1 clock disable (default = 0 = enable)

bit[3:2]: APB clock division factor

bit[4]: UART2 clock disable (default = 1 = disable)

MTC-20285

• ASB: Advanced System Bus

ASB clock: i.e. ARM clock,

frequency user-programmable

• APB: Advanced Peripheral Bus

APB clock: frequency user-

programmable

The ARM processor will operate in

‘Little Endian’ mode when treating the

bytes in memory. It is the ARM that

decides whether an 8-bit (byte b_0),

16-bit (bytes = b_1, b_0 with b_0 =

LSB byte) or 32-bit word (bytes b_3,

b_2, b_1, b_0 with b_0 = LSB byte) is

accessed.

• Dedicated Logic registers are 8-bit

wide, so the ARM will only request

for an 8-bit access and the APB

bridge will only support SingleByte

access (see section 3.7.1)

• The External Memory interface can

be set to operate in one of four

The ARM7TDMI

bridge is optimized to reduce as much

as possible the wait cycles.

On-chip Memory

RAM of 4 kByte is on-chip. Read access

is performed in one single cycle, for

8-bit, 16-bit as 32-bit word accesses.

Writing 32-bit wide words is always

done in 1 cycle. Write accesses of 8-

bit and 16-bit words require 2 RAM

cycles. In order to reduce the processor

wait cycles, an internal FSM will only

introduce a wait cycle if the previous

internal memory access operation is

not fully completed (this is identical to

the APB bridge case). This can only

occur when an 8- or 16-bit write

access is scheduled just after another

8- or 16-bit write access to the same

on-chip memory. Generally, the ARM

will not execute 2 write operations

successively, but will fetch a new

instruction between write operations.

possible modes (see section 3.8);

depending on the mode, 16-bit

and 32-bit accesses will be auto-

matically transformed into one,

2 consecutive TwoByte accesses,

or two, 4 consecutive SingleByte

accesses respectively.

• The internal memory allows direct

access to a 1-, 2- or 4-byte word

(see section 3.7.2)

APB Bridge

The APB clock is derived from the

ASB clock by a programmable

division factor (see CLK_3 register).

However, depending on the ASB

clock (= processor clock), the APB

clock will be modulated in order to

minimize the cycles needed for the

read and write operations. Processor

wait cycles will be introduced by the

hardware only when needed. The

MTC-20285 240300 [53]

MTC-20285

PIN (function)

MC0..5 (ncs_i)

NOE

NWR

MC6

MC7(a0)

A21..1

DQ7..0

DQ15..8

EXT MEM

Add0

Add21..1

Data7..0

Fig.17: ARM7TDMI and Interfaces

MTC-20285

The external memory interface

consists of:

• A[21:1] and MC7:

22-bits address bus

• DQ[15:0]:

16-bits data bus allowing Single-

Byte or TwoByte transfers; the

MSB of the data bus DQ[15] may

have a special function depending

on the selected MemoryAccess

configuration

• NWR,NOE:

2 control signals with fixed function

• MC7..0:

8 Memory control output signals,

of which the function depends on

the selected MemoryAccess mode

(e.g. MC7 might be the LSB of the

address bits)

• MM1, MM0:

2 MemoryAccess configuration bits

External Memory Interface

Memory Access Modes

Depending on the MemoryAccess

mode, up to 6 blocks of 4 Mbytes

can be accessed (24 Mbytes). The

selection of the appropriate block

will be done with the control signals

MC7..0, performing the function of

‘chip select’ signals (see Table 20).

The MemoryAccess input pins must

be strapped to VDD/VSS in order to

select one of 4 possible access modes.

The different modes allow interfacing

with simple and ordinary byte-

oriented external memories, or more

advanced 2 byte oriented memories.

Note that the selected MemoryAccess

mode is valid for each block and all

external memories. Each block in the

MTC-20285 address space is

handled in the same way.

Basically the following 4 modes are

supported by the MTC-20285:

MTC-20285 240300 [54]

Table 20: Memory Access Modes

Case MM1 and MM0 Description

a 0 0 WordAccess Disabled (only single-byte access possible)

b 1 1 WordAccess Enabled with ChipSelect/Low/Up control outputs

c 1 0 WordAccess Enabled with ChipSelect/Nbyte/Addr0 control outputs

d 0 1 WordAccess Enabled with ChipSelectUp/ChipSelectLow control outputs

MTC-20285

When the WordAccess Mode is

disabled, the MTC-20285 Memory

interface will always convert the

8-, 16- or 32-bit access of the ARM

into one, two or four consecutive

SingleByte external accesses.

When the WordAccess Mode is

enabled, the MTC-20285 Memory

interface will decide whether an

access is performed in TwoByte (using

the full 16-bit data bus DQ[15:0]) or

SingleByte mode (using only 8-bits of

the 16-bit data bus). One SingleByte

access for an 8-bit ARM access, and

one. TwoByte accesses for a 16-bit

and 32-bit ARM access respectively.

The alignment of the bytes onto the

data bus depends on the selected

mode, as shown in the Table 20.

The 3 versions of WordAccess Mode

Enabled allow controlling of different

types of external memory by the MTC-

20285, each interconnected and

controlled in a different way. There-

fore the meaning of the control signals

MC7..0 that are sent to the external

memory will depend on the selected

version.

The following memory types and

configurations are supported:

CASE C: (see Fig.20)

• external memory with integrated

single/double byte access mode

(controlled by CS,OE,WE,BYTE,A0)

(e.g. AMD or INTEL memories)

• addressed in SingleByte or TwoByte

access by MTC-20285

(WordAccess Enabled)

CASE D: (see Fig.21)

• normal byte-oriented external

memory (controlled by CS,OE,WE)

• two memories allocated (one for

LSByte, one for MSByte)

• addressed in SingleByte or TwoByte

access by MTC-20285 (Word-

Access Enabled)

• without glue logic for chip-select

signal generation in between MTC-

20285 and the memory

CASE A: (see Fig.18)

• normal byte-oriented external

memory (controlled by CS,OE,WE)

• one memory allocated to store both

LSB and MSBytes

• addressed in SingleByte access

mode only by MTC-20285 (Word-

Access Disabled)

CASE B: (see Fig.19)

• normal byte-oriented external

memory (controlled by CS,OE,WE)

• two memories allocated (one for

LSByte, one for MSByte)

• addressed in SingleByte or TwoByte

access by MTC-20285 (Word-

Access Enabled)

• glue logic needed for chip-select

signal generation in between MTC-

20285 and the memory. Note this

Configuration is not recommended

because the delay through the glue

logic must be compensated on the

address bus and control signals

MTC-20285 240300 [55]

MTC-20285

PIN (function)

MC0..5 (ncs_i)

NOE

NWR

MC6

MC7(a0)

A21..1

DQ7..0

DQ15..8

EXT MEM

Add0

Add21..1

Data7..0

Fig.18: MTC-20285 - External Memory Connections for ‘Case a’

MTC-20285

MTC-20285 240300 [56]

MTC-20285

PIN (function)

MC0..5 (ncs_i)

NOE

NWR

MC6 (nup)

MC7 (nlow)

A21..1

DQ7..0

DQ15..8

EXT MEM (MSB)

Add20..0

Data7..0

EXT MEM (LSB)

Add20..0

Data7..0

Fig.19: MTC-20285 - External Memory Connections for ‘Case b’

Case c (AMD)

MTC-20285

PIN (function)

MC0..5 (ncs_i)

NOE

NWR

MC6v (nByte)

MC7 (a0)

A21..1

DQ14..0

DQ15

EXT MEM (AMD type)

A20..0

DQ14..0

DQ15/A_1

BYTE

Case c (INTEL)

MTC-20285

PIN (function)

MC0..5 (ncs_i)

NOE

NWR

MC6 (nByte)

MC7 (a0)

A21..1

DQ14..0

DQ15

EXT MEM (INTEL type)

CE1, CE0

A21..1

DQ14..0

DQ15

BYTE

Fig.20: MTC-20285 - External Memory Connections for ‘Case c’

MTC-20285

MTC-20285 240300 [57]

MTC-20285

PIN (function)

MC0,2,6,4 (nCsLow)

NOE

NWR

MC1,3,7,5 (nCsUp)

A21..1

DQ7..0

DQ15..8

EXT MEM (MSB)

Add20..0

Data7..0

EXT MEM (LSB)

Add20..0

Data7..0

Fig.21: MTC-20285 - External Memory Connections for ‘Case d’

MTC-20285

Meaning of the codes:

• SingleByte: selected by memory interface hardware controller:

alignment of any byte_i to be transferred to/from external memory at certain times

• TwoByte: selected by memory interface hardware controller:

alignment of any byte_i to be transferred to/from external memory at certain times

• - -: not occurring situation

• x: the output is not used in this mode; it will not be floating but fixed to a certain value (preferably VDD)

• z: the bi-directional I/O is not used in this mode; it will be set into tri-state (input)

• pio: pins used as parallel I/O: ports DQ15..12 = PE3..0 and DQ11..8 = PF3..0

• a0: LSB of address

• a0*: the LSB of the address will not be used and be put in tri-state, if and only if a TwoByte access is selected; this is

done to be compatible with AMD memories, for which DQ15 and a0 must be connected to the same pin

• ncs: active low chip select for block in the memory map (both LSByte and MSByte)

• ncl: active low chip select for block in the memory map (only LSByte)

• ncu: active low chip select for block in the memory map (only MSByte)

• nlow: active low indication that lower byte is transferred

• nup: active low indication that upper byte is transferred

• nwr: active low indication for write enable

• noe: active low indication for read enable

• nbyte: active low indication for SingleByte transfer selection, TwoByte (nbyte = 1) or SingleByte (nbyte = 0)

The following logical relationship must hold between the signals:

• nlow = (nbyte + a0)*not(nbyte)

• nup = (nbyte + not(a0))*not(nbyte)

• ncl = (ncs + nlow)

• ncu = (ncs + nup)

NOTE: (In case d)

• Each chip select output is split into 2 signals, one for the lower byte and one for the upper byte memory selection. Only

the lower 4 blocks of the memory map are addressable, blocks 5 and 6 are not. Instead, you have the advantage that

no glue logic is needed to control the chip select pins of the external memories.

• Take care that memory block 2 is controlled by MC6 and MC7.

MTC-20285 240300 [58]

The output pins have the following

logical meaning depending on the

mode:

SingleByte TwoByte

MM NWR NOE MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 A DQ DQ DQ DQ

1:0 21:1 15:8 7:0 15:8 7:0

a 0 0 nwr noe ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 x a0 addr pio b_i - - - -

21:1

b 1 1 nwr noe ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 nup nlow addr b_1 b_0 b_1 b_0

21:1 b_3 b_2 b_3 b_2

c 1 0 nwr noe ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 nbyte a0* addr z b_i b_1 b_0

21:1 b_3 b_2

d 0 1 nwr noe ncl0 ncu0 ncl1 ncu1 ncl3 ncu3 ncl2 ncu2 addr b_1 b_0 b_1 b_0

21:1 b_3 b_2 b_3 b_2

MTC-20285

Wait Cycle(s) per Block

For each of the 6 external blocks, wait

cycles can be specified in order to

optimize the external components

configuration. Via the registers

CHIP_WTC1, 2 and 3, up to 15 wait

cycles can be inserted per block. The

default value after reset is 15 wait

cycles for each block.

Timing

Fig.22 shows the timing relationship

of the memory interface for a 2 byte

access making use of the nbyte

control signal.

MTC-20285 240300 [59]

ARM clock

NBYTE/NUP/NLOW

NCS0,1,2,3

Memory access cycle

1 wait cycle

READ

NBYTE/NUP/NLOW

NCS0,1,2,3

WRITE

NOE

NWR

Fig.22: Memory interface

NOTES:

• Timing is compatible with standard SRAM and Flash, when NCS controlled

• When no wait state is specified, the NCS strobe corresponds to the low level

of the internal ASB clock. The width of the low and the high level of NCS is

symmetric and corresponds to the selected ASB clock speed

• When wait states are specified, an equivalent number of ASB cycles is added

to the external access timing, so ONLY the low level of NCS is extended (as

required for slower SRAMs). It is always possible to keep the levels symmetric

by decreasing the ASB clock speed, instead of placing wait states

Memory Space Organisation

The MSB bits of the 32-bit internal

ARM address word, are decoded to

split the memory space into 8 blocks

assigned as follows:

0: external block 0

1: external block 1

2: external block 2

3: external block 3

4: external block 4

5: external block 5

6: internal fast memory

7: APB bus

When the ARM accesses one of the

external blocks , the MTC-20285

will bring the corresponding chip

select control signal nCS active

low. Note that there are no gaps

between addresses of successive

external memory blocks. For both the

‘internal fast memory’ and the ‘APB

memory’ a full length page of 0x1000

0000 bytes is allocated. Although the

current MTC-20285 design uses only

0x1000 and 0x800 bytes

respectively for these memories.

Data in the ‘ 4 kByte internal RAM’

can be either a byte, half-word or

word. Their addresses are LSB

aligned, making use of the 12 LSB of

the ARM address bus (from 0xC000

0000 up to 0xC000 0FFF).

All data of the ‘APB memory’ are

bytes. Their addresses are ‘word-

aligned’ (LSB+2bits) such that the data

byte is always LSB aligned onto the

data bus. The ARM address bits

[12..2] are used to address the full

memory map, the 2 LSB of the

address being zero (from 0xE000

0000 up to 0xE0000 1FFC).

At reset the ARM will start-up at the

fixed boot address 0x0000 0000,

accessing the external block 0.

In order to re-define the code in

external block 0, the addresses of

block 0 can be swapped with block 3

MTC-20285

NOTE:

The timings are valid in all the operating range conditions

MTC-20285 240300 [60]

NBYTE / NUP / NLOW

NCS0,1,2,3

READ

WRITE

NOE

tas tah

tco toh

data valid

tes teh

A / NWR

NBYTE / NUP / NLOW

NCS0,1,2,3

tas tah

tos toh

data valid

tcw

Fig.23 Timings of the Memory Interface

READ tas min. TBD ns

tah min. TBD ns

tcw (0.5 + TBD) * ASB period

min TBD

x = wait cycles ns

tes min. TBD ns

teh min. TBD ns

tco max. (tcw - TBD) ns

toh min. TBD ns

WRITE tas min. TBD ns

tah min. TBD ns

tcw (0.5 + TBD) * ASB period

min TBD

x = wait cycles ns

tos max. TBD ns

toh min. TBD ns

MTC-20285

memories location (write to APB

address 0x01), the program counter

(PC) has to be located outside the

blocks involved (0 and 3). For

instance, a small loop can be defined

in the data ram space while

swapping.

under software control as soon as the

bit CHIP_CFG[7] = 1 is set. At reset

the blocks are not swapped.

NOTE:

To avoid disruption of the program

execution while swapping the

MTC-20285 240300 [61]

ARM addr.

0040 0000 Hex

003F FFFF Hex

0000 0000 Hex = boot address

0080 0000 Hex

007F FFFF Hex

00C0 0000 Hex

00BF FFFF Hex

0100 0000 Hex

00FF FFFF Hex

0140 0000 Hex

013F FFFF Hex

C000 0000 Hex

017F FFFF Hex

E000 0000 Hex

CFFF FFFF Hex

EFFF FFFF Hex

0 : external block 0

1 : external block 1

7 : APB bus

6 : internal fast memory

5 : external block 5

4 : external block 4

3 : external block 3

2 : external block 2

default

unswapped configuration

CHIP_CFG[7]=0

3 : external block 3

1 : external block 1

7 : APB bus

6 : internal fast memory

5 : external block 5

4 : external block 4

0 : external block 0

2 : external block 2

swapped configuration

CHIP_CFG[7]=1

Fig.24 ARM Address Space Organisation

Name Address (byte) Function

CHIP_CFG[7] 01 (004) Swap addresses for external memory block 0 and 3 (1-bit):

0 = unswapped (default at reset, address 00 in block 0),

1 = swapped (address 00 in block 3)

CHIP_WTC1 04 (010) Wait cycles for external memory blocks (default 15: slow at reset)

bit[3:0]: for memory block 0

bit[7:4]: for memory block 1

CHIP_WTC2 05 (014) Wait cycles for external memory blocks (default 15: slow at reset)

bit[3:0]: for memory block 2

bit[7:4]: for memory block 3

CHIP_WTC3 06 (018) Wait cycles for external memory blocks (default 15: slow at reset)

bit[3:0]: for memory block 4

bit[7:4]: for memory block 5

Table 21: Memory Register Table

MTC-20285

The chip contains several interrupt

sources. These sources are split into

two types of interrupts, a fast (NFIQ)

and normal (NIRQ) interrupt. Priority

within one class is resolved in

software. Interrupts are controlled by

writing to / reading from a set of

control/status registers:

• IRQ1_* and IRQ3_* for NFIQ

• IRQ2_* and IRQ4_* for NIRQ.

Each source can be masked by

clearing a bit in a control register

(ENCLR) or unmasked by setting a bit

Interrupts

(ENSET). At reset, by default all

sources are masked. All ‘interrupt

request’ bits from the various sources

are readable in a register and can be

cleared. Both the masked (ST) and the

unmasked ‘raw’ (STR) interrupt status

can be checked. As soon as a non-

masked interrupt occurs, the

NFIQ/NIRQ pin of the ARM goes

active low. The interrupt can be

cleared by writing to the acknowledge

control register (ACK). If all interrupts

in IRQx_ST are cleared, the

NFIQ/NIRQ pin goes inactive high

again. See Table 22 and Table 23.

MTC-20285 240300 [62]

Name Address (byte) Function

IRQx_ST R only

x = 1 94 (250) Interrupt status after masking with IRQx_EN

x = 2 9A (268) IRQx_ST(i) = 1 if interrupt(i) is active after masking

x = 3 194 (650)

x = 4 19A (668)

IRQx_STR R only

x = 1 95 (254) Interrupt status without masking

x = 2 9B (26C) IRQx_STR(i) = 1 if interrupt(i) is active

x = 3 195 (654)

x = 4 19B (66C)

IRQx_EN R only

x = 1 96 (258) Interrupt mask register used to generate IRQx_ST

x = 2 9C (270) IRQx_EN(i) = 1 if interrupt(i) must not be masked

x = 3 196 (658)

x = 4 19C (670)

IRQx_ENSET W only

x = 1 97 (25C) Control register to unmask an interrupt

x = 2 9D (274) IRQx_ENSET(i) = 1 results in IRQx_EN(i) = 1, i.e. unmask interrupt(i)

x = 3 197 (65C)

x = 4 19D (674)

IRQx_ENCLR W only

x = 1 98 (260) Control register to mask an interrupt

x = 2 9E (278) IRQx_ENCLR(i) = 1 results in IRQx_EN(i) = 0, i.e. mask interrupt(i)

x = 3 198 (660)

x = 4 19E (678)

IRQx_ACK W only

x = 1 99 (264) Control register to clear an interrupt

x = 2 9F (27C) IRQx_ACK(i) = 1 resets the interrupt(i) detection in IRQx_ST(R) (i)

x = 3 199 (664)

x = 4 19F (67C)

Table 22: Interrupt Register Table

MTC-20285

Table 23: Interrupt Mapping

reg. bit trigger Assignment

FIQ IRQ1 0 edge Internal GCI frame (always running)

1 level HDLC1

2 level HDLC2

3 level HDLC3

4 edge Timer1

5 edge PA

6 edge PF

7 level HDLC4

IRQ3 0 level USB channel 0

1 level USB channel 1

2 level USB channel 2

3 level USB channel 3

4 level USB channel 4

5 level USB channel 5

6 level USB channel 6

7 level HDLC5

IRQ IRQ2 0 level UART1

1 edge PB

2 edge External interrupt

3 level D-CI activity detection

4 edge Timer2

5 edge PC

6 edge PD

7 edge PE

IRQ4 0 level UART2

1 edge master GCI frame (see section 3.3)

2 edge USB device

3 inactive

4 inactive

5 inactive

6 inactive

7 inactive

MTC-20285 240300 [63]

NOTES:

• Edge trigger: the interrupt will be activated when a rising edge appears on the specific control signal. In general, that

detection is used when the interrupt comes directly from the source and not from a second level of interruption (as for

HLDC, UART, etc)

• Level trigger: the interrupt stays active when the control signal is high. In general, that detection is used when the

interrupt comes from a second level of interruption. Therefore, the second level must be first acknowledged/cleared

before acknowledging the FIQ/IRQ registers.

MTC-20285

The external interrupt can be made

edge or level sensitive by writing the

appropriate value to the control

• In case of pin IT edge detection,

a rising transition is generated

towards the IRQ register (see

section 3.9).

• In case of pin IT level detection,

continuous rising transitions are

generated towards the IRQ register

in order to keep the IRQ interrupt

active.

External Interrupt

MTC-20285 240300 [64]

Name Address (byte) Function

CHIP_CFG[2..1] 01 (040) Type of external interrupt to detect (2bit):

- 00 = negative-edge

- 01 = positive-edge

- 10 = low-level

- 11 = high-level (default)

Table 24: External Interrupt Register Table

MTC-20285

The chip contains 2 UARTs (Universal

Asynchronous Receiver/Transmitter) of

the 16550 family which are fully

programmable by the microprocessor.

• UART1: directly mapped on MTC-

20285 pins

• UART2: mapped on the configurable

PC pins

Common Features

(UART1 and UART2)

• Word lengths from 5 to 8-bits

• Optimal parity bit, even, odd or

forced to a defined state

• 1 or 2 stop bits

• Baud rate generator

• Interrupt generated from any one of

10 sources of the UART module itself

UART1 Features

• Two 64 byte FIFO’s, one for trans-

mit and one for receive

• RXD, TXD, CTS, RTS on permanent

external pins

• Extended modem control signals

DCD / OUT2, RI / OUT1, DSR

and DTR multiplexed on external

pins PB0..PB3 (see section 3.12)

• FIFO trigger level software

configurable

• RXD can be connected with a timer

for software Baud rate detection

UART2 Features

• Two 16 byte FIFO’s, one for trans-

mit and one for receive

• RXD, TXD, CTS, RTS multiplexed

on external pins PC0..PC3 (see

section 3.12)

• Extended modem control signals

not available

• Fixed FIFO trigger level

UART Interfaces

MTC-20285 240300 [65]

Table 25: Baud Rate Examples

Baud Rate (bps) Division Factor (DL)

2400 96

4800 48

9600 24

19200 12

57600 4

115200 2

230400 1

DTE / DCE Mode

Details only the UART1 module.

The extended modem control signals

multiplexed on PB pins can be confi-

gured in DTE or DCE mode as follows:

Mode Pin Pin I/O Function

DTE PB0 input DCD: data carrier detect

PB1 output OUT2: signal controlled via software

DCE PB0 input RI: ring indicator

PB1 output OUT1: signal controlled via software

Baud Rate Generators

The Baud rates are separately con-

figurable for UART1 and UART2. They

are specified by the divisor registers

DL (DLM = MSB; DLL = LSB) (see

230400 bps

baudrate = ——————

The register configuration required is:

CHIP_CFG[0] CHIP_CFG2[0]

0 - not applicable because extended modem

control signals not accessible

1 0 DTE

1 1 DCE

MTC-20285

Software Baud Rate Detection

For software Baud rate detection, the

UART1 RXD pin can replace the

functionality of the pin PA port.

MTC-20285 240300 [66]

PIO module

activity detector

latching

Timer Capture

module

Irq Controller

irqPA

PA[3:0]

(RXD,0,0,0)

CHIP_CFG2[2]

Fig.25: Baud Rate Detection Block Diagram

• RXD pin level can be measured by

reading PAB_IN register

• RXD transitions can be evaluate via

the PA interrupt bit

• RXD timing can be measured by

mean of the capture logic in the

Timer1 module

Table 26: Default Register Set

Name Address (byte) Function

UARTx_RBR R only Receiver Buffer Register

x = 1 50 (140) This register is updated from the receive shift register at the end of

x = 2 F0 (3C0) a receive sequence.

UARTx_THR W only Transmitter Holding Register

x = 1 50 (140) Data is held in this register until transferred to the transmitter shift register

x = 2 F0 (3C0)

UARTx_IER Interrupt Enable Register

x = 1 51 (144) = [x, x, x, x, EDSSI, ELSI, ETBEI, ERBFI]

x = 2 F1 (3C4) - EDSSI: Enable Modem Status Interrupt

When set (‘1’), an UART interrupt is generated if D0, D1, D2 or D3 of

the Modem Status Register become set.

- ELSI: Enable Rx Status Interrupt

When set (‘1’), an interrupt is generated if D1, D2, D3 or D4 of the Line

Status Register become set.

- ETBEI: Enable Tx Holding Register Empty Interrupt

When set (‘1’), an interrupt is generated if THRE = 1 or the Transmitting

Holding Register is empty.

- ERBFI: Enable Receiver Buffer Register

When set (‘1’), an interrupt is generated if the Receive Buffer contains data.

MTC-20285

UARTx_IIR R only Interrupt Identification Register

x = 1 52 (148) = [FIFOE, FIFOE, x, x, ID2, ID1, ID0, NINT]

x = 2 F2 (3C8) FIFOE

Returns 1 if FIFO’s enabled, otherwise 0

ID[4:0]: Interrupt ID

- 0.: Modem status change (interrupt cleared when reading the modem

status register)

- 1.: Transmitter holding register empty or Tx FIFO trigger (interrupt

cleared when reading this register or when writing to the transmitter

holding register)

- 2.: Receive Data available or Rx FIFO trigger (interrupt cleared when

reading receive buffer register)

- 3.: Receiver line status change (interrupt cleared when reading the line

status register)

- 4.: Character timeout indication (interrupt cleared when reading receive

buffer register)

NINT

Interrupt pending, active low

Notes:

1. Receive timeout interrupt occurs if all the following apply:

- there is at least one character in the FIFO

- the most recent character was received longer than 4 character periods

ago (inclusive of all start, parity, and stop bits)

- the most recent CPU read of the FIFO was longer than 4 character

periods ago

The timeout timer is restarted on receipt of a new byte from the input shift

2. Tx FIFO interrupt occurs when Tx FIFO is under its threshold level. This

interrupt will be delayed one character period minus the last stop bit period

whenever; THRE = 1 and there has not been at least 2 bytes in the Tx FIFO

simultaneously since the last time THRE = 1. If the Tx interrupt is enabled,

setting bit 0 of the FCR will generate an immediate interrupt.

3. If the FIFO’s are enabled and at least one of the active bits in IER is

disabled, then the UART will operate in the FIFO polled mode. Since the

Tx and Rx paths are controlled separately, either one or both can be in the

polled mode. The application software should check Tx and Rx status using

the LSR.

UARTx_FCR W only FIFO Control Register

x = 1 52 (148) = [RFTL1, RFTL0, TFTL1, TFTL0, DMA1, CLRT, CLRR, FIFOE]

x = 2 F2 (3C8) RFTL[1:0]: RX FIFO trigger level

Defines RX FIFO trigger level in number of bytes

UART1:

- 00: 01 bytes

- 01: 16 bytes

- 10: 32 bytes

- 11: 62 bytes

UART2:

- 00: 01 bytes

- 01: 04 bytes

- 10: 08 bytes

- 11: 14 bytes

MTC-20285 240300 [67]

MTC-20285

TFTL[1:0]: TX FIFO trigger level

Defines TX FIFO trigger level in number of bytes

UART1:

if Extended functions are enabled:

- 00: 01 bytes

- 01: 16 bytes

- 10: 32 bytes

- 11: 62 bytes

if Extended functions are not enabled:

- 1 byte

UART2:

- 1 byte

DMA1

Set DMA mode 1.

In the MTC-20285 configuration, no DMA support is provided.

CLRT

Clear TX FIFO

CLRR

Clear RX FIFO

FIFOE

Enable FIFO when the FIFO is either enabled or disabled, both Rx and

Tx FIFO’s are reset. This bit must be a 1 for any of the other bits in the

UARTx_LCR Line Control Register

x = 1 53 (14C) = [DLAB, SB, SP, EPS, PEN, STB, WLS1, WLS0]

x = 2 F3 (3CC) DLAB: Divisor Latch Access bit

When clear ‘0’, Receive and Transmitter Registers are read/written

address 50 (F0) and IER register at address 51 (F1). When set ‘1’,

Divisor Latch LS is read/written at address 50 (F0) and Divisor Latch MS

read/written at address 51 (F1).

SB: Set Break

When set ‘1’, TXD signal is forced into the ‘0’ state

SP: Stick Parity

When set ‘1’, parity bit is forced into a defined state, dependent upon

state of EPS, PEN:

If EPS = ’1’ and PEN = ’1’ parity bit is set and checked = ‘0’

If EPS = ’0’ and PEN = ’1’ parity bit is set and checked = ‘1’

EPS: Even Parity Select

When set ‘1’ and PEN = ‘1’ an even number of ones is sent and checked.

When clear ‘0’ and PEN = ‘1’ an odd number of ones is sent and checked.

PEN: Parity Enable

When set ‘1’ parity is transmitted and checked. Parity bit is added after

the data field and before the STOP bits. When clear ‘0’ parity is neither

transmitted or checked.

STB: Number of STOP bits

When set ‘1’ two STOP bits are added after each character is sent,

except if character length is 5, then 1_ STOP bits are added. When

clear ‘0’ one STOP bit is always added. Only the transmit STOP bits are

programmable, only the receive stage expects one STOP bit irrespective

of the state of STB.

WLS[1:0]: Word Length Select

Transmitted and received character size defined as follows:

MTC-20285 240300 [68]

MTC-20285

MTC-20285 240300 [69]

- 00 = 5-bit

- 01 = 6-bit

- 10 = 7-bit

- 11 = 8 -bit

UARTx_MCR Modem Control Register

x = 1 54 (150) = [x, x, x, LOOP, OUT2, OUT1, RTS, DTR]

x = 2 F4 (3D0) LOOP: Loop back mode

When set ‘1’ the following conditions are implemented:

- TXD is forced to ‘1’

- RXD is disconnected from the Rx input shift register

- The Rx input shift register is connected to the Tx output shift register

- The modem status signals are disconnected

- The modem control signals are connected to modem status inputs

OUT1,OUT2

- UART1: Control the state of the corresponding outputs (used in DCE

mode), even in loop mode.

- UART2: Not used

RTS

Control the state of the corresponding output, even in loop mode.

DTR

- UART1: Control the state of the corresponding output, even in loop mode.

- UART2: Not used

UARTx_LSR Line Status Register

x = 1 55 (154) = [FIFOERR, TEMT, THRE, BI, FE, PE, OE, DR]

x = 2 F5 (3D4) FIFOERR: RX Data Error in FIFO

This bit is set to ‘1’ when there is at least one PE, FE, or BI in the RX FIFO.

It is cleared by a read from the LSR register, if there are no subsequent

errors in the FIFO.

TEMT: Transmitter Empty or below the threshold

If the FIFO is disabled, this bit is set to ‘1’ whenever the transmitter

holding register and the transmitter shift register are empty.

If the FIFO is enabled, this bit is set whenever the Tx FIFO is below the

threshold and the transmitter shift register is empty.

THRE: Transmitter Holding Register Empty

If the FIFO is disabled, this bit is set to ‘1’ whenever the transmitter

holding register is empty and ready to accept new data, this bit is

cleared when the data is transferred to the transmitter shift register.

If the FIFO is enabled, this bit is set to ‘1’ whenever the Tx FIFO is below

the threshold. It is cleared when it goes again above the threshold.

BI: Break Interrupt

If the FIFO is disabled, this bit is set whenever the RXD is held in the zero

state for more than a transmission time (START bit + DATA bits + PARITY

+ STOP bits). BI is reset by the CPU reading this register. If the FIFO is

enabled, this error is associated with the corresponding character in the

FIFO. The error is flagged when this byte is at the top of the FIFO. When

a break occurs only one zero character is loaded into the FIFO, the next

character transfer is enabled when RXD goes into the marking state and

receives the next valid start bit.

FE: Framing Error

If the FIFO is disabled, this bit is set if the received data did not have a

valid STOP bit, FE is reset by the CPU reading this register. If the FIFO

is enabled, the state of this bit is revealed when the byte it refers to is at

MTC-20285

the top of the FIFO.

PE: Parity Error

If the FIFO is disabled, this bit is set if the received data does not have a

valid parity bit, PE is reset by the CPU reading this register. If the FIFO is

enabled, the state of this bit is revealed when the byte it refers to is at the

top of the FIFO

OE: Overrun Error

If the FIFO is disabled, this bit is set if the receive buffer was not read

by the CPU before new data from the receive shift register over wrote

previous contents. OE is cleared when the CPU reads this register. If the

FIFO is enabled, an overrun error occurs when the Rx FIFO is full and

the Rx shift register becomes full. OE is set as soon as this happens. The

character in the shift register is then overwritten, but is not transferred to

the FIFO.

DR: Data Ready

This bit is set whenever the receive buffer is full, or by a byte being trans-

ferred into the FIFO. DR is cleared by the CPU reading the receive buffer

or by reading all of the FIFO bytes. This bit is also cleared whenever the

FIFO enable bit is changed.

UARTx_MSR Modem Status Register

x = 1 56 (158) = [DCD, RI, DSR, CTS, DDCD, TERI, DDSR, DCTS]

x = 2 F6 (3D8) DCD: Data Carry Detect

- When Loop = ‘0’ this is the input signal DCD

- When Loop = ‘1’ this is equal to OUT2

RI: Ring Indicator

- When Loop = ‘0’ this is the input signal RI

- When Loop = ‘1’ this is equal to OUT1

DSR: Data Set Ready

- When Loop = ‘0’ this is the input signal DSR

- When Loop = ‘1’ this is equal to DTR

CTS: Clear To Send

- When Loop = ‘0’ this is the input signal CTS

- When Loop = ‘1’ this is equal to RTS

DDCD: Delta Data Carry Detect

This bit is set (‘1’) if the state of DSR has changed since this register

was last read.

TERI: Trailing Edge Ring Indicator

This bit is set if the RI input changes from ‘1’ to ‘0’ since this register

was last read.

DDSR: Delta Data Set Ready

This bit is set (‘1’) if the state of DSR has changed since this register

was last read.

DCTS: Delta Clear to Send

This bit is set (‘1’) if the state of CTS has changed since this register

was last read.

UARTx_SCR Scratch Register

x = 1 57 (15C) General purpose read/write register, undefined after reset.

x = 2 F7 (3DC)

MTC-20285 240300 [70]

MTC-20285

MTC-20285 240300 [71]

Name Address (byte) Function

UARTx_DLL Divisor Latch, MSB and LSB for Baud rate control

x = 1 50 (140) (see Table 25)

x = 2 F0 (3C0) After reset DLM, DLL are undefined.

UARTx_DLM

x = 1 51 (144)

x = 2 F1 (3C4)

Table 27: Baud Rate Generator Divisor Register Set (selected when LCR[7] = 1)

Name Address (byte) Function

UART1_EFR 52 (148) Extended Function Register

= [x, x, 0, EME, x, x, x, x]

EME: Enhancement Mode Enable

When set to ‘1’ enable the extended functions. This is to ensure the back-

ward compatibility for software written for the 16550A device family.

Table 28: Enhanced Register Set (selected when LCR = 0xBF)

MTC-20285

Eight 4-bit bi-directional I/O ports are

provided (PA[3..0], PB[3..0], PC[3..0],

PD[3..0], PE[3..0], PF[3..0], PG[3..0],

PH[3..0]) to allow extra user-defined

functionality. The application software

can define the access direction of

any of the 4 pins and have a total

visibility of the pin activity (read

and write access). One interrupt

signal is generated per parallel I/O

source with two exceptions, the ports

PG[3:0] and PH[3:0]. These 2 ports

are available on the MSByte of the

Parallel I/O Ports

external databus (see Fig.1) only

when the WordAccess mode of the

external memory interface is disabled

(see case a, section 3.8.1).

Each port can generate an interrupt

based on activity detection only, for

the bits that are set in input mode.

However, depending of the device

configuration registers (CHIP_CFGx

registers), some ports can have others

functions as follows:

MTC-20285 240300 [72]

Pin Direction Configuration Timer function

PA0 output CHIP_CFG[3] = 1 T2O: Timer2 output toggling when time-out

PA1 input CHIP_CFG[4] = 1 T2i: Timer2 trigger input

PA2 output CHIP_CFG[5] = 1 T1O: Timer1 output toggling when time-out

PA3 input CHIP_CFG[6] = 1 T1i: Timer1 trigger input

Table 29: Port PA: Timer Extended Functions

Pin Direction Configuration UART1 function

PB0 - CHIP_CFG[0] = 1 DCD / OUT2

PB1 - CHIP_CFG[0] = 1 RI / OUT1

PB2 input CHIP_CFG[0] = 1 DSR

PB3 output CHIP_CFG[0] = 1 DTR

Table 30: Port PB: UART1 Extended Functions (see section 3.11)

Pin Direction Configuration UART2 access

PC0 input CHIP_CFG2[1] = 1 RXD2

PC1 output CHIP_CFG2[1] = 1 TXD2

PC2 input CHIP_CFG2[1] = 1 CTS2

PC3 output CHIP_CFG2[1] = 1 RTS2

Table 31: Port PC: UART2 Access

NOTES:

• The special port configurations overrule the port direction setting registers.

• The special port configurations do not overrule the port interruption systems.

MTC-20285

MTC-20285 240300 [73]

Name Address (byte) Function

PAB_OUT A0 (280) Data register used to drive:

- bit[3:0]: PB[3..0]

- bit[7:4]: PA[3..0]

if set in output direction

PAB_IN A1 (284) Data register to store value of:

- bit[3:0]: PB[3..0]

- bit[7:4]: PA[3..0]

PAB_DIR A2 (288) Selection of the direction of each bit:

- bit[3:0]: PB[3..0] Biti = 0: set to input node

- bit[7:4]: PA[3..0] 1: set to output node

reset value = 0 hex: all bits set in INPUT mode

PCD_OUT A3 (28C) Data register used to drive:

- bit[3:0]: PD[3..0]

- bit[7:4]: PC[3..0]

if set in output direction

PCD_IN A4 (290) Data register to store value of:

- bit[3:0]: PD[3..0]

- bit[7:4]: PC[3..0]

PCD_DIR A5 (294) Selection of the direction of each bit:

- bit[3:0]: PD[3..0] Biti = 0: set to input node

- bit[7:4]: PC[3..0] 1: set to output node

reset value = 0 hex: all bits set in INPUT mode

PEF_OUT A6 (298) Data register used to drive:

- bit[3:0]: PF[3..0]

- bit[7:4]: PE[3..0]

if set in output direction

PEF_IN A7 (29C) Data register to store value of:

- bit[3:0]: PF[3..0]

- bit[7:4]: PE[3..0]

PEF_DIR A8 (2A0) Selection of the direction of each bit:

- bit[3:0]: PF[3..0] Biti = 0: set to input node

- bit[7:4]: PE[3..0] 1: set to output node

reset value = 0 hex: all bits set in INPUT mode

PGH_OUT A9 (2A4) Data register used to drive:

- bit[3:0]: PH[3..0]

- bit[7:4]: PG[3..0]

if set in output direction

PGH_IN AA (2A8) Data register to store value of:

- bit[3:0]: PH[3..0]

- bit[7:4]: PG[3..0]

PGH_DIR AB (2AC) Selection of the direction of each bit:

- bit[3:0]: PH[3..0] Biti = 0: set to input node

- bit[7:4]: PG[3..0] 1: set to output node

reset value = 0 hex: all bits set in INPUT mode

Table 32: Port Register Table

MTC-20285

Count Down Timers with

Interrupt Generation

Two timers are provided (Timer1 and

Timer2) with the following functions:

• 16-bit loadable down counters

• counts down as long as counter is

enabled (count = 1). Restarts auto-

matically at the initial value when

timer value = 0 is reached

• generates an interrupt on timeout

(whenever timer value = 0), as well

as a ‘toggling’ output signal (T1O,

T2O), toggling at each timeout

occurrence. The toggling signal can

Timers

MTC-20285 240300 [74]

Mode BASECLK = 0 BASECLK = 1

slow internal 15.36 MHz / 16 = 960 kHz 30.72 MHz / 16 = 1920 kHz

max period: 216 / 960 kHz = 68 ms max period: 216 / 1920 kHz = 34 ms

fast internal 15.36 MHz / 4 = 3840 kHz 30.72 MHz / 4 = 7680 kHz

max period: 216 / 3840 kHz = 17 ms max period: 216 / 960 kHz = 8.5 ms

Table 33: Count Down Timer Modes

be brought outside via the Parallel

I/O port A (see section 3.12)

• can be read on-the-fly (no need to

put count = 0 to read)

• by default, the counters operate

on ‘internal count mode’, counting

based on one of two possible fixed

counting frequencies. See Table 33.

• can be made to count external

positive-edge events of an input

signal (T1I, T2I) applied on the

parallel I/O port A (see section

3.12). The ‘external count mode’ is

Furthermore, Timer1 has an extra

capture register to store the actual

value of the timer register whenever

capturing is enabled (capEn = 1) and

the capture control signal (capSig)

generated by a hardware event

becomes true.

The following sources can be used to

generate the capSig signal:

• the D-CI activity detection signal

(detection of change in CI bit

values)

• the port PA activity detection signal

(detection of change on bits, set in

input mode)

• the External interrupt input signal

(either pos/neg edge or high/low

level detection)

• the port PB activity detection signal

(detection of change on bits, set in

input mode)

These four signals correspond to

the unmasked interrupt status bit as

described in sections 3.9 and 3.2.6.

The capturing is done only once,

for the first event occurring since the

capEn bit was set by software. When

captured the bit is reset by the hard-

ware. This prevents the hardware

from capturing twice before reading /

re-enabling the capturing registers. In

addition, the bit gets an acknowledge-

ment function, reading the bit value

checks whether a capture event

occurred or not.

Timer Values and Pre-scaler

Function

A pre-scaler function is added in

MTC-20285 due to the hardware

implementation, some care has to be

taken in order to avoid dependency

of timer's value with the clock ASB. If

you follow the pre-scaler constraints

defined in Table 34, then the timer

values will be independent of the

ASB clock.

The timer value stays dependent of the

APB clock (as in the MTC-20280).

used as soon as the CHIP_CFG bit

corresponding to T1I or T2I is set.

Two variants exist:

- slow external mode (fast = 0):

the counter is decreased every

fourth time a pos-edge is detected

- fast external mode (fast = 1):

the counter is decreased every

single time a pos-edge is detected

• can be reset on-the-fly

• can be stopped on-the-fly

MTC-20285

MTC-20285 240300 [75]

Clock APB Full Speed (CLK_3[3:2] = 0)

BASECLK = 0 BASECLK = 1

Pre-scaler clock ASB slow fast slow fast

reg. TI_PRE constraint

00 CLK_2[3:0] < 16 granularity: 2083 ns granularity: 2083 ns granularity: 1041 ns granularity: 1041 ns

01 CLK_2[3:0] < 8 granularity: 1041 ns granularity: 1041 ns granularity: 521 ns granularity: 521 ns

10 CLK_2[3:0] < 4 granularity: 521 ns granularity: 521 ns granularity: 260 ns granularity: 260 ns

11 CLK_2[3:0] = 0 granularity: 260 ns granularity: 260 ns granularity: 130 ns granularity: 130 ns

Clock APB (CLK_3[3:2] = 0)

count rate: 960 kHz count rate: 3840 kHz count rate: 1920 kHz count rate: 7680 kHz

max period: 68 ms max period: 17 ms max period: 34 ms max period: 8.5 ms

Clock APB / 4 (CLK_3[3:2] = 1)

count rate: 240 kHz count rate: 960 kHz count rate: 480 kHz count rate: 1920 kHz

max period: 273 ms max period: 68 ms max period: 136 ms max period: 34 ms

Clock APB / 8 (CLK_3[3:2] = 2)

count rate: 120 kHz count rate: 480 kHz count rate: 240 kHz count rate: 960 kHz

max period: 546 ms max period: 136 ms max period: 273 ms max period: 68 ms

Clock APB / 32 (CLK_3[3:2] = 3)

count rate: 30 kHz count rate: 120 kHz count rate: 60 kHz count rate: 240 kHz

max period: 2.2 s max period: 546 ms max period: 1.1 ms max period: 273 ms

Table 34: Clock Timer Restraints

After reset, the counters are initialized

as follows:

• Timer CMD register (TI_CMD) =

0x00 (no-count, not-init, capturing

disabled, slow internal mode)

• (Internal mode selected because

at reset CHIP_CFG[6,4] = 0)

• Timer registers (TI_1L, TI_1M, TI_2L,

TI_2M) = 0xFF

• Timer1 capture registers (TI_C1L,

TI_C1M) = 0xFF

• Pre-scaler (TI_PRE) = 0x0

MTC-20285

MTC-20285 240300 [76]

Name Address (byte) Function

TI_1L C0 (300) Timer 1 counter 16-bits (TI_1: LSB and MSB)

TI_1M C1 (304) Read: counter value

Write: initial value

TI_2L C2 (308) Timer 2 counter 16-bits (TI_2: LSB and MSB)

TI_2M C3 (30C) Read: counter value

Write: initial value

TI_CMD C4 (310) Timers command register:

Timer 1:

- bit[0]: count (= 1:counting; = 0:not counting)

- bit[1]: init (set to 1 to re-initialize; self-clearing bit)

- bit[2]: fast (= 1: fast clock = Xtal/4; = 0: slow clock = Xtal/16)

- bit[3]: capEn (= 1:capture enabled; = 0:disabled)

(cleared by HW when captured)

Timer 2:

- bit[4]: count (= 1:counting; = 0:not counting)

- bit[5]: init (set to 1 to re-initialize; self-clearing bit)

- bit[6]: fast (= 1: fast clock = Xtal/4; = 0: slow clock = Xtal/16)

- bit[7]: / (not used)

TI_C1L C5 (314) Timer 1 capture registers: 16 bits (LSB and MSB)

TI_C1M C6 (318) Read only

TI_CSEL C7 (31C) capture source selection register:

- 00: CI change (default)

- 01: external interrupt IT

- 10: PB input port change

- 11: PA input port change

TI_PRE CA (328) bit[1:0]: Timer pre-scaler

Table 35: Timer Register Table

MTC-20285

A watchdog timer, working on the APB

clock is provided. APB clock frequency

is selectable using CLK_3[3:2]. It is a

countdown timer, which is by default

disabled after power-up reset of the

MTC-20285. It can be disabled,

enabled and kicked under software

control by writing a specific ‘magic’

word value to the WD_MAGIC

watchdog FSM, of which the state can

be monitored by reading the state bit

values in the WD_SC status/control

Writing a single sequence of 3 words

to the WD_MAGIC register ‘magic1-

word’, ‘magic2-word’ and ‘magic3-

word’ causes disabling. This can

avoid accidental unwanted disabling

of the timer. If the sequence is inter-

rupted by writing any other value to the

WD_MAGIC register, the sequence

must be restarted from the beginning

in order to disable the watchdog.

However, the sequence may be

interleaved without harm by write

commands to other registers or read

commands to any register, including

WD_MAGIC.

A single write of any value to the

WD_MAGIC register causes enabling.

Once enabled, the watchdog can be

kicked by writing the specific kick-

value to WD_MAGIC. Kicking the

watchdog performs a re-initialization

at one of 4 possible values. This

prevents the timer to reach the zero

value and generate a reset for the

ARM. The initialization value is

selected by the 2 control bits in the

WD_SC register.

The output of the watchdog timer

controls the active-low open-drain

WDALARM output of the chip. This

signal is made externally available

for system reset. It can be externally

connected to the NRST input of

the ARM processor that resets all

functional MTC-20285 blocks.

It goes active low, as soon as the

timer reaches the zero value, and

stays low for a certain period after

which it becomes inactive high again.

Watchdog Timer

MTC-20285 240300 [77]

Init

Count

Unlock1

Unlock2

Disable

Write(X)

Write(Magic1)

Write(Magic2)

Write(Magic3)

reset

Write(Kick)

Write(not Magic3)

Write(not Magic2)

Write(not-Magic1,

not-kick)

Fig.26 Watchdog State Machine

BASECLK = 0 BASECLK = 1

clock APB / 1 (CLK_3[3:2] = 0) 4.2 ms 2.1 ms

clock APB / 4 (CLK_3[3:2] = 0) 17 ms 8.5 ms

clock APB / 8 (CLK_3[3:2] = 0) 34 ms 17 ms

clock APB / 32 (CLK_3[3:2] = 0) 136 ms 68 ms

Watchdog reset length:

216 * APB_period

MTC-20285

Watchdog Time out

Counting Mechanism

The Watchdog time-out value selec-

tion is done using WD_SC[7..4,1..0].

A 26-bit counter, clocked on the APB

clock is counting from its initial value

down to 0. The initial value of this

counter is composed as follows:

MTC-20285 240300 [78]

BASECLK = 0 BASECLK = 1

Clock APB / 1 (CLK_3[3:2] = 0) 3840 kHz 7680 kHz

Clock APB / 4 (CLK_3[3:2] = 0) 960 kHz 1920 kHz

Clock APB / 8 (CLK_3[3:2] = 0) 480 kHz 960 kHz

Clock APB / 32 (CLK_3[3:2] = 0) 120 kHz 240 kHz

Table 36: Watchdog Count Down Frequency

Example of time-out value calculation

BASECLK = 1

CLK_3[3:2] = ‘01’

WD_SC[1:0] = ‘11’

WD_SC[7:4] = ‘0011’

Clock frequency = 1920 kHz

Initial Counter value [25:0] = ‘0011_1111_000000000000000000’ = 0x0FC0000 = 16515072

initialValue 16515072

timeOut = ——————————— = ————— = 8.6 sec

downCountingFrequency 1920e3

Name Address (byte) Function

WD_SC [7..0] C8 (320) Watchdog Status and Control register (8-bit)

bit[7..4,1..0]: Initial value selection

bit[3..2]: State of watchdog FSM (R only)

- 00: init and count

- 01: unlock1

- 10: unlock2

- 11: disable (default)

WD_MAGIC C9 (324) Watchdog Magic word register (8-bit), gives a command to the watchdog

by writing a specific value:

- value = DC: Kick command

- value = A5: Magic1-word command

- value = 5A: Magic2-word command

- value = AF: Magic3-word command

Table 37: Watchdog Register Table

• Initial Counter[17:0]

= all ‘0’s (always)

• Initial Counter[21:18]

= ‘0111’ if WD_SC[1:0] = ‘00’

= ‘1001’ if WD_SC[1:0] = ‘01’

= ‘1101’ if WD_SC[1:0] = ‘10’

= ‘1111’ if WD_SC[1:0] = ‘11’

• Initial Counter[25:22]

= WD_SC[7:4]

As the watchdog timer is clocked

on the APB clock, its time-out value

is dependent on the APB clock

frequency.

MTC-20285

MTC-20285 240300 [79]

Hardware Identification Code

The MTC-20285 contains a read-only

code. Writing to this register will

cause no harm.

The ID code corresponds to the next 8-

bits:

FFF RR SSS with:

FFF = product family code (010 for

MTC-20285 = ‘20285’)

RR = revision code

SSS = mask set version (000:first,

001:second, etc)

The following ID codes are for MTC-

20285 variants:

MTC-20285 version

HW identification code = 0x<MN>

MTC-20285.NAA

0x 010 00 000 = 0x40

Name Address (byte) Function

CHIP_ID 00 (000) Returns the chip identification code 0x<MN>

(Hardware version dependent)

Table 38: Chip Register Table

MTC-20285

Many of the on-chip functions use

device pins, which can be made

available as general-purpose parallel

I/O if the particular feature is not

used. The CHIP_CFG registers allow

software configuration of these various

hardware features, as indicated in

the table.

Chip_CFG Registers

MTC-20285 240300 [80]

Name Address (byte) Access Width Reset Function

(bits) (hex)

♦CHIP_CFG 01(004) RW 8 06 bit[0] = 1: Configures PB[3..0] in

PB2Uart mode

bit[2,1] = external interrupt (IT) type

- 00: neg-edge 01:pos-edge

- 10: low-level 11:high-level (default)

bit[3] = 1: use PA0 as Timer output T2O

bit[4] = 1: use PA1 as Timer input T2I

bit[5] = 1: use PA2 as Timer output T1O

bit[6] = 1: use PA3 as Timer input T1I

(see also CHIP_CFG2[2])

bit[7] = 1: swap addresses for external

memory block 0 and 3

• CHIP_CFG2 07(01C) RW 3 00 bit[0] = Main UART DTE/DCE Mode

- 0 = DTE

- 1 = DCE

bit[1] = Pio / UART2 Mode

- 0 = Pio on ports PC

- 1 = UART2 on ports PC

bit[2] = PA/RXD multiplexing

- 0 = PA

- 1 = RXD

Table 39: CHIP_CFG Registers

MTC-20285

Next follows a summary of the com-

plete memory map of the parameters

discussed in the previous sections. All

parameters related to the same hard-

ware unit, are put together in registers

on the same ‘page’.

NOTES:

• Addresses, which are not listed in

section 3.17.1 must not be used,

because they are allocated for

possible further (compatible)

upgrades/extension of the memory

map for products to be derived from

the MTC-20285.

• the first column indicates the com-

patibility with the MTC-20280 chip

(MTC-20280)

( ): fully compatible

(•): new register

(♦): register with extended function

(♣): software compatibility must be

verified

• The APB address space is limited to

11-bits, corresponding to the ARM

address bits 12 down to 2 (word

aligned addresses), located in the

7th block of the ARM address space

(see this section). The data is of type

‘byte’ and is LSB aligned onto the

data bus.

• The following table lists the address

of each register as a word address

(4 bytes per word) and for clarity,

as a byte-address.

APB Address

bit[10..4]: page selection

0x00: chip configuration

0x01: HDLC1

0x02: HDLC2

0x03: HDLC3

0x04: HDLC ext

0x05: UART1

0x06: GCI router

0x07: GCI router

0x08: GCI router

0x09: clock, Interrupt

0x0A: parallel I/O’s

0x0B: GCI router (ext’)

0x0C: Timers and Watchdog

0x0D: HDLC4

0x0E: HDLC5

0x0F: UART2

0x10: USB channel 0

0x11: USB channel 1

0x12: USB channel 2

0x13: USB channel 3

0x14: USB channel 4

0x15: USB channel 5

0x16: USB channel 6

0x17: USB device

0x18: /

0x19: Interrupt (ext')

0x20 to 0x3F: /

0x40 to 0x4F: USB memory (1K bytes)

MTC-20285 240300 [81]

MTC-20285

MTC-20285 240300 [82]

Name Address Access Width Reset Function

(byte) (bits) (hex)

MTC-20285 Configuration

♣CHIP_ID 00 (000) R 8 <MN> Returns the chip identification code =

0x<MN>

(HW version dependent)

♦CHIP_CFG 01 (004) RW 8 06 bit[0 ]= 1: Configures PB[3..0] in PB2Uart

mode

bit[2,1] = external interrupt (IT) type

- 00: neg-edge 01:pos-edge

- 10: low-level 11:high-level (default)

bit[3] = 1: use PA0 as Timer output T2O

bit[4] = 1: use PA1 as Timer input T2I

bit[5] = 1: use PA2 as Timer output T1O

bit[6] = 1: use PA3 as Timer input T1I

(see also CHIP_CFG2[2])

bit[7] = 1: swap addresses for external

memory block 0 and 3

• CHIP_CFG2 07 (01C) RW 3 00 bit[0] = Main UART DTE/DCE Mode

- 0 = DTE

- 1 = DCE

bit[1] = Pio / UART2 Mode

- 0 = Pio on ports PC

- 1 = UART2 on ports PC

bit[2] = PA/RXD multiplexing

- 0 = PA

- 1 = RXD

CHIP_GCI_L 02 (080) R 8 00 Data rate detected on the master GCI

interface

(data bits per frame).

LSB bits of data rate

CHIP_GCI_M 03 (0C0) R 8 00 MSB bits of data rate

CHIP_WTC1 04 (100) RW 8 FF Wait cycles for external memory blocks

bit[3:0]: memory block 0

bit[7:4]: memory block 1

CHIP_WTC2 05 (140) RW 8 FF bit[3:0]: memory block 2

bit[7:4]: memory block 3

CHIP_WTC3 06 (180) RW 8 FF bit[3:0]: memory block 4

bit[7:4]: memory block 5

HDLC Formatters

HD1_MODE 10 (040) RW 8 00 HDLC mode register

HD1_EMODE 11 (044) RW 8 00 HDLC Extended mode register

HD1_CMD 12 (048) W 8 00 HDLC Command register

HD1_SSTAT 13 (04C) R 8 00 HDLC Serial Status register

HD1_FSTAT 14 (050) R 8 32 FIFO Status register

HD1_ISTAT 15 (054) R 8 00 Interrupt Status Register

HD1_ISRV 16 (058) R 8 00 Interrupt Service Request Register

HD1_IMASK 17 (05C) RW 8 00 Interrupt Mask Register

HD1_FIFO 18 (060) RW 8 00 Rx/Tx FIFO data register

Table 40: Address Table

MTC-20285

MTC-20285 240300 [83]

HD1_RFBC 19 (064) R 8 00 Receive Frame Byte Count

HD1_TA1 1A (068) RW 8 00 Transmit Address 1

HD1_TA2 1B (06C) RW 8 00 Transmit Address 2

HD1_RAW1 1C (070) RW 8 00 Receive Address Wildcard 1

HD1_RAW2 1D (074) RW 8 00 Receive Address Wildcard 2

HD1_RA1 1E (078) RW 8 00 Receive Address Register 1

HD1_RA2 1F (07C) RW 8 00 Receive Address Register 2

HD2_MODE 20 (080) RW 8 00 HDLC mode register

HD2_EMODE 21 (084) RW 8 00 HDLC Extended mode register

HD2_CMD 22 (088) W 8 00 HDLC Command register

HD2_SSTAT 23 (08C) R 8 00 HDLC Serial Status register

HD2_FSTAT 24 (090) R 8 32 FIFO Status register

HD2_ISTAT 25 (094) R 8 00 Interrupt Status Register

HD2_ISRV 26 (098) R 8 00 Interrupt Service Request Register

HD2_IMASK 27 (09C) RW 8 00 Interrupt Mask Register

HD2_FIFO 28 (0A0) RW 8 00 Rx/Tx FIFO data register

HD2_RFBC 29 (0A4) R 8 00 Receive Frame Byte Count

HD2_TA1 2A (0A8) RW 8 00 Transmit Address 1

HD2_TA2 2B (0AC) RW 8 00 Transmit Address 2

HD2_RAW1 2C (0B0) RW 8 00 Receive Address Wildcard 1

HD2_RAW2 2D (0B4) RW 8 00 Receive Address Wildcard 2

HD2_RA1 2E (0B8) RW 8 00 Receive Address Register 1

HD2_RA2 2F (0BC) RW 8 00 Receive Address Register 2

HD3_MODE 30 (0C0) RW 8 00 HDLC mode register

HD3_EMODE 31 (0C4) RW 8 00 HDLC Extended mode register

HD3_CMD 32 (0C8) W 8 00 HDLC Command register

HD3_SSTAT 33 (0CC) R 8 00 HDLC Serial Status register

HD3_FSTAT 34 (0D0) R 8 32 FIFO Status register

HD3_ISTAT 35 (0D4) R 8 00 Interrupt Status Register

HD3_ISRV 36 (0D8) R 8 00 Interrupt Service Request Register

HD3_IMASK 37 (0DC) RW 8 00 Interrupt Mask Register

HD3_FIFO 38 (0E0) RW 8 00 Rx/Tx FIFO data register

HD3_RFBC 39 (0E4) R 8 00 Receive Frame Byte Count

HD3_TA1 3A (0E8) RW 8 00 Transmit Address 1

HD3_TA2 3B (0EC) RW 8 00 Transmit Address 2

HD3_RAW1 3C (0F0) RW 8 00 Receive Address Wildcard 1

HD3_RAW2 3D (0F4) RW 8 00 Receive Address Wildcard 2

HD3_RA1 3E (0F8) RW 8 00 Receive Address Register 1

HD3_RA2 3F (0FC) RW 8 00 Receive Address Register 2

• HD4_MODE D0 (340) RW 8 00 HDLC mode register

• HD4_EMODE D1 (344) RW 8 00 HDLC Extended mode register

• HD4_CMD D2 (348) W 8 00 HDLC Command register

• HD4_SSTAT D3 (34C) R 8 00 HDLC Serial Status register

• HD4_FSTAT D4 (350) R 8 32 FIFO Status register

• HD4_ISTAT D5 (354) R 8 00 Interrupt Status Register

• HD4_ISRV D6 (358) R 8 00 Interrupt Service Request Register

• HD4_IMASK D7 (35C) RW 8 00 Interrupt Mask Register

MTC-20285

MTC-20285 240300 [84]

• HD4_FIFO D8 (360) RW 8 00 Rx/Tx FIFO data register

• HD4_RFBC D9 (364) R 8 00 Receive Frame Byte Count

• HD4_TA1 DA (368) RW 8 00 Transmit Address 1

• HD4_TA2 DB (36C) RW 8 00 Transmit Address 2

• HD4_RAW1 DC (370) RW 8 00 Receive Address Wildcard 1

• HD4_RAW2 DD (374) RW 8 00 Receive Address Wildcard 2

• HD4_RA1 DE (378) RW 8 00 Receive Address Register 1

• HD4_RA2 DF (37C) RW 8 00 Receive Address Register 2

• HD5_MODE E0 (380) RW 8 00 HDLC mode register

• HD5_EMODE E1 (384) RW 8 00 HDLC Extended mode register

• HD5_CMD E2 (388) W 8 00 HDLC Command register

• HD5_SSTAT E3 (38C) R 8 00 HDLC Serial Status register

• HD5_FSTAT E4 (390) R 8 32 FIFO Status register

• HD5_ISTAT E5 (394) R 8 00 Interrupt Status Register

• HD5_ISRV E6 (398) R 8 00 Interrupt Service Request Register

• HD5_IMASK E7 (39C) RW 8 00 Interrupt Mask Register

• HD5_FIFO E8 (3A0) RW 8 00 Rx/Tx FIFO data register

• HD5_RFBC E9 (3A4) R 8 00 Receive Frame Byte Count

• HD5_TA1 EA (3A8) RW 8 00 Transmit Address 1

• HD5_TA2 EB (3AC) RW 8 00 Transmit Address 2

• HD5_RAW1 EC (3B0) RW 8 00 Receive Address Wildcard 1

• HD5_RAW2 ED (3B4) RW 8 00 Receive Address Wildcard 2

• HD5_RA1 EE (3B8) RW 8 00 Receive Address Register 1

• HD5_RA2 EF (3BC) RW 8 00 Receive Address Register 2

HD1_SRC 40 (100) RW 8 00 Source data:

[1:0]: line selection (0..2: U,S,A)

[4:2]: burst selection (0 … 7)

[6:5]: channel selection (0..2: B1-B2-D)

HD2_SRC 41 (104) RW 8 00 Source data:

[1:0]: line selection (0..2: U,S,A)

[4:2]: burst selection (0…7)

[6:5]: channel selection (0..2: B1-B2-D)

HD3_SRC 42 (108) RW 8 00 Source data:

[1:0]: line selection (0..2: U,S,A)

[4:2]: burst selection (0…7)

[6:5]: channel selection (0..2: B1-B2-D)

• HD4_SRC 47 (10C) RW 8 00 Source data:

[1:0]: line selection (0..2: U,S,A)

[4:2]: burst selection (0…7)

[6:5]: channel selection (0..2: B1-B2-D)

• HD5_SRC 48 (110) RW 8 00 Source data:

[1:0]: line selection (0..2: U,S,A)

[4:2]: burst selection (0…7)

[6:5]: channel selection (0..2: B1-B2-D)

♦HD_BREV 43 (114) RW 8 0 Bit-reverse data byte (LSB <-> MSB)

read/written from/to the HDLC FIFO’s

bit[0] = 1: bit-reverse data for

HDLC 1 formatter

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bit[1] = 1: bit-reverse data for

HDLC 2 formatter

bit[2] = 1: bit-reverse data for

HDLC 3 formatter

bit[3] = 1: bit-reverse data for

HDLC 4 formatter

bit[4] = 1: bit reversed per block of 2 for

D channel transmission through HDLC1

in transparent mode

bit[5] = 1: bit reversed per block of 2 for

D channel transmission through HDLC2

in transparent mode

bit[6] = 1: bit reversed per block of 2 for

D channel transmission through HDLC3

in transparent mode

bit[7] = 1: bit reversed per block of 2 for

D channel transmission through HDLC4

in transparent mode

HD1_TX 44 (118) R 8 X HDLC packet ready to be transmitted

in the current frame

HD2_TX 45 (11C) R 8 X HDLC packet ready to be transmitted

in the current frame

HD3_TX 46 (120) R 8 X HDLC packet ready to be transmitted

in the current frame

• HD4_TX 49 (124) R 8 X HDLC packet ready to be transmitted

in the current frame

• HD5_TX 4A (128) R 8 X HDLC packet ready to be transmitted

in the current frame

USB Interface

• USB_DCMD 170 (1C0) RW 4 04 USB Device Command register

• USB_DSTAT 171 (1C4) R 4 00 USB Device Status register

• USB_ALTSET 172 (1C8) R 6 00 USB Alternate Settings for Inferface1,2,3

• USB_DIMASK 174 (1D0) RW 4 00 USB Device Interrupt Mask register

• USB0_CMD 100 (400) RW 5 00 USB Command register

• USB0_FSTAT 101 (404) R 8 32 USB FIFO Status register

• USB0_ISTAT 102 (408) R 8 00 USB Interrupt Status Register

• USB0_ISRV 103 (40C) R 8 00 USB Interrupt Service Request Register

• USB0_IMASK 104 (410) RW 8 00 USB Interrupt Mask Register

• USB0_FIFO 105 (414) RW 8 XX USB Rx/Tx FIFO data register

• USB1_CMD 110 (440) RW 8 00 USB Command register

• USB1_FSTAT 111 (444) R 8 32 USB FIFO Status register

• USB1_ISTAT 112 (448) R 8 00 USB Interrupt Status Register

• USB1_ISRV 113 (44C) R 8 00 USB Interrupt Service Request Register

• USB1_IMASK 114 (450) RW 8 00 USB Interrupt Mask Register

• USB1_FIFO 115 (454) RW 8 XX USB Rx/Tx FIFO data register

• USB1_SET 116 (458) RW 3 01 USB FIFO Settings Register

• USB2_CMD 120 (480) RW 8 00 USB Command register

• USB2_FSTAT 121 (484) R 8 32 USB FIFO Status register

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• USB2_ISTAT 122 (488) R 8 00 USB Interrupt Status Register

• USB2_ISRV 123 (48C) R 8 00 USB Interrupt Service Request Register

• USB2_IMASK 124 (490) RW 8 00 USB Interrupt Mask Register

• USB2_FIFO 125 (494) RW 8 XX USB Rx/Tx FIFO data register

• USB_SET 126 (498) RW 3 01 USB FIFO Settings Register

• USB3_CMD 130 (4C0) RW 8 00 USB Command register

• USB3_FSTAT 131 (4C4) R 8 32 USB FIFO Status register

• USB3_ISTAT 132 (4C8) R 8 00 USB Interrupt Status Register

• USB3_ISRV 133 (4CC) R 8 00 USB Interrupt Service Request Register

• USB3_IMASK 134 (4D0) RW 8 00 USB Interrupt Mask Register

• USB3_FIFO 135 (4D4) RW 8 XX USB Rx/Tx FIFO data register

• USB3_SET 136 (4D8) RW 3 01 USB FIFO Settings Register

• USB4_CMD 140 (500) RW 8 00 USB Command register

• USB4_FSTAT 141 (504) R 8 32 USB FIFO Status register

• USB4_ISTAT 142 (508) R 8 00 USB Interrupt Status Register

• USB4_ISRV 143 (50C) R 8 00 USB Interrupt Service Request Register

• USB4_IMASK 144 (510) RW 8 00 USB Interrupt Mask Register

• USB4_FIFO 145 (514) RW 8 XX USB Rx/Tx FIFO data register

• USB4_SET 146 (518) RW 3 01 USB FIFO Settings Register

• USB5_CMD 150 (540) RW 8 00 USB Command register

• USB5_FSTAT 151 (544) R 8 32 USB FIFO Status register

• USB5_ISTAT 152 (548) R 8 00 USB Interrupt Status Register

• USB5_ISRV 153 (54C) R 8 00 USB Interrupt Service Request Register

• USB5_IMASK 154 (550) RW 8 00 USB Interrupt Mask Register

• USB5_FIFO 155 (554) RW 8 XX USB Rx/Tx FIFO data register

• USB5_SET 156 (558) RW 3 01 USB FIFO Settings Register

• USB6_CMD 160 (580) RW 8 00 USB Command register

• USB6_FSTAT 161 (584) R 8 32 USB FIFO Status register

• USB6_ISTAT 162 (588) R 8 00 USB Interrupt Status Register

• USB6_ISRV 163 (58C) R 8 00 USB Interrupt Service Request Register

• USB6_IMASK 164 (590) RW 8 00 Interrupt Mask Register

• USB6_FIFO 165 (594) RW 8 XX USB Rx/Tx FIFO data register

• USB6_SET 166 (598) RW 3 01 USB FIFO Settings Register

UART1

Default register set

UART1_RBR 50 (140) R 8 00 Receiver Buffer Register

UART1_THR 50 (140) W 8 00 Transmitter Holding Register

UART1_IER 51 (144) RW 8 00 Interrupt Enable Register

UART1_IIR 52 (148) R 8 00 Interrupt Identification Register

♦UART1_FCR 52 (148) W 8 00 FIFO Control Register

UART1_LCR 53 (14C) RW 8 00 Line Control Register

UART1_MCR 54 (150) RW 8 00 Modem Control Register

UART1_LSR 55 (154) R 8 60 Line Status Register

UART1_MSR 56 (158) RW 8 00 Modem Status Register

UART1_SCR 57 (15C) RW 8 00 Scratch Register

UART1_DLL 50 (140) RW 8 00 Divisor Latch Register (LSB)

UART1_DLM 51 (144) RW 8 00 Divisor Latch Register (MSB)

UART1_EFR 52 (148) RW 8 00 Enhancement Enable register

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Baud rate generator divisor register set

Selected when LCR[7] = 0x1

UART1_DLL 50 (140) RW 8 00 Divisor Latch Register (LSB)

UART1_DLM 51 (144) RW 8 00 Divisor Latch Register (MSB)

Enhanced register set

Selected when LCR = 0xBF

• UART1_EFR 52 (148) RW 8 00 Extended Function Register

UART2

Default register set

• UART2_RBR F0 (3C0) R 8 00 Receiver Buffer Register

• UART2_THR F0 (3C0) W 8 00 Transmitter Holding Register

• UART2_IER F1 (3C4) RW 8 00 Interrupt Enable Register

• UART2_IIR F2 (3C8) R 8 00 Interrupt Identification Register

• UART2_FCR F2 (3C8) W 8 00 FIFO Control Register

• UART2_LCR F3 (3CC) RW 8 00 Line Control Register

• UART2_MCR F4 (3D0) RW 8 00 Modem Control Register

• UART2_LSR F5 (3D4) R 8 60 Line Status Register

• UART2_MSR F6 (3D8) RW 8 00 Modem Status Register

• UART2_SCR F7 (3DC) RW 8 00 Scratch Register

Baud rate generator divisor register set

Selected when LCR[7] = 0x1

• UART2_DLL 50 (140) RW 8 00 Divisor Latch Register (LSB)

• UART2_DLM 51 (144) RW 8 00 Divisor Latch Register (MSB)

GCI Router

Ui_B1_CPU 60 (180) RW 8 X CPU value for the B1 upstream Ui channel

Ui_B2_CPU 61 (184) RW 8 X CPU value for the B2 upstream Ui channel

Ui_M_CPU 62 (188) RW 8 X CPU value for the M upstream Ui channel

Ui_E_CPU 63 (18C) RW 8 X CPU value for the C/I byte upstream

Ui channel

bit[7:6] = D bits

bit[5:2] = CI bits

bit[1:0] = AE bits

Si_B1_CPU 64 (190) RW 8 X CPU value for the B1 downstream Si channel

Si_B2_CPU 65 (194) RW 8 X CPU value for the B2 downstream Si channel

Si_M_CPU 66 (198) RW 8 X CPU value for the M downstream Si channel

Si_E_CPU 67 (19C) RW 8 X CPU value for the C/I byte downstream

Si channel

bit[7:6] = D bits

bit[5:2] = CI bits

bit[1:0] = AE bits

Ai_B1_CPU 68 (1A0) RW 8 X CPU value for the B1 downstream Ai channel

Ai_B2_CPU 69 (1A4) RW 8 X CPU value for the B2 downstream Ai channel

Ai_M_CPU 6A (1A8) RW 8 X CPU value for the M downstream Ai channel

Ai_E_CPU 6B (1AC) RW 8 X CPU value for the C/I byte downstream

Ai channel

bit[7:6] = D bits

bit[5:2] = CI bits

bit[1:0] = AE bits

Ui_B1_RX 6C (1B0) R 8 X B1 channel read from the Ui downstream

GCI frame

Ui_B2_RX 6D (1B4) R 8 X B2 channel read from the Ui downstream

GCI frame

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Ui_M_RX 6E (1B8) R 8 X M channel read from the Ui downstream

GCI frame

Ui_E_RX 6F (1BC) R 8 X [D,CI,AE] channel read from the Ui down

GCI frame

Si_B1_RX 70 (1C0) R 8 X B1 channel read from the Si upstream

GCI frame

Si_B2_RX 71 (1C4) R 8 X B2 channel read from the Si upstream

GCI frame

Si_M_RX 72 (1C8) R 8 X M channel read from the Si upstream

GCI frame

Si_E_RX 73 (1CC) R 8 X [D,CI,AE] channel read from the S up

GCI frame

Ai_B1_RX 74 (1D0) R 8 X B1 channel read from the Ai upstream

GCI frame

Ai_B2_RX 75 (1D4) R 8 X B2 channel read from the Ai upstream

GCI frame

Ai_M_RX 76 (1D8) R 8 X M channel read from the Ai upstream

GCI frame

Ai_E_RX 77 (1DC) R 8 X [D,CI,AE] channel read from the Ai

upstream GCI frame

GCI_CPU_RX 78 (1E0) W 8 0 Specify the burst targeted by the

microprocessor

CPU registers access

Rx registers access

bit[1:0] = target line U-S-A

bit[4:2] = CPU target burst

bit[7:5] = Rx target burst

GCI_ITU 79 (1E4) RW 8 00 bit[i]: CI activity detected on U, burst i

- Read bit[I] = 1: activity detection;

- Write bit[I] = 1: interrupt cleared

GCI_ITS 7A (1E8) RW 8 00 bit[i]: CI activity detected on S, burst i

GCI_ITA 7B (1EC) RW 8 00 bit[i]: CI activity detected on A, burst i

GCI_MSKU 7C (1F0) RW 8 FF bit[i] = 1: mask CI activity detected

on U, burst i

GCI_MSKS 7D (1F4) RW 8 FF bit[i] = 1: mask CI activity detected

on S, burst i

GCI_MSKA 7E (1F8) RW 8 FF bit[i] = 1: mask CI activity detected

on A, burst i

• GCI_MSKUD B8 (2E0) RW 8 00 bit[i] = 1: mask D bits activity detected

on U, burst i

• GCI_MSKSD B9 (2E4) RW 8 00 bit[i] = 1: mask D bits activity detected

on S, burst i

• GCI_MSKAD BA (2E8) RW 8 00 bit[i] = 1: mask D bits activity detected

on A, burst i

• GCI_PULL BB (2EC) RW 6 00 GCI asynchronous pull-up / pull-down

GCI_SRC_BUR 7F (1FC) RW 3 X Target burst selection for reading _SRC

registers

♦U_B1_SRC 80 (200) RW 8 X Source control register for target U_B1

upstream:

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[7:5] source burst

[4:3] source line

[2:0] target burst

♦U_B2_SRC 81 (204) RW 8 X Source control register for target

U_B2 upstream

♦U_D_SRC 82 (208) RW 8 X Source control register for target

U_D upstream

♦U_CI_SRC 83 (20C) RW 8 X Source control register for target

U_CI upstream

♦U_M_SRC 84 (210) RW 8 X Source control register for target

U_M upstream

♦U_AE_SRC 85 (214) RW 8 X Source control register for target

U_AE upstream

♦S_B1_SRC 86 (218) RW 8 X Source control register for target

S_B1 downstream

♦S_B2_SRC 87 (21C) RW 8 X Source control register for target

S_B2 downstream

♦S_D_SRC 88 (220) RW 8 X Source control register for target

S_D downstream

♦S_CI_SRC 89 (224) RW 8 X Source control register for target

S_CI downstream

♦S_M_SRC 8A (228) RW 8 X Source control register for target

S_M downstream

♦S_AE_SRC 8B (22C) RW 8 X Source control register for target

S_AE downstream

♦A_B1_SRC 8C (230) RW 8 X Source control register for target

A_B1 downstream

♦A_B2_SRC 8D (234) RW 8 X Source control register for target

A_B2 downstream

♦A_D_SRC 8E (238) RW 8 X Source control register for target

A_D downstream

♦A_CI_SRC 8F (23C) RW 8 X Source control register for target

A_CI downstream

♦A_M_SRC B0 (2C0) RW 8 X Source control register for target

A_M downstream

♦A_AE_SRC B1 (2C4) RW 8 X Source control register for target A_AE

downstream

U_B1_SWP B2 (2C8) RW 8 X bit[i] = swap / no swap for B1 channel

on U burst i

U_B2_SWP B3 (2CC) RW 8 X bit[i] = swap / no swap for B2 channel

on U burst i

S_B1_SWP B4 (2D0) RW 8 X bit[i] = swap / no swap for B1 channel

on S burst i

S_B2_SWP B5 (2D4) RW 8 X bit[i] = swap / no swap for B2 channel

on S burst i

A_B1_SWP B6 (2D8) RW 8 X bit[i] = swap / no swap for B1 channel

on A burst i

A_B2_SWP B7 (2DC) RW 8 X bit[i] = swap / no swap for B2 channel

on A burst i

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Clock Generation

CLK_GCI 90 (240) RW 8 00 bit[5:0]: GCI DCL clock selection per

interface U,S,A:

bit[1:0] = for the U GCI router

bit[3:2] = for the S GCI router

bit[5:4] = for the A GCI router

- 0 = non-active (default at reset)

- 1 = master: dclMstr / fscMstr

- 2 = 512k: dcl512 / fsc512

- 3 = 4096k: dcl4096 / fsc4096

bit[7:6]: GCI Master FSC selection (fscMstr)

- 0 = Xtal (default at reset)

- 1 = U

- 2 = S

- 3 = A

CLK_1 91 (244) RW 4 LSB 00 Parameters for CKOUT:

W 4 MSB bits [7..4]: Disabled if equal to ‘1001’

bits [3..0]: Freq. Division par. CLK_1

for CKOUT

CLK_2 92 (248) RW 8 00 Parameters for ARM Clock:

bits [7..4]: Disabled if equal to ‘1001’

bits [3..0]: Freq. Division par. CLK_2 for

ARM clock

CLK_3 93 (24C) RW 5 10 bit[0]: DPLL status (read only)

0 = internal GCI clocks not synchronized

with the external reference; DPLL is tracking

1 = internal GCI clocks synchronized

bit[1]: Main UART clock disable

(default = 0 = enabled)

bit[3:2]: APB clock division factor

- 0 = Xtal / 4 (max. speed)

- 1 = Xtal / 8

- 2 = Xtal / 16

- 3 = Xtal / 32

bit[4]: AUX UART clock disable

(default = 1= disabled)

Interrupt

IRQ1_ST 94 (250) R 8 00 1st NFIQ Interrupt status after mask

IRQ1_STR 95 (254) R 8 00 1st NFIQ Interrupt status without mask

IRQ1_EN 96 (258) R 8 00 1st NFIQ Interrupt mask to be used

IRQ1_ENSET 97 (25C) W 8 00 1st NFIQ Set maskbit control input register

IRQ1_ENCLR 98 (260) W 8 00 1st NFIQ Clear maskbit control input register

IRQ1_ACK 99 (264) W 8 00 1st NFIQ Clear interrupt status register

IRQ2_ST 9A (268) R 8 00 1st NIRQ Interrupt status after mask

IRQ2_STR 9B (26C) R 8 00 1st NIRQ Interrupt status without mask

IRQ2_EN 9C (270) R 8 00 1st NIRQ Interrupt mask to be used

IRQ2_ENSET 9D (274) W 8 00 1st NIRQ Set maskbit control input register

IRQ2_ENCLR 9E (278) W 8 00 1st NIRQ Clear maskbit control input register

IRQ2_ACK 9F (27C) W 8 00 1st NIRQ Clear interrupt status register

• IRQ3_ST 194 (650) R 8 00 2nd NFIQ Interrupt status after mask

• IRQ3_STR 195 (654) R 8 00 2nd NFIQ Interrupt status without mask

• IRQ3_EN 196 (658) R 8 00 2nd NFIQ Interrupt mask to be used

• IRQ3_ENSET 197 (65C) W 8 00 2nd NFIQ Set maskbit control input register

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• IRQ3_ENCLR 198 (660) W 8 00 2nd NFIQ Clear maskbit control input register

• IRQ3_ACK 199 (664) W 8 00 2nd NFIQ Clear interrupt status register

• IRQ4_ST 19A (668) R 8 00 2nd NIRQ Interrupt status after mask

• IRQ4_STR 19B (66C) R 8 00 2nd NIRQ Interrupt status without mask

• IRQ4_EN 19C (670) R 8 00 2nd NIRQ Interrupt mask to be used

• IRQ4_ENSET 19D (674) W 8 00 2nd NIRQ Set maskbit control input register

• IRQ4_ENCLR 19E (678) W 8 00 2nd NIRQ Clear maskbit control input register

• IRQ4_ACK 19F (67C) W 8 00 2nd NIRQ Clear interrupt status register

Parallel I/O

PAB_OUT A0 (280) RW 8 00 bit[7..4]: PA output data register

bit[3:0]: PB output data register

PAB_IN A1 (284) R 8 00 bit[7..4]: PA input data register

bit[3:0]: PB input data register

PAB_DIR A2 (288) RW 8 00 bit[7..4]: PA direction control register

(0 = input)

bit[3:0]: PB direction control register

(0 = input)

PCD_OUT A3 (28C) RW 8 00 bit[7..4]: PC output data register

bit[3:0]: PD output data register

PCD_IN A4 (290) R 8 00 bit[7..4]: PC input data register

bit[3:0]: PD input data register

PCD_DIR A5 (294) RW 8 00 bit[7..4]: PC direction control register

(0 = input)

bit[3:0]: PD direction control register

(0 = input)

PEF_OUT A6 (298) RW 8 00 bit[7..4]: PE output data register

bit[3:0]: PF output data register

PEF_IN A7 (29C) R 8 00 bit[7..4]: PE input data register

bit[3:0]: PF input data register

PEF_DIR A8 (2A0) RW 8 00 bit[7..4]: PE direction control register

(0 = input)

bit[3:0]: PF direction control register

(0 = input)

• PGH_OUT A9 (2A4) RW 8 00 bit[7..4]: PG output data register

bit[3:0]: PH output data register

• PGH_IN AA (2A8) R 8 00 bit[7..4]: PG input data register

bit[3:0]: PH input data register

• PGH_DIR AB (2AC) RW 8 00 bit[7..4]: PG direction control register

(0 = input)

bit[3:0]: PH direction control register

(0 = input)

GCI Router ext.

See GCI B0-BA See GCI Router section

Router (2C0-2E8)

Timers and Watchdog

TI_1L C0 (300) RW 8 FF timer 1 LSB

R: counter value

W: initial value

TI_1M C1 (304) RW 8 FF timer 1 MSB

R: counter value

W: initial value

TI_2L C2 (308) RW 8 FF timer 2 LSB

R: counter value

W: initial value

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TI_2M C3 (30C) RW 8 FF timer 2 MSB

R: counter value

W: initial value

TI_CMD C4 (310) RW 8 00 Timer command register:

Timer 1:

bit[0]: count

(= 1:counting; = 0:not counting)

bit[1]: init

(set to 1 to re-initialize; self-clearing bit)

bit[2]: fast

(= 1: fast clock = Xtal/4; = 0: slow clock

= Xtal/16)

bit[3]: capEn

(= 1:capture enabled; = 0:disabled)

(cleared by HW when captured)

Timer 2:

bit[4]: count

(= 1:counting; = 0:not counting)

bit[5]: init

(set to 1 to re-initialize; self-clearing bit)

bit[6]: fast

(= 1: fast clock = Xtal/4; = 0: slow clock

= Xtal/16)

bit[7]: /

(not used)

TI_C1L C5 (314) R 8 FF timer 1 capture register: LSB

TI_C1M C6 (318) R 8 FF timer 1 capture register: MSB

TI_CSEL C7 (31C) RW 2 0 capture source selection register:

- 00: CI change (default)

- 01: external interrupt IT

- 10: PB input port change

- 11: PA input port change

WD_SC C8 (320) 8 F Watchdog status and control register

RW bit[7..4, 1..0]: Init_value selection

(See Watchdog pages)

bit[3..2]: State of watchdog FSM

(Read only)

- 00: init and count

- 01: unlock1

R - 10: unlock2

- 11: disable (default)

WD_MAGIC C9 (324) RW 8 00 Watchdog magic word register:

- value written: command issued

- value = DC: Kick command

- value = A5: Magic1-word command

- value = 5A: Magic2-word command

- value = AF: Magic3-word command

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4. POWER MANAGEMENT

To measure power dissipation, we consider next equation:

UsbUartHdlcApbClkOutASBBase PPPPPfPP++++++=

2/1

(1)

Each of the components of this equation will now be explained and measured in

the next chapters.

PBase

Configuration settings:

• We work with maximal power

supply: 3.45V.

• All Gci lines work at 512kHz.

• There is a path from the CPU

via U/B1/burst0/downstream to

S/B1/burst0/downstream and

S/B1/burst0/upstream. The rest

of the lines are idle.

• Apb clock is divided maximally.

• All clocks are stopped, USB clock

included.

• The ARM is suspended.

• !!! The ARM clock is first divided

maximally before the ARM is

suspended. This is due to the fact

that disabling the ARM doesn’t stop

the Asb clock. As a consequence,

memory access is not disabled

when the ARM is suspended.

To measure the current, we dis-

connected all the chip VccIO pins

and connected them, via an Ampere

meter, with an external power supply.

Afterwards we executed the program

”CurrentMeasLowActivity512”. This

program initialises ITCC with the

settings that are mentioned above.

The configuration results in a power

dissipation of (6.4mA) * (3.45V) =

22mW

Obsevation:

To have a view of the influence of

the Gci clock on the global power

dissipation, the same experiment was

done for a Gci clock frequency of

4.096MHz:

To measure the current, we dis-

connected all the chip VccIO pins

and connected them, via an Ampere

meter, with an external power supply.

Afterwards we executed the program

“CurrentMeasLowActivity4096”.

This configuration results in a power

dissipation of (7.7mA) * (3.45V) =

26.6mW

In the rest of the power measurement

we will proceed with a 512kHz Gci

clock.

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CLK_2 Value ARM clock (MHz) APB clock (kHz) Current (mA) P2 (mW) Linear regression2

Disabled 0 0 6.13 21.0872 20.72168526

15 1.024 32 6.6 22.704 23.35444624

14 1.097142857 34.28571429 6.7 23.048 23.5425006

12 1.28 40 6.85 23.564 24.01263649

10 1.536 48 7.07 24.3208 24.67082674

8 1.92 60 7.31 25.1464 25.65811211

6 2.56 80 7.88 27.1072 27.30358772

5 3.072 96 8.29 28.5176 28.61996821

4 3.84 120 8.94 30.7536 30.59453895

3 5.12 160 9.97 34.2968 33.88549018

2 7.68 240 12.08 41.5552 40.46739265

1 15.36 480 18.06 62.1264 60.21310004

0 30.72 960 28.64 98.5216 99.70451481

Slope 2.571056

Interception 20.72169

The term a.fApb

One waitcycle,

16 bit memory access

To measure the influence of the ASB

clockfrequency on power dissipation,

we repeat the experiment of 1.1.1 for

different ASB clock frequencies. After

initialisation, the ARM performs a

while loop.

Configuration settings:

• We work with maximal power

supply: 3.45V.

• All Gci lines work at 512kHz.

• There is a path from the CPU

via U/B1/burst0/downstream to

S/B1/burst0/downstream and

S/B1/burst0/upstream. The rest of

the lines are idle.

• Apb clock is divided maximally.

• All clocks are stopped, USB clock

included.

• The ARM frequency is manipulated

and the code is compiled in thumb

mode.

• 16 bit access for the memory.

• One waitcycle for memory access.

Execute the program “PowerFormula”

and vary the ASB clock frequency.

Measure the current:

MTC-20285

MTC-20285 240300 [95]

Zero waitcycles,

16 bit memory access

The same test is repeated with 0

waitcycles. The maximum ARM

clock frequency in this configuration

in 15MHz.

Configuration settings:

• We work with maximal power

supply: 3.45V.

• All Gci lines work at 512kHz.

• There is a path from the CPU

via U/B1/burst0/downstream

to S/B1/burst0/downstream and

S/B1/burst0/upstream. The rest

of the lines are idle.

• Apb clock is divided maximally.

• All clocks are stopped, USB clock

included.

• The ARM frequency is manipulated

and the code is compiled in thumb

mode.

• 16 bit access for the memory.

• Zero waitcycles for memory access.

Measurements:

CLK_2 Value ARM clock (MHz) APB clock (kHz) Current (mA) P2 (mW)

Disabled 0 0 6.13 21.0872

1 15.36 480 27.15 93.396

Slope 4.7076

Interception 20.72169

Zero waitcycles,

8 bit memory access

The same test is repeated with 0

waitcycles and 8 bit memory access.

The maximum ARM clock frequency

in this configuration in 15MHz.

Configuration settings:

• We work with maximal power

supply: 3.45V.

• All Gci lines work at 512kHz.

• There is a path from the CPU

via U/B1/burst0/downstream to

S/B1/burst0/downstream and

S/B1/burst0/upstream. The rest

of the lines are idle.

• Apb clock is divided maximally.

• All clocks are stopped, USB clock

included.

• The ARM frequency is manipulated

and the code is compiled in thumb

mode.

• 8 bit access for the memory.

• Zero waitcycles for memory access.

CLK_2 Value ARM clock (MHz) APB clock (kHz) Current (mA) P3 (mW) Linear regression3

Disabled 0 0 6.49 22.3256 22.04059963

15 1.024 32 7.12 24.4928 24.80565931

11 1.396363636 43.63636364 7.43 25.5592 25.81113556

8 1.92 60 7.96 27.3824 27.22508654

5 3.072 96 8.79 30.2376 30.33577869

3 5.12 160 10.44 35.9136 35.86589806

2 7.68 240 12.52 43.0688 42.77854728

1 15.36 480 18.43 63.3992 63.51649493

Slope 2.700254

Interception 22.0406

Chart

The following chart summarises the

performed measurements:

MTC-20285

MTC-20285 240300 [96]

One waitcycle,

8 bit memory access

The same test is repeated with 1

waitcycle and 8 bit memory access.

Configuration settings:

• We work with maximal power

supply: 3.45V.

• All Gci lines work at 512kHz.

• There is a path from the CPU

via U/B1/burst0/downstream to

S/B1/burst0/downstream and

S/B1/burst0/upstream. The rest

of the lines are idle.

• Apb clock is divided maximally.

• All clocks are stopped, USB clock

included.

• The ARM frequency is manipulated

and the code is compiled in thumb

mode.

• 8 bit access for the memory.

• One waitcycle for memory access.

Measurements:

CLK_2 Value ARM clock (MHz) APB clock (kHz) Current (mA) P3 (mW)

Disabled 0 0 6.49 22.3256

0 30.72 960 20.28 69.7632

Slope 1.5442

Interception 22.0406

Power management

100

110

0 5 10 15 20 25 30 35

ARM frequency (MHz)

Power (mW)

MP 16bit/1WTC

LR 16bit/1WTC

MP 8bit/0WTC

LR 8bit/0WTC

MP 16bit/0WTC

MP 8bit/1WTC

MP= measurement points

LR= linear regression on the MP's

Power Management

MTC-20285

MTC-20285 240300 [97]

Conclusion

ASBBaseASBPS

UsbUartHdlcApbClkOutASBPS

UsbUartHdlcApbClkOutASBBase

fPfP

and

PPPPPfPP

+++++=

++++++=

)(

)( 2/1

2/1

(2)

PClkOut

To measure the influence of CkOut

on power dissipation, we start from

the experiment in 1.1.2.1 and a ASB

clock frequency of 30MHz (for this

experiment we measured 98.5mW).

After enabling CkOut with a minimal

division factor, we measure a power

dissipation of 99.76mW. This is a

difference of 99.76mW - 98.5mW =

1.24mW.

PApb

To measure the influence of the APB

clock on power dissipation, we start

from the experiment in 1.1.3 (for this

experiment we measured 99.76mW).

After minimizing the division factor of

the APB clock, we measure a power

dissipation of 156.6mW. This is a

difference of 156.6mW – 99.76mW

= 56.86mW.

PHdlc

To measure the influence of the HDLC

cells on power dissipation, we start

from the experiment in 1.1.4 (for this

experiment we measured 156.6mW).

Additionally, we will simulate normal

operation on the HDLC cells by using

the same mechanism as in Error!

Reference source not found.

After building the program which you

can find in “CurrentMeasHighActivity”,

we measure a power dissipation of

168.2mW. This is a difference of

168.2mW – 156.6mW = 11.59mW.

PUart1/2

To measure the influence of the Uart

interfaces on power dissipation, we

start from the experiment in 1.1.5

(for this experiment we measured

168.2mW). Additionally, we will

simulate normal operation on the

UART interfaces by using the same

mechanism as in Error! Reference

source not found.

After building the program which you

can find in “CurrentMeasHighActivity”,

we measure a power dissipation of

171.0mW. This is a difference of

171.0mW – 168.2mW = 2.8mW.

PUsb

To measure the influence of USB on

power dissipation, we start from the

experiment in 1.1.6 (for this experiment

we measured 171mW). Additionally,

we will simulate normal operation on

the USB interfaces, performing a con-

figuration of the device by the host.

Run the program “CurrentMeasHigh-

Activity” and program the host to

configure the device. We measure

a power dissipation of 191.6mW.

This is a difference of 191.6mW –

171.0mW = 20.6mW.

MTC-20285

MTC-20285 240300 [98]

values:

PBase = 21.5mW

Pmin = PBase = 21.5mW

Pmax = 100mW -> 16bit/Thumb mode

α(mW/MHz) 16-bit access 8-bit access

0 waitcycles 4.71 2.7

1 waitcycle 2.57 1.54

MW Power save Activity

PClkOut 0 CLK_2 = 0x90 1.24 CLK_2 = 0x00

PApb ~0 CLK_3[3:2] = 3 56.86 CLK_3[3:2] = 0

PHdlc ~0 No hdlc interrupts; 11.59 Hdlc1/2/3/4/5 full activity

almost no Gci activity

PUart 0 Uarts disabled: 2.8 Uart1 and Uart2 full activity

CLK_3(bit1 = 1, bit4 = 1)

PUsb ~0 Usb disabled: 20.6 USB activity

USB_DCMD(bit3 = 1)

MTC-20285

If we consider:

then (2) becomes:

First approximation equation

MTC-20285 240300 [99]

ASB

bits

WTC

MIPS ??

=16

)1(

bits

WTC

WTCbits

and

PPPPPMIPSPP

PPPPPf

bits

WTC

UsbUartHdlcApbClkOutBase

UsbUartHdlcApbClkOutASBBase

)1(

),(#

)1(

2/1

+++++?+=

+++++??

?+=

ßa

(3)

We become a value ß that is

independent of the number of access

bits and the waitcycles. A value for ß

is estimated out of the 4 different

values of α.

UsbUartHdlcApbClkOutASBBase PPPPPf

bits

WTC

PP+++++??

?+=

2/1

)1(

ß = 5.6 mW/MIPS

100

MTC-20285

Sequence of instructions to limit power consumption

MTC-20285 240300 [100]

ITCC[CHIP_WTC1] = 0x11; -> 1 wait-cycle for memory access.

ITCC[CHIP_WTC2] = 0x11;

ITCC[CHIP_WTC3] = 0x11;

ITCC[CLK_GCI] = 0x2a; -> All Gci clocks working on 512kHz

ITCC[USB_DCMD] = 0x08; -> USB clocking disabled

ITCC[CLK_1] = 0x9f; -> CKOUT disabled

ITCC[CLK_3] = 0x1e; -> UART clocks disabled and APB clock lowest speed

ITCC[CLK_2] = 0x9f; -> ARM clock disabled and maximally divided

101

MTC-20285

MTC-20285 240300 [101]

The JTAG interface isolates and/or

accesses the ARM7TDMI core and

special purpose test registers. This

interface has multiple functions as

follows:

1. ATE test mode, puts the MTC-

20285 in a specific test mode.

2. External Boundary Scan.

3. Software debug monitoring, for

use during normal and functional

operation.

The JTAG interface is compatible

with the 1149.1 IEEE standard, as

described in the ARM7TDMI data

sheet. The TAP controller writes a

4-bit instruction in the instruction

the instruction dictionary that is

implemented, refer to the ARM7TDMI

data sheet.

The SCAN_N instruction selects a

scan chain by writing one of the

following 4-bit codes into the Scan

Chain Select Register:

5. DEBUG INTERFACE AND ATE TEST

Scan chain 4-bit code Function Usage

Chain 0: 0000 ARM Macrocell scan test ATE (ARM test)

Chain 1: 0001 Debug Demon

Chain 2: 0010 ICEbreaker programming Demon

Chain 3: 0011 External boundary scan Ext. boundary scan

Chain 4: 0100 Reserved

Chain 8: 1000 Reserved

Chain 15: 1111 MTC-20285 Test configuration register ATE

The MTC-20285 has boundary scan

cells added next to the I/O cells in

order to support external boundary

scan (chain 3) of the MTC-20285 on

PCB level. Note that the MTC-20280

did not have this support.

The IEEE 1149.1 standard requires

pull-up resistors on the JTAG ‘TDI’ and

‘TMS’ input ports. The ARM7TDMI

core does not implement any pull-up

resistors. Therefore the JTAG I/O pins

of the MTC-20285 are provided with

pull-ups (TDI, TMS, TCK) and a pull-

down for the active low reset input

(NTRST), such that no external

pull-ups / pull-downs are required

for this interface.

Also the pins may be left unconnected

(DNC) when the interface is not used

in normal operation.

102

MTC-20285

A Debug Host computer with appro-

priate protocol converter can be

connected to the JTAG interface to

control the MTC-20285 in normal

operation mode.

The JTAG interface of the MTC-20285

gives access to the ARM7TDMI core

with hardware support for debugging,

TAP controller and integrated

Icebreaker. See ARM7TDMI

documentation for more information.

Debug Monitoring

The MTC-20285 is a full digital chip,

and requires the following tests:

ATE Test

MTC-20285 240300 [102]

Test Description Test Mode

ATPG Glue logic testing 2

ARM ARM Core testing 1

BIST Integrated RAM test 1

NandTree Input level testing 3

OutLevel Output level testing 3

IddQ 2

Esd/Latchup 3

IR register = 0010 : SCAN_N JTAG instruction

DR register = 1111 : select the scan chain 15

IR register = 0000 : EXTEST JTAG instruction

DR register = 00000abc : testConfig register content

[a]: by-pass of the Reset synchronization

[b,c]: 2-bit value representing the test mode

In order to perform these tests, a

special purpose test configuration

must be downloaded via the JTAG

interface with the value shown in the

previous table. When in a specific

test-mode, the I/O pin functions are

redefined.

Note that after JTAG reset, the Test-

Conf register is reset to value 000,

corresponding to the MTC-20285

functional mode.

The following instructions need to

be sent via the JTAG to modify the

test mode:

103

MTC-20285

MTC-20285 240300 [103]

Output levels

All the output and bi-directional pins

can be forced to GND and VDD levels,

so their output levels can be checked.

Level GND:

DIA = ‘0’

DIU = ‘1’

DIS = ‘0’

Level VDD:

DIA = ‘0’

DIU = ‘0’

DIS = ‘1’

ESD and Latchup

For ESD and Latchup testing, the bi-

directional and tri-state pins are put in

tri-state.

DIA = ‘1’

DIU = don’t care

DIS = don’t care

Test Mode 1: Test Macro’s

TestConfig register = 0000101

ARM

Test vectors applied and checked

exclusively via the JTAG interface.

BIST

The 6 internal RAMS are checked via

dedicated logic.

Oscillators and PLL block

• The 30.72 MHz oscillator / PLL

output is seen on pin CKOUT.

• The 48 MHz oscillator output is

seen on pin USB_CFG.

Test mode 2: Electrical Tests

TestConfig register = 00000111

This mode permits:

• control of the direction of the bi-

directional I/O’s

• level measurement of the output pins

- pin DIA: forceZ (force all bi-

directional I/O’s in input mode)

- pin DIU: force0 (force all output

level at GND, bi-direction also if

forceZ is not active)

- pin DIS: force1 (force all output

level at VDD, bi-direction also if

forceZ is not active)

Nand-tree

All the input pins, except DIA, and all

the bi-directional I/O’s are in the nand-

tree. So the input levels of all inputs

and bi-directional pins can be checked.

A1 = nand-tree output

DIA = ‘1’

DIU = don’t care

DIS = don’t care

The external boundary scan chain is

enabled by selecting chain 3 using

the SCAN_N instruction. It contains

1 boundary scan cell per I/O pin,

except for the JTAG pins (TDI, TDO,

TMS, TCK, NTRST) and the XTAL

pins (XTAL1, XTAL2, USB_XTAL1,

USB_XTAL2). The chain contains 110

boundary scan cells, starting at pin 1

(DQ0) and ending at pin 134 (PA3).

NOTES:

• Restriction: No boundary scan cells

are inserted on any of the tri-state

enable signals of bi-directional and

tri-state output pins.

• ‘HIGHZ’ instruction support: Only

bi-direction pins and output pins

that are tri-state in normal mode are

driven in tri-state during HIGHZ.

That is, output pins that are not tri-

state in normal mode, are not

driven in tri-state during HIGHZ.

External Boundary Scan

Symbol Parameter Conditions Min Max Unit

VIH High Level Input Voltage 2.0 V

VIL Low Level Input Voltage 0.8 V

VOH High Level Output Voltage Ioh = rated buffer current 2.4 V

VOL Low Level Output Voltage Iol = rated buffer current 0.4 V

Vt+ Schmitt trigger rising threshold 1.3 1.9 V

Vt- Schmitt trigger falling threshold 0.8 1.3 V

CIN Input Capacitance, all inputs 1 pF

COUT Load Capacitance, all outputs 100 pF

104

MTC-20285

This section describes the characteris-

tics of the TTL and CMOS I/O cells, as

described in the standard cell library.

Which I/O cells are CMOS or TTL

compatible as well as the rated buffer

current, is found in section 2.4. Note

also that some inputs are Schmitt

Trigger inputs.

Electrical Characteristics and Ratings

MTC-20285 240300 [104]

Table 41: TTL DC Electrical Characteristics*

* Rated for Vdd = 2.7V to 3.6V and Ambient Temp from -55 to +125 deg

Symbol Parameter Conditions Min Max Unit

VIH High Level Input Voltage 80% of VDD V

VIL Low Level Input Voltage 20% of VDD V

VOH High Level Output Voltage Ioh = rated buffer current 85% of VDD V

VOL Low Level Output Voltage Iol = rated buffer current 0.4 V

Vt+ Schmitt trigger rising threshold 1.8 2.5 V

Vt- Schmitt trigger falling threshold 0.8 1.3 V

CIN Input Capacitance, all inputs 1 pF

COUT Load Capacitance, all outputs 100 pF

Table 42: CMOS DC Electrical Characteristics*

* Rated for Vdd = 2.7V to 3.6V and Ambient Temp from -55 to +125 deg C

105

MTC-20285

6. ABSOLUTE MAXIMUM RATINGS, OPERATING RANGES & STORAGE CONDITIONS

MTC-20285 240300 [105]

Stresses above those listed in this

section can cause permanent device

failure. Exposure to absolute maximum

ratings for extended periods can

affect device reliability.

Absolute Maximum Ratings

Symbol Conditions Min Max Unit

VDD power supply voltage VSS - 0.3 3.63 V

VIN input voltage on any pin VSS - 0.3 VDD + 0.3 AND < 3.63 V

VIN5 input voltage on any 5V tolerant pin VSS - 0.3 5.5 V

Operating ranges define the limits for

functional operation and schematic

characteristics of the device as

described above, and for the

reliability specifications as listed

in section 7. Functionality outside

these limits is not implied.

Total cumulative dwell time outside the

normal power supply voltage range

or the ambient temperature under bias

must be less than 0.1% of the useful

life as defined in section 7.3.

Furthermore, for the 5V tolerant I/O

cells and in case a 5V interface is

used, the system should be designed

such that no 5V inputs are applied

when the 3.3V power supply is not

present as this limits the lifetime of the

device. However, if the cumulated

time when this situation occurs does

not exceed 5 hours (18000 s) over

the total life of the device, the impact

on the total lifetime will remain

negligible.

Therefore the 5V and 3.3V power

supplies must always be present

together, except during the short

power on/off transient states which

rarely occur.

Operating Ranges

Symbol Conditions Min Max Unit

VDD Power supply 3.0 3.45 V

PTOT (1) Full operation power consumption 200 mW

PPD (2) Stand-by power consumption 25 mW

Tamb Ambient temperature -40 85 deg C

NOTES:

1. Power with all blocks of the MTC-20285 operational and maximum clock frequencies used at nominal power supply

voltage (3.3V) + 5%.

2. Power with all blocks of the MTC-20285 operational, except the ARM which is in power down at nominal power

supply voltage (3.3V) + 5%.

106

MTC-20285

MTC-20285 240300 [106]

The components are designed for

applications in equipment for indoor

operation with convection air flow

and not forced cooling.

Operating Environment

The rated storage and transportation

temperature range prior to printed

board assembly is as follows:

-55 deg C to +110 deg C

In case of IC deliveries in dry bag, the

conditions of time and humidity during

storage are specified in Alcatel

Microelectronics specification 16650.

In case of IC deliveries not in dry bag,

the conditions for a maximum storage

period of 2 years are as follows:

Storage and Transportation Conditions

Ambient Temperature (deg C) Relative Humidity (%)

20 80

30 70

40 60

50 50

107

MTC-20285

7. QUALITY

MTC-20285 240300 [107]

All products are tested 100%, at

ambient temperature with full

temperature range guard band, by

means of production test programs

that guarantees optimal coverage of

the product specification.

Product Acceptance Tests

Lot conformance to specification

of products delivered in volume

production is guaranteed by means

of following tests:

Lot-by-Lot Acceptance Tests

Test Conditions AQL Level Inspection Level

Electrical, functional To product specification at Tamb = 25 deg C 0.04 II

and parametric with full temperature range performance guard band.

External visual Physical damage to body or leads. 0.04 II

Dimensions affecting PCB manufacturability such as

bent leads, coplanarity, etc

External visual Correctness of marking 0.65 II

Each delivery lot is accompanied by

a Certificate of Conformance.

Delivery Lot Certification

A quality system with certification

against ISO9001 is maintained.

Quality System

108

MTC-20285

In order to guarantee the specified

reliability, Alcatel Microelectronics

performs a product qualification

for each product. This qualification

is described in the Alcatel Micro-

electronics specification document

15503.

In order to minimize reliability testing,

structural similarity is applied.

Methods and criteria are defined

8. RELIABILITY SPECIFICATION

in the Alcatel Microelectronics

specification documents 15501

(assembly) and 15502 (wafer

fabrication).

Monitoring of assembly and wafer

fabrication is performed according

to the Alcatel Microelectronics

specifications 15910 and 15205.

These monitoring tests include the

solderability tests.

MTC-20285 240300 [108]

When operating the component under

benign conditions, the intrinsic failure

rate will not exceed:

• 5000 ppm during the early failure

period defined below

• the long term failure rate as

specified in the table below after

the early failure period

The Intrinsic Failure Rate

Failures due to external over stresses

such as ESD, voltage and current over

stress (e.g. due to EMI), excessive

mechanical and thermal shocks, are

not included in these figures (see

section 7.2).

Tjunction (deg C) Early Failure Period (Hrs) Long Term Failure Rate (FIT)

55 8760 100

65 4000 200

75 2000 400

85 1000 800

90 800 1000

109

MTC-20285

MTC-20285 240300 [109]

Electrostatic Discharge

The device withstands 1000 Volts

Standardized Human Body Model

ESD pulses when tested according

to MIL883C method 3015.

Latch-up

Static latch-up protection level is

100 mA at 25 deg C when tested

according to JEDEC no. 17.

External Stress Immunity

The useful life, when used under

moderate conditions, is at least 10

years. The term useful life is specified

as the point in the lifetime where the

intrinsic failure rate exceeds the

longterm failure rate specified above.

The Useful Life

110

MTC-20285

ASB: Advanced System Bus

APB: Advanced Peripheral Bus

FIFO: First In First Out

FSM: Finite State Machine

LSB: Least Significant bit

LT: Line Termination

MSB: Most Significant bit

NC: Not connected

NT: Network Termination

PABX: Private Automatic Branch

Exchange

PLL: Phase Locked Loop

SIC: S-Bus Interface Circuit

TE: Terminal Equipment

USB: Universal Serial Bus

9. ABBREVIATIONS AND CONVENTIONS

Signals and their numerical types are

described with the following symbols:

• us<wl,bp>:

unsigned (i.e. positive) fixed point

signal with length = ‘wl’ bits and

‘bp’ number of fractional bits (for

example: us<4,1> (value = 4,5) =

‘100.1’)

• tc<wl,bp>:

two’s complement representation

of fixed point signal with length =

‘wl’ bits and ‘bp’ number of

fractional bits (for example:

tc<4,1> (value = -3,5) = ‘100.1’)

• SIGNAME[wl-1,0]:

signal represented as a bit vector

of ‘wl’ bits with the MSB being bit

SIGNAME[wl-1] and the LSB being

bit SIGNAME[0]

• Upstream:

direction from subscriber to

exchange

• Downstream:

direction from exchange to

subscriber

• TX:

Transmit direction of a module

corresponds to an output stream

of the module

• RX:

Receive direction of a module

corresponds to an input stream

of the module

MTC-20285 240300 [110]

111

MTC-20285

1. ISDN/IDSL + USB TERMINAL CONTROLLER ....................................................................................................1

• General Description ......................................................................................................................................3

- Clock Generation and Control......................................................................................................................3

- Memory Bus ..............................................................................................................................................3

- 3-way GCI Interface....................................................................................................................................3

- HDLC Controllers ........................................................................................................................................3

- DTMF Decoding ........................................................................................................................................4

- Serial I/O..................................................................................................................................................4

- Parallel I/O Ports........................................................................................................................................4

- Interrupt Control ........................................................................................................................................4

- Timers / Watchdog ....................................................................................................................................4

- CPU ..........................................................................................................................................................4

- USB Controller ..........................................................................................................................................4

2. MECHANICAL DATA, PIN FUNCTIONS AND EXTERNAL COMPONENTS..........................................................5

• Package and PIn-out ......................................................................................................................................5

- Package Orientation ..................................................................................................................................6

• Marking on the Package ................................................................................................................................6

- Topside Marking (PQFP)..............................................................................................................................6

- Reverse Side Marking ................................................................................................................................6

• Delivery........................................................................................................................................................7

• Pin Description and Assignment ......................................................................................................................7

- Important Notes on 5 V Tolerant Pins ............................................................................................................7

• Pin Function in Normal (Non-test) Mode ........................................................................................................11

• Pin Functions in Test Mode ............................................................................................................................14

• Application Schematic and External Components ............................................................................................14

3. GENERAL ASPECTS ....................................................................................................................................16

• Convention Upstream / Downstream..............................................................................................................16

- GCI Frame Formats ..................................................................................................................................17

- Parameter Updating, Timing and Initial Values ............................................................................................18

• GCI Router..................................................................................................................................................20

- Architecture ............................................................................................................................................20

- Multiplexer ..............................................................................................................................................20

- Examples ................................................................................................................................................23

- CPU Registers (ARM ! GCI) ........................................................................................................................24

- RX Registers (GCI ! ARM) ..........................................................................................................................26

- D/CI Activity Detection..............................................................................................................................27

- Asynchronous Pull-up / Pull-down ..............................................................................................................28

• GCI Clocks Generation ................................................................................................................................29

- Hardware Implementation of the Multiplexing ..............................................................................................30

• HDLC Formatter ..........................................................................................................................................32

- Description ..............................................................................................................................................32

- HDLC Protocol..........................................................................................................................................32

- Control Registers ......................................................................................................................................32

• USB Interface USB Disabled ..........................................................................................................................40

- USB Disabled ..........................................................................................................................................40

- Description ..............................................................................................................................................40

- USB Logical Architecture............................................................................................................................40

- Architecture ............................................................................................................................................41

- USB Ram Memory ....................................................................................................................................41

Table of Contents

MTC-20285 240300 [111]

112

MTC-20285

- USB RX FIFO ............................................................................................................................................42

- USB TX FIFO ............................................................................................................................................43

- USB CONFIG ..........................................................................................................................................44

- USB Error Indication..................................................................................................................................44

- ISDN <-> USB Data Flow Mechanism..........................................................................................................44

- USB Control/Status Registers......................................................................................................................45

- Start-up Sequence ....................................................................................................................................49

- USB Ram Accesses....................................................................................................................................49

- Device Configuration ................................................................................................................................49

• Clock Generation ........................................................................................................................................50

• The ARM7TDMI ..........................................................................................................................................53

- APB Bridge ..............................................................................................................................................53

- On-chip Memory ......................................................................................................................................53

• External Memory Interface ............................................................................................................................54

- Memory Access Modes ............................................................................................................................54

- Wait Cycle(s) per Block ............................................................................................................................59

- Timing ....................................................................................................................................................59

- Memory Space Organisation ....................................................................................................................60

• Interrupts ....................................................................................................................................................62

• External Interrupt..........................................................................................................................................64

• UART Interfaces ..........................................................................................................................................65

• Parallel I/O Ports ........................................................................................................................................72

• Timers ........................................................................................................................................................74

- Count Down Timers with Interrupt Generation ..............................................................................................74

• Watchdog Timer..........................................................................................................................................77

• Hardware Identification Code ......................................................................................................................79

• CHIP_CFG Registers ....................................................................................................................................80

• Register Table..............................................................................................................................................81

- APB Address ............................................................................................................................................81

4. POWER MANAGEMENT ............................................................................................................................93

5. DEBUG INTERFACE AND ATE TEST............................................................................................................101

• Debug Monitoring ....................................................................................................................................102

• ATE Test ..................................................................................................................................................102

• External Boundary Scan..............................................................................................................................103

• Electrical Characteristics and Ratings ..........................................................................................................104

6. ABSOLUTE MAXIMUM RATINGS, OPERATING RANGES AND STORAGE CONDITIONS ................................105

• Absolute Maximum Ratings ........................................................................................................................105

• Operating Ranges ....................................................................................................................................105

• Operating Environment ..............................................................................................................................106

• Storage and Transportation Conditions ........................................................................................................106

7. QUALITY..................................................................................................................................................107

• Product Acceptance Tests............................................................................................................................107

• Lot-by-lot Acceptance Tests ..........................................................................................................................107

MTC-20285 240300 [112]

113

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MTC-20285 240300 [113]

• Delivery Lot Certification ............................................................................................................................107

• Quality System ..........................................................................................................................................107

8. RELIABILITY SPECIFICATION ......................................................................................................................108

• The Intrinsic Failure Rate ............................................................................................................................108

• External Stress Immunity..............................................................................................................................109

• The Useful Life ..........................................................................................................................................109

9. ABBREVIATIONS AND CONVENTIONS ....................................................................................................110

114

MTC-20285

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Figure 1: ISDN/IDSL Terminal Controller - Typical Application................................................................................1

Figure 2: MTC-20285 - IDSN/IDSL with USB Controller - Block Diagram ................................................................2

Figure 3: MTC-20285 pin-out names (Top View) ..................................................................................................5

Figure 4: Package Orientation (top view) ............................................................................................................6

Figure 5: Topside Marking ................................................................................................................................6

Figure 6: External Components ........................................................................................................................12

Figure 7: Upstream and Downstream Convention ..............................................................................................14

Figure 8: Timing of Register Updating ..............................................................................................................16

Figure 9: GCI Router Architecture ....................................................................................................................17

Figure 10: D/CI Activity Detection ....................................................................................................................22

Figure 11: GCI Clock Generation ....................................................................................................................24

Figure 12: Multiplexing for the U-GCI Clocks ....................................................................................................26

Figure 13: HDLC Frame Format ........................................................................................................................28

Figure 14: USB RX FIFO Block Organisation ......................................................................................................37

Figure 15: USB TX FIFO Block Organisation ......................................................................................................38

Figure 16: ISDN <->USB Data Flow Mechanism ................................................................................................39

Figure 17: ARM7TDMI and Interfaces ..............................................................................................................49

Figure 18: MTC-20285 - External Memory Connections for ‘Case a’.....................................................................51

Figure 19: MTC-20285 - External Memory Connections for ‘Case b’.....................................................................51

Figure 20: MTC-20285 - External Memory Connections for ‘Case c’.....................................................................52

Figure 21: MTC-20285 - External Memory Connections for ‘Case d’.....................................................................52

Figure 22: Memory interface............................................................................................................................54

Figure 23: Timings of the Memory Interface ......................................................................................................55

Figure 24: ARM Address Space Organisation....................................................................................................56

Figure 25: Baud Rate Detection Block Diagram ..................................................................................................60

Figure 26: Watchdog State Machine ................................................................................................................71

List of Figures

115

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MTC-20285 240300 [115]

Table 1: Pin Assignment ..................................................................................................................................10

Table 2: Pin Function and Description................................................................................................................12

Table 3: GCI Related Components....................................................................................................................13

Table 4: XTAL Input Related Components ..........................................................................................................13

Table 5: USB XTAL Input Related Components ....................................................................................................13

Table 6: Power Supply Decoupling Related Components ....................................................................................13

Table 7: Hardware Reset Related Components ..................................................................................................13

Table 8: GCI Frame Formats ............................................................................................................................14

Table 9: SCR Register Table ............................................................................................................................19

Table 10: CPU Register Table ..........................................................................................................................20

Table 11: RX Register Table ............................................................................................................................21

Table 12: GCI Register Table ..........................................................................................................................23

Table 13: GCI_PULL Register Table ..................................................................................................................23

Table 14: CLK_GCI Register Table ....................................................................................................................27

Table 15: Control Registers ..............................................................................................................................34

Table 16: CKOUT Frequency ..........................................................................................................................46

Table 17: ASB Clock Frequency ......................................................................................................................47

Table 18: APB Clock Frequency ......................................................................................................................47

Table 19: Clock Register Table ........................................................................................................................48

Table 20: Memory Access Modes ....................................................................................................................50

Table 21: Memory Register Table ....................................................................................................................57

Table 22: Interrupt Register Table ....................................................................................................................58

Table 23: Interrupt Mapping ............................................................................................................................58

Table 24: External Interrupt Register Table ........................................................................................................59

Table 25: Baud Rate Examples ........................................................................................................................60

Table 26: Default Register Set ..........................................................................................................................66

Table 27: Baud Rate Generator Divisor Register Set (selected when LCR[7] 1)......................................................66

Table 28: Enhanced Register Set (selected when LCR = 0xBF) ..............................................................................66

Table 29: Port PA: Timer Extended Functions......................................................................................................67

Table 30: Port PB: UART1 Extended Functions (see section 3.11)..........................................................................67

Table 31: Port PC: UART2 Access ....................................................................................................................67

Table 32: Port Register Table............................................................................................................................68

Table 33: Count Down Timer Modes ................................................................................................................69

Table 34: Clock Timer Restraints ......................................................................................................................70

Table 35: Timer Register Table ........................................................................................................................70

Table 36: Watchdog Count Down Frequency ....................................................................................................72

Table 37: Watchdog Register Table..................................................................................................................72

Table 38: Chip Register Table ..........................................................................................................................73

Table 39: CHIP_CFG Registers ........................................................................................................................73

Table 40: Address Table..................................................................................................................................83

Table 41: TTL DC Electrical Characteristics (1)....................................................................................................86

Table 42: CMOS DC Electrical Characteristics (1) ..............................................................................................87

List of Tables

MTC-20285 240300 [116]

MTC-20285

03/00-0284a

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