DPDD32MX16WSCY5-DP-0715 - DPAC Technologies Corp.

512 Mega bit CMOS DDR SDRAM

DPDD32MX16WSCY5

AD VANCED IN FOR MA TION

DE SCRIP TION:

The LP-Stack™ series is a family of interchangeable memory

devices. The 512 Megabit Double Data Rate Synchronous

DRAM is a member of this family which utilizes the new and

innovative space saving TSOP stacking technology. The

devices are constructed with two 16 Meg x 16 DDR SDRAM’s.

The 512 Megabit LP-Stack™ modules DPDD32MX16WSCY5,

based on 256 Megabit devices, has been designed to fit in the

same footprint as the 16 Meg x 16 DDR SDRAM TSOP

monolithic. This allows for system upgrade without electrical or

mechanical redesign. Providing an immediate and low cost

memory solution.

FEA TURES:

•Configurations Available:

32 Meg x 16 (2 Banks of 4 Meg x 16 bits x 4)

•Clock Frequencies:

100, 125, 133, 143 MHz

•2.5 Volt DQ Supply

•JEDEC Standard SSTL_2 Interface for all Inputs/Outputs

•Four Bank Operation

•Programmable Burst Type:

Burst Length and Read Latency

•Refresh:

8192 Cycles/64ms

•Refresh Types:

Auto and Self

•JEDEC Approved Footprint and Pinout

•Package:

66-Pin Leadless TSOP Stack

30A246-00

REV. A This document contains information on a product under consideration for development at Dense-Pac Microsystems, Inc.

Dense-Pac reserves the right to change or discontinue information on this product without prior notice.

PIN-OUT DI A GRAM

FUNC TIONAL BLOCK DI A GRAM

PIN NAMES

A0 - A12 Row Address: A0 - A12

Column Address: A0 - A8

BA0,BA1 Bank Select Address

A10 / AP Auto Precharge

DQ0 - DQ15 Data In / Data Out

CAS Column Address Strobe

CS0, CS1 Chip Selects

RAS Row Address Strobe

WE Data Write Enable

CK, CK Differential Clock Inputs

CKE0, CKE1 Clock Enables

UDQS, LDQS Upper/Lower Data Strobe

UDM, LDM Upper/Lower Data Mask

VDD Power Supply (+2.5V)

VSS Ground

VDDQ DQ Power Supply (+2.5V)

VSSQ DQ Ground

VREF Reference Voltage for Inputs

N.C. No Connect

NU Not Used