1
LTC1746
1746f
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
BLOCK DIAGRA
W
Low Power,14-Bit, 25Msps ADC
■
Sample Rate: 25Msps
■
77.5dB SNR and 91dB SFDR (3.2V Range)
■
74dB SNR and 96dB SFDR (2V Range)
■
No Missing Codes
■
Single 5V Supply
■
Low Power Dissipation: 390mW
■
Selectable Input Ranges: ±1V or ±1.6V
■
240MHz Full Power Bandwidth S/H
■
Pin Compatible Family
25 Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
50 Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
65 Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
80 Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
■
Telecommunications
■
Medical Imaging
■
Receivers
■
Base Stations
■
Spectrum Analysis
■
Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC
®
1746 is a 25Msps, sampling 14-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. Pin selectable input ranges of ±1V
and ±1.6V along with a resistor programmable mode
allow the LTC1746’s input range to be optimized for a wide
variety of applications.
The LTC1746 is perfect for demanding communications
applications with AC performance that includes 77.5dB
SNR and 91dB spurious free dynamic range. Ultralow jitter
of 0.3ps
RMS
allows undersampling with excellent noise
performance. DC specs include ±3LSB INL maximum and
no missing codes over temperature.
The digital interface is compatible with 5V, 3V and 2V logic
systems. The ENC and ENC inputs may be driven differen-
tially from PECL, GTL and other low swing logic families or
from single-ended TTL or CMOS. The low noise, high gain
ENC and ENC inputs may also be driven by a sinusoidal
signal without degrading performance. A separate digital
output power supply can be operated from 0.5V to 5V,
making it easy to connect directly to low voltage DSPs
or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
25Msps, 14-Bit ADC with a ±1V Differential Input Range
14-BIT
PIPELINED ADC
14
S/H
AMP
±1V
DIFFERENTIAL
ANALOG INPUT
A
IN+
A
IN–
SENSE
V
CM
4.7µF
DIFF AMP
REFLA REFHB
GND
1746 BD
ENC
4.7µF
1µF1µF
0.1µF 0.1µF
REFHAREFLB
BUFFER
RANGE
SELECT
2.35V
REF
OUTPUT
LATCHES
CONTROL LOGIC
OV
DD
V
DD
OGND
0.5V TO 5V
5V
0.1µF
1µF 1µF 1µF
D13
D0
CLKOUT
OF
•
•
•
ENC
DIFFERENTIAL
ENCODE INPUT
OEMSBINV
0.1µF
2
LTC1746
1746f
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ●14 Bits
Integral Linearity Error (Note 6) ●–3 ±1 3 LSB
Differential Linearity Error ●–1 ±0.5 1 LSB
Offset Error (Note 7) ●–30 ±530 mV
Gain Error External Reference (SENSE = 1.6V) ●–2.5 ±1 2.5 %FS
Full-Scale Tempco I
OUT(REF)
= 0 ±40 ppm/°C
ORDER PART
NUMBER
OVDD = VDD (Notes 1, 2)
Supply Voltage (V
DD
)............................................. 5.5V
Analog Input Voltage (Note 3) .... –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) ..... –0.3V to (V
DD
+ 0.3V)
Digital Output Voltage................. –0.3V to (V
DD
+ 0.3V)
OGND Voltage..............................................–0.3V to 1V
Power Dissipation............................................ 2000mW
Operating Temperature Range
LTC1746C ............................................... 0°C to 70°C
LTC1746I............................................ – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
LTC1746CFW
LTC1746IFW
T
JMAX
= 150°C, θ
JA
= 35°C/W
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
ABSOLUTE MAXIMUM RATINGS
W
WW
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PACKAGE/ORDER INFORMATION
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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FW PACKAGE
48-LEAD PLASTIC TSSOP
48
47
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43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SENSE
V
CM
GND
A
IN+
A
IN–
GND
V
DD
V
DD
GND
REFLB
REFHA
GND
GND
REFLA
REFHB
GND
V
DD
V
DD
GND
V
DD
GND
MSBINV
ENC
ENC
OF
OGND
D13
D12
D11
OV
DD
D10
D9
D8
D7
OGND
GND
GND
D6
D5
D4
OV
DD
D3
D2
D1
D0
OGND
CLKOUT
OE
CO VERTER CHARACTERISTICS
U
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (Note 8) 4.75V ≤ V
DD
≤ 5.25V ●±1 to ±1.6 V
I
IN
Analog Input Leakage Current ●–1 1 µA
C
IN
Analog Input Capacitance Sample Mode ENC < ENC 8 pF
Hold Mode ENC > ENC 4 pF
t
ACQ
Sample-and-Hold Acquisition Time ●15 18 ns
t
AP
Sample-and-Hold Acquisition Delay Time 0 ns
t
JITTER
Sample-and-Hold Acquisition Delay Time Jitter 0.3 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio 1.0V < (A
IN–
= A
IN+
) < 3.5V 80 dB
The ● indicates specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
A ALOG I PUT
UU
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LTC1746
1746f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input Signal (2V Range) 74 dBFS
5MHz Input Signal (3.2V Range) ●75.5 77.5 dBFS
30MHz Input Signal (2V Range) 73.5 dBFS
30MHz Input Signal (3.2V Range) 76.5 dBFS
70MHz Input Signal (2V Range) 72.5 dBFS
70MHz Input Signal (3.2V Range) 75 dBFS
SFDR Spurious Free Dynamic Range 5MHz Input Signal (2V Range) 96 dB
5MHz Input Signal (3.2V Range) ●80 91 dB
30MHz Input Signal (2V Range) 95 dB
30MHz Input Signal (3.2V Range) 86.5 dB
70MHz Input Signal (2V Range) 79 dB
70MHz Input Signal (3.2V Range) 71 dB
S/(N + D) Signal-to-(Noise + Distortion) Ratio 5MHz Input Signal (2V Range) 74 dBFS
5MHz Input Signal (3.2V Range) ●75 77.5 dBFS
30MHz Input Signal (2V Range) 73.5 dBFS
30MHz Input Signal (3.2V Range) 76.5 dBFS
70MHz Input Signal (2V Range) 71.5 dBFS
70MHz Input Signal (3.2V Range) 70 dBFS
THD Total Harmonic Distortion 5MHz Input Signal, First 5 Harmonics (2V Range) –92 dB
5MHz Input Signal, First 5 Harmonics (3.2V Range) –90 dB
30MHz Input Signal, First 5 Harmonics (2V Range) –90.5 dB
30MHz Input Signal, First 5 Harmonics (3.2V Range) –85.5 dB
70MHz Input Signal, First 5 Harmonics (2V Range) –77.5 dB
70MHz Input Signal, First 5 Harmonics (3.2V Range) –70 dB
IMD Intermodulation Distortion f
IN1
= 4MHz, f
IN2
= 5.1MHz (2V Range) 86 dBc
f
IN1
= 4MHz, f
IN2
= 5.1MHz (3.2V Range) 84 dBc
Sample-and-Hold Bandwidth R
SOURCE
= 50Ω240 MHz
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
DY A IC ACCURACY
UW
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CM
Output Voltage I
OUT
= 0 2.29 2.35 2.41 V
V
CM
Output Tempco I
OUT
= 0 ±30 ppm/°C
V
CM
Line Regulation 4.75V ≤ V
DD
≤ 5.25V 3 mV/V
V
CM
Output Resistance 1mA ≤ I
OUT
≤ 1mA 4 Ω
(Note 5)
I TER AL REFERE CE CHARACTERISTICS
UU U
4
LTC1746
1746f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE
Sampling Frequency (Note 9) ●1 25 MHz
t
1
ENC Low Time (Note 9) ●19 20 1000 ns
t
2
ENC High Time (Note 9) ●19 20 1000 ns
t
3
Aperture Delay of Sample-and-Hold (Note 8) 0 ns
t
4
ENC to Data Delay C
L
= 10pF (Note 8) ●1.4 4 10 ns
t
5
ENC to CLKOUT Delay C
L
= 10pF (Note 8) ●0.5 2 5 ns
t
6
CLKOUT to Data Delay C
L
= 10pF (Note 8) ●02 ns
t
7
DATA Access Time After OE ↓C
L
= 10pF (Note 8) 10 25 ns
t
8
BUS Relinquish Time (Note 8) 10 25 ns
Data Latency 5 cycles
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Positive Supply Voltage 4.75 5.25 V
I
DD
Positive Supply Current 2V Range, Full-Scale Input ●78 93 mA
P
DIS
Power Dissipation 2V Range, Full-Scale Input ●390 465 mW
OV
DD
Digital Output Supply Voltage 0.5 V
DD
V
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
TI I G CHARACTERISTICS
UW
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND
(unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, f
SAMPLE
= 25MHz, differential ENC/ENC = 2V
P-P
25MHz
sine wave, input range = ±1.6V differential, unless otherwise specified.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from –0.5 LSB
when the output code flickers between 00 0000 0000 0000 and 11
1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 5.25V ●2.4 V
V
IL
Low Level Input Voltage V
DD
= 4.75V ●0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±10 µA
C
IN
Digital Input Capacitance MSBINV and OE Only 1.5 pF
V
OH
High Level Output Voltage OV
DD
= 4.75V I
O
= –10µA 4.74 V
I
O
= –200µA●4V
V
OL
Low Level Output Voltage OV
DD
= 4.75V I
O
= 160µA 0.05 V
I
O
= 1.6mA ●0.1 0.4 V
I
OZ
Hi-Z Output Leakage D13 to D0 V
OUT
= 0V to V
DD
, OE = High ●±10 µA
C
OZ
Hi-Z Output Capacitance D13 to D0 OE = High (Note 8) ●15 pF
I
SOURCE
Output Source Current V
OUT
= 0V –50 mA
I
SINK
Output Sink Current V
OUT
= 5V 50 mA
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
POWER REQUIRE E TS
WU
5
LTC1746
1746f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Nonaveraged, 32768 Point FFT,
Input Frequency = 5MHz,
3.2V Range
CODE
0
–1.0
INL ERROR (LSB)
–0.5
0
0.5
1.0
4000 8000
1746 G01
12000 16000
CODE
0
–1.0
DNL ERROR (LSB)
–0.5
0
0.5
1.0
4000 8000
1746 G02
12000 16000
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–70
–80
–90
–100
–110
–120
–50
–40
0
–20
26812
–10
–30
410
1746 G03
Typical INL Typical DNL
Nonaveraged, 32768 Point FFT,
Input Frequency = 30MHz,
2V Range
Nonaveraged, 32768 Point FFT,
Input Frequency = 30MHz,
3.2V Range
Nonaveraged, 32768 Point FFT,
Input Frequency = 5MHz,
2V Range
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–70
–80
–90
–100
–110
–120
–50
–40
0
–20
26812
–10
–30
410
1746 G04
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–70
–80
–90
–100
–110
–120
–50
–40
0
–20
26812
–10
–30
410
1746 G05
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–70
–80
–90
–100
–110
–120
–50
–40
0
–20
26812
–10
–30
410
1746 G06
Nonaveraged, 32768 Point
2-Tone FFT, Input Frequency =
4MHz and 5.1MHz, 3.2V Range
Nonaveraged, 32768 Point FFT,
Input Frequency = 70MHz,
2V Range
Nonaveraged, 32768 Point
2-Tone FFT, Input Frequency =
4MHz and 5.1MHz, 2V Range
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–70
–80
–90
–100
–110
–120
–50
–40
0
–20
26812
–10
–30
410
1746 G07
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–70
–80
–90
–100
–110
–120
–50
–40
0
–20
26812
–10
–30
410
1746 G08
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–70
–80
–90
–100
–110
–120
–50
–40
0
–20
26812
–10
–30
410
1746 G09
6
LTC1746
1746f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Grounded Input Histogram SNR vs Sample Rate,
Input Frequency = 5MHz, –1dB
CODE
8167
0
COUNT
5000
10000
15000
20000
25000
8168 8169 8170 8171
1746 G10
8172
SAMPLE RATE (Msps)
0
66
SNR (dBFS)
68
70
72
74
78
10 20 30 40
1746 G11
50 60
76
67
69
71
73
77
75
3.2V RANGE
2V RANGE
SAMPLE RATE (Msps)
0
50
SFDR (dB)
60
70
80
90
110
10 20 30 40
1746 G12
50 60
100
3.2V RANGE
2V RANGE
SFDR vs Sample Rate,
Input Frequency = 5MHz, –1dB
SNR vs Input Frequency and
Amplitude 3.2V Range SNR vs Input Frequency and
Amplitude 2V Range
INPUT FREQUENCY (MHz)
50
SNR (dB)
60
70
80
55
65
75
20 40 60 80
1746 G13
10010030507090
–1dBFS
–6dBFS
–20dBFS
INPUT FREQUENCY (MHz)
50
SNR (dB)
60
70
80
55
65
75
20 40 60 80
1746 G14
10010030507090
–1dBFS
–6dBFS
–20dBFS
SFDR vs Input Frequency
and Amplitude, 3.2V Range
INPUT FREQUENCY (MHz)
0
40
SFDR (dBFS)
50
70
80
90
110
10 50 70
1746 G15
60
100
40 90 100
20 30 60 80
–1dBFS
–6dBFS
–20dBFS
SFDR vs Input Frequency
and Amplitude, 2V Range
INPUT FREQUENCY (MHz)
0
40
SFDR (dBFS)
50
70
80
90
110
50
1746 G16
60
100
150 200
100
–1dBFS
–6dBFS
–20dBFS
7
LTC1746
1746f
2nd and 3rd Harmonic vs Input
Frequency, 3.2V Range, –1dB
INPUT FREQUENCY (MHz)
0
DISTORTION (dB)
–70
–50
–30
80
1746 G17
–90
–110
–130 10 20 30 40 50 60 70 90 100
2ND HARMONIC
3RD HARMONIC
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INPUT FREQUENCY (MHz)
0
DISTORTION (dB)
–70
–50
–30
100
1746 G18
–90
–110
–130 50 150 200
2ND HARMONIC
3ND HARMONIC
INPUT FREQUENCY (MHz)
0
DISTORTION (dB)
–80
–70
–60
80
1746 G19
–90
–100
–110 10 20 30 40 50 60 70 90 100
2nd and 3rd Harmonic vs Input
Frequency, 2V Range, –1dB Worst Harmonic 4th or Higher vs
Input Frequency, 3.2V Range, –1dB
Worst Harmonic 4th or Higher vs
Input Frequency, 2V Range, –1dB
INPUT FREQUENCY (MHz)
0
DISTORTION (dB)
–80
–70
–60
100
1746 G20
–90
–100
–110 50 150 200
SFDR vs Input Amplitude,
2V Range, 5MHz Input Frequency
INPUT AMPLITUDE (dBFS)
–60
SFDR (dBc AND dBFS)
80
90
SFDR dBFS
SFDR dBc
1746 G21
70
60 –40 –20 0
110
100
Power vs Sample Rate,
Input Frequency = 5MHz
SAMPLE RATE (Msps)
0
300
POWER (mW)
340
380
420
10 20 30 40
1746 G22
50
460
500
320
360
400
440
480
60
3.2V RANGE
2V RANGE
8
LTC1746
1746f
SENSE (Pin 1): Reference Sense Pin. Ground selects
±1V. V
DD
selects ±1.6V. Greater than 1V and less than
1.6V applied to the SENSE pin selects an input range of
±V
SENSE
, ±1.6V is the largest valid input range.
V
CM
(Pin 2): 2.35V Output and Input Common Mode Bias.
Bypass to ground with 4.7µF ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC
Power Ground.
A
IN+
(Pin 4): Positive Differential Analog Input.
A
IN–
(Pin 5): Negative Differential Analog Input.
V
DD
(Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to GND
with 1µF ceramic chip capacitor.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10
with 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF
ceramic capacitor and to ground with 1µF ceramic
capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15
with 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF
ceramic capacitor and to ground with 1µF ceramic
capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 11.
PI FU CTIO S
UUU
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on
the positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended encode signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z.
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
D0-D3 (Pins 28 to 31): Digital Outputs. D0 is the LSB.
OV
DD
(Pins 32, 43): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1µF ceramic chip capacitor.
D4-D6 (Pins 33 to 35): Digital Outputs.
D7-D10 (Pins 39 to 42): Digital Outputs.
D11-D13 (Pins 44 to 46): Digital Outputs. D13 is the
MSB.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
9
LTC1746
1746f
14-BIT
PIPELINED ADC
14
S/H
AMP
±1V
DIFFERENTIAL
ANALOG INPUT
A
IN+
A
IN–
SENSE
V
CM
4.7µF
DIFF AMP
REFLA REFHB
GND
1746 BD
ENC
4.7µF
1µF1µF
0.1µF 0.1µF
REFHAREFLB
BUFFER
RANGE
SELECT
2.35V
REF
OUTPUT
LATCHES
CONTROL LOGIC
OV
DD
V
DD
OGND
0.5V TO 5V
5V
0.1µF
1µF 1µF 1µF
D13
D0
CLKOUT
OF
•
•
•
ENC
DIFFERENTIAL
ENCODE INPUT
OEMSBINV
0.1µF
t
4
1746 TD
t
3
t
6
t
5
t
5
N
t
1
t
2
DATA (N – 5)
D11 TO D0
ANALOG
INPUT
ENCODE
DATA
CLKOUT
DATA (N – 4)
D11 TO D0 DATA (N – 3)
D11 TO D0
t
7
t
8
DATA N
D11 TO D0, OF AND CLKOUT
OE
DATA
TI I G DIAGRA
UWW
FU CTIO AL BLOCK DIAGRA
UU
W
10
LTC1746
1746f
APPLICATIO S I FOR ATIO
WUUU
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S / (N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD Log VVV Vn
V
=+++
20 234
1
222 2
...
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD.
IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc.
The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC.
This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
JITTER
= –20log (2π) • F
IN
• T
JITTER
11
LTC1746
1746f
CONVERTER OPERATION
As shown in Figure 1, the LTC1746 is a CMOS pipelined
multistep converter. The converter has four pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later, see the Timing Diagram section.
The analog input is differential for improved common
mode noise immunity and to maximize the input range.
Additionally, the differential input drive will reduce even
order harmonics of the sample-and-hold circuit. The en-
code input is also differential for improved common mode
noise immunity.
The LTC1746 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For
brevity, the text will refer to ENC greater than ENC as ENC
high and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
APPLICATIO S I FOR ATIO
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DIFF
REF
AMP
REF
BUF
INTERNAL
CLOCK SIGNALS
INTERNAL
REFERENCES TO ADC
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
RANGE
SELECT
2.35V
REFERENCE
ENC ENC
OUTPUT
DRIVERS
SHIFT REGISTER AND CORRECTION
OEMSBINV OGND
OF
OV
DD
0.5V TO
5V
D13
D0
CLKOUT
1746 F01
INPUT
S/H
FIRST STAGE
SENSE
V
CM
A
IN–
A
IN+
4.7µF
SECOND STAGE THIRD STAGE FOURTH STAGE
•
•
•
5-BIT
PIPELINED
ADC STAGE
4-BIT
PIPELINED
ADC STAGE
4-BIT
PIPELINED
ADC STAGE
4-BIT
FLASH
ADC
CONTROL
LOGIC
REFLA REFHB
4.7µF
1µF1µF
0.1µF 0.1µF
REFHAREFLB
Figure 1. Functional Block Diagram
12
LTC1746
1746f
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample Hold Operation
Figure 2 shows an equivalent circuit for the LTC1746
CMOS differential sample-and-hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(C
SAMPLE
) through CMOS transmission gates. This direct
capacitor sampling results in the lowest possible noise for
a given sampling capacitor size. The capacitors shown
attached to each input (C
PARASITIC
) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC/ENC is low, the
transmission gate connects the analog inputs to the sam-
pling capacitors, and they charge to and track the differen-
tial input voltage. When ENC/ENC transitions from low to
high the sampled input voltage is held on the sampling
capacitors. During the hold phase when ENC/ENC is high
the sampling capacitors are disconnected from the input
and the held voltage is passed to the ADC core for
processing. As ENC/ENC transitions from high to low the
inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small the charging glitch seen at the input will be
small. If the input change is large, such as the change seen
with input frequencies near Nyquist, then a larger charging
glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
±0.8V for the 3.2V range or ±0.5V for the 2V range, around
a common mode voltage of 2.35V. The V
CM
output pin
(Pin␣ 2) may be used to provide the common mode bias
level. V
CM
can be tied directly to the center tap of a trans-
former to set the DC input level or as a reference level to
an op amp differential driver circuit. The V
CM
pin must be
bypassed to ground close to the ADC with 4.7µF or greater
capacitor.
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Figure 2. Equivalent Input Circuit
C
SAMPLE
4pF
C
PARASITIC
4pF
C
PARASITIC
4pF
V
DD
LTC1746
A
IN+
1746 F02
C
SAMPLE
4pF
BIAS
V
DD
5V
A
IN–
ENC
ENC
2V
6k
2V
6k
13
LTC1746
1746f
APPLICATIO S I FOR ATIO
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Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC1746 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2F
ENCODE
); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100Ω or less for each input. The S/H
circuit is optimized for a 50Ω source impedance. If the
source impedance is less than 50Ω, a series resistor
should be added to increase this impedance to 50Ω. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC1746 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100Ω for each ADC input. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
Figure 4 demonstrates the use of operational amplifiers to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
The 25Ω resistors and 12pF capacitors on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
frequencies higher than 50MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
Figure 3. Single-Ended to Differential
Conversion Using a Transformer Figure 4. Differential Drive with Op Amps
1:1 25Ω
0.1µF
ANALOG
INPUT
VCM
AIN+
AIN–
100Ω100Ω12pF
12pF
12pF
1746 F03
4.7µF
25Ω
25Ω
25Ω
LTC1746
25Ω
5V
SINGLE-ENDED
INPUT
2.35V ±1/2
RANGE
V
CM
A
IN
+
A
IN
–
12pF
12pF
12pF
1746 F04
4.7µF
25Ω25Ω
100Ω
500Ω500Ω
25Ω
LTC1746
–
+
1/2 LT1810
–
+
1/2 LT1810
14
LTC1746
1746f
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Reference Operation
Figure 5 shows the LTC1746 reference circuitry consisting
of a 2.35V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of 2V(±1V differential) or 3.2V(±1.6V differential). Tying
the SENSE pin to ground selects the 2V range; tying the
SENSE pin to V
DD
selects the 3.2V range.
The 2.35V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry.
An external bypass capacitor of 4.7µF or larger is required
for the 2.35V reference output, V
CM
. This provides a high
frequency low impedance path to ground for internal and
external circuitry. This is also the compensation capacitor
for the reference. It will not be stable without this
capacitor.
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins: REFHA and REFHB
for the high reference and REFLA and REFLB for the low
reference. The doubled output pins are needed to reduce
package inductance. Bypass capacitors must be con-
nected as shown in Figure 5.
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 6a. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device since the logic threshold is close to ground and
V
DD
. The SENSE pin should be tied high or low as close to
the converter as possible. If the SENSE pin is driven
externally, it should be bypassed to ground as close to the
device as possible with a 1µF ceramic capacitor.
V
CM
REFHA
REFLB
SENSE
TIE TO V
DD
FOR 3.2V RANGE;
TIE TO GND FOR 2V RANGE;
RANGE = 2 • V
SENSE
FOR
1V < V
SENSE
< 1.6V
2.35V
REFLA
REFHB
4.7µF
4.7µF
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1µF
1746 F05
LTC1746
4Ω
DIFF AMP
1µF
1µF0.1µF
INTERNAL ADC
LOW REFERENCE
2.35V BANDGAP
REFERENCE
1.6V 1V
RANGE
DETECT
AND
CONTROL
Figure 5. Equivalent Reference Circuit
V
CM
SENSE
2.35V
1.1V
4.7µF
12.5k
1µF
11k
1746 F06a
LTC1746
V
CM
SENSE
2.35V
5V 1.25V64
1, 2
4.7µF
1µF0.1µF
1746 F06b
LTC1746
LT1790-1.25
Figure 6a. 2.2V Range ADC
Figure 6b. 2.5V Range ADC with an External Reference
15
LTC1746
1746f
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Input Range
The input range can be set based on the application. For
oversampled signal processing in which the input fre-
quency is low (<10MHz), the largest input range will
provide the best signal-to-noise performance while main-
taining excellent SFDR. For high input frequencies
(>10MHz), the 2V range will have the best SFDR perfor-
mance but the SNR will degrade by 3.5dB. See the Typical
Performance Characteristics section.
Driving the Encode Inputs
The noise performance of the LTC1746 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
V
DD
LTC1746
1746 F07
BIAS
V
DD
5V
ENC
ENC
ANALOG INPUT
2V BIAS
2V BIAS
1:4
0.1µF
CLOCK
INPUT 50Ω
6k
6k
TO INTERNAL
ADC CIRCUITS
Figure 7. Transformer Driven ENC/ENC with Equivalent Encode Input Circuit
1746 F08a
ENC2V
V
THRESHOLD
= 2V ENC
0.1µF
LTC1746
1746 F08b
ENC
ENC
130Ω
3.3V
3.3V 130Ω
D0
Q0
Q0
MC100LVELT22
LTC1746
83Ω83Ω
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
16
LTC1746
1746f
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Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
The encode inputs have a common mode range of 1.8V to
V
DD
. Each input may be driven from ground to V
DD
for
single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1746 is 25Msps. For
the ADC to operate properly the encode signal should have
a 50% (±5%) duty cycle. Each half cycle must have at least
19ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.
At sample rates slower than 25Msps the duty cycle can
vary from 50% as long as each half cycle is at least 19ns.
The lower limit of the LTC1746 sample rate is determined
by the droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals
on small valued capacitors. Junction leakage will dis-
charge the capacitors. The specified minimum operating
frequency for the LTC1746 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
LTC1746
1746 F09
OV
DD
V
DD
V
DD
0.1µF
43ΩTYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V TO
V
DD
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 9. Equivalent Circuit for a Digital Output Buffer
17
LTC1746
1746f
Output Loading
As with all high speed/high resolution converters the
digital output loading can affect the performance. The
digital outputs of the LTC1746 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Format
The LTC1746 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MSBINV pin; high selects offset binary.
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. When OF outputs a logic high
the converter is either overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. Data
will be updated just after CLKOUT falls and can be latched
on the rising edge of CLKOUT.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 3V
supply then OV
DD
should be tied to that same 3V supply.
OV
DD
can be powered with any voltage up to 5V. The logic
outputs will swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF and
CLKOUT. The data access and bus relinquish times are too
slow to allow the outputs to be enabled and disabled
during full speed operation. The output Hi-Z state is
intended for use during long periods of inactivity.
GROUNDING AND BYPASSING
The LTC1746 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. The pinout of the
LTC1746 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC.
APPLICATIO S I FOR ATIO
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18
LTC1746
1746f
APPLICATIO S I FOR ATIO
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High quality ceramic bypass capacitors should be used at
the V
DD,
V
CM
, REFHA, REFHB, REFLA and REFLB pins as
shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recomended. The large 4.7µF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC1746 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
An analog ground plane separate from the digital process-
ing system ground should be used. All ADC ground pins
labeled GND should connect to this plane. All ADC V
DD
bypass capacitors, reference bypass capacitors and input
filter capacitors should connect to this analog plane. The
LTC1746 has three output driver ground pins, labeled
OGND (Pins 27, 38 and 47). These grounds should con-
nect to the digital processing system ground. The output
driver supply, OV
DD
should be connected to the digital
processing system supply. OV
DD
bypass capacitors should
bypass to the digital system ground. The digital process-
ing system ground should be connected to the analog
plane at ADC OGND (Pin 38).
HEAT TRANSFER
Most of the heat generated by the LTC1746 is transferred
from the die through the package leads onto the printed
circuit board. In particular, ground pins 12, 13, 36 and 37
are fused to the die attach pad. These pins have the lowest
thermal resistance between the die and the outside envi-
ronment. It is critical that all ground pins are connected to
a ground plane of sufficient area. The layout of the evalu-
ation circuit shown on the following pages has a low ther-
mal resistance path to the internal ground plane by using
multiple vias near the ground pins. A ground plane of this
size results in a thermal resistance from the die to ambient
of 35°C/W. Smaller area ground planes or poorly connected
ground pins will result in higher thermal resistance.
19
LTC1746
1746f
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
PACKAGE DESCRIPTIO
U
FW48 TSSOP 0502
0.09 – 0.20
(.0035 – .008)
0° – 8°
0.45 – 0.75
(.018 – .029) 0.17 – 0.27
(.0067 – .0106)
0.50
(.0197)
BSC
6.0 – 6.2**
(.236 – .244)
7.9 – 8.3
(.311 – .327)
134
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
12.4 – 12.6*
(.488 – .496)
1.20
(.0473)
MAX
0.05 – 0.15
(.002 – .006)
2
48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 2547
C.10
-T-
-C-
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
*
**
0.32 ±0.05 0.50 TYP
6.2 ±0.10
8.1 ±0.10
RECOMMENDED SOLDER PAD LAYOUT
0.95 ±0.10
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20
LTC1746
1746f
L INEAR TECHNOLOGY CO RPO R ATION 2003
LT/TP 0903 1K • PRINTED IN THE USA
PART NUMBER DESCRIPTION COMMENTS
LT1019 Precision Bandgap Reference 0.05% Max Initial Accuracy, 5ppm/°C Max Drift
LTC1196 8-Bit, 1Msps Serial ADC 3V to 5V, SO-8
LTC1405 12-Bit, 5Msps, Sampling ADC 5V or ±5V Pin Compatible with the LTC1420
LTC1406 8-Bit, 20Msps ADC Undersampling Capability Up to 70MHz Input
LTC1410 12-Bit, 1.25Msps ADC ±5V, 71dB SINAD
LTC1411 14-Bit, 2.5Msps ADC 5V, No Pipeline Delay, 80dB SINAD
LTC1412 12-Bit, 3Msps, Sampling ADC ±5V, No Pipeline Delay, 72dB SINAD
LTC1414 14-Bit, 2.2Msps ADC ±5V, 81dB SINAD and 95dB SFDR
LTC1415 Single 5V, 12-Bit, 1.25Msps 55mW Power Dissipation, 72dB SINAD
LTC1419 14-Bit, 800ksps ADC ±5V, 95dB SFDR
LTC1420 12-Bit, 10Msps ADC 71dB SINAD and 83dB SFDR at Nyquist
LT1460 Micropower Precision Series Reference 0.075% Accuracy, 10ppm/°C Drift
LTC1604/LTC1608 16-Bit, 333ksps/500ksps ADCs 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
LTC1668 16-Bit, 50Msps DAC 87dB SFDR at 1MHz f
OUT
, Low Power, Low Cost
LTC1740 14-Bit, 6Msps ADC Low Power, 79dB SINAD, 91dB SFDR
LTC1741 12-Bit, 65Msps ADC Pin Compatible with the LTC1746
LTC1742 14-Bit, 65Msps ADC Pin Compatible with the LTC1746
LTC1743 12-Bit, 50Msps ADC Pin Compatible with the LTC1746
LTC1744 14-Bit, 50Msps ADC Pin Compatible with the LTC1746
LTC1745 12-Bit, 25Msps ADC Pin Compatible with the LTC1746
LTC1747 12-Bit, 80Msps ADC Pin Compatible with the LTC1746
LTC1748 14-Bit, 80Msps ADC Pin Compatible with the LTC1746
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
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