Bringing the Best Together
Product Selector Guide
2
3
Lattice Solutions
Bringing the Best Together
Introduction
Lattice Semiconductor, the company that pioneered In-System
Programmability (ISP™), offers the industry’s broadest and
most diverse portfolio of programmable system solutions.
• The world’s rst non-volatile, innitely recongurable
FPGAs: ispXPGA™ family
• ORCA® FPGAs, featuring gate densities up to 899K
system gates with system-level features
• Field Programmable System-on-a-Chip (FPSC) products
provide total communications solutions supporting
features such as high-speed SERDES at up to 3.7Gbps
combined with FPGA gates for customized logic
• Industry leadership Complex PLDs (CPLDs) and 3rd gen-
eration ispXPLD™ devices with on-chip memory
• High performance signal routing and interface,
including the XPIO™ 110GXS low-power 10Gbps trans-
ceiver and ispGDX2™ programmable crosspoint devices
• Programmable analog and mixed-signal products, includ-
ing the ispPAC® Power Manager
• The industry-standard SPLD product portfolio: ispGAL®
and GAL® families
Lattice delivers the industry's broadest offering of ISP solutions.
From FPGAs to innovative programmable analog devices, Lat-
tice offers design engineers the means to reduce time-to-market
and greatly simplify the system design process.
Field Programmable Gate Arrays
The ispXPGA™ (in system programmable eXpanded eld Pro-
grammable Gate Array) family of devices allows the creation of
high-performance logic designs that are both non-volatile and
innitely recongurable. Other FPGA solutions force a com-
promise, being either re-programmable, or recongurable, or
non-volatile. Lattice’s ispXPGA family offers all these capabilities
with a mainstream architecture containing the features required
for today’s system-level design.
ORCA Series 4 FPGAs by Lattice Semiconductor are built on
the familiar Optimized Recongurable Cell Array (ORCA) ar-
chitecture. This FPGA device family offers many features and
architectural enhancements not available in earlier FPGA gener-
ations. Bringing together highly exible SRAM-based program-
mable logic, powerful system features, a rich hierarchy of rout-
ing and interconnect resources, and meeting multiple interface
standards, the ORCA family of FPGAs accommodates the most
complex and high-performance design challenges.
Field Programmable System-on-a-Chip
Lattice Semiconductor pioneered the approach of putting ASIC
macrocells and FPGA gates on the same silicon die. We call this
a Field Programmable System-on-a-Chip (FPSC). Lattice FPSCs
combine FPGA logic with on-chip bus interface and high-speed
SERDES transceiver circuitry. With this combination, Lattice
FPSCs easily support a wide range of high-speed interfaces
including XAUI, Fibre Channel, SONET and XBSI and can be
used in a variety of advanced system designs.
Interface Products
Lattice delivers the high-speed line of ispGDX2 (in-system
programmable Generic Digital Crosspoint) bus switching and
interface products. These exible devices offer low-cost SERDES
solutions and high-performance programmable crossbar switch-
ing. ispGDX2 devices replace discrete transceivers and signi-
cantly reduce the number of board layers.
Lattice also offers the XPIO family of low power, 10Gbps trans-
ceivers supporting SONET OC-192 and 10GE/FC interfaces.
Complex Programmable Logic Devices
Through its optimized portfolio of CPLDs, Lattice delivers
products a generation ahead of other CPLD solutions. These
architectures are optimized to t a variety of CPLD design chal-
lenges. This contrasts to the “one size ts all” approach of other
CPLD vendors.
The ispXPLD 5000MX family combines memory with Lattice’s
SuperWIDE™ architecture and SuperBIG™ density. The
ispXPLD 5000MX family represents a new class of devices
called eXpanded Programmable Logic Devices (XPLDs). These
devices are built around a new building block, the Multi-Func-
tion Block (MFB). MFBs can be individually congured as
SuperWIDE (136-input) logic, single- or dual-port memory,
FIFO, or CAM depending on the application. This architecture
delivers the ultimate PLD exibility through ispXP™.
The ispMACH™ 4000Z family of zero-power CPLDs features
standby currents down to 10µA and are available in the space-
saving Chip Scale BGA (csBGA) packages (6mm x 6mm body
size).
Programmable Analog
The ispPAC® family truly represents a revolution in analog
design. ispPAC delivers all the time-to-market benets of ISP
to the analog world. ispPAC supports precision analog per-
formance and the ability to integrate numerous analog com-
ponents into a single chip. The ispPAC design environment is
fast and easy, allowing rapid prototype development. The new
ispPAC Power Manager family combines programmable analog
and programmable logic to provide optimized power supply
management.
2
3
Design Tools and Intellectual Property
Lattice’s ispLEVER™ software supports exible, top-down de-
sign methodologies optimized for high density design. With
Lattice’s leading-edge software tools, designers can realize the
benets of designing using Hardware Description Languages
(HDLs) without sacricing performance or utilization. The
ispLEVER software supports Lattice ORCA FPGA and FPSC,
ispXPGA, ispXPLD, ispMACH, MACH®, ispLSI®, ispGDX®,
ispGAL, and GAL products. Third-party logic synthesis and
verication tool support is also available to make complex logic
design easier than ever.
With Lattice’s ispVM™ System, in-system programming is made
easy. All Lattice ISP devices may be programmed with the tools
included in the ispVM System. Devices may be programmed
serially or in parallel from a PC or by using the industry’s lead-
ing ATE equipment. Special programming utilities are available
to make embedded programming and reprogramming a reality.
Lattice’s PAC-Designer® software supports all ispPAC devices
and includes schematic entry, lter macros, simulation and pro-
gramming tools.
Lattice and its ispLeverCORE™ Connections partners offer a
wide range of Bus Interface, communications, digital signal
processing, microcontroller and other IP cores to speed the
implementation of complex functions in any design. Hardware
support, including evaluation boards, programming cables and
desktop programmers, is available and designed to provide
complete evaluation, design and programming solutions.
Category Product Family Design Requirements Page
FPGAs and FPSCs
ispXPGA • Mainstream FPGA + 850Mbps SERDES
• Non-Volatile, Instant-on, Innitely Recongurable 4
ORCA 4 • SRAM FPGA
ORCA 2 & 3 • SRAM FPGA 4-5
ORLI10G • 10Gbps Ethernet Line Interface + FPGA
6
ORT82G5 and ORT42G5 • XAUI / FC + FPGA
• 3.7Gbps SERDES, 8/4 Channels
ORSO82G5 and ORSO42G5 • SONET + FPGA
• 2.7Gbps SERDES, 8/4 Channels
ORT8850H/L • SONET + FPGA
• 850Mbps SERDES, 8 Channels
CPLDs
ispXPLD 5000MC/B/V • CPLD + Memory / FIFO
• Innitely Recongurable, Multiple I/O Standards
8
ispMACH 4000C/B/V • High-Perfomance Mainstream CPLD
• Industry’s Highest Perfomance (tPD = 2.5ns)
ispMACH 4000Z • Zero-Power, Mainstream CPLD
• Lowest Priced CPLD
ispMACH 5000B • SuperWIDE, High-Performance CPLD, Multiple I/O Standards
9
ispLSI 5000VE • SuperWIDE, High-Performance CPLD
ispMACH 4A5 • Mainstream CPLD
SPLDs
ispGAL • In System Programmable SPLD
• World’s Fastest PLD at 2.3ns tPD 10
GAL • Industry Standard SPLD Architectures
Interface
XPIO • 10Gbps Low Power Transceiver
7
ispGDX2 • High Speed Programmable Crossbar Switch
• 850Mbps SERDES, Multiple I/O Standards
ispGDX/V • Programmable Crossbar Switch
Programmable
Mixed Signal / Analog
ispPAC Power Manager
• Programmable Analog + Digital
• Power Supply Sequencing and Monitoring
• Manages Multiple Power Supplies 12
ispPAC • Programmable Analog
Automotive
ispMACH 4000V/Z • Mainstream CPLDs 8, 11
ispPAC Power Manager • Power Supply Sequencing and Monitoring 11, 12
Military
ispLSI 1000 • Mainstream CPLD
11
GAL • Mainstream SPLDs
Design Tools, Hardware and
Intellectual Property All Device Families
• Software
• Evaluation Boards
• Programming Cables/Hardware
• Intellectual Property Cores
12-15
Quick Reference Guide
4
FPGA Products
5
FPGA Products
ORCA OR4E (1.5V) Family — SRAM-based FPGAs
Speed Grade
(Fastest to Slowest) Package (I/O)
FPGA System Gates
(K)
LUTs
Registers
Distributed RAM Bits
(K)
EBR RAM Blocks
EBR RAM Bits (K)
PLLs
High Speed I/O
IEEE1149.1
Boundary Scan Test
I/O Standards
-3 -2 -1*
BA352
35x35
1.27mm
BM416
27x27
1.0mm
BM680
40x40
1.0mm
352-ball
PBGA
416-ball
PBGAM
680-ball
PBGAM
OR4E02 *262 290 405 201-397 4,992 6,816 80 8 74 8 3.3/2.5/1.8/1.5V: LVTTL, LVCMOS2.5/
1.8, PCI3.3, GTL, GTL+, HSTL I/III/IV,
SSTL2I/II, SSTL3I/II, LVDS, BLVDS,
PECL, LVPECL
OR4E04 *262 290 466 333-643 10,368 13,392 166 12 111 8
OR4E06 262 466 471-899 16,192 20,376 259 16 148 8
*Available in industrial grade.
ORCA OR3L (2.5V) Family — SRAM-based FPGAs
Speed Grade Package (I/O)
Usable Gates (K)
LUTs
Registers
Max User Ram (K)
IEEE1149.1
Boundary Scan Test
I/O Standards
-8 -7* PS208
28x28,
0.5mm
PS240
32x32
0.5mm
BA352
35x35
1.27mm
BC432
40x40
1.27mm
BM680
40x40
1.0mm
16-Bit
Counter
(MHz)
176 151
208-pin
SQFP2
240-pin
SQFP2
352-ball
PBGA
432-ball
EBGA
680-ball
PBGAM
OR3L165B 162 184 286 326 442 120-244 8,192 10,752 131 5/3.3/2.5V: TTL, LVTTL,
LVCMOS3.3/2.5, PCI3.3
OR3L225B 326 442 166-340 11,552 14,820 185
*Available in industrial grade.
ORCA OR3T (3.3V) and OR3C (5V) Families — SRAM-based FPGAs
Speed Grade Package (I/O)
Usable Gates (K)
LUTs
Registers
Max User Ram (K)
IEEE1149.1
Boundary Scan Test
I/O Standards
-7 -6* -5 -4* S208
28x28
0.5mm
PS208
28x28
0.5mm
S240
32x32
0.5mm
PS240
32x32
0.5mm
F256
17x17
1.0mm
BA352
35x35
1.0mm
BC432
40x40
1.27mm
BM680
40x40
1.0mm
16-Bit
Counter
(MHz)
168 131 102 78
208-pin
SQFP
208-pin
SQFP2
240-pin
SQFP
240-pin
SQFP2
256-ball
PBGA
352-ball
PBGA
432-ball
EBGA
600-ball
EBGA
OR3T20 171 192 192 192 36 1,152 1,872 18
5/3.3V:
TTL, LVTTL,
LVCMOS3.3/2.5,
PCI3.3
OR3T30 171 192 221 48 1,568 2,436 25
OR3T55 171 192 223 288 80 2,592 3,780 42
OR3T80 171 192 298 342 116 3,872 5,412 62
OR3T125 171 192 298 342 448 186 6,272 8,400 100
OR3C80 171 192 298 116 3,872 5,412 62
*Available in industrial grade.
ispXPGA Family (C (1.8V) or B (2.5V/3.3V)) — Non-volatile, Recongurable FPGAs + SERDES
Speed Grade
(Fastest to Slowest) Package (I/O)
System Gates
PFUs
LUT-4
Logic FFs
sysMEM Memory
Distributed Memory
EBR RAM Blocks
sysHSI Channels
SERDES
PLLs
ISP Programming
I/O Standards
-5*** -4** -3*
F256
17x17
1.0mm
FH516
31x31
1.0mm
FE680
40x40
1.0mm
F900
31x31
1.0mm
256-ball
fpBGA
516-ball
fpBGA
680-ball
fpSBGA
900-ball
fpBGA
LFX125C/B 160 176 139K 484 1,936 3.8K 92K 30K 20 4 8 ispXP 5/3.3/2.5/1.8V:
LVTTL, LVCMOS
3.3/2.5/1.8, PCI3.3,
GTL+, HSTL I/III,
SSTL2/3, AGP-1X,
CTT 3.3/2.5, LVDS,
BLVDS, LVPECL
LFX200C/B 160 208 210K 676 2,704 5.4K 111K 43K 24 8 8 ispXP
LFX500C/B 336 336 476K 1,764 7,056 14.1K 184K 112K 40 12 8 ispXP
LFX1200C/B 496 496 1.25M 3,844 15,376 30.7K 414K 246K 90 20 8 ispXP
*Available in industrial grade.
**Available in industrial grade in “B” version only.
***Available in “B” version only.
4
FPGA Products
5
FPGA Products
ORCA OR2T (3.3V) Family — SRAM-based FPGAs
Speed Grade Package (I/O)
Usable Gates (K)
LUTs
Registers
Max User RAM (K)
IEEE1149.1
Boundary Scan Test
I/O Standards
-8 -7 -7* -6* -5 -4* M84
29.2x29.2
1.27mm
T100
14x14
0.5mm
T144
20x20
0.5mm
J160
28x28
0.65mm
S208
28x28
0.5mm
PS208
28x28
0.5mm
S240
32x32
0.5mm
PS240
32x32
0.5mm
BA256
27x27
1.27mm
BA352
35x35
1.27mm
BC432
45x45
1.27mm
16-Bit
Counter
(MHz)
149 145 132 130 104 87
84-pin
PLCC
100-pin
TQFP
144-pin
TQFP
160-pin
QFP
208-pin
SQFP
208-pin
SQFP2
240-pin
SQFP
240-pin
SQFP2
256-ball
PBGA
352-ball
PBGA
432-ball
EBGA
OR2T04A 74 110 152 11 400 400 6.4
5/3.3V:
TTL,
LVTTL,
LVCMOS
3.3/2.5,
PCI3.3
OR2T08A 62 126 163 184 209 22 784 784 12.5
OR2T10A 62 126 163 184 209 28 1,024 1,024 16.4
OR2T15A 62 163 163 184 184 211 286 44 1,600 1,600 25.6
OR2T15B 171 192 223 298 44 1,600 1,600 25.6
OR2T26A 163 184 286 326 64 2,304 2,304 36.9
OR2T40A 163 184 286 326 99 3,600 3,600 57.6
OR2T40B 171 298 342 99 3,600 3,600 57.6
*Available in industrial grade.
ORCA OR2C (5.0V) Family — SRAM-based FPGAs
Speed
Grade Package (I/O)
Usable Gates (K)
LUTs
Registers
Max User RAM (K)
IEEE1149.1
Boundary Scan Test
I/O Standards
-4 -3* M84
29.2x29.2
1.27mm
T100
14x14
0.5mm
T144
20x20
0.5mm
J160
28x28
0.65mm
S208
28x28
0.5mm
PS208
28x28
0.5mm
S240
32x32
0.5mm
PS240
32x32
0.5mm
BA256
27x27
1.27mm
S304
40x40
0.5mm
PS304
40x40
0.5mm
BA352
35x35
1.27mm
BC432
45x45
1.27mm
16-Bit
Counter
(MHz)
87 67
84-pin
PLCC
100-pin
TQFP
144-pin
TQFP
160-pin
QFP
208-pin
SQFP
208-pin
SQFP2
240-pin
SQFP
240-pin
SQFP2
256-ball
PBGA
304-pin
SQFP
304-pin
SQFP2
352-ball
PBGA
432-ball
EBGA
OR2C04A 64 77 114 130 160 11 400 400 6.4
5/3.3V:
TTL,
LVTTL,
LVCMOS
3.3/2.5,
PCI3.3
OR2C06A 64 77 114 130 171 192 192 16 576 576 9.2
OR2C08A 64 130 171 192 22 784 784 12.5
OR2C10A 64 130 171 192 221 256 28 1,024 1,024 16.4
OR2C12A 64 171 192 223 252 288 36 1,296 1,296 20.7
OR2C15A 64 171 171 192 192 223 252 298 44 1,600 1,600 25.6
OR2C26A 171 192 252 298 342 64 2,304 2,304 36.9
OR2C40A 171 192 252 342 99 3,600 3,600 57.6
*Available in industrial grade.
6
FPSC Products
7
Interface Products
ORLI10G (1.5V) Family — 10 Gbit Ethernet Line Interface + FPGA
Speed Grade
(Fastest to Slowest)
Package
(I/O)
FPGA System Gates
(K)
LUTs
Registers
Distributed RAM Bits
(K)
EBR RAM Blocks
EBR RAM Bits (K)
PLLs
High Speed I/O
Max Parallel I/O
Data Rate
# High Speed I/Os
SERDES
IEEE1149.1
Boundary Scan Test
I/O Standards
-3 -2* -1*
BM680
35x35
1.0mm
680-ball
PBGAM
ORLI10G 316 333-643 10,368 12,960 166 12 111 4 850Mbps 16 –
3.3/2.5/1.8/1.5V: LVTTL,
LVCMOS2.5/1.8, PCI3.3,
GTL, GTL+, HSTL I/III/IV,
SSTL2I/II, SSTL3I/II, LVDS,
BLVDS, PECL, LVPECL
*Available in Industrial Grade
ORT82G5 / ORT42G5 (1.5V) Family — 3.7Gbps SERDES + XAUI / FC + FPGA
Speed Grade
(Fastest to Slowest) Package (I/O)
FPGA System Gates
(K)
LUTs
Registers
Distributed RAM Bits
(K)
EBR RAM Blocks
EBR RAM Bits (K)
PLLs
High Speed I/O
Max Serial
Data Rate
# Channels
SERDES
IEEE1149.1
Boundary Scan Test
I/O Standards
-3 -2* -1*
BM484
23x23
1.0mm
BM680
35x35
1.0mm
484-ball
PBGAM
680-ball
PBGAM
ORT82G5 372 333-643 10,368 12,912 166 12 111 4 3.7Gbps 8 3.3/2.5/1.8/1.5V: LVTTL,
LVCMOS2.5/1.8, PCI3.3,
GTL, GTL+, HSTL I/III/IV,
SSTL2I/II, SSTL3I/II, LVDS,
BLVDS, PECL, LVPECL
ORT42G5 204 333-643 10,368 12,912 166 12 111 4 3.7Gbps 4
*Available in industrial grade.
ORSO82G5 / ORSO42G5 (1.5V) Family — 2.7Gbps SERDES + SONET + FPGA
Speed Grade
(Fastest to Slowest) Package (I/O)
FPGA System Gates
(K)
LUTs
Registers
Distributed RAM Bits
(K)
EBR RAM Blocks
EBR RAM Bits (K)
PLLs
High Speed I/O
Max Serial
Data Rate
# Channels
SERDES
IEEE1149.1
Boundary Scan Test
I/O Standards
-3 -2* -1*
BM484
23x23
1.0mm
BM680
35x35
1.0mm
484-ball
PBGAM
680-ball
PBGAM
ORSO82G5 372 333-643 10,368 12,912 166 12 111 4 2.7Gbps 8 3.3/2.5/1.8/1.5V: LVTTL,
LVCMOS2.5/1.8, PCI3.3,
GTL, GTL+, HSTL I/III/IV,
SSTL2I/II, SSTL3I/II, LVDS,
BLVDS, PECL, LVPECL
ORSO42G5 204 333-643 10,368 12,912 166 12 111 4 2.7Gbps 4
*Available in industrial grade.
ORT8850 (1.5V) Family — 850Mbps SERDES + SONET + FPGA
Speed Grade
(Fastest to Slowest)
Package
(I/O)
FPGA System Gates
(K)
LUTs
Registers
Distributed RAM Bits
(K)
EBR RAM Blocks
EBR RAM Bits (K)
PLLs
High Speed I/O
Max Serial Data Rate
# Channels
SERDES
IEEE1149.1
Boundary Scan Test
I/O Standards
-3 -2 -1*
BM680
35x35
1.0mm
680-ball
PBGAM
ORT8850L *278 201-397 4,992 6,504 80 8 74 4 850Mbps 8 3.3/2.5/1.8/1.5V: LVTTL,
LVCMOS2.5/1.8, PCI3.3,
GTL, GTL+, HSTL I/III/IV,
SSTL2I/II, SSTL3I/II, LVDS,
BLVDS, PECL, LVPECL
ORT8850H 297 471-899 16,192 19,824 259 16 148 4 850Mbps 8
*Available in industrial grade.
6
FPSC Products
7
Interface Products
XPIO (1.3V) Transceiver Family — Low-Power, 10Gbps Interface
Package
Supported
Data Rates
(Gbps)
# of
Channels
Power
Consumption I/O Voltage
Protocols
Supported
Standard
Compliance Key Features
CF269
15x15
0.8mm
269-ball
fcBGA
LS110GXS 9.95, 10.31, 10.52,
10.66, 10.71 1 0.8W 2.5V
SONET OC-192, 10GE,
10GFC, OCI-192 FEC,
G.709 FEC
GR-253,
IEEE 802.3ae
& XFP
• XSBI/SFI4.1 Support
• 16-bit LVDS parallel interface
• Ultra-low jitter
ispGDX2 – C/B/V (1.8V/2.5V/3.3V) Family — Programmable SERDES + Interconnect
Speed Grade Package (I/O)
I/O
GDX Blocks
Max. Bandwidth
Gbps (SERDES)
Max. Bandwidth
Gbps (w/o SERDES)
LVDS/Bus LVDS
(pairs)
850 Mbps Duplex
SERDES Channels
PLLs
ISP Programming
IEEE1149.1 Bound-
ary Scan Test
I/O Standards
-3 -32 -5** F100
11x11
1.0mm
B208
17x17
1.0mm
F484
23x23
1.0mm
tPD(ns) 3 3.2 5
100-ball
fpBGA
208-ball
fpBGA
484-ball
fpBGA
fMAX(MHz) 330 312 180
LX64C/B/V* 64 64 4 3.5 11 32 4 2 5/3.3/2.5/1.8V: LVTTL, LVCMOS 3.3/
2.5/1.8, PCI3.3, PCI-X, GTL+, HSTL
I/III/IV, SSTL2I/II, SSTL3I/II, AGP-1X,
CTT33/25, LVDS, BLVDS, LVPECL
LX128C/B/V* 128 128 8 7 21 64 8 2
LX256C/B/V 256 256 16 13.6 38 128 16 4
*Advance information, contact factory for availability.
**Available in industrial grade.
ispGDXV (3.3V) Family — Programmable Interface + Interconnect
Speed Grade Package (I/O)
I/O
Dedicated Clocks
ISP Programming
IEEE1149.1 Bound-
ary Scan Test
I/O Standards
-3 -3 -4 -5* -7* -9* -10* T100
14x14
0.5mm
Q208
28x28
0.5mm
B208
17x17
1.0mm
B272
27x27
1.27mm
B388
35x35
1.27mm
tPD(ns) 3 3.5 4.5 5 7 9 10
100-pin
TQFP
208-pin
PQFP
208-ball
fpBGA
272-ball
BGA
388-ball
BGA
fMAX(MHz) 250 250 200 143 100 83 71
ispGDX80VA 80 80 2 JTAG 5/3.3/2.5V:
TTL, LVTTL,
PCI3.3
ispGDX160VA 160 160 160 160 4 JTAG
ispGDX240VA  240 240 4 JTAG
*Available in industrial grade.
ispGDX (5V) Family — Programmable Interface + Interconnect
Speed Grade Package (I/O)
I/O
Dedicated Clocks
ISP Programming
IEEE1149.1
Boundary Scan Test
I/O Standards
-5 -7 T100
14x14
0.5mm
Q160
28x28
0.65mm
T176
24x24
0.5mm
Q208
28x28
0.5mm
B272
27x27
1.27mm
tPD(ns) 5 7
100-pin
TQFP
160-pin
PQFP
176-pin
TQFP
208-pin
PQFP
272-ball
BGA
fMAX(MHz) 143 100
ispGDX80A 80 80 2 ISP/ JTAG -
5V:
TTL
ispGDX120A 120 120 120 4 ISP/ JTAG -
ispGDX160A 160 160 160 4 ISP/ JTAG -
8
CPLD Products
9
CPLD Products
ispXPLD 5000MC/B/V (1.8V/2.5V/3.3V) Family — High-Density CPLD + Memory
Speed Grade Package (I/O)
Macrocells
System Gates (K)
Memory (kbit)
PLLs
ISP Programming
I/O Standards
-4 -45 -5* -52 -75* Q208
28x28
0.5mm
F256
17x17
1.0mm
F484
23x23
1.0mm
F672
27x27
1.0mm
tPD(ns) 4.0 4.5 5.0 5.2 7.5
208-pin PQFP
256-ball fpBGA
484-ball fpBGA
672-ball fpBGA
tS(ns) 2.2 2.9 3.0 3.0 4.9
tCO(ns) 2.8 3.0 3.8 3.8 5.0
fMAX(MHz) 300 250 240 235 150
LC5256MC/B/V  141 256 75 128 2 ispXP
5/3.3/2.5/1.8V:
LVCMOS3.3/2.5/1.8, SSTL2I/II,
SSTL3I/II, HSTLI/III/IV,
PCI3.3, GTL+, LVDS, LVPECL, LVTTL
LC5512MC/B/V 149 193 253 512 150 256 2 ispXP
LC5768MC/B/V** 193 317 768 225 384 2 ispXP
LC51024MC/B/V 317 381 1024 300 512 2 ispXP
*Available in industrial grade.
** Advance information, contact factory for availability.
ispMACH 4000C/B/V (1.8V/2.5V/3.3V) Family — Highest Speed, Lowest Power CPLDs
Speed Grade Package (I/O + Dedicated Inputs)
Macrocells
Total Registers
ISP Programming
IEEE1149.1 Boundary Scan
Test
Typical Icc (mA)
I/O Standards
-25 -27 -3 -35 -5* -75* -10** T44
10x10
0.8mm
T48
7x7
0.5mm
T100
14x14
0.5mm
T128
14x14
0.4mm
T144***
20x20
0.4mm
T176
24x24
0.5mm
F256
17x17
1.0mm
tPD(ns) 2.5 2.7 3.0 3.5 5.0 7.5 10.0
44-pin TQFP
48-pin TQFP
100-pin TQFP
128-pin TQFP
144-pin TQFP
176-pin TQFP
256-ball fpBGA
tS(ns) 1.8 1.8 2.0 2.0 3.0 4.5 5.5
tCO(ns) 2.2 2.7 2.7 2.7 3.4 4.5 6.0
fMAX(MHz) 400 333 322 322 227 168 125
LC4032C/B/V 30 + 2 32 + 4 32 32 JTAG 1.3
5/3.3/2.5/1.8V:
LVTTL,
LVCMOS3.3,
Extended
LVCMOS3.3,
LVCMOS2.5/
1.8, PCI3.3
LC4064C/B/V 30 + 2 32 + 4 64 + 10 64 64 JTAG 1.5
LC4128C/B/V 64 + 10 92 + 4 96 + 4 128 128 JTAG 1.5
LC4256C/B/V 64 + 10 96 + 4 128 + 4 128 + 4
160 + 4 256 256 JTAG 2.0
LC4384C/B/V 128 + 4 192 + 4 384 384 JTAG 2.5
LC4512C/B/V 128 + 4 208 + 4 512 512 JTAG 3.0
*Available in industrial grade.
** Available in Industrial Grade Only
*** 3.3V (4000V) Only
ispMACH 4000Z (1.8V) Family — Zero Power, High Speed CPLDs
Speed Grade Package (I/O + Dedicated Inputs)
Macrocells
Total Registers
ISP Programming
IEEE1149.1 Boundary
Scan Test
Typical Static Icc (µA)
I/O Standards
-35 -37 -42 -5* -75** M56
6x6
0.5mm
M132
8x8
0.5mm
T48
7x7
0.5mm
T100
14x14
0.5mm
T176
24x24
0.5mm
tPD(ns) 3.5 3.7 4.2 5.0 7.5
56-ball csBGA
132-ball csBGA
48-pin TQFP
100-pin TQFP
176-pin TQFP
tS(ns) 2.2 2.7 2.7 3.0 4.5
tCO(ns) 3.0 3.2 3.9 4.2 4.5
fMAX(MHz) 265 250 220 200 150
LC4032ZC 32 + 4 32 + 4 32 32 JTAG 10
5/3.3/2.5/1.8V:
LVTTL, LVCMOS3.3,
Extended LVCMOS3.3,
LVCMOS2.5/1.8, PCI3.3
LC4064ZC 32 + 12 64 + 10 32 + 4 64 + 10 64 64 JTAG 11
LC4128ZC 96 + 4 64 + 10 128 128 JTAG 12
LC4256ZC*** 96 + 6 64 + 10 128 + 4 256 256 JTAG tbd
*Available in industrial grade.
**Available in Industrial in Automotive Grades
***Advance information, contact factory for availability.
8
CPLD Products
9
CPLD Products
ispMACH 5000B (2.5V) Family — SuperWIDE, High Performance CPLDs
Speed Grade Package (I/O)
Macrocells
Total Registers
ISP Programming
IEEE1149.1 Boundary
Scan Test
Typical Icc (mA)
I/O Standards
-3 -4 -45 - 5* -75* -10* -12** T128
14x14
0.4mm
Q208
28x28
0.5mm
F256
17x17
1.0mm
F484
23x23
1.0mm
tPD(ns) 3.0 4.0 4.5 5.0 7.5 10.0 12.0
128-pin TQFP
208-pin PQFP
256-ball fpBGA
484-ball fpBGA
tS(ns) 1.7 2.1 2.5 3.0 5.0 6.5 7.5
tCO(ns) 2.2 2.7 2.8 3.0 4.0 5.5 6.5
fMAX(MHz) 275 250 200 180 150 110 90
LC5128B 92 128 128 JTAG 83 3.3/2.5/1.8V:
LVTTL, LVCMOS3.3/2.5/1.8,
SSTL2I/II, SSTL3I/II, CTT3.3, CTT2.5,
HSTLI/III, PCI3.3, GTL+, AGP-1X,
LVDS (clock input), LVPECL (clock
input)
LC5256B 92 144 144 256 256 JTAG 130
LC5384B 156 186 384 384 JTAG 216
LC5512B 156 196 256 512 512 JTAG 270
*Available in industrial grade.
**Available in industrial grade only.
ispLSI 5000VE (3.3V) Family — SuperWIDE, High Performance CPLDs
Speed Grade Package (I/O)
Macrocells
Total Registers
ISP Programming
IEEE1149.1 Boundary
Scan Test
Typcal Static Icc (mA)
Low Power / High Speed
I/O Standards
-180 -165 -155 -125* -100* - 80** LT100
14x14
0.5mm
LT128
14x14
0.4mm
LF256
17x17
1.0mm
LB272
27x27
1.27mm
LF388
23x23
1.0mm
LB388
35x35
1.27mm
tPD(ns) 5 6 6.5 7.5 10 12
100-pin TQFP
128-pin TQFP
256-ball fpBGA
272-ball BGA
388-ball fpBGA
388-ball BGA
tSU(ns) 3.5 4 4.5 5 7 8
tCOS(ns) 3 3 3.5 4.5 6 7
fMAX(MHz) 180 165 155 125 100 80
ispLSI 5128VE 96 128 128 JTAG 100/113
5/3.3/2.5V:
TTL, LVTTL
ispLSI 5256VE 72 96 144 144 256 256 JTAG 150/180
ispLSI 5384VE 192 144 384 384 JTAG 225/255
ispLSI 5512VE 192 192 256 256 512 512 JTAG 290/325
*Available in industrial grade.
**Available in industrial grade only.
ispMACH 4A5 (5V) Family — High Performance CPLDs
Speed Grade Package (I/O + Dedicated Inputs)
Macrocells
Total Registers
ISP Programming
IEEE1149.1 Boundary
Scan Test
Typical Icc (mA)
I/O Standards
-5 -55 - 6 - 65 -7* -10* -12** JC
16.5x16.5
1.27mm
VC
10x10
0.8mm
VC 48
7x7
0.5mm
YC
14x20
0.65mm
VC
14x14
0.5mm
VC
20x20
0.5mm
YC
28x28
0.5mm
tPD(ns) 5 5.5 6 6.5 7.5 10 12
44-pin PLCC
44-pin TQFP
48-pin TQFP
100-pin PQFP
100-pin TQFP
144-pin TQFP
208-pin PQFP
tSS(ns) 3 3.5 3.5 3.5 5 5.5 7
tCOS(ns) 4 4 4.5 5 5.5 6 6.5
fMAX(MHz) 182 167 160 154 125 118 95
M4A5-32/32 32+2 32+2 32+2 32 32 JTAG 20
5/3.3V:
LVTTL,
TTL,
PCI3.3
M4A5-64/32 32+2 32+2 32+2 64 96 JTAG 25
M4A5-96/48 48+8 96 144 JTAG 40
M4A5-128/64 64+6 64+6 128 192 JTAG 55
M4A5-192/96 96 +16 192 288 JTAG 85
M4A5-256/128 128 +14 256 384 JTAG 100
*Available in industrial grade.
**Available in industrial grade only.
Note: All ispMACH 4A devices have SpeedLocked™ performance at <=20 product terms per output.
10
SPLD Products
11
Automotive / Military Products
ispGAL Family — In-System Programmable PLDs
Commercial
Industrial
20-pin PLCC
20-pin PDIP
24-pin PDIP
28-pin PLCC
28-pin PDIP
28-pin SSOP
32-pin QFN
Tpd
(ns)
Fmax
(MHz)
Icc Typ
(mA)
Icc Max
(mA) I/Os Dedicated
Inputs
MAX. PT
per Output Features
ispGAL
22V10AC
ispGAL22V10AC-23L 2.3 455 0.15* 80
10 11 8-16
1.8V In-System
Programmable
22V10
ispGAL22V10AC-28L 2.8 357 0.15* 80
ispGAL22V10AC-5L 5 200 0.15* 80
ispGAL22V10AC-75L 7.5 166 0.15* 80
ispGAL
22V10AB
ispGAL22V10AB-23L 2.3 455 7* 90
10 11 8-16
2.5V In-System
Programmable
22V10
ispGAL22V10AB-28L 2.8 357 7* 90
ispGAL22V10AB-5L 5 200 7* 90
ispGAL22V10AB-75L 7.5 166 7* 90
ispGAL
22V10AV
ispGAL22V10AV-23L 2.3 455 7* 90
10 11 8-16
3.3V In-System
Programmable
22V10
ispGAL22V10AV-28L 2.8 357 7* 90
ispGAL22V10AV-5L 5 200 7* 90
ispGAL22V10AV-75L 7.5 166 7* 90
ispGAL
22V10
ispGAL22V10C-7L 7.5 111 90 140
10 11 8-16
5V In-System
Programmable
22V10
ispGAL22V10C-10L 10 105 90 140
ispGAL22V10C-15L 15 83.3 90 140
ispGAL
22LV10
ispGAL22LV10-4L 4 250 90 130
10 11 8-16
3.3V In-System
Programmable
22V10
ispGAL22LV10-5L 5 200 90 130
ispGAL22LV10-7L 7.5 166 90 130
ispGAL22LV10-10L 10 111 90 130
ispGAL22LV10-15L 15 83.3 90 130
*Typical standby current
CMOS GAL Families — World's Fastest and Lowest Power PLDs
20-pin PLCC
20-pin PDIP
24-pin PDIP
28-pin PLCC
28-pin PDIP
-3 -4 -5 -7 -10 -15 -20 -25 -30 Tpd
(ns)
Fmax
(MHz)
Icc Max
(mA) I/Os Dedicated
Inputs Features
GAL16V8 ***** * 3.5 - 25 250 - 41.6 55 - 115 8 8 Half & Quarter Power
GAL16LV8 3.5 - 15 250 - 62.5 65 3.3V
GAL20V8 **** 5 - 25 166 - 41.6 55 - 115 8 12 Half & Quarter Power
GAL20LV8 3.5 - 7.5 250 - 125 70 3.3V
GAL22V10 ****** * 4 - 25 250 - 38.5 55 - 150 10 12 Half & Quarter Power
GAL22LV10 4 - 15 250 - 83 75 - 130 3.3V
GAL18V10 7.5 - 20 111 - 62.5 115 10 8 22V10 Subset
GAL20RA10 * 7.5 - 30 83.3 - 25 100 10 10 Asynchronous Clock
GAL26V12 *** 7.5 - 20 142.8 - 62.5 105 - 130
12 14
22V10 Superset
GAL26CV12 ** ** 7.5 - 20 142.8 - 62.5 130 - 150 22V10 Superset
GAL26CLV12 5 - 7.5 200 - 142 130 3.3V
*Available in industrial grade.
** Available in industrial grade only.
10
SPLD Products
11
Automotive / Military Products
Automotive Temperature Grade (-40 to 125°C T
A) Devices
Speed Grade Package (I/O + Dedicated Inputs)
Macrocells
Total Registers
ISP Programming
IEEE1149.1 Boundary Scan
Test
Typical Static Icc
I/O Standards
-75 -75 T44 T48 T100 T128 T144 T176
tPD(ns) 7.5 7.5
44-pin TQFP
48-pin TQFP
44TQFP
100-pin TQFP
128-pin TQFP
144-pin TQFP
176-pin TQFP
tS(ns) 4.5 4.5
tCO(ns) 4.5 4.5
fMAX(MHz) 168 150
LC4032V (3.3V) 30 + 2 32 + 4 32 32 JTAG 11.3mA
5/3.3/2.5/1.8V:
LVTTL, LVCMOS3.3,
Extended
LVCMOS3.3,
LVCMOS2.5/1.8,
PCI3.3
LC4064V (3.3V) 30 + 2 32 + 4 64 + 10 64 64 JTAG 11.5mA
LC4128V (3.3V) 64 + 10 92 + 4 96 + 4 128 128 JTAG 11.5mA
LC4256V (3.3V) 64 + 10 96 + 4 128 + 4 256 256 JTAG 12mA
LC4032ZC (1.8V)* 32 + 4 32 32 JTAG 22µA
LC4064ZC (1.8V)* 32 + 4 64 + 10 64 64 JTAG 37µA
LC4128ZC (1.8V)* 64 + 10 128 128 JTAG 42µA
LC4256ZC (1.8V)* 64 + 10 128 + 4 256 256 JTAG tbd
ispPAC-POWR1208 See page 12 for ispPAC-POWER1208/604 details.
ispPAC-POWR604
*Advance information, contact factory for availability.
CPLD Military Grade Products (883 Qualied / 5V)
Part # SMD # Macrocells I/O tPD(ns) fMAX(MHz) ICC Package
Typ (mA) Max (mA)
ispLSI 1016 ispLSI 1016-60LH/883 5962-9476201MXC 64 32 20 60 100 170 44-Pin JLCC
ispLSI 1024 ispLSI 1024-60LH/883 5962-9476101MXC 96 48 20 60 135 220 68-Pin JLCC
ispLSI 1032 ispLSI 1032-60LG/883 5962-9308501MXC 128 64 20 60 135 220 84-Pin CPGA
ispLSI 1048C ispLSI 1048C-50LG/883 5962-9558701MXC 192 96 22 50 165 235 133-Pin CPGA
SPLD Military Grade Products (883 Qualied / 5V)
Part # SMD # tPD(ns) fMAX(MHz) ICC Package
Typ (mA) Max (mA)
GAL16V8
GAL16V8D-7LD/883 5962-8983907RA 7.5 100 75 130 20-Pin CERDIP
GAL16V8D-7LR/883 5962-89839072A 7.5 100 75 130 20-Pin LCC
GAL16V8D-10LD/883 5962-8983904RA 10 62.5 75 130 20-Pin CERDIP
GAL16V8D-10LR/883 5962-89839042A 10 62.5 75 130 20-Pin LCC
GAL16V8D-15LD/883 5962-8983903RA 15 50 75 130 20-Pin CERDIP
GAL16V8D-15LR/883 5962-89839032A 15 50 75 130 20-Pin LCC
GAL16V8D-20LD/883 5962-8983902RA 20 41.6 75 130 20-Pin CERDIP
GAL16V8D-20LR/883 5962-89839022A 20 41.6 75 130 20-Pin LCC
GAL16V8D-30LD/883 5962-8983901RA 30 33.3 75 130 20-Pin CERDIP
GAL20V8
GAL20V8B-10LD/883 5962-8984004LA 10 62.5 75 130 24-Pin CERDIP
GAL20V8B-10LR/883 5962-89840043A 10 62.5 75 130 28-Pin LCC
GAL20V8B-15LD/883 5962-8984003LA 15 50 75 130 24-Pin CERDIP
GAL20V8B-15LR/883 5962-89840033A 15 50 75 130 28-Pin LCC
GAL20V8B-20LD/883 5962-8984002LA 20 41.6 75 130 24-Pin CERDIP
GAL20V8B-20LR/883 5962-89840023A 20 41.6 75 130 28-Pin LCC
GAL22V10
GAL22V10D-10LD/883 5962-8984106LA 10 166 90 150 24-Pin CERDIP
GAL22V10D-10LR/883 5962-89841063A 10 166 90 150 28-Pin LCC
GAL22V10D-15LD/883 5962-8984103LA 15 62.5 90 150 24-Pin CERDIP
GAL22V10D-15LR/883 5962-89841033A 15 62.5 90 150 28-Pin LCC
GAL22V10D-20LD/883 5962-8984102LA 20 33 90 150 24-Pin CERDIP
GAL22V10D-20LR/883 5962-89841023A 20 33 90 150 28-Pin LCC
GAL22V10D-25LD/883 5962-8984104LA 25 33 90 150 24-Pin CERDIP
GAL22V10D-30LD/883 5962-8984101LA 30 25 90 150 24-Pin CERDIP
12
Analog Products
13
Development Tools
ispPAC Power Manager Family – Optimized Power Supply Management
Programmable
Sense Inputs
Supervisory
Outputs
FET Drivers/
Digital Outputs
Reprogrammable
Timers
CPLD
Macrocells
Power Supply
Voltage Packaging
Temp. Range
Ind. Auto.
ispPAC-POWR1208 12 (1V - 5.7V) 4 4 4 16 2.25V - 5.5V 44-pin TQFP
ispPAC-POWR604 6 (1V - 5.7V) 4 – 2 8 2.25V - 5.5V 44-pin TQFP
ispPAC Power Manager Family – Applications
Power
Supply
Sequencing
Tracking Softstart
Monotonic
Supply
Ramp
Reset
Generation
Push Button
Reset Input
Over &
Under
Voltage
Indication
Watchdog
Timer
Number of
Supplies
Monitored
Number
of Control
Outputs
ispPAC-POWR1208 12 8
ispPAC-POWR604 6 4
ispPAC Family – Programmable Analog Circuits
Max Bandwidth Precision Filter
Range Input Voltage Range Programmable Gain
Range
Conguration
Memory Packaging
ispPAC10 550 kHz 10 kHz - 100 kHz 1 V - 4 V 0 - 10,000 V/V
Step 1 V/V EEPROM 28-pin PDIP
28-pin SOIC
ispPAC20 550 kHz 10 kHz - 100 kHz 1 V - 4 V 0 - 400 V/V
Step 1 V/V EEPROM 44-pin PLCC
44-pin TQFP
ispPAC30 1.5 MHz 49 kHz - 1.57 MHz 0 V - 2.8 V 0 - 42 V/V
Step 0.008 V/V
SRAM /
EEPROM
28-pin PDIP
24-pin SOIC
ispPAC80 and
ispPAC81
750 kHz /
75 kHz
50 kHz - 750 kHz /
10 kHz - 75 kHz 1 V - 4 V 1,2,5,10 V/V EEPROM 16-pin PDIP
16-pin SOIC
ispPAC Family – Applications
Amplication Attenuation Filters Control Loop Sensor
Interface
Voltage/
Current
Monitor
Offset
Correction &
PGA
Comparators
and Threshold
Detection
ispPAC10
ispPAC20
ispPAC30
ispPAC80 and
ispPAC81
Mixed Signal/Analog Design Tools and Evaluation Boards
Software Cable Eval Board OPN
ispPAC
Development Kits
ispPAC10 pDS-4102-DL2 ispPAC10-EV PAC-SYSTEM10
ispPAC20 pDS-4102-DL2 ispPAC20-EV PAC-SYSTEM20
ispPAC30 pDS-4102-DL2 ispPAC30-EV PAC-SYSTEM30
ispPAC80/81 pDS-4102-DL2 ispPAC80/81-EV PAC-SYSTEM80/81
ispPAC Power Manager 1208/604 pDS-4102-DL2 ispPACPOWR1208-EV PAC-SYSTEMPOWR1208
Devices on Board OPN
ispPAC
Evaluation
Boards
ispPAC10 ispPAC10 ispPAC10-EV
ispPAC20 ispPAC20 ispPAC20-EV
ispPAC30 ispPAC30 ispPAC30-EV
ispPAC80/81 ispPAC80 and 81 ispPAC80/81-EV
ispPAC Power Manager 1208/604 ispPAC-POWR1208 ispPACPOWR1208-EV
12
Analog Products
13
Development Tools
Lattice Software Offering
PC Development Systems
Workstation
Development
Systems
Software
Product
ispLEVER-
HDL
(Base)
ispLEVER-
HDL
(Advanced)
ispLEVER-
Exemplar
(Advanced)
ispLEVER
(Advanced)
ispLEVER
(Starter)
FPSC
Upgrade
for
LS-HDL-
BASE-
PC-N
ispLEVER
(Advanced)
Device
Support
ispMACH & MACH
ispLSI
ispGDX
ispGAL & GAL
ORCA FPGA
ORCA FPSC
ispXPLD
ispXPGA 125/200
Design Entry
VHDL & Verilog Mentor Graphics
Synplicity
Schematic Lattice
ABEL
Simulation
VHDL and Verilog RTL Model Technology
Timing Model Technology
Lattice
Functional
Static Timing Analyzer
Design
Assistants
Constraints Editor
Revision Control
Floorplanner
Explore Tool
Pin Editor
Operating
System
Windows 98/2000/XP
Windows NT 4.0
Solaris 2.8
License Single User
Floating Node
Part Number
LS-HDL-BASE-PC-N
LS-HDL-ADV-PC-N
LS-EXM-ADV-PC-F
LS-ADV-PC-F
Downloadable
LS-FPSC-UPG
LS-ADV-WS-F
Maintenance
Part Number
LS-HDL-BASE-PCM-N
LS-HDL-ADV-PCM-N
LS-EXM-ADV-PCM-F
LS-ADV-PCM-F
—
—
LS-ADV-WSM-F
Maintenance
Reinstatement
Part Number
LS-HDL-BASE-PCMR-N
LS-HDL-ADV-PCMR-N
LS-EXM-ADV-PCMR-F
LS-ADV-PCMR-F
—
—
LS-ADV-WSMR-F
14
Development Tools
15
Development Tools
Digital Evaluation Boards
Devices on Board Cable OPN
FPSC Evaluation Boards
ORT8850 pDS-4102-DL2 ORT8850-FPSC-EV
ORT82G5 pDS-4102-DL2 ORT82G5-FPSC-EV
ORSO82G5 pDS-4102-DL2 ORSO82G5-FPSC-EV
ORLI10G pDS-4102-DL2 ORLI10G-FPSC-EV
FPSC/ispGDX2/Power
Manager Evaluation Boards
ORT82G5, ispGDX256, ispPAC-POWR1208 pDS-4102-DL2 ORT82G5-G2-PAC-EV
ORSO82G5, ispGDX256, ispPAC-POWR1208 pDS-4102-DL2 ORSO82G5-G2-PAC-EV
FPGA/Power Manager Evaluation Boards ispXPGA1200, ispPAC-POWR1208 pDS-4102-DL2 LF1200-PAC-EV
ispXPLD/Power Manager Evaluation Boards ispXPLD5512MC, ispPAC-POWR1208 pDS-4102-DL2 LC5512M-PAC-EV
ispDOWNLOAD Cables
Programming Voltages Supported
5 3.3 2.5 1.8 1.5 OPN
1x8 AMP Connector pDS-4102-DL2
2x5 JTAG Connector HW7265-DL2
Flywire Design HW7265-DL3
USB (1MB/sec Rate) HW-USB-1A
Desktop Programmers and Adapters
Power Supply OPN
Model 300 60Hz pDS4102-PM300
Model 300 (Europe) Note 1 pDS4102E-PM300
1. Requires local purchase of compatible 50Hz power supply.
Note: Programming adapters are device-specic. See the Lattice Semiconductor web site for a complete list of adapters available from Lattice or other vendors.
Intellectual Property (IP)
The tables below show a selection of IP Cores available from Lattice and our ispLeverCORE Connections partners. See the Lattice
Semiconductor web site at www.latticesemi.com/ip for additional cores.
Lattice IP Cores
Device Families Supported
ORCA 4 ispXPGA Type ORCA 4 OPN ispXPGA OPN
Digital
Signal
Processing
Reed-Solomon Encoder Netlist REEDS-ENCO-O4-N1 REEDS-ENCO-XP-N1
Reed-Solomon Decoder Netlist REEDS-DECO-O4-N1 REEDS-DECO-XP-N1
Convolutional Encoder Netlist CONV-ENCO-O4-N1 CONV-ENCO-XP-N1
Turbo Encoder Netlist TURBO-ENCO-O4-N1 TURBO-ENCO-XP-N1
Turbo Decoder Netlist TURBO-DECO-O4-N1 TURBO-DECO-XP-N1
Viterbi Decoder (Includes Convolutional Encoder) Netlist VTERB-DECO-O4-N1 VTERB-DECO-XP-N1
Parallel FIR Filter Netlist FIR-PARA-XP-N1
Serial FIR Filter Netlist FIR-SER-XP-N1
Communications
10Gigabit Ethernet PCS Bitstream 10GBE-PCS-O4-B1
10Gigabit Ethernet XGXS Netlist XGBE-XGXS-O4-N1
Quad Gigabit Ethernet Over SONET Bitstream ETHER-1GQD-O4-B1
ispLever
CORE
Connection
14
Development Tools
15
Development Tools
ispLeverCORE Connections Partners
Cast, Inc.
Device Families Supported
ORCA 4 ispXPGA Type ORCA 4 OPN ispXPGA OPN
Bus Interface
CUSB: USB1.1 Device Controller Netlist Contact partner Contact partner
CUSB2: USB2.0 Device Controller *Netlist Contact partner Contact partner
SPI_MS: Serial Peripheral Interface Master/Slave Netlist Contact partner Contact partner
Communications H16550S: UART with FIFOs and Synchronous
CPU Interface Netlist Contact partner Contact partner
Processor,
Controller and
Peripherals
C8051: Legacy-Speed 8-bit Processor Netlist Contact partner Contact partner
R8051: 8-bit RISC-like Microcontroller Netlist Contact partner Contact partner
SDLC Controller Netlist Contact partner Contact partner
*ORCA Series 4 FPSC devices only.
Digital Core Design
Device Families Supported
ORCA 4 ispXPGA Type ORCA 4 OPN ispXPGA OPN
Bus Interface
DI2CM: I2C Bus Interface - Master Netlist Contact partner Contact partner
DI2CS: I2C Bus Interface - Slave Netlist Contact partner Contact partner
DI2CSB: I2C Bus Interface Slave - Base Version Netlist Contact partner Contact partner
DSPI: Serial Peripheral Interfacce - Master/Slave Netlist Contact partner Contact partner
Communications D16550: Congurable UART with FIFO Netlist Contact partner
Basic Elements/
Math
DFPADD: Floating Point Pipelined Adder Unit Netlist Contact partner Contact partner
DFPMUL: Floating Point Pipelined Multiplier Unit Netlist Contact partner
DFPDIV: Floating Point Pipelined Divider Unit Netlist Contact partner Contact partner
DINT2FP: Integer to Floating Point Pipelined
Converter Netlist Contact partner Contact partner
DFP2INT: Floating Point to Integer Pipelined
Converter Netlist Contact partner Contact partner
DFPMU: Floating Point Mathematics Unit Netlist Contact partner Contact partner
Processor,
Controller and
Peripherals
DF6811: 8-bit FAST Microcontrollers Family Netlist Contact partner Contact partner
DF6811CPU: 8-bit FAST Microcontrollers Family Netlist Contact partner Contact partner
DFPIC1655X: High Performance Congurable
8-bit RISC Microcontroller Netlist Contact partner Contact partner
DF8051CPU: High Performance Congurable
8-bit Microcontroller Netlist Contact partner
D8254: Programmable Interval Timer Netlist Contact partner Contact partner
DR8051XP: High Performance Congurable
8-bit Microcontroller Netlist Contact partner
DRPIC1655X: High Performance Congurable
8-bit RISC Microcontroller Netlist Contact partner Contact partner
DR80390CPU: High Performance Congurable
8-bit Microcontroller Netlist Contact partner
Eureka Technology, Inc.
Device
Family
Supported
ispXPGA Type ispXPGA OPN
Processor,
Controller and
Peripherals
EP100: PowerPC Bus Slave Netlist Contact partner
EP201: PowerPC Bus Master Netlist Contact partner
EP300: PowerPC Bus Arbiter Netlist Contact partner
EP510: CompactFlash/PCMCIA Host Adapter Netlist Contact partner
Lattice Semiconductor Corporation
5555 Northeast Moore Court
Hillsboro, Oregon 97124 U.S.A.
Telephone: (503) 268-8000 • FAX: (503) 268-8556
Applications & Literature Hotline: 1-800-LATTICE
www.latticesemi.com
August 2003
Order #: I0162
Copyright © 2003 Lattice Semiconductor Corporation.
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), E2CMOS, GAL, Generic Array Logic, ISP, ispDOWNLOAD, ispGAL, ispGDS, ispGDX,
ispGDXV, ispGDXVA, ispGDX2, ispLEVER, ispLSI, ispMACH, ispPAC, ispVM, ispXPGA, ispXPLD, MACH, ORCA, PAC, PAC-Designer, Performance Analyst, SCUBA, Silicon Forest, Speedlocked, Speed Locking,
SuperBIG, SuperFAST, SuperWIDE, sysCLOCK, sysIO, Twin GLB, UltraMOS and XPIO, are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States
and/or other countries. ISP is a service mark of Lattice Semiconductor Corporation.