1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Feature list
• Single-channel non-isolated gate-drive IC with true dierential inputs
• Very large common-mode input voltage range (CMR) up to ± 150 V (Table 1)
• Supply voltage (VDD) up to 20 V
• 2 UVLO options: 4 V and 8 V
• Separate low impedance source and sink outputs
- 4 A / 0.85 Ω source
- 8 A / 0.35 Ω sink
• 45 ns propagation delay with -7 / +10 ns accuracy
• SOT23 6-pin package
• Fully qualified for industrial applications according to JEDEC
Description
1EDNx550 is a new family of single-channel non-isolated gate-driver ICs. Due to the unique fully dierential
input circuitry with excellent common-mode rejection, the logic driver state is exclusively controlled by the
voltage dierence between the two inputs, completely independent of the driver’s reference (ground) potential.
This eliminates the risk for wrong triggering and thus is a significant benefit in all applications exhibiting
voltage dierences between driver and controller ground, a problem typical for systems with
• 4-pin packages (Kelvin Source connection)
• high parasitic PCB inductances (long distances, single-layer PCB)
• bipolar gate drive
In addition, within the allowed common-mode voltage range, CMR (Table 1), 1EDNx550 allows to address even
high-side applications.
Table 1 Product portfolio
Part number CMR static CMR dynamic UVLO Package Orderable Part Number
1EDN7550B + 72 V / - 84 V ± 150 V 4 V PG-SOT23-6 1EDN7550BXTSA1
1EDN8550B + 72 V / - 84 V ± 150 V 8 V PG-SOT23-6 1EDN8550BXTSA1
GND
OUT_SRC
VDD
VDD
IN+
OUT_SNK
Rgon
Rgoff
1EDNx550
Rin1
Rin2
SGND
DVRin
IN-
CVDD
ZVDD
Figure 1 Typical application
Datasheet Please read the Important Notice and Warnings at the end of this document Rev. 2.0
www.infineon.com 2018-05-14
Table of contents
Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Dierential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.1 Common mode input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.2 Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.3 Supply voltage and Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.5 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Switches with Kelvin source connection (4-pin packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6.2 Applications with significant parasitic PCB-inductances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Switches with bipolar gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.4 High-side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Table of contents
Datasheet 2 Rev. 2.0
2018-05-14
1 Pin configuration and description
The pin configuration for the SOT23 6-pin package is illustrated in Figure 2; a description is given in Table 2 . For
functional details, please read Chapter 3.
IN-
GND
IN+
OUT_SNK
OUT_SRC
VDD
SOT23-6
6
5
4
3
2
1
Figure 2 Pin configuration SOT23 6-pin (top side view)
Table 2 Pin description
Symbol Description
IN+ Positive input
connected to PWM output of controller via resistor (typically 33 kΩ)
IN- Negative input
connected to controller ground via resistor (typically 33 kΩ)
GND Ground
negative gate drive voltage ("o" state)
VDD Positive supply voltage
positive gate drive voltage ("on" state)
OUT_SNK Driver output sink
low-impedance switch to GND (8 A / 0.35 Ω)
OUT_SRC Driver output source
low-impedance switch to VDD (4 A / 0.85 Ω)
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Pin configuration and description
Datasheet 3 Rev. 2.0
2018-05-14
2 Block diagram
A simplified functional block diagram of 1EDNx550 is given in Figure 3.
IN+
IN-
GND
VDD
OUT_SNK
OUT_SRC
Differential
Schmitt
Trigger
Diff. Amp.
+ LPF
UVLO
Logic
Figure 3 Block diagram
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Block diagram
Datasheet 4 Rev. 2.0
2018-05-14
3 Functional description
1EDNx550 is a fast single-channel non-isolated gate driver. However, compared with standard drivers, this new
gate driver family extends the range of possible applications into fields usually reserved for isolated drivers,
thereby generating significant system cost benefits.
The key to make this possible, is moving from the standard ground related to a true dierential input with very
high common-mode rejection. The required symmetry of the input circuitry is achieved by on-chip trimming; it
finally allows to deal with peak common-mode voltages of up to ± 150 V between driver reference (GND) and
system ground (SGND). 1EDNx550 is not only ideally suited for any application with unwanted shis between
driver and system ground, but may also be utilized as a high-side driver within the allowed common-mode
range. Besides, switches requiring a bipolar driving voltage can be operated very easily.
3.1 Dierential input
Figure 4 depicts the signal path from the controller’s PWM output to the logic gate driver signal as implemented
on 1EDNx550.
IN+
IN-
Differential
Schmitt
Trigger
Av = 4.5
12 MHz
2nd order
Lowpass
Controller
PWM
SGND
0Rin1
Rin2
2kW
2kW
1kW
1kW
15pF
15pF
1EDNx550
GND
Pulse
Extender
Cp2
Cp1
VS
DVRin DVRin / k
k = (Rin [kW] + 3) / 3
Figure 4 1EDNx550 input signal path
The controller output signal, switching between controller supply VS and zero, is applied at the one leg of a
dierential voltage divider, while the other is connected to the controller ground SGND. The divider ratio has to
be adapted to VS to allow a fixed Schmitt-Trigger threshold voltage. For VS = 3.3 V, Rin1 and Rin2 are chosen to be
33 kΩ, resulting in a static divider ratio of k = 12 at the driver inputs and 36 at the internal voltage amplifier. With
VS other than 3.3 V, Rin has to fulfil the relation: Rin1 =Rin2 = 10.9 VS −3 kΩ
Amplified by a factor of 4.5, the signal is filtered by a 2nd order low-pass filter. Taking into account the RC filter in
front of the amplifier, the overall input path exhibits the frequency behavior of a 3rd order low-pass filter with a
corner frequency around 12 MHz. The suppression of high frequencies is important for two reasons. Inductive
common-mode ringing in fast-switching power systems is typically in the 100 MHz and above range and thus is
eectively damped. The high-frequency symmetry of the voltage divider is influenced by parasitic capacitances,
particularly Cp1 and Cp2, the parallel capacitances of Rin1 and Rin2. They are typically in the 50 to 100 fF range,
rather independent of resistor size. Without filtering, any asymmetry would translate high-frequency common-
mode into dierential signals.
The filtered signal is then applied to a dierential Schmitt-Trigger with accurate trimmed threshold levels and
converted to the logic switch control signal. The subsequent pulse extender function guarantees that no pulses
shorter than 25 ns are transmitted to the output, thereby further improving noise immunity.
Due to the filtering requirements the input-to-output propagation delay is slightly increased to around 45 ns. By
means of on-chip trimming, however, the usually more relevant propagation delay variation can still be kept
low at +10 / -7 ns.
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Functional description
Datasheet 5 Rev. 2.0
2018-05-14
3.1.1 Common mode input range
There are two eects limiting the common-mode input range, i.e. the maximum allowed voltage dierence
between controller outputs PWM/SGND and driver reference GND: the circuit and technology-related input
voltage restrictions and the finite common-mode rejection in the input signal path due to asymmetries.
The static voltage range at the input pins is limited to + 6 / - 7 V to guarantee accurate linear operation of the
input circuitry. Taking into account the proposed DC voltage divider ratio, this translates to a static common-
mode range of + 72 / - 84 V. This range, however, is increased, if the high-frequency common-mode voltages
typical for inductive ringing in fast-switching power systems are considered, as in this case the maximum
ratings at the input pins are applicable (± 10 V). Together with the frequency-dependence of the voltage divider
ratio due to the input RC-filter this leads to a usable dynamic common-mode range of ± 150 V.
The second limitation results from the fact that any imbalance in the signal path converts a common-mode to a
dierential signal. To utilize the full common-mode range as calculated above, the high accuracy of the
trimmed on-chip network must not be aected by the external voltage divider resistors. This condition is easily
fulfilled when choosing Rin1 and Rin2 with 0.1% tolerance; resistors with only 1% accuracy, however, would
reduce the common-mode range significantly to ± 40 V.
3.2 Driver outputs
The rail-to-rail driver output stage realized with complementary MOS transistors is able to provide a typical 4 A
sourcing and 8 A sinking current. The low on-resistance coming together with high driving current is particularly
beneficial for fast switching of very large MOSFETs. With a Ron of 0.85 Ω for the sourcing pMOS and 0.35 Ω for
the sinking nMOS transistor the driver can be considered in most applications to behave like an ideal switch.
The p-channel sourcing transistor allows real rail-to-rail behavior without suering from the source-follower’s
voltage drop typical for n-channel output stages.
In case of floating inputs or insuicient supply voltage the driver output is actively clamped to the “low” level
(GND).
3.3 Supply voltage and Undervoltage Lockout (UVLO)
The Undervoltage Lockout function ensures that the output can be switched only, if the supply voltage VDD
exceeds the UVLO threshold voltage. Thus it can be guaranteed that the switch transistor is not operated, if the
driving voltage is too low to achieve a complete and fast transition to the "on" state, thereby avoiding excessive
power dissipation.
1EDNx550 is available in two versions diering in UVLO threshold to support switches with a broad range of
threshold voltages
• 1EDN7550 with a typical UVLO threshold of 4.2 V (0.3 V hysteresis)
• 1EDN8550 with a typical UVLO threshold of 8 V (1 V hysteresis)
In addition, the high maximum VDD of 20 V makes the driver family well suited for a broad variety of power
switch types.
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Functional description
Datasheet 6 Rev. 2.0
2018-05-14
4 Electrical characteristics and parameters
The absolute maximum ratings are listed in Table 3 . Stresses beyond these values may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods may aect device
reliability.
4.1 Absolute maximum ratings
Table 3 Absolute Maximum Ratings
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Supply voltage VDD -0.3 – 22 V Voltage between VDD to
GND
Voltage at pins IN+ and IN- VIN -10 – 10 V –
Voltage at pins OUT_SRC and
OUT_SNK
VINPUT -0.3 – VDD+0.3 V –
Peak reverse current at
OUT_SRC
ISRC_rev -5 – – A < 500 ns
Peak reverse current at
OUT_SRC
ISRC_rev – – 5 A < 500 ns
Junction temperature Tj-40 – 150 °C –
Storage temperature TS-55 – 150 °C –
ESD capability VESD_HBM – – 2 kV Human Body Model
(HBM)1)
ESD capability VESD_CDM – – 0.5 kV Charged Device Mode
(CDM)
1According to EIA/JESD22-A114-B (discharging 100 pF capacitor through 1.5 kΩ resistor)
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Electrical characteristics and parameters
Datasheet 7 Rev. 2.0
2018-05-14
4.2 Thermal characteristics
Table 4 Thermal characteristics
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Thermal resistance junction-
ambient2)
RthJA25 – 170 – K/W –
Thermal resistance junction-
case (top)3)
RthJC25 – 81 – K/W –
Thermal resistance junction-
board4)
RthJB25 – 52 – K/W –
Characterization parameter
junction-case (top)5)
Ψ
thJC25 – 14 – K/W –
Characterization parameter
junction-board6)
Ψ
thJB25 – 51 – K/W –
4.3 Operating range
Table 5 Operating Range
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Supply voltage VDD 4.5 – 20 V Min defined by UVLO
Voltage at pins IN+ and IN- VIN -7 – 6 V –
Junction temperature Tj-40 – 150 °C 7)
2Obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment
described in JESD51-2a
3Obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a
close description can be found in the ANSI SEMI standard G30-88
4Obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as
described in JESD51-8
5Estimates the junction temperature of a device in a real system and is extracted from the simulation data
for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)
6Estimates the junction temperature of a device in a real system and is extracted from the simulation data
for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)
7Continuous operation above 125°C may reduce life time
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Electrical characteristics and parameters
Datasheet 8 Rev. 2.0
2018-05-14
4.4 Electrical characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. They
are valid within the full operating range. The supply voltage is VVDD= 12 V. Typical values are given at Tj=25°C.
Table 6 Power Supply
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
VDD quiescent current IVDDh – 0.86 – mA OUT = high
VDD quiescent current IVDDl – 1.06 – mA OUT = low
Table 7 Undervoltage Lockout 1EDN7550 (Logic level MOSFET)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO)
turn on threshold
UVLOon 3.9 4.2 4.5 V –
Undervoltage Lockout (UVLO)
turn o threshold
UVLOo – 3.9 – V –
UVLO threshold hysteresis UVLOhys 0.25 0.3 0.35 V –
Table 8 Undervoltage Lockout 1EDN8550 (Standard MOSFET)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO)
turn on threshold
UVLOon 7.4 8.0 8.6 V –
Undervoltage Lockout (UVLO)
turn o threshold
UVLOo – 7.0 – V –
UVLO threshold hysteresis UVLOhys 0.8 1.0 1.2 V –
Table 9 Inputs IN+, IN-
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Dierential input voltage
threshold for transition LH at
input resistor
∆VRinH – 1.7 – V Independent of VDD
Rin1/Rin2 = 33 kΩ 8)
Dierential input voltage
threshold for transition HL at
input resistor
∆VRinL – 1.5 – V Independent of VDD
Rin1/Rin2 = 33 kΩ 8)
Total input resistance on each
leg
Rin1 / Rin2 – 36 – kΩ Rin1/Rin2 = 33 kΩ 8)
8See Figure 1
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Electrical characteristics and parameters
Datasheet 9 Rev. 2.0
2018-05-14
Table 10 Static Output Characteristics
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
High-level (sourcing) 0utput
resistance
Ron_SRC – 0.85 – Ω ISRC = 50 mA
High-level (sourcing) output
current
ISRC_peak – 4.0 9) A –
Low-level (sinking) output
resistance
Ron_SNK – 0.35 – Ω ISNK = 50 mA
Low-level (sinking) output
current
ISNK_Peak – -8.0 10) A –
For an illustration of the dynamic characteristics see Figure 5 and Figure 6
Table 11 Dynamic Characteristics
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Input-to-output propagation
delay
tPDon 38 45 55 ns CLOAD= 200 pF, VDD= 12 V
Input-to-output propagation
delay
tPDo 38 45 55 ns CLOAD= 200 pF, VDD= 12 V
Rise time trise — 6.5 1511) ns CLOAD= 1.8 nF, VDD= 12 V
Fall time tfall — 4.5 1511) ns CLOAD= 1.8 nF, VDD= 12 V
Rise time trise — 1 511) ns CLOAD= 200 pF, VDD= 12 V
Fall Time tfall — 1 511) ns CLOAD= 200 pF, VDD= 12 V
Minimum input pulse width
that changes output state
tPW — 25 — ns CLOAD= 1.8 nF, VDD= 12 V
9Actively limited by design to approx. 5.2 Apk, parameter is not subject to production test - verified by
design / characterization
10 Actively limited by design approx. -10.4 Apk, parameter is not subject to production test - verified by
design / characterization
11 Parameter verified by design, not 100% tested in production
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Electrical characteristics and parameters
Datasheet 10 Rev. 2.0
2018-05-14
4.5 Timing diagram
Figure 5 depicts rise, fall and delay times as given in the Chapter 4.
IN+ - IN-
OUTx tPDon
50%
tPDoff
10%
90%
trise tfall
1.7
1.5
Figure 5 Propagation delay, rise and fall time
Figure 6 illustrates the Undervoltage Lockout function.
OUT
VDD
UVLOon UVLOoff
Figure 6 UVLO Behavior (output state high)
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Electrical characteristics and parameters
Datasheet 11 Rev. 2.0
2018-05-14
5 Typical characteristics
3.7
3.9
4.1
4.3
4.5
-50 0 50 100 150
VDD [V]
Tj[ °C]
UVLO on
UVLO off
Figure 7 Undervoltage Lockout threshold
(1EDN7550) vs temperature
6.4
6.8
7.2
7.6
8.0
8.4
8.8
-50 0 50 100 150
VDD [V]
Tj[°C]
UVLO on
UVLO off
Figure 8 Undervoltage Lockout threshold
(1EDN8550) vs temperature
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
-50 0 50 100 150
Tj[°C]
ON threshold
OFF threshold
VDD=12V
Vin=3.3V
∆VRin [V]
Figure 9 Dierential input voltage threshold vs
temperature
0.6
0.8
1.0
1.2
1.4
-50 0 50 100 150
Tj[ °C]
OUT High
OUT Low
IVDD [mA]
Figure 10 Typical quiescent current vs
temperature
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Typical characteristics
Datasheet 12 Rev. 2.0
2018-05-14
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0 5 10 15 20 25
VDD [V]
OUT High
OUT Low
IVDD [mA]
Figure 11 Typical quiescent current vs supply
voltage
0
10
20
30
40
50
0 200 400 600 800 1000
Frequency [kHz]
VDD 4.5V
VDD 12V
VDD 20V
Duty Cycle 50%
CLoad = 1.8nF
IVDD [mA]
Figure 12 Total operating current consumption
with capacitive load vs frequency
40
42
44
46
48
50
52
54
-50 0 50 100 150
Tj[ °C]
turn-on
turn-off
VDD=12V
Vin=3.3V
tPD [ns]
Figure 13 Typical propagation delay vs
temperature
3
4
5
6
7
8
-50 0 50 100 150
Tj[ °C]
turn-on
turn-off
VDD=12V
Cload=1.8nF
trise/fall [ns]
Figure 14 Typical rise and fall time vs
temperature
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Typical characteristics
Datasheet 13 Rev. 2.0
2018-05-14
6 Typical applications
6.1 Switches with Kelvin source connection (4-pin packages)
This is one of the key target applications of 1EDNx550. The 4-pin configuration depicted in Figure 15 is a very
eective measure to improve the switching performance of transistors in packages with high source inductance
LS as is typical for the widely used TO-packages. Although the Kelvin Source connection SS solves the problem
of the largely increased switching losses due to LS, it is evident, that the gate driver reference potential is
moving by the inductive voltage drop vLS with respect to the system ground SGND. In fast-switching
applications at high current, vLS can reach 100 V and above. This is why 4-pin systems so far either used isolated
drivers or external filters with relatively low corner frequency that add significant signal delay. Now, however,
1EDNx550 provides an optimum solution for this case.
Figure 15 also indicates that the usually SGND-related VDD cannot be used directly as the driver supply. But due
to the high frequency of vLS (> 100 MHz), a filter composed of impedance ZVDD together with the blocking cap
CVDD is well suited to generate a suiciently stable driver supply. ZVDD can be either a resistor (e.g. 22 Ω with a
typical CVDD of 1 µF) or, even better, a proper ferrite bead.
GND
OUT_SRC
VDD
VDD
IN+
OUT_SNK
ZVDD
Rgoff
1EDNx550
Rin1
Rin2
SGND
IN-
CVDD
PWM_Out
SGND
Controller
vLS LS
MOSFET
D
G
S
SS
Rgon
DVRin
Figure 15 1EDN driving 4-pin MOSFET
6.2 Applications with significant parasitic PCB-inductances
In fast switching power systems the unavoidable parasitic inductance associated with any electrical connection
may cause significant inductive voltage drops, particularly if the PCB-layout cannot be optimized, the most
common reasons being limitations in the number of PCB-layers, geometric restrictions or also the lack of
specific experience. In such situations the high robustness of 1EDNx550 with respect to “switching noise” (high-
frequency voltage between reference potential of driver and controller) is extremely valuable and allows good
performance even in systems with formerly critical layout. Figure 16 indicates a respective example, indicating
the most relevant parasitic PCB-inductances.
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Typical applications
Datasheet 14 Rev. 2.0
2018-05-14
GND
OUT_SRC
VDDIN+
OUT_SNK
Rgon
Rgoff
1EDNx550
Rin1
Rin2
SGND
IN-
CVDD
PWM_Out
SGND
Controller MOSFET
D
G
S
VDD
ZVDD
DVRin
Figure 16 Application with significant PCB inductance
6.3 Switches with bipolar gate drive
Another application 1EDNx550 is tailored for, is driving power switches that require a negative gate-to-source
voltage to safely hold them in the “o” state. Although MOSFETs are usually operated at zero “o” voltage, in
certain situations a negative gate drive voltage can be very helpful. Particularly the fast switching “o” of high
current when using switches with large common source inductance (e.g. in 3-pin TO-packages) may become
critical in terms of losses and stability with a zero “o” level. In such cases a negative gate drive voltage is able
to significantly improve switching performance. As depicted in Figure 17, this kind of application is completely
uncritical and handled easily with 1EDNx550, while standard drivers cannot be applied directly without
adaptations.
GND
OUT_SRC
VDD
IN+
OUT_SNK
Rgon
Rgoff
1EDNx550
Rin1
Rin2
SGND
IN-
PWM_Out
SGND
Controller MOSFET
D
G
S
VSS
VDD
DVRin
Figure 17 Bipolar gate drive for 3-pin MOSFET
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Typical applications
Datasheet 15 Rev. 2.0
2018-05-14
6.4 High-side switches
Due to the large static input common-mode range, even driving high-side switches is an interesting application
field for 1EDNx550. Although not providing galvanic isolation, 1EDNx550 can functionally be used as a high-side
driver, as long as the power-loop voltage VP does not cause a violation of the allowed common-mode range.
In high-side operation as depicted in Figure 18, the driver ground GND switches between zero (“o” state) and
VP (“on" state) with respect to SGND; the resulting common-mode voltage at the driver input pins
(0 and –VP / 12, resp.) is restricted to - 7 V (Table 5) and by that limits VP to 84 V. In many applications the driver
supply voltage can be generated by means of the well-known bootstrapping method also indicated in Figure 18.
GND
OUT_SRC
VDD
VDD
IN+
OUT_SNK
Rgon
Rgoff
1EDNx550
Rin1
Rin2
IN-
Cboot
PWM_Out
SGND
Controller
D
G
S
D
G
S
VP < 84V
SGND
Vsw
HS-MOSFET
Dboot
Rboot
DVRin
Figure 18 1EDNx550 as a high-side driver
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Typical applications
Datasheet 16 Rev. 2.0
2018-05-14
7 Layout guidelines
It is well-known that the layout of a fast-switching power system is a critical task with strong influence on the
overall performance. This is why there exists a huge number of rules, recommendations, guidelines, tips and
tricks exist that should help to finally end up with a proper system layout.
With 1EDNx550 one of the central layout problems, namely the design of the grounding network, has become
much less critical due to the highly reduced sensitivity of the dierential concept with respect to ground voltage
dierences. So layout rules can be restricted to the following rather simple and evident ones:
• place input resistors Rin close to the driver and make layout of input signal path as symmetric and as
compact as possible
• use a low-ESR decoupling capacitance for the VDD supply and place it as close as possible to the driver
• minimize power loop inductance as the most critical limitation of switching speed due to the resulting
unavoidable voltage overshoots
A layout recommendation for the input path is given in Figure 19.
CVDD
RGON
RGOFF
RIN1
RIN2
RVDD
GND
IN-
IN+
OUT_SNK
OUT_SRC
VDD
IN_N
IN_P
VIN
OUT
DRV_GND
1EDN7550
Figure 19 Layout recommendation
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Layout guidelines
Datasheet 17 Rev. 2.0
2018-05-14
8 Package dimensions
Figure 20 SOT23 6-pin outline dimensions
Figure 21 SOT23 6-pin footprint dimension
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Package dimensions
Datasheet 18 Rev. 2.0
2018-05-14
Figure 22 SOT23 6-pin packaging dimensions
Notes:
1. For further details, please visit www.infineon.com/packages
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Package dimensions
Datasheet 19 Rev. 2.0
2018-05-14
Revision history
Document
version
Date of
release
Description of changes
Rev. 2.0 2018-05-14 Final Datasheet created
1EDN7550 and 1EDN8550
Single-channel EiceDRIVER™ with true dierential inputs
Revision history
Datasheet 20 Rev. 2.0
2018-05-14
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-05-14
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
IFX-fkz1513594931854
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