Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc.
1
Rev. I
11/22/05
IS61LV6416
IS61LV6416L ISSI
®
FEATURES
• High-speed access time: 8, 10, 12 ns
• CMOS low power operation
— 61LV6416:
75 mW (typical) operating current
0.5 mW (typical) standby current
— 61LV6416L:
65 mW (typical) operating current
50 µW (typical) standby current
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
DESCRIPTION
The ISSI IS61LV6416/IS61LV6416L is a high-speed,
1,048,576-bit static RAM organized as 65,536 words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs, CE and OE. The active
LOW Write Enable (WE) controls both writing and reading
of the memory. A data byte allows Upper Byte (UB) and
Lower Byte (LB) access.
The IS61LV6416/IS61LV6416L is packaged in the JEDEC
standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin
mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
NOVEMBER 2005
A0-A15
CE
OE
WE
64K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
IS61LV6416
IS61LV6416L
2
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
ISSI
®
PIN CONFIGURATIONS
44-Pin SOJ (K)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
44-Pin TSOP-II (T)
48-Pin mini BGA (6mm x 8mm) (B) PIN DESCRIPTIONS
A0-A15 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
VDD Power
GND Ground
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 NC
I/O
8
UB A3 A4 CE I/O
0
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
GND I/O
11
NC A7 I/O
3
V
DD
V
DD
I/O
12
NC NC I/O
4
GND
I/O
14
I/O
13
A14 A15 I/O
5
I/O
6
I/O
15
NC A12 A13 WE I/O
7
NC A8 A9 A10 A11 NC
IS61LV6416
IS61LV6416L
Integrated Silicon Solution, Inc.
3
Rev. I
11/22/05
1
2
3
4
5
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7
8
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12
ISSI
®
OPERATING RANGE
Range Ambient Temperature VDD (8,10 ns) VDD (12 ns)
Commercial 0°C to +70°C 3.3V+10%,-5% 3.3V ± 10%
Industrial –40°C to +85°C 3.3V+10%,-5% 3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VDD –2 2 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –2 2 µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to VDD+0.5 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TRUTH TABLE
I/O PIN
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE LBLB
LBLB
LB UBUB
UBUB
UB I/O0-I/O7 I/O8-I/O15 VDD Current
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
IS61LV6416
IS61LV6416L
4
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
ISSI
®
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
IS61LV6416
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. — 140 — 120 — 100 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 150 — 130 — 110
typ.
(2)
— 105 — 95—75
ISB1TTL Standby Current VDD = Max., Com. — 15 — 15 — 15 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 20 — 20 — 20
CE ≥ VIH , f = 0
ISB2CMOS Standby VDD = Max., Com. — 5 — 5 — 5 mA
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 10 — 10 — 10
VIN ≥ VDD – 0.2V, or typ.
(2)
— 0.5 — 0.5 — 0.5
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested.
IS61LV6416L
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. — 100 — 95mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 110 — 105
typ.
(2)
—75 —70
ISB1TTL Standby Current VDD = Max., Com. — 15 — 15 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 20 — 20
CE ≥ VIH , f = 0
ISB2CMOS Standby VDD = Max., Com. — 1 — 1 mA
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 1.5 — 1.5
VIN ≥ VDD – 0.2V, or typ.
(2)
— 0.05 — 0.05
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested.
IS61LV6416
IS61LV6416L
Integrated Silicon Solution, Inc.
5
Rev. I
11/22/05
1
2
3
4
5
6
7
8
9
10
11
12
ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — ns
tAA Address Access Time — 8 — 10 — 12 ns
tOHA Output Hold Time 3 — 3 — 3 — ns
tACE CE Access Time — 8 — 10 — 12 ns
tDOE OE Access Time — 5 — 5 — 6 ns
tHZOE
(2)
OE to High-Z Output — 5 — 5 — 6 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — ns
tHZCE
(2
CE to High-Z Output 0 4 0 5 0 6 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — 3 — ns
tBA LB, UB Access Time — 6 — 6 — 6 ns
tHZB LB, UB to High-Z Output 0 4 0 5 0 6 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1a and 1b
AC TEST LOADS
Figure 1a. Figure 1b.
319 Ω
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
IS61LV6416
IS61LV6416L
6
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
ISSI
®
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
tRC
tOHA
tAA
tDOE
tLZOE
tACE
tLZCE
tHZOE
HIGH-Z DATA VALID
tHZB
ADDRESS
OE
CE
LB, UB
D
OUT
tHZCE
tBA
tLZB
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
IS61LV6416
IS61LV6416L
Integrated Silicon Solution, Inc.
7
Rev. I
11/22/05
1
2
3
4
5
6
7
8
9
10
11
12
ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — ns
tSCE CE to Write End 6 — 8 — 9—ns
tAW Address Setup Time 8 — 8 — 9—ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPBW LB, UB Valid to End of Write 7 — 8 — 9—ns
tPWE1/tPWE2WE Pulse Width (OE = HIGH/LOW) 6 — 8 — 9—ns
tSD Data Setup to Write End 6 — 6 — 6 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 4 — 5 — 6 ns
tLZWE
(2)
WE HIGH to Low-Z Output 3 — 3 — 3 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
IS61LV6416
IS61LV6416L
8
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
ISSI
®
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t WC
VALID ADDRESS
t SCE
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t PBW
t HD
t SA
t HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN DATAIN VALID
t LZWE
t SD
UB_CEWR1.eps
IS61LV6416
IS61LV6416L
Integrated Silicon Solution, Inc.
9
Rev. I
11/22/05
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2
3
4
5
6
7
8
9
10
11
12
ISSI
®
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
OE
DATAIN VALID
t
LZWE
t
SD
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR3.eps
WRITE CYCLE NO. 2(1)
(WE Controlled, OE = HIGH during Write Cycle)
IS61LV6416
IS61LV6416L
10
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
ISSI
®
DATA UNDEFINED
t WC
ADDRESS 1 ADDRESS 2
t WC
HIGH-Z
t PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t HD
t SA
t HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t SD
t PBW
DATA
IN
VALID
t
SD
t HD
t SA
t HA t HA
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write)(1,3)
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
IS61LV6416
IS61LV6416L
Integrated Silicon Solution, Inc.
11
Rev. I
11/22/05
1
2
3
4
5
6
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10
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ISSI
®
DATA RETENTION WAVEFORM (CE Controlled)
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Options Min. Typ.
(1)
Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 2.0 — 3.6 V
IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V IS61LV6416 — 0.5 10 mA
IS61LV6416L — 0.05 1.5
tSDR Data Retention Setup Time See Data Retention Waveform 0 — — ns
tRDR Recovery Time See Data Retention Waveform tRC ——ns
Note 1: Typical values are measured at V
DD
= 3.0V, T
A
= 25
O
C and not 100% tested.
V
DD
CE ≥ VDD
- 0.2V
tSDR tRDR
VDR
CE
GND
Data Retention Mode
IS61LV6416
IS61LV6416L
12
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
ISSI
®
IS61LV6416
ORDERING INFORMATION
Speed (ns) Order Part No. Package Temperature Range
8 IS61LV6416-8T Plastic TSOP Commercial (0°C to +70°C )
8 IS61LV6416-8TL Plastic TSOP Commercial (0°C to +70°C ), Lead-free
8 IS61LV6416-8BI mini BGA (6mm x 8mm) Industrial (-40°C to +85°C )
8 IS61LV6416-8TI Plastic TSOP Industrial (-40°C to +85°C )
8 IS61LV6416-8KL
400-mil Plastic SOJ
Commercial (0°C to +70°C ), Lead-free
10 IS61LV6416-10T Plastic TSOP Commercial (0°C to +70°C )
10 IS61LV6416-10TL Plastic TSOP Commercial (0°C to +70°C ), Lead-free
10 IS61LV6416-10K
400-mil Plastic SOJ
Commercial (0°C to +70°C )
10 IS61LV6416-10BI mini BGA (6mm x 8mm) Industrial (-40°C to +85°C )
10 IS61LV6416-10BLI mini BGA (6mm x 8mm) Industrial (-40°C to +85°C ), Lead-free
10 IS61LV6416-10TI Plastic TSOP Industrial (-40°C to +85°C )
10 IS61LV6416-10TLI Plastic TSOP Industrial (-40°C to +85°C ), Lead-free
10 IS61LV6416-10KI
400-mil Plastic SOJ
Industrial (-40°C to +85°C )
10 IS61LV6416-10KLI
400-mil Plastic SOJ
Industrial (-40°C to +85°C ), Lead-free
12 IS61LV6416-12T Plastic TSOP Commercial (0°C to +70°C )
12 IS61LV6416-12K
400-mil Plastic SOJ
Commercial (0°C to +70°C )
12 IS61LV6416-12KL
400-mil Plastic SOJ
Commercial (0°C to +70°C ), Lead-free
12 IS61LV6416-12BI mini BGA (6mm x 8mm) Industrial (-40°C to +85°C )
IS61LV6416L
ORDERING INFORMATION
Speed (ns) Order Part No. Package Temperature Range
8 IS61LV6416L-8T Plastic TSOP Commercial (0°C to +70°C )
8 IS61LV6416L-8BI mini BGA (6mm x 8mm) Industrial (-40°C to +85°C )
8 IS61LV6416L-8TI Plastic TSOP Industrial (-40°C to +85°C )
8 IS61LV6416L-8KI
400-mil Plastic SOJ
Industrial (-40°C to +85°C )
10 IS61LV6416L-10T Plastic TSOP Commercial (0°C to +70°C )
10 IS61LV6416L-10BI mini BGA (6mm x 8mm) Industrial (-40°C to +85°C )
10 IS61LV6416L-10TI Plastic TSOP Industrial (-40°C to +85°C )
10 IS61LV6416L-10KI
400-mil Plastic SOJ
Industrial (-40°C to +85°C )
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
400-mil Plastic SOJ
Package Code: K
Notes:
1. Controlling dimension:
millimeters.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
SEATING PLANE
1
N
E1
D
E2
E
B
eA1
A
C
A2
b
N/2+1
N/2
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 28 32 36
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
PA CKA GING INFORMATION ISSI
®
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 40 42 44
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
01/15/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array
Package Code: B (48-pin)
Notes:
1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 48
A — — 1.20 — — 0.047
A1 0.24 — 0.30 0.009 — 0.012
A2 0.60 — — 0.024 — —
D 7.90 — 8.10 0.311 — 0.319
D1 5.25 BSC 0.207 BSC
E 5.90 — 6.10 0.232 — 0.240
E1 3.75 BSC 0.148 BSC
e 0.75 BSC 0.030 BSC
b 0.30 0.35 0.40 0.012 0.014 0.016
mBGA - 8mm x 10mm
MILLIMETER INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 48
A — — 1.20 — — 0.047
A1 0.24 — 0.30 0.009 — 0.012
A2 0.60 — — 0.024 — —
D 9.90 — 10.10 0.390 — 0.398
D1 5.25 BSC 0.207 BSC
E 7.90 — 8.10 0.311 — 0.319
E1 3.75 BSC 0.148 BSC
e 0.75 BSC 0.030 BSC
b 0.30 0.35 0.40 0.012 0.014 0.016
SEATING PLANE
A
A1
A2
A
B
C
D
E
F
G
H
e
e
D1
E1E
D
φ b (48x)
Top Vie w Bottom View
6 5 4 3 2 11 2 3 4 5 6
A
B
C
D
E
F
G
H
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Plastic TSOP
Package Code: T (Type II)
D
SEATING PLANE
b
eC
1N/2
N/2+1N
E1
A1
A
E
Lα
ZD
.
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
Plastic TSOP (T - Type II)
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 32 44 50
A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008
D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830
E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471
e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC
L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024
ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF
α0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5°
