Aclel Preliminary vi.2 54SX Family FPGAs RadTolerant and HiRel Features RadTolerant 54SX Family * Tested Total lonizing Dose (TID) Survivability Level * Devices Available from Tested Lots * Radiation Performance to 100K Rads * Up to 160 MHz On-Chip Performance * Offered as E-Flow (Actel Space Level Flow) and Class B HiRel 54SX Family * Fastest HiRel FPGA Family Available * Up to 240 MHz On-Chip Performance * Low Cost Prototyping Vehicle for RadTolerant Devices * Offered as Commercial or Military Temperature Tested and Class B High Density Devices * 16,000 and 32,000 Available Logic Gates * Up to 225 User I/Os * Upto 1,080 Dedicated Flip-Flops Easy Logic Integration * Non-Volatile, User Programmable * Highly Predictable Performance with 100% Automatic 100% Resource Utilization with 100%Pin Locking * Mixed Voltage Support3.3V Operation with 5.0V Input Tolerance * JTAG Boundary Scan Testing in Compliance with IEEE Standard 1149.1 * Secure Programming Technology Prevents Reverse Engineering and Design Theft * Permanently Programmed for Instantaneous Operation on Power-Up * Unique In-System Diagnostic and Debug Facility with Silicon Explorer * Actel Designer Series Design Tools, Supported by Cadence, Exemplar, Mentor Graphics, Model Tech, Synopsys, Synplicity, and Viewlogic Design Entry and Simulation Tools General Description The New SX Family of FPGAs Actels SX Family of FPGAs features a revolutionary new sea-of-modules architecture that delivers next-generation device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further speed Place and Route time-to-market for performance-intensive applications. SX Product Profile RT54SX16 A54SX16 RT54SX32 A54SX32 Gate Capacity 16,000 16,000 32,000 32,000 Logic Modules 1,452 1,452 2,880 2,880 Register Cells 528 528 1,080 1,080 Combinatorial Cells 924 924 1,800 1,800 User I/Os (Maximum) 177 176 224 225 JTAG Yes Yes Yes Yes Packages (by pin count) CQFP 208, 256 208, 256 208, 256 208, 256 February 1999 1999 Actel CorporationsActel Actels RadTolerant (RT) and HiRel versions of the SX Family of FPGAs offer all of these advantages for applications such as commercial and military satellites, deep space probes, and all types of military and high reliability equipment. The RT and HiRel versions are fully pin compatible allowing designs to migrate across different applications that may or may not have radiation requirements. Also the HiRel devices can be used as alow cost prototyping tool for RT designs. The programmable architecture of these devices offer high performance, design flexibility and fast and inexpensive prototypingall without the expense of test vectors, NRE charges, long lead times and schedule and cost penalties for design modifications required by ASIC devices. Device Description The RT54SX16 and A54SX16 devices have 16,000 available gates and up to 177 |/Os. The RT54SX32 and A54SX32 have 32,000 available gates and up to 225 I/Os. All of these devices support JTAG boundary scan testability. All of these devices are available in Ceramic Quad Flat Pack (CQFP) packaging, with 208-pin and 256-pin versions. The 256-pin version offers the user the highest I/O capability, while the 208-pin version offers pin compatibility with the commercial Plastic Quad Flat Pack (PQFP-208). This compatibility allows the user to prototype using the very low cost plastic package and then switch to the ceramic package for production. For more information on plastic packages, please refer to the SX Series FPGAs data sheet, located on the Actel web site at: http://www.actel.com/products/devices/datasheets.html. The A54SX16 and A54SX32 are manufactured using a 0.35u technology at the Chartered Semiconductor facility in Singapore. These devices offer the highest speed performance available in FPGAs today. The RT54SX16 and RT54SX32 are manufactured using a 0.6u technology at the Matsushita (MEC) facility in Japan. These devices offer levels of radiation survivability far in excess of typical CMOS devices. Radiation Survivability Total dose results are summarized in two ways. First, the maximum total dose level that is reached when the parts fail to meet a device specification but remain functional. For Actel FPGAs, the parameter that exceeds the specification first is ICC, the standby supply current. Second, the maximum total dose that is reached prior to the functional failure of the device. The RT devices have varying total dose radiation survivability. The ability of these devices to survive radiation effects is both device and lot dependent. The customer must evaluate and determine the applicability of these devices to their specific design and environmental requirements. Typical results for the RT devices have shown from 60 to 100 Krads (S) for standby ICC, and up to 240 Krads for functional failure. Actel will provide total dose radiation testing on each lot that is available for sale. Actel will provide these reports on our website or you can contact your local sales representative to receive a copy. We will also provide a listing of available lots and devices. These results are only provided for reference and for customer information. A summary of the radiation performance of Actel products (Radiation Performance of Actel Products) can be found on the Actel Web site at http://www.actel .com/products/devices/radhard/radperf.paf This summary will also show SEU and SEL testing that has been performed. Disclaimer All radiation performance information is provided for information purposes only and is not guaranteed. The total dose effects are lot-dependent, and Actel does not warrant that future devices will continue to exhibit similar radiation characteristics. In addition, actual performance can vary widely due to a variety of factors, including but not limited to, characteristics of the orbit, radiation environment, proximity to satellite exterior, amount of inherent shielding from other sources within the satellite and actual bare die variations. For these reasons, Actel does not warrant any level of radiation survivability, and it is solely the responsibility of the customer to determine whether the device will meet the requirements of the specific design. Design Tool Support As with all Actel FPGAs, these devices are fully supported by Actels Designer Series development tools, which include: * DirectTime for automated, timing-driven place and route; * ACTgen for fast development using a wide range of macro functions; and * ACTmap for logic synthesis. Designer Series supports industry-leading VHDL- and Verilog-based design tools, including synthesis tools from industry leaders such as Exemplar Logic, Synplicity, and Synopsys. 1. Designer Series also supports design entry and simulation tools from Cadence, Mentor Graphics, and Viewlogic.54SX Family FPGAs RadTolerant and HiRel In addition, these devices are supported by Actels new Silicon Explorer diagnostic and debugging tool kit. Silicon Explorer dramatically reduces verification time from several hours per cycle to a few seconds by enabling real-time, in-circuit debugging. Silicon Explorer includes: * Probe Pilot, a high-speed signal acquisition and control tool that samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Probe Pilot features 18 probing channels and connects to the users PC via a standard serial port connection. * Diagnostic software, which turns the PC into a fully-featured, 100 MHz logic analyzer for easy graphical analysis of waveforms. Silicon Explorer probes 100 percent of the device circuitry using Probe Pilots powerful, 18-channel signal acquisition capability. Individual bugs are then isolated and passed to the user interface, providing the user with complete waveform data. Fast and Flexible New Architecture Actels SX architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell), each optimized for fast and efficient mapping of synthesized logic functions. Optimal use of the silicon is made by locating the routing and interconnect resources in the metal layers above the logic modules, enabling the entire floor of the device to be spanned with an uninterrupted grid of Ordering Information RT54SX32 - 1 cQ 256 ___ Speed Grade Blank -1 - Part Number A54SX16 = 16,000 Gates A54SX32 = 32,000 Gates RT54SX16 = Package Type CQ = Ceramic Quad Flat Pack fine-grained, synthesis-friendly logic modules (or sea-of-modules) which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX devices employ both local and general routing resources. The high-speed local routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (typically 90% of connections use only three antifuses). The unique local and general routing structure featured in SX devices gives fast and predictable performance, allows 100% pin-locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with a minimum of effort. Further complementing the SXs flexible routing structure, a hard-wired, constantly-loaded clock network has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clock-to-out or fast input set-up times. SX devices have easy-to-use I/O cells which do not require HDL instantiation, facilitating design re-use and reducing design and debugging time. i Application (Temperature Range) Blank = Commercial (0 to +70C) M = Military (-55 to +125C) B = MIL-STD-883 E = E-Flow (Actel Space Level Flow) Package Lead Count Standard Speed Approximately 15% Faster than Standard 16,000 GatesRadTolerant RT54SX32 = 32,000 GatesRad TolerantsActel Product Plan Speed Grade Application Std -1* Cc M B E RT54SX16 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) P P P P P P 256-Pin Ceramic Quad Flat Pack (CQFP) P P P P P P A54SX16 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) P P P P P _ 256-Pin Ceramic Quad Flat Pack (CQFP) P P P P P _ RT54SX32 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) P P P P P P 256-Pin Ceramic Quad Flat Pack (CQFP) P P P P P P A54SX32 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) P P P P P _ 256-Pin Ceramic Quad Flat Pack (CQFP) P P P P P _ Consult your local Actel sales representative for product availability. Applications; C = Commercial Availability: &% = Available M = Military P = Planned B = MIL-STD-883 = Not Planned E = E-flow (Actel Space Level Flow) Plastic Device Resources User I/Os Device CQFP 208-Pin | CQFP 256-Pin RT54SX16 171 176 A54SX16 172 177 RT548X32 170 224 A548X32 171 225 Package Definitions: CQFP = Ceramic Quad Flat Pack (Consult your local Actel sales representative for product availability.) * Speed Grade: -1 Approx. 15% Faster than Standard54SX Family FPGAs RadTolerant and HiRel Pin Description CLKA Clock A (Input) TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOWor HIGH on the board. It must not be left floating. CLKB Clock B (Input) TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOWor HIGH on the board. It must not be left floating. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock (Input) TTL clock input for sequential modules. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. 1/0 Input/Output (Input, Output) The I/O pin functions as an input, output, three-state, or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are tri-stated by the Designer Series software. NC No Connection This pin is not connected to circuitry within the device. PRA ActionProbe A (Output) The ActionProbe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the ActionProbe B pin to allow real-time diagnostic output of any signal path within the device. The ActionProbe A pin can be used as a user-defined I/O when debugging has been completed. PRB ActionProbe B (Output) The ActionProbe B pin is used to output data from any node within the device. This diagnostic pin can be used in conjunction with the ActionProbe A pin to allow real-time diagnostic output of any signal path within the device. The ActionProbe B pin can be used as a user-defined I/O when debugging has been completed. TCK Test Clock (Input) Test clock input for diagnostic probe and device programming. In flexible mode (refer to the JTAG pins functionality table) , TCK becomes active when the TMS pin is set LOW. This pin functions as an I/O when the JTAG state machine reaches the logic reset state. TDI Test Data Input (Input) Serial input for JTAG and diagnostic probe. In flexible mode, (refer to the JTAG pins functionality table), TDI is active when the TMS pin is set LOW. This pin functions as an I/O when the JTAG state machine reaches the logic reset state. TDO Test Data Output (output) Serial output for JTAG. In flexible mode (Refer to the JTAG pins functionality table), TDO is active when the TMS pin is set LOW. This pin functions as an I/O when the JTAG state machine reaches the logic reset state. TMS Test Mode Select (Input) The TMS pin controls the use of JTAG pins (TCK, TDI, TDO). In flexible mode (refer to the JTAG pins functionality table), when the TMS pin is set LOW, the TCK, TDI, and TDOpins are JTAG pins. Once the JTAG pins are in JTAG mode they will remain in JTAG mode until the internal JTAG state machine reaches the logic reset state. At this point the JTAG pins will be released and will function as regular I/O pins. The logic reset state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated JTAG mode, TMS functions as specified in the IEEE 499.1 JTAG Specifications. JTAG operation is further described on page 6. TRST Test Reset Pin (Input) JTAG reset pin (active LOW). This pin is used to reset the JTAG state machine in test-logic-reset state to avoid accidental shifts into various JTAG operations due to the effects of heavy ions in a radiation environment. When this pin is tied LOW, the device is held in the itest-logic-resetf state and the JTAG functionality cannot be used. When this pin is tied HIGH, the JTAG function can operate. This pin should not be left floating. Vecl Supply Voltage Supply voltage for 1/Os. Veca Supply Voltage Supply voltage for Array. Vecr Supply Voltage Supply voltage for input tolerance (required for internal biasing).sActel SX JTAG Pins Functionality Table All SX devices feature hard-wired IEEE 1149.1 JTAG Boundary Scan Test circuitry. Figure 1 is a block diagram of the A54SX JTAG circuitry and Figure 2 shows the RT54SX JTAG circuitry. The RT548X devices include a TRST pin which is used to reset the JTAG state machine in test-logic-reset mode. SX devices offer superior diagnostic and testing capabilities by rpoviding JTAG and probing capabilities. These functions are controlled through the special JTAG pins in conjunction with the program fuse. The functionality of each pin is described in Table 1 below. In the dedicated JTAG mode, TCK, TDI and TDO are dedicated JTAG pins and cannot be used as regular I/Os. In flexible mode, TMS should be set HIGH through a pull-up Table? + JTAG Program Fuse Blown Program Fuse Not Blown (Dedicated JTAG Mode) (Flexible Mode) TCK, TDI, TDO are TCK, TDI, TDO are flexible dedicated JTAG pins and may be used as I/Os No need for pull-up Use a pull-up resistor of 10K resistor for TMS ohm on TMS resistor of 10K ohm. TMS can be pulled LOW to initiate the JTAG sequence. The program fuse determines whether the device is in dedicated or flexible mode. The default (fuse not blown) is flexible mode. Regardless of which mode is chosen, tying the TRST pin LOW will disable all JTAG functionality. -_-_--- y TDI et. Data Registers (DRs) y roc | et output a > stage wi TDO m1 Instruction Register (IR) clocks and/or controls TMS = TAP Controller Tck E#__ Powerup Reset Figure? + A54SX JTAG Circuitry54SX Family FPGAs RadTolerant and HiRel TUS ai. TcK E-> TRST external hard-wired pin y Data Registers (DRs) roc o | y ti output a > stage | TDO Instruction Register (IR) clocks and/or controls T+ TAP Controller Figure2 + RT54SX JTAG CircutirysActel SX Family Architecture The SX Family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. Programmable Interconnect Element Actels new SX Family provides much more efficient use of silicon by locating the routing interconnect resources between the Metal 2 (M2) and Metal 3 (M3) layers (see Figure 3). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs) , and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using Actels patented metal-to-metal programmable antifuse interconnect elements, which are embedded between the M2 and M3 layers. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The extremely small size of these interconnect elements gives the SX Family abundant routing resources and provides excellent protection against design pirating. Reverse engineering is virtually impossible as it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and there is no configuration bitstream to intercept. Additionally, the interconnect (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. Routing Tracks J} fo Metal 3 a@ Amorphous Silicon/ <__ Dielectric Antifuse Tungsten Plug Via Tungsten Plug Via Tungsten Plug Contact _> Metal 1 Figure3 + SX Family Interconnect Elements54SX Family FPGAs RadTolerant and HiRel Logic Module Design The SX Family architecture has been called a sea-of-modules architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing (see Figure 4). Actel provides two types of logic modules, the R-cell and the C-cell. The Rell (or register cell) contains a flip-flop featuring more control signals than in previous Actel architectures, including asynchronous clear, asynchronous preset, and clock enable (using the SO and Si lines). The R-cell (Figure 5) registers feature programmable clock polarity, selectable on a register-by-register basis. This provides the designer with additional flexibility while allowing mapping of synthesized functions into the SX FGPA. The clock source for the R-cell can be chosen from the hard-wired clock or the routed clock. The C-cell (or combinatorial cell, Figure6) implements a range of combinatorial functions up to 5-inputs. Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions which can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the SX architecture. An example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions with 2 ns propagation delays. At the same time, the C-cell structure is extremely synthesis-friendly, simplifying the overall design and reducing synthesis time. Chip Architecture The SX Family's chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. Channelled Array Architecture Sea-of-Modules Architecture Figure 4 + Channelled Array and Sea-of-Modules ArchitecturessActel Routed Data Input St PSETB Direct Connect D Q Y Input HCLK | CLKA, CLRB CLKB CKS CKP Figure5 + R-Cell DO D1 l Y D2 D3 l Sa Sb DB > AO! |IBO Ail |B1 Figure6 + C-Cell Module Organization Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into Super Clusters (see Figure 7). SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. SX devices feature significantly more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. Routing Resources Clusters and SuperClusters can be connected through the use of two innovative new local routing resources called FastConnect and DirectConnect which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (see Figure 8 and Figure 9). This routing architecture also dramatically reduces the number of antifuses required to complete acircuit, ensuring the highest possible performance. 1054SX Family FPGAs RadTolerant and HiRel R-Cell C-Cell Cluster 1 Cluster 2 Type 1 SuperCluster Cluster 2 Cluster 1 Type 2 SuperCluster Figure7 + Cluster Organization DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster, and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path. In addition to DirectConnect and FastConnect, the architecture makes use of two globally-oriented routing resources known as segmented routing and high-drive routing. Actels segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100% automatic place and route software to minimize signal propagation delays. Actels high-drive routing structure provides three clock networks. The first clock, called HCLK, is hard-wired from the HCLK buffer to the clock select MUX in each R-cell. This provides a fast propagation path for the clock signal. The hard-wired clock is tuned to provide clock skew as low as 0.25 ns. The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal signal logic within the SX device. 11_Actel Direct Connect *No antifuses > Fast Connect * One antifuse p> Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 1 SuperClusters Figure 8 + DirectConnect and FastConnect for Type 1 Super Clusters A > Direct Connect * No antifuses > Fast Connect 0 * One antifuse > Routing Segments * Typically 2 antifuses * * Max. 5 antifuses Type 2 SuperClusters Figure9 + DirectConnect and FastConnect for Type 2 SuperClusters 1254SX Family FPGAs RadTolerant and HiRel 3.3V/5V Operating Conditions Absolute Maximum Ratings Recommended Operating Conditions Symbol Parameter Limits Units Parameter Commercial Military Units 3 2 4 Vecr DC Supply Voltage 0.3 to +6.0 Vv remperature 0 to +70 55 to +125 C Veca DC Supply Voltage -0.3 to +4.0 Vv ang DC Supply Voltage oN Tole +10 +10 %Voc Veo? (A54SX08, A54SX16, -0.3t0+4.0 V upply tolerance A548X32) 5V Power Supply +5 +10 %Voo Tolerance Ven DC Supply Voltage -0.3 to +6.0 Vv CCl (A54SX16P) eto. Note: _ I. Ambient temperature (T,) is used for commercial and VI Input Voltage 0.5 to +5.5 Vv military; case temperature (Tc) is used for military. Vo Output Voltage 0.5 to +3.6 Vv 1/0 Source Sink lio 3 -30 to +5.0 mA Current Tsta Storage Temperature -40to+125 C Notes: 1. Stresses beyond those listed unde Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than Voc + 0.5Vor less than GND 0.5V, the internal protection diodes will forward-bias and can draw excessive current. 3. Vecr must be greater than or equal to Vcc; during power-up and power-down sequences and during normal operation. Electrical Specifications Commercial Military Symbol Parameter Min. Max. Min. Max. Units (lon = -20UA) (CMOS) (Vec-0.1) Vec (Vec-0.1) Vec Vou (lo = -8mA) (TTL) 2.4 Vec Vv (lo = -6mA) (TTL) 2.4 Voc (loL= 20UA) (CMOS) 0.10 VoL (lo, = 12mA) (TTL) 0.50 Vv (lo, = 8MA) (TTL) 0.50 Vit 0.8 0.8 Vv Vin 2.0 2.0 Vv tp, te Input Transition Time tp, te 50 50 ns Cio Cig /O Capacitance 10 10 pF loc Standby Current, loc 4.0 20 mA lec(p) loop) lbynamic Voc Supply Current See Power Dissipation on page 15. mA 13(el Power-Up Sequencing RT54SX16, A54SX16, RT54SX32, A54SX32 Voca Vocr Vecl Power-Up Sequence Comments 5.0V First . . 3.3V Second No possible damage to device. 3.3V 5.0V 3.3V 33VE . irst . . 5.0V Second No possible damage to device. Power-Down Sequencing RT54SX16, A54SX16, RT54SX32, A54SX32 Veca Vocr Vec Power-Down Sequence Comments 5.0V First . . 3.3V Second No possible damage to device. 3.3V 5.0V 3.3V 33V Enel . irs . . 5.0V Second No possible damage to device. Package Thermal Characteristics Maximum junction temperature is 150C. The device junction to case thermal characteristicis ,,and A sample calculation of the absolute maximum power the junction to ambient air characteristic is 0. The thermal dissipation allowed for an RTS4SX16 in a CQFP 256-pin characteristics for @,, are shown with two different air flow package at military temperature and still air is as follows: rates. Max. junction temp. (C) Max. ambient temp. (C) _ 150C 125C Absolute Maximum Power Allowed = 4 CCIW) 23C]W = 1.09W Oa Package Type Pin Count Vic Still Air Units RT54SX16 Ceramic Quad Flatpack (CQFP) 208 7.5 29 CAN Ceramic Quad Flatpack (CQFP) 256 4.6 23 CAN RT54SX32 Ceramic Quad Flatpack (CQFP) 208 6.9 35 CAN Ceramic Quad Flatpack (CQFP) 256 3.5 20 CAN RT54SX16 Ceramic Quad Flatpack (CQFP) 208 7.9 30 CAN Ceramic Quad Flatpack (CQFP) 256 5.6 25 CAN RT54SX16 Ceramic Quad Flatpack (CQFP) 208 7.6 30 CAN Ceramic Quad Flatpack (CQFP) 256 4.8 24 CAN 1454SX Family FPGAs RadTolerant and HiRel Power Dissipation P= [locstandby + lecactive] * Voca + lo. * Vo. * N+ lou (Voca - Vou) * M Where: lecstandby is the current flowing when no inputs or outputs are changing. Iocactive is the current flowing due to CMOS switching. lo, loy are TTL sink/source currents. Vo., Vou are TTL level output voltages. N equals the number of outputs driving TTL loads to Vo, . M equals the number of outputs driving TTL loads to Voy. An accurate determination of N and M is problematical because their values depend on the design and on the system 1/0. The power can be divided into two components: static and active. Static Power Component The power due to standby current is typically a small component of the overall power. Standby power is shown below for military, worst case conditions (70C). Power 7omW loc Voc 20mA 3.6V Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent, a function of the logic and the external 1/0. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external An additional component of the active power dissipation is the totempole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. Equivalent Capacitance The power dissipated by a CMOS circuit can be expressed by the Equation 1. Power (uW) = Ceg* Voca?* F (1) Where: Ceqis the equivalent capacitance expressed in pF. Veca is the power supply in volts. F isthe switching frequency in MHz. Equivalent capacitance is calculated by measuring Icactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of Voca. Equivalent capacitance is frequency-independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. Ceg Values (pF) To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power = Vga? * [(m * Cequ* fn) modules + (n* Ceqi * fh) inputst (P (Ceao + CL) * fp) outputst 0.5* (4 * Cegor * fy1) routed_cikt + (14 * fgt)routed_clkt + 0.5* (do * Cegor * fy2) routed_cik2t (Fo * foe) routed_clk2 + capacitance due to PC board traces and load device inputs. 0.5 * (s; * Ceqon * fst) dedicated CLK] (2) Table2 - RT54SX16 A54SX16 RT54SX32 A54SX32 Equivalent Capacitance (pf) Modules Ceaqm 7.0 3.9 7.0 3.9 Input Buffers Ceqy 2.0 1.0 2.0 1.0 Output Buffers CEQo 10.0 5.0 10.0 5.0 Routed Array Clock Buffer Loads Ceacr 0.4 0.2 0.6 0.3 Dedicated Clock Buffer Loads Ceacp 0.25 0.15 0.34 0.23 Fixed Capacitance (pF) routed_Clk1 ry 120 60 210 107 routed_Clk2 lp 120 60 210 107 Fixed Clock Loads Clock Loads on Dedicated Array Clock S1 528 528 1,080 1,080 15sActel Where: m n p q; Qe ry Po Number of logic modules switching at f,, Number of input buffers switching at f, Number of output buffers switching at f, Number of clock loads on the first routed array clock Number of clock loads on the second routed array clock Fixed capacitance due to first routed array clock Fixed capacitance due to second routed array clock Fixed number of clock loads on the dedicated array clock= (528 for A54SX16) Equivalent capacitance of logic modules in pF Equivalent capacitance of input buffers in pF Equivalent capacitance of output buffersin pF Equivalent capacitance of routed array clock in pF Equivalent capacitance of dedicated array clock in pF Output lead capacitance in pF Average logic module switching ratein MHz Average input buffer switching rate in MHz Average output buffer switching rate in MHz Average first routed array clock rate in MHz Average second routed array clock rate in MHz Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) Inputs Switching (n) Out puts Switching (p) First Routed Array Clock Loads (q,) Second Routed Array Clock Loads (2) Load Capacitance (C,) Average Logic Module Switching Rate (f,,) Average Input Switching Rate (f,) Average Output Switching Rate (f,) Average First Routed Array Clock Rate (f,1) Average Second Routed Array Clock Rate (fyo) Average Dedicated Array Clock Rate (fs) 80% of modules #inputs/4 # output/4 40%of sequential modules 40%of sequential modules 35 pF F/10 F/5 F/10 F/2 F/2 F 1654SX Family FPGAs RadTolerant and HiRel Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, Ty = 70C, Veca = 3.0V) Junction Temperature (Ty) Veca 40 0 25 70 85 125 3.0 0.78 0.87 0.89 1.00 1.04 1.16 3.3 0.73 0.82 0.83 0.93 0.97 1.08 3.6 0.69 0.77 0.78 0.87 0.92 1.02 5435xX Timing Model Input Delays Internal Delays Predicted Output Delays Routing Delays r/O Module |] Combinatorial [ 70 Moduie | ih =2.2N8 | taps =1.2ns | | \ tpHL = 2-8 ns ! DHL = <: 1 1 : | a L__ tpp =0.9 ns vot = OO ne nn RD4 =<: traps = 4.3 ns - 1/0 Module 4 toHL =2.8ns Register Register | ell Cell | | D D | wt | | Q | trot = 0-7 ns| Q | trot = 0.7 ns tx] | teNZH = 2.8 ns | tsup =0.8ns | | | tup = 0.0 ns | | taco 2 6.6 ns incon 0.6ns L___ _ tackH =2.8ns (1 00% Load) FMax = 175 MHz Hard-Wired Clock tucKH =1.3ns FumMax = 240 MHz *Values shown for AS4SX16-1, worst-case commercial conditions. Hard-Wired Clock External Set-Up = tiny + tinpy + tsup - tuokH = 22+ 0.7+ 0.8-1.7=2.0ns Clock-to-Out (Pin-to-Pin) = tHckH + trco+ tap1 + tpHL = 17+ 06+ 0.7+ 28=58ns Routed Clock External Set-Up = tiny + tirpy + tsup -treKy = 22+ 0.7+ 0.8-24= 1.3ns Clock-to-Out (Pin-to-Pin) = tack + tacot trpt + toHL = 24+ 0.6+ 0.7+ 28 = 6.5ns 17sActel Output Buffer Delays tENHZ AC Test Loads Load 1 (Used to measure propagation delay) To the output under test Load 2 (Used to measure rising/falling edges) Voc GND e e 50 pF R to Veco for te_ztpz. R to GND for tpyz/tpzy = To the output under test R=1kQ 50 pF input Buffer Delays C-Cell Delays Y PAD 3V tiny tiny Voc S,AorBy50% 50%N__GND_ Voc Out 50% 50% GND tpp Out 50% tep 1854SX Family FPGAs RadTolerant and HiRel Register Cell Timing Characteristics Flip-Flops D__|PRESE} @ CLK+ CLR (Positive edge triggered) | tuo k= D_ OX xX - tsup>>| tupwH. -->| |}< typ +| CLK 1 tRewH | 1 rT 4 . l typwi, >| taco | tRewL Q Z X / torr tereser | CLR | twasyn PRESET | Timing Characteristics Timing characteristics for 54SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all 54SX family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the users design is complete. Delay values may then be determined by using the DirectTime Analyzer utility or performing simulation with post-layout del ays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the netsin adesign are typical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6%of netsin a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout (FO=24) routing delays in the data sheet specifications section. Timing Derating 54SX devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. 19sActel A54SXK16 Timing Characteristics (Worst-Case Military Conditions, Vocr= 4-75 V, Voeca,Veci = 3-0 V, Ty = 125C) C-Cell Propagation Delays 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tpp Internal Array Module 0.9 1.0 ns Predicted Routing Delays? toc FO=1 Routing Delay, Direct Connect 0.1 0.1 ns tec FO=1 Routing Delay, Fast Connect 0.6 0.7 ns trp FO=1 Routing Delay 0.7 0.8 ns tape FO=2 Routing Delay 1.2 1.4 ns taps FO=3 Routing Delay 1.7 2.0 ns trp4 FO=4 Routing Delay 2.2 2.6 ns tapos FO=8 Routing Delay 4.3 5.0 ns tap12 FO=12 Routing Delay 5.6 6.6 ns tapis FO=18 Routing Delay 9.4 11.0 ns tape FO=24 Routing Delay 12.4 14.6 ns R-Cell Timing trco Sequential Clock-to-Q 0.6 0.8 ns tcLr Asynchronous Clear-to-Q 0.6 0.8 ns tsup Flip-Flop Data Input Set-Up 0.8 0.9 ns tub Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 2.4 2.9 ns Notes: 1. For dual-module macros, usetpp + tani + tep,, tacot taps t+ tpn OF tepy + taps + tsyp, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-routetiming analysis or simulation is required to deter mine actual worst-case per for mance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 2054SX Family FPGAs RadTolerant and HiRel A54SK16 Timing Characteristics (continued) (Worst-Case Military Conditions) I/O Module Input Propagation Delays 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tINYH Input Data Pad-to-Y HIGH 2.2 2.6 ns tINYL Input Data Pad-to-Y LOW 2.2 2.6 ns Predicted Input Routing Delays tirnp4 FO=1 Routing Delay 0.7 0.8 ns tinpe FO=2 Routing Delay 1.2 1.4 ns tirnDs FO=3 Routing Delay 1.7 2.0 ns tirnpa FO=4 Routing Delay 2.2 2.6 ns tinps FO=8 Routing Delay 4.3 5.0 ns tinp12 FO=12 Routing Delay 5.6 6.6 ns tinD18 FO=18 Routing Delay 9.4 11.0 ns tinpe4 FO=24 Routing Delay 12.4 14.6 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 21sActel A54SK16 Timing Charateristics(continued) (Worst-Case Military Conditions) 1/O Module TTL Output Timing 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units toLH Data-to-Pad LOW to HIGH 2.8 3.3 ns toHL Data-to-Pad HIGH to LOW 2.8 3.3 ns tENZL Enable-to-Pad, Z to L 2.3 2.8 ns tENZH Enable-to-Pad, Z to H 2.8 3.3 ns tENLZ Enable-to-Pad, L to Z 4.5 5.2 ns tENHZ Enable-to-Pad, H to Z 2.2 2.6 ns GtLy Delta LOW to HIGH 0.05 0.06 ns/pF OTHL Delta HIGH to LOW 0.05 0.08 ns/pF Note: 1. Delays based on 35pF loading, except teyz and texzy. For ten and teyzy the loading is 5pF. 2254SX Family FPGAs RadTolerant and HiRel A54SK16 Timing Characteristics (continued) (Worst-Case Military Conditions) Dedicated (Hard-Wired) Array Clock Network 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.7 2.0 ns tHcKL Input HIGH to LOW (Pad to R-Cell Input) 1.9 2.2 ns tHPWH Minimum Pulse Width HIGH 2.1 2.4 ns tuPWL Minimum Pulse Width LOW 2.1 2.4 ns tucksw Maximum Skew 0.4 0.4 ns tup Minimum Period 4.2 4.9 ns fuMax Maximum Frequency 240 205 MHz Routed Array Clock Networks tRcKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.4 2.9 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.7 3.1 ns tackH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.9 3.3 ns tRcKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.9 3.5 ns tackH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.8 3.3 ns tRcKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.9 3.5 ns tRPWH Min. Pulse Width HIGH 3.1 3.7 ns tRPWL Min. Pulse Width LOW 3.1 3.7 ns tracKksw Maximum Skew (Light Load) 0.6 0.8 ns tacksw Maximum Skew (50% Load) 0.8 0.9 ns tacksw Maximum Skew (100% Load) 0.8 0.9 ns 23sActel RT54SX16 Timing Characteristics (Worst-Case Military Conditions, Vocr= 4-75 V, Voeca,Veci = 3-0 V, Ty = 125C) C-Cell Propagation Delays 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tpp Internal Array Module 1.7 1.8 ns Predicted Routing Delays? toc FO=1 Routing Delay, Direct Connect 0.2 0.2 ns tec FO=1 Routing Delay, Fast Connect 1.1 1.3 ns tap1 FO=1 Routing Delay 1.3 1.5 ns tape FO=2 Routing Delay 2.2 2.6 ns taps FO=3 Routing Delay 3.1 3.6 ns tapa FO=4 Routing Delay 4.0 4.7 ns tapos FO=8 Routing Delay 7.8 9.0 ns tap12 FO=12 Routing Delay 10.1 11.9 ns tapis FO=18 Routing Delay 17.0 19.8 ns tape FO=24 Routing Delay 22.4 26.3 ns R-Cell Timing trco Sequential Clock-to-Q 1.5 2.0 ns tcLr Asynchronous Clear-to-Q 1.5 2.0 ns tsup Flip-Flop Data Input Set-Up 2.0 2.2 ns tub Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 4.4 5.3 ns Notes: 1. For dual-module macros, usetpp + tani + tep,, tacot taps t+ tpn OF tepy + taps + tsyp, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-routetiming analysis or simulation is required to deter mine actual worst-case per for mance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 2454SX Family FPGAs RadTolerant and HiRel RT54SX16 Timing Characteristics (continued) (Worst-Case Military Conditions) I/O Module Input Propagation Delays 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tINYH Input Data Pad-to-Y HIGH 4.0 4.7 ns tINYL Input Data Pad-to-Y LOW 4.0 4.7 ns Predicted Input Routing Delays tiap1 FO=1 Routing Delay 1.3 1.5 ns tinpe FO=2 Routing Delay 2.2 2.6 ns tirnDs FO=3 Routing Delay 3.1 3.6 ns tinp4 FO=4 Routing Delay 4.0 4.7 ns tinps FO=8 Routing Delay 7.8 9.0 ns tinp12 FO=12 Routing Delay 10.1 11.9 ns tinD18 FO=18 Routing Delay 17.0 19.8 ns tinpe4 FO=24 Routing Delay 22.4 26.3 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 25sActel RT54SX16 Timing Charateristics (continued) (Worst-Case Military Conditions) 1/O Module TTL Output Timing 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units toLy Data-to-Pad LOW to HIGH 5.1 6.0 ns toHL Data-to-Pad HIGH to LOW 5.1 6.0 ns teENZL Enable-to-Pad, Z to L 4.2 5.1 ns tENZH Enable-to-Pad, Z to H 5.1 6.0 ns tENLZ Enable-to-Pad, L to Z 8.1 9.4 ns teNHz Enable-to-Pad, H to Z 4.0 4.7 ns GtLy Delta LOW to HIGH 0.09 0.11 ns/pF OTHL Delta HIGH to LOW 0.09 0.15 ns/pF Note: 1. Delays based on 35pF loading, except teyz and texzy. For ten and teyzy the loading is 5pF. 2654SX Family FPGAs RadTolerant and HiRel RT54SX16 Timing Characteristics (continued) (Worst-Case Military Conditions) Dedicated (Hard-Wired) Array Clock Network 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tHCKH Input LOW to HIGH (Pad to R-Cell Input) 3.1 3.6 ns tHcKL Input HIGH to LOW (Pad to R-Cell Input) 3.5 4.0 ns tHPWH Minimum Pulse Width HIGH 3.8 4.4 ns tuPWL Minimum Pulse Width LOW 3.8 4.4 ns tucksw Maximum Skew 0.8 0.8 ns tup Minimum Period 7.6 8.9 ns fuMax Maximum Frequency 130 110 MHz Routed Array Clock Networks tRcKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 4.4 5.3 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 4.9 5.6 ns tackH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 5.3 6.0 ns tRcKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 5.3 6.3 ns tackH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 5.1 6.0 ns tRcKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 5.3 6.3 ns tRewH Min. Pulse Width HIGH 5.6 6.7 ns tRPWL Min. Pulse Width LOW 5.6 6.7 ns tracKksw Maximum Skew (Light Load) 1.1 1.5 ns tacksw Maximum Skew (50% Load) 1.5 1.7 ns tacksw Maximum Skew (100% Load) 1.5 1.7 ns 27sActel A54SX32 Timing Characteristics (Worst-Case Military Conditions, Vocr= 4-75 V, Voeca,Veci = 3-0 V, Ty = 125C) C-Cell Propagation Delays 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tpp Internal Array Module 0.9 1.0 ns Predicted Routing Delays? toc FO=1 Routing Delay, Direct Connect 0.1 0.1 ns tec FO=1 Routing Delay, Fast Connect 0.6 0.7 ns trp FO=1 Routing Delay 0.7 0.8 ns tape FO=2 Routing Delay 1.2 1.4 ns taps FO=3 Routing Delay 1.7 2.0 ns trp4 FO=4 Routing Delay 2.2 2.6 ns tapos FO=8 Routing Delay 4.3 5.0 ns tap12 FO=12 Routing Delay 5.6 6.6 ns tapis FO=18 Routing Delay 9.4 11.0 ns tape FO=24 Routing Delay 12.4 14.6 ns R-Cell Timing trco Sequential Clock-to-Q 0.6 0.8 ns tcLr Asynchronous Clear-to-Q 0.6 0.8 ns tsup Flip-Flop Data Input Set-Up 0.8 0.9 ns tub Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 2.4 2.9 ns Notes: 1. For dual-module macros, usetpp + tani + tep,, tacot taps t+ tpn OF tepy + taps + tsyp, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 2854SX Family FPGAs RadTolerant and HiRel A54SXK32 Timing Characteristics (continued) (Worst-Case Military Conditions) I/O Module Input Propagation Delays 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tINYH Input Data Pad-to-Y HIGH 2.2 2.6 ns tINYL Input Data Pad-to-Y LOW 2.2 2.6 ns Predicted Input Routing Delays tirnp4 FO=1 Routing Delay 0.7 0.8 ns tinpe FO=2 Routing Delay 1.2 1.4 ns tirnDs FO=3 Routing Delay 1.7 2.0 ns tirnpa FO=4 Routing Delay 2.2 2.6 ns tinps FO=8 Routing Delay 4.3 5.0 ns tinp12 FO=12 Routing Delay 5.6 6.6 ns tinD18 FO=18 Routing Delay 9.4 11.0 ns tinpe4 FO=24 Routing Delay 12.4 14.6 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 29sActel A54SXK32 Timing Charateristics (continued) (Worst-Case Military Conditions) 1/O Module TTL Output Timing 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units toLH Data-to-Pad LOW to HIGH 2.8 3.3 ns toHL Data-to-Pad HIGH to LOW 2.8 3.3 ns tENZL Enable-to-Pad, Z to L 2.3 2.8 ns tENZH Enable-to-Pad, Z to H 2.8 3.3 ns tENLZ Enable-to-Pad, L to Z 4.5 5.2 ns tENHZ Enable-to-Pad, H to Z 2.2 2.6 ns GtLy Delta LOW to HIGH 0.05 0.06 ns/pF OTHL Delta HIGH to LOW 0.05 0.08 ns/pF Note: 1. Delays based on 35pF loading, except teyz and texzy. For ten and teyzy the loading is 5pF. 3054SX Family FPGAs RadTolerant and HiRel A54SXK32 Timing Characteristics (continued) (Worst-Case Military Conditions) Dedicated (Hard-Wired) Array Clock Network 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.7 2.0 ns tHcKL Input HIGH to LOW (Pad to R-Cell Input) 1.9 2.2 ns tHPWH Minimum Pulse Width HIGH 2.1 2.4 ns tuPWL Minimum Pulse Width LOW 2.1 2.4 ns tucksw Maximum Skew 0.4 0.4 ns tup Minimum Period 4.2 4.8 ns fuMax Maximum Frequency 240 205 MHz Routed Array Clock Networks tRcKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.4 2.9 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.7 3.1 ns tackH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.9 3.3 ns tRcKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.9 3.5 ns tackH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.8 3.3 ns tRcKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.9 3.5 ns tRPWH Min. Pulse Width HIGH 3.1 3.7 ns tRPWL Min. Pulse Width LOW 3.1 3.7 ns tracKksw Maximum Skew (Light Load) 0.6 0.8 ns tacksw Maximum Skew (50% Load) 0.8 0.9 ns tacksw Maximum Skew (100% Load) 0.8 0.9 ns 31sActel RT54SX32 Timing Characteristics (Worst-Case Military Conditions, Vocr= 4-75 V, Voeca,Veci = 3-0 V, Ty = 125C) C-Cell Propagation Delays 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tpp Internal Array Module 1.7 1.8 ns Predicted Routing Delays? toc FO=1 Routing Delay, Direct Connect 0.2 0.2 ns tec FO=1 Routing Delay, Fast Connect 1.1 1.3 ns tap1 FO=1 Routing Delay 1.3 1.5 ns tape FO=2 Routing Delay 2.2 2.6 ns taps FO=3 Routing Delay 3.1 3.6 ns tapa FO=4 Routing Delay 4.0 4.7 ns tapos FO=8 Routing Delay 7.8 9.0 ns tap12 FO=12 Routing Delay 10.1 11.9 ns tapis FO=18 Routing Delay 17.0 19.8 ns tape FO=24 Routing Delay 22.4 26.3 ns R-Cell Timing trco Sequential Clock-to-Q 1.5 2.0 ns tcLr Asynchronous Clear-to-Q 1.5 2.0 ns tsup Flip-Flop Data Input Set-Up 2.0 2.2 ns tub Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 4.4 5.3 ns Notes: 1. For dual-module macros, usetpp + tani + tep,, tacot taps t+ tpn OF tepy + taps + tsyp, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 3254SX Family FPGAs RadTolerant and HiRel RT54SX32 Timing Characteristics (continued) (Worst-Case Military Conditions) I/O Module Input Propagation Delays 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tINYH Input Data Pad-to-Y HIGH 4.0 4.7 ns tINYL Input Data Pad-to-Y LOW 4.0 4.7 ns Predicted Input Routing Delays tiap1 FO=1 Routing Delay 1.3 1.5 ns tinpe FO=2 Routing Delay 2.2 2.6 ns tirnDs FO=3 Routing Delay 3.1 3.6 ns tinp4 FO=4 Routing Delay 4.0 4.7 ns tinps FO=8 Routing Delay 7.8 9.0 ns tinp12 FO=12 Routing Delay 10.1 11.9 ns tinD18 FO=18 Routing Delay 17.0 19.8 ns tinpe4 FO=24 Routing Delay 22.4 26.3 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 33sActel RT54SX32 Timing Charateristics (continued) (Worst-Case Military Conditions) 1/O Module TTL Output Timing 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units toLy Data-to-Pad LOW to HIGH 5.1 6.0 ns toHL Data-to-Pad HIGH to LOW 5.1 6.0 ns teENZL Enable-to-Pad, Z to L 4.2 5.1 ns tENZH Enable-to-Pad, Z to H 5.1 6.0 ns tENLZ Enable-to-Pad, L to Z 8.1 9.4 ns teNHz Enable-to-Pad, H to Z 4.0 4.7 ns GtLy Delta LOW to HIGH 0.09 0.11 ns/pF OTHL Delta HIGH to LOW 0.09 0.15 ns/pF Note: 1. Delays based on 35pF loading, except teyz and texzy. For ten and teyzy the loading is 5pF. 3454SX Family FPGAs RadTolerant and HiRel RT54SX32 Timing Characteristics (continued) (Worst-Case Military Conditions) Dedicated (Hard-Wired) Array Clock Network 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Units tuckH Input LOW to HIGH (Pad to R-Cell Input) 3.1 3.6 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 3.5 4.0 ns tHPWH Minimum Pulse Width HIGH 3.8 4.4 ns tuPWL Minimum Pulse Width LOW 3.8 4.4 ns tucksw Maximum Skew 0.8 0.8 ns tup Minimum Period 7.6 8.9 ns fuMax Maximum Frequency 130 110 MHz Routed Array Clock Networks tRcKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 4.4 5.3 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 4.9 5.6 ns tackH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 5.3 6.0 ns tRcKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 5.3 6.3 ns tackH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 5.1 6.0 ns tRcKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 5.3 6.3 ns tRewH Min. Pulse Width HIGH 5.6 6.7 ns tRPWL Min. Pulse Width LOW 5.6 6.7 ns tracKksw Maximum Skew (Light Load) 1.1 1.5 ns tacksw Maximum Skew (50% Load) 1.5 1.7 ns tacksw Maximum Skew (100% Load) 1.5 1.7 ns 35sActel Package Pin Assignments 208-Pin CQFP (Top View) 208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157 Pin #1 Index e 208-Pin e CQFP 53 54 55 56 57 58 59 60 61 97 98 99 100 101 102 103 104 Notes: 1. All unlisted pin numbers areuser 1/Os. 2. NC: Denotes No Connection 3. MODE should be terminated to GND through a 10K reistor to enable ActionProve usage, other wise it can be terminated directly to GND. 3654SX Family FPGAs RadTolerant and HiRel 208-PIN CQFP A54SX16 RT54SX16 A54SX32 RT54SX32 Pin Number Function Function Function Function 1 GND GND GND GND 2 TDI, /O TDI, VO TDI, /O TDI, VO 11 TMS TMS TMS TMS 12 Vecl Vee! Vecl Vee! 25 Vecr Vecr Vecr Vecr 26 GND GND GND GND 27 Veca Veca Veca Veca 28 GND GND GND GND 30 V/O TRST V/O TRST 40 Vee! Vecl Vee! Vecl 41 Veca Veca Voca Veca 52 GND GND GND GND 60 Vee! Vecl Vee! Vecl 65 V/O /O NC NC 76 PRB, I/O PRB, I/O PRB, I/O PRB, I/O 77 GND GND GND GND 78 Veca Veca Veca Veca 79 GND GND GND GND 80 Vecr Vecr Vecr Vecr 82 HCLK HCLK HCLK HCLK 98 Vecl Vee! Vecl Vee! 103 TDO, I/O TDO, I/O TDO, I/O TDO, I/O 105 GND GND GND GND 114 Veca Veca Veca Veca 115 Vee! Vecl Vee! Vecl 129 GND GND GND GND 130 Veca Veca Veca Veca 131 GND GND GND GND 132 Vecr Vecr Vecr Vecr 145 Veca Veca Voca Veca 146 GND GND GND GND 148 Vee! Vecl Vee! Vecl 157 GND GND GND GND 164 Vee! Vecl Vee! Vecl 180 CLKA CLKA CLKA CLKA 181 CLKB CLKB CLKB CLKB 182 Vecr Vecr Vecr Vecr 183 GND GND GND GND 184 Veca Veca Veca Veca 185 GND GND GND GND 186 PRA, I/O PRA, I/O PRA, I/O PRA, I/O 201 Vecl Vee! Vecl Vee! 208 TCK, I/O TCK, I/O TCK, I/O TCK, I/O 37sActel Package Pin Assignments (continued) 256-Pin CQFP (Top View) 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 Pin #1 Index 256-Pin e CQFP 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 Notes: 1. All unlisted pin numbers areuser 1/Os. 2. NC: Denotes No Connection 3. MODE should be terminated to GND through a 10K reistor to enable ActionProve usage, other wise it can be terminated directly to GND. 3854SX Family FPGAs RadTolerant and HiRel 256-Pin CQFP A54SX16 RT54SX16 A54SX32 RT54SX32 Pin Number Function Function Function Function 1 GND GND GND GND 2 TDI, /O TDI, VO TDI, /O TDI, VO 11 TMS TMS TMS TMS 12 NC NC V/O /O 13 NC NC V/O /O 16 NC NC V/O /O 20 NC NC V/O /O 28 Vecl Vee! Vecl Vee! 29 GND GND GND GND 30 Veca Veca Veca Veca 31 GND GND GND GND 32 NC NC V/O /O 34 V/O TRST V/O TRST 36 NC NC V/O /O 41 NC NC V/O /O 46 Veca Veca Veca Veca 48 NC NC V/O /O 51 NC NC V/O /O 54 NC NC V/O /O 57 NC NC V/O /O 59 GND GND GND GND 61 NC NC V/O /O 63 NC NC V/O /O 68 NC NC V/O /O 73 NC NC V/O /O 77 NC NC V/O /O 90 PRB, I/O PRB, I/O PRB, I/O PRB, I/O 91 GND GND GND GND 92 Vecl Vee! Vecl Vee! 93 GND GND GND GND 94 Veca Veca Veca Veca 96 HCLK HCLK HCLK HCLK 98 NC NC V/O /O 102 NC NC V/O /O 106 NC NC V/O /O 110 GND GND GND GND 114 NC NC V/O /O 118 NC NC V/O /O 122 NC NC V/O /O 125 NC NC V/O /O 126 TDO, I/O TDO, I/O TDO, I/O TDO, I/O 127 NC NC V/O /O 128 GND GND GND GND 138 NC NC V/O /O 139 NC NC V/O /O 39sActel 256-Pin CQFP (Continued) A54SX16 RT54SX16 A54SX32 RT54SX32 Pin Number Function Function Function Function 140 NC NC V/O /O 144 Veca Veca Veca Veca 155 NC NC V/O /O 156 NC NC V/O /O 157 NC NC V/O /O 158 GND GND GND GND 159 Vecr Vecr Vecr Vecr 160 GND GND GND GND 161 Vee! Vecl Vee! Vecl 174 Veca Veca Veca Veca 175 GND GND GND GND 176 GND GND GND GND 178 NC NC V/O /O 181 NC NC V/O /O 184 NC NC V/O /O 187 NC NC V/O /O 189 GND GND GND GND 191 NC NC V/O /O 192 NC NC V/O /O 195 NC NC V/O /O 200 NC NC V/O /O 204 NC NC V/O /O 208 NC NC V/O /O 219 CLKA CLKA CLKA CLKA 220 CLKB CLKB CLKB CLKB 221 Vecl Vee! Vecl Vee! 222 GND GND GND GND 223 Vecr Vecr Vecr Vecr 224 GND GND GND GND 225 PRA, I/O PRA, I/O PRA, I/O PRA, I/O 227 NC NC V/O /O 232 NC NC V/O /O 236 NC NC V/O /O 239 NC NC V/O /O 240 GND GND GND GND 243 NC NC V/O /O 247 NC NC V/O /O 250 NC NC V/O /O 253 NC NC V/O /O 256 TCK, I/O TCK, I/O TCK, I/O TCK, I/O 4054SX Family FPGAs RadTolerant and HiRel Package Mechanical Drawings Ceramic Quad Flatpack (CQFPCavity Up) La H >| Ceramic Tie Bar At Lead Kovar Notes: All dimensions arein inches except CQ208 and CQ256 which arein millimeters. Outside leadframe holes (from dimension H) arecircular for the CQ208 and CQ256. Seal ring and lid are connected to Ground. Lead material is Kovar with minimum 60 miconiches gold over nickel. Packages are shipped unformed with the ceramic tie bar. 32200DX CQ208 has heat sink on the backside. QarA WD > 41sActel Ceramic Quad Flatpack (CQFP) CQ208 CQ256 Symbol] Min Nom. Max Min Nom. Max A 278 | 317 | 356 | 228 | 267 | 3.06 At 243 | 279 | 3.15 | 193 | 229 | 265 b 0.18 | 0.20 | 0.22 | 0.18 | 0.20 | 0.22 c 0.11 0.15 | 017 | 0.11 0.15 | 0.18 D1/E1 | 28.96 | 29.21 | 29.46 | 35.64 | 36.00 | 36.36 D2/E2 25.5 BSC 31.5 BSC e 0.50 BSC 0.50 BSC F 7.05 | 7.75 | 8.45 | 7.05 | 7.75 | 8.45 H 70.00 BSC 70.00 BSC K 65.90 BSC 65.90 BSC L1 74.60 | 75.00 | 75.40 | 74.60 | 75.00 | 75.40 Note: 1. All dimensions arein inches except CQ208 and CQ256, which isin millimeters. 2. BSC equals Basic Spacing between Centers. This isa theoretical true position dimension and so has no tolerance. 4254SX Family FPGAs RadTolerant and HiRel 43Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. =JAcfel http:/Awww.actel.com Actel Europe Ltd. Actel Corporation Actel Asia-Pacific Daneshill House, Lutyens Close 955 East Arques Avenue EXOS Ebisu Bldg. 4F Basingstoke, Hampshire RG24 8AG Sunnyvale, California 94086 1-24-14 Ebisu Shibuya-ku United Kingdom USA Tokyo 150 Japan Tel: +44.(0)1256.305600 Tel: 408.739.1010 Tel: +81.(0)3.3445.7671 Fax: +44.(0)1256.355420 Fax: 408.739.1540 Fax: +81.(0)3.3445.7668 5172141-2/2.99