Advance information AS7C31024LL aa 3.3V 128K x8 Intelliwatt low power CMOS SRAM Features e Tnteliw att active pow er reduction ciraitry 277V to 3 .6V operating range Organization: 131,072 wordsx 8 bis eH igh speed - 35/55/70/100 nsaddress acesstime low pow erconsum ption -Actve: 126mW max (55 nscyck) -Typical: <40mW (55 nscycek) - Standby :3 6UW max, CMOST/O - Very low DC com ponent in active pow er e 1 5V data retention Logic block diagram 14 Vpp > Vss > Input buffer - 1/07 128Kx8 Array (1,048,576) Row decoder Sense amp p00 4 Fasy mem ory expansion w ith CEI, CE2, OE inputs TTL/LVTTL-com patio k, three-state 1/0 EDEC registered packaging 32-p5 TSOP package -48-ball8mm x 6mm C&P BGA e ESD protection > 2000 volts e Latchwp aunent= 200mA Industrialand com m ercialtem perature avaikbe Other vo lage versions avaikbk -1.65V to 1 95V S7C1810241L) - 2 3V to 3 OV @S7C2510241L) Pin arrangement (top view) Alc 32 OF a9 420 31 ALO A8 [13 304 CEI Al3 C4 29-4 Yo? WE (-]5 28) 1/06 CE2 546 27) yo4 Als 2 264 1/05 co 25 3 Vee =] 9 TSOP 8x20 mf SI Ve Al6 LJ 10 23 yo? Ai4 Coll 22) yo AR CQ? 21 Foo a7 E13 20F5 ao A6 114 19F9 ar A5 (15 184 a2 A4 (16 175 a3 48-CSP BalkG rid rray Package (hading indicates no ball) 1 2 3 4 5 6 Column decoder Control logic, rp WE A Ao Ay A3 Ag Ag Power reductionke CEI B YOu Ao Ag Aq Yoo CE2 agaagsns r c [ws Zs we taededtadde D Veg Vpp E Vop Veg F | Yo, VOo G Vo Vos H Ag Aig Selection guide 7E3B1L02Z4T1-35 FCO3BLO2Z4TI-55 FO3L024TI-70 7O31L024TI-100 Unit Maximum address access tim e 35 55 70 100 ns Maximum outputenabk accesstme 15 25 35 50 ns Maxmum operating cunent 40 35 30 25 mA Maxmum standby curent 1 1 1 1 A ea reer ALLIANCE SEMICONDUCTOR rs Copyright 1998 Alliance Semiconductor, All rights reserved,Seu AS7C31024LL Advance information ee Functional description The AS7C3102411 is a high perform ance CMOS 1,048,576-bit Static Random AccessMem ory (SRAM ) organized as 131,072 wordlsx 8 bits. Eisdesigned forporteble applications w here fast data access, Jong battery Iie, and sim pk interfacing are desired. Equaladdress access and cycle tin es (tag, tre: ty c) Of 35/55/70/100 nsw ith outputenabk accesstim es (}z) Of 15/25/35/50 ns are deal for high perform ance applications. Active high and low chip enabks CEI, CE2) pem it easy mem ory expansion w ith multiplebank men ory sys=m s. When CE1l is HIGH or CE2 js LOW the device enters sandby mode. The AS/C31024LL js quaranteed not to exceed 3.6 UW power consam ption in standby m ode. Thisdevice also retums data when Vec js reduced to 1 5V, foreven low erpow erconsum ption . Aw rite cycle isacoom plished by asserting w rife enable W E) and both chip enabkes CEI, CE2) .Data on the inputpins /0 0-7/0 7 isw ritten on the rising edge ofWE Write cycle 1) orthe activwetoinactive edge of CEL or CE2 (write cyck 2). To avoid bus contention, extemal devices hou drive YO pinsony after outputs have been disabled w ith outputenak (OE) orwriteendk WE). A read cyck is accom plished by asserting outputenable OF) and both chip enabks CEI, CE2), w ith write end WE) HIGH. The chip drives 1/O pinsw ith the data word referenced by the input address. W hen either chip enabk or outputenak is inactive, orw rite end is achive, cutoutdrivers say in high-=m pedancem ode. The device is packaged In common industry standard packages. Chip sale BGA packaging, easy to use in m anufachirng, provides the sn alestpossibk footprint. This 48-ballL EDEC registered package has a ballpitch of 0.75mm andextemaldm ensionsof8mm x 6mm. Low power design th the AS7C31024LL design, priority was placed on low powey while m antaming moderately high perform ance. To reduce dandby and daa retention current, a 6-twansistor mem ory cell was utilized. Active power w as reduced considerably over traditional designs by using Thteliw att pow er reduction cirauitry. W ith Inteliw at, SRAM powersdow n unused cirmuits betw een access operations, resiliing in longer cycle times and bwer duty cycles, and providing incem ental power savings. During periods of inactivity Intelw att SRAM power consumption can be as low as filly deactivated standby pow ey even though the chip is enabled. This power savings, both jn active and Inactive m odes, resi tts in longerbattery Hie, and better system m arketabilty. Allchip inputs and outputs ae TTI-com patib'e, and operation isfom asngle3 3V suppy. Absolute maximum ratings Param eter Sym bol Min Max Unit Voltge on any Inputpin Ve -05 +45 Vv Voltage on any I/O pin Vi -05 Vpp + 05 Vv Pow er dissipation Py - 10 W Storage tem perature (plastic) Tess -55 +150 c DC outputcunent Bot - 20 mA Stresses greater than those listed under AtduleMaxinum Ringsm ay cause perm anent.dam age to the device. This isa stress rating ony and flunctionaloperation ofthe device at these orany other conditions outside those indicated jn the operational sections of this goecification isnotm plied. Exposure to absolutem ax- Jmum rating conditions fr extended periodsm ay affect reliability. Truth table CEL CE2 WE OE Data Mode H xX xX xX High Z Standby (Ey, Ii) xX L xX xX High Z Standby (Eg, Is) L H H H High Z Output disse L H H L Deut Read L H L xX Din W rite Key: X = DontCare, L= LOW,H = HGH 118 ALLIANCE SEMICONDUCTOR Cee eeeAdvance information AS7C31024LL Or: Recommended operating conditions Param eter Sym bol Min Typ Max Unit Vop 27 33 36 Vv Supply voltage Ves 00 00 00 V Vv 20 - Vpopt05 V DC mputvoltge = ; - Vi -05 - 08 Vv Comm ercial Ty 0 - 70 C Am bient operating tem perature Thdusial Th. 40 - 85 C tyymin= 3 OV forpulsew idth essthan tae/2. DC input/output characteristics 35 55 -70 100 Pavan eter Sym bol Test conditions Mn Max] Mn Max! Mn Max] Min Max|Unt Input kakage canent lExl OVS Vian S$ Vpp - 1 - 1 - 1 - 1 | pA Oo Oo ts disabled, utputkeakage IE | utputs clisal. _ 1 _ 1 _ 1 _ 1 WA cunent OV S Vout Vpp br= 4MA,Vpp = Min - O04] - oO4}] - O04] - 04 Vi V CF Bp = LOO MA, Vpp = Mn - oa] - oa] - oa] - oa Output volege hg = -4MA,Vpp =Min 24 - | 24 - 24 - 24 - Vv Vop - Vop - Vop - Vop - Vv Phy = BOHR, = man | BR Y Mon | Ngo | Moo Power consumption characteristics 35 -55 -10 100 Condition Sym bol. Test conditions Minn Max] Min Max] Min Max|] Min Max]/Unt O pexating, CES Vz,Vpp = Max, pe By mr Ypp as - ao] - 35] - 30] - 25 ]ma active f= fue = Wt Operating, CE=GND,Vpp = Max, f= atic pi 0 BD IL 100 100 100 100] pA Standby, ks CE2Vy+Vpp =Max, L - 100 - 100 - 100 - 100} WA bus toggling f= fra = 1/tec mB} - a5} - ais} - 13] - 13|ma dby, CE2Vpp-0 2V,Vpp =Mex, L - 500} - 500} - 500} - 500] HA bus Ls Vi, GND + 02V or a Vin 2 Vpp 0 2V, f= 0 Sn Capacitance ? (f = 1 MHz, T, = Room temperature, Vpp = 3.3V) Param eter Symbol = Signals Test conditions M ax Unit Tnput capacitance on A,CEL,CE2,WE,OE V.,= 0V 5 pF YO capacitance Cyo Yo Van = Vour= OV 7 pF $B aa i ESPEeL En Rott = fan BP eeeC Lt ALLIANCE SEMICONDUCTOR ] ] cfSeu AS7C31024LL Read cycle 3? Ay Advance information 35 -55 -70 -L00 Pavam eter Sym bol Min Max|Mmn Max |Mm Max|]Min Max] Unt Notes Read cycke tme tec 35 - 55 - 70 - 100 - ns Address access tim e ta - 35 - 55 - 70 - 100 | ns 3 Chip enable (CE) acoesstim e tacr - 35 - 55 - 70 - 100] ns 3 Outputendre (OE) acesstine tor - 3 - 3 - 4 - 5 ns Outputhol from address change toy 3 - 3 - 3 - 3 - ns 5 CE Low to output in Low Z ter 3 - 3 - 3 - 3 - ns 4,5 CE H igh to output in H igh Z tenz - 10 - 10 - 10 - 15] ns 4,5 OE Low to outputin Low Z tow 3 - 3 - 3 - 3 - ns 4,5 Byte select access tim e tan - 8 - 12 - 16 - 20 ns Byte sekectLow to Low -Z tay 3 - 3 - 3 - 3 - ns 4,5 Byte select H igh to H igh-Z tens - 10 - 10 - 10 - 15 ns 4,5 OE H igh to output in High Z tong - 10 - 10 - 10 - 15] ns 4,5 Pow erup tme toy 0 - 0 - 0 - 0 - ns 4,5 Pow er down tme tep - 35 - 55 - 70 - 100 | ns 4,5 Key to switching waveforms VEZ, Rising input QQ Falling input Read waveform 1 7,679.12 Undefined output/dont care Address controlled Address out Read waveform 2 368912 tou Data valid CEI and CE? controlled CEI yk mee x CE2 r * OF are | MMMMMMM@M@@XM|@#M Dout ft : Data valid _ K teLz1.tCLz2 | tpp lee Current tpu | supply 7 50% 50% Isp rae) ALLIANCE SEMICONDUCTOR {a8 E18 tee ora Baye raryAdvance information AS7C31024LL Write cycle 35 55 70 100 Pavan eter Symbol] Mn Max|Mm Max|Minn Max|Mn Max] Unt Notes W rte cycetme tw 35 - 55 - 70 - 100 - ns Chip enabk CEL) to w rite end tew 1 30 - 40 - 40 - 80 - ns 12 Chip enabk CE2) to w rite end tow 2 30 - 40 - 40 - 80 - ns 12 Addiess setup to w rite end tw 30 - 40 - 50 - 80 - ns Addiess setup tim e tas 0 - 0 - 0 - 0 - ns 12 W rte pulse w idth typ 30 - 40 - 50 - 80 - ns Addiesshold from end ofw nite tan 0 - 0 - 0 - 0 - ns Data valid to w rite end tow 25 - 25 - 25 - 35 - ns Datahoh tme tor 0 - 0 - 0 - 0 - ns 4,5 W rite enadbk tb output in High Z ty z - 10 - 10 - 10 - 10 ns 4,5 Outputachve fom w nte end tow 5 - 5 - 5 - 5 - ns 4,5 Write waveform 1 141112 Address Write waveform 2 141112 taw twe Data valid WE controlled CET and CE? controlled Address CEL tew1, tew2 belie Plo tates eee ALLIANCE SEMICONDUCTOR 7a)Seu AS7C31024LL Advance information Ay Data retention characteristics Pavan eter Sym bol Test conditions Mm M ax Unit N otes Voc Prdaa wtention Vor Veo = 15V 15 - Vv Data wetention curent kcpr CE2 Vpp-0 2V - 04 HA 5 Chip deselect to data retention tme tener Vin2 Vpp02Va 0 - ns 5 Opezation recovery tim e te Vin $ O2V tre - ns 5 Data retention waveform Data retention mode Vpp 2.7V K Vpr 2 L.5V Jt 2.1N tcpr Vopr AC test conditions 33V output load: se FiqueB, except as noted see Figurec. Inputpulse vel GND to 3 OV. &e FigqueaA. Input ns and falltmes: 5 ns. See FiquieA. Tnputand output tm ing wference kvels: 1 5V. 43.3V 43.3V 320Q 320Q 43.0V _ sincludin 90% 90% on 30 pE* OS 5 pF* and jig capacitance 10% 10% GND Figure A: Input waveform Figure B: Out ia load Figure C: Outparie load for toyz, tcyz, toLz tonz, tow Notes During Vee pow erup, apulhip resistorto Vcc on CEL is required to m eet ky specification . This paran eter is sam pd andnot100% tested. For test conditions, see AC Tat Contig FiguresA,B,C. ter and tey, are specified w ith CL= SpF as in Figure C. Transition ism easured 500m V from steady-state voltage. This param eter Js quayanteed but not tested. WEisHGH formed cycke. CEI and OER aeLOW and CE2 isHIGH forresd cyck. Address valid priorto or coincidentw ith CE tansition Low . Allread cycle tin ings ave referenced from the /ast valid address to the first tansitioning address. CEI orW Emustbe HGH orCF2 LOW during address tansitions. Allw rite cycle tin ings ae referenced from the ast valid address to the first tansitioning address. CEI and CE2 have denticaltin ing. Oo OwmwA Do PB WHY PF a NRO a4 ALLIANCE SEMICONDUCTOR Cee eeeAdvance information AS7C31024LL ; or Package dimensions Zor aesoeak - K/B}mlofo} 2) a) 2] > OOWOOOO00 a = OOO0O0000 "Is JSF | sp ise 5 a-OOOOOOO0) +18 - OO0O0O0O000 wile oo ol eed el ad ed Bd OOOOCC0O00 w Le e[S|'jalalalslalslrg OCOD990 OQ) r QO : : m 0 ti eS cabana 4 - LN |; a S = ar y < Or |: r 4 ePNP eZ < Eos wee eg g FE > 5 = Fes = |e eo 2 [* S 5 8 BS S $B aa i ESPEeL En Rott = fan BP eeeC Lt ALLIANCE SEMICON DUCTOR ] is)Seu AS7C31024LL Ay AS7C31024LL ordering codes Package \ Access tin e TSOP 8x20 CSP BGA AS7C31024LL part numbering system ASIC ig 35 ns AS7C31024LL-35TC AS7C31024LL-35TI AS7C31024LL-35BC AS7C31024LL-35BI 102415 3=33V CMOS SRAM prefix 25=2 5V CMOS 18=1 8V CMOS Thtelliw at! 4s atradan ark ofA Iiance San dconductorCorporation a . Acosss Device num ber Advance information 55 ns AS1C31024LL-55TC AS7/1C31024LL-55TI AS7C31024LL-55BC AS7C31024LL-55BI Package: T=TSOP 8x20 B=C&P BGA TO 0s AS7C31024LL-70TC AS7C31024LL-70TI AS7C31024LL-70BC AS71C31024LI-70BI x 100 ns AS7C31024LL-100TC AS7C31024LL-100TI AS7C31024LL-100BC AS7C31024LL-100BI C= Comm ercialtem perature range, 0C to 70 C T= Induswialten peranire range, 40C to 85C ALLIANCE SEMICONDUCTOR {a8 E18 tee ora Baye rary