FEBRUARY FEBRUARY
FEBRUARY FEBRUARY
FEBRUARY 2001
DSC-3514/10
1
©2000 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆128K x 8 advanced high-speed CMOS static RAM
◆◆
◆◆
◆JEDEC revolutionary pinout (center power/GND) for
reduced noise.
◆◆
◆◆
◆Equal access and cycle times
– Commercial and Industrial: 12/15/20ns
◆◆
◆◆
◆One Chip Select plus one Output Enable pin
◆◆
◆◆
◆Bidirectional inputs and outputs directly TTL-compatible
◆◆
◆◆
◆Low power consumption via chip deselect
◆◆
◆◆
◆Available in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
Description
The IDT71124 is a 1,048,576-bit high-speed static RAM orga-
nized as 128K x 8. It is fabricated using IDT’s high-performance,
high-reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs. The JEDEC
centerpower/GND pinout reduces noise generation and improves
system performance.
The IDT71124 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71124 are TTL-compatible
and operation is from a single 5V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
The IDT71124 is packaged in a 32-pin 400 mil Plastic SOJ.
ADDRESS
DECODER 1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
•
•
•
A
0
A
16
3514 drw 01
8
8
I
/O
0
- I/O
7
•
8
•
•
•
CONTROL
LOGIC
WE
OE
CS
,
CMOS Static RAM
1 Meg (128K x 8-Bit )
Revolutionary Pinout
IDT71124
6.422
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 8 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 8 pF
3514 t bl 0 3
Recommended DC Operating
Conditions
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5. 5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2
____
V
CC
+0.5 V
V
IL
Input Low Voltage -0.5
(1)
____
0.8 V
3514 tbl 05
Grade Temperature GND V
CC
C om m e rcial 0° C to + 70°C 0V 5. 0V ± 10%
I ndustrial –40° C t o +85°C 0V 5. 0V ± 10%
3514 tbl 04
Recommended Operating
Temperature and Supply Voltage
Pin Configuration
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliabilty.
2. VTERM must not exceed Vcc + 0.5V.
Truth Table(1,2)
SOJ
Top View
5
6
7
8
9
10
11
12
A
0
A
1
A
2
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
A
15
A
3
CS
I/O
1
V
CC
A
14
OE
I/O
7
I/O
6
GND
I/O
5
3514 drw 02
G
ND
13 20
14 19
15 18
16
A
7
17
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
12
A
11
A
10
A
9
A
8
SO32-3
I/O
0
A
16
A
13
V
CC
I/O
4
,
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs ≥ VHC or ≤ VLC.
CS OE WE I/O Function
LLHDATA
OUT
Read Data
LXLDATA
IN
Wri t e Data
L H H High-Z Output Disabled
H X X High-Z Deselected - Sta ndby (I
SB
)
V
HC(3)
X X High-Z Deselected - Standby (I
SB1
)
3514 tbl 01
Absolute Maximum Ratings(1)
Symbol Rating Value Unit
V
TERM
(2)
Terminal Voltage w it h
Respect to GND -0.5 to +7.0
(2)
V
T
A
Operating Tem perature 0 to +70
o
C
T
BIAS
Temperature
Under Bias -5 5 to +125
o
C
T
STG
Storage
Temperature -5 5 to +125
o
C
P
T
P ow er D issipat ion 1. 25 W
I
OUT
DC Output Current 50 m A
3514 tbl 02
6.42
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
3
3514 drw 03
480Ω
255Ω30pF
D
ATA
OUT
5V
.
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
AC Test Conditions
DC Electrical Characteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
3514 drw 04
480Ω
255Ω5pF*
D
ATA
OUT
5V
.
DC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
Symbol Parame ter Test C onditions Min. M ax. Unit
|I
LI
| I nput Leakage Current V
CC
= Max., V
IN
= GND to V
CC
___
5µA
|I
LO
| Out put Leak age Current V
CC
= Max., CS = V
IH
, V
OUT
= GND to V
CC
___
5µA
V
OL
Out put Low Volt age I
OL
= 8m A, V
CC
= Min.
___
0.4 V
V
OH
Out put H igh Voltage I
OH
= –4m A, V
CC
= Min. 2.4
___
V
3514 tbl 06
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
71124S12 71124S15 71124S20
Symbol Parameter Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit
ICC Dynamic Operating Current
CS < VIL, Outputs Open, VCC = Max., f = fMAX
(2)
160 160 155 155 140 140 mA
ISB Standby Po we r Supply Current (TTL Level)
CS > VIH, Outputs Open, VCC = Max., f = fMAX
(2)
40 40 40 40 40 40 mA
ISB1 Full Standby Power Supply Current (CMOS Level)
CS > VHC, Outputs Open, VCC = Max., f = 0
(2)
VIN < VLC or VIN > VHC
10 10 10 10 10 10 mA
3514 t bl 0 7
Input Pulse Lev els
Input Rise/Fall Tim es
Input Tim ing Reference Levels
Out put R eference Lev els
AC Test Load
GND t o 3.0V
3ns
1.5V
1.5V
See Figure 1 and 2
3514 tbl 08
AC Test Loads
6.424
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71124S12 71124S15 71124S20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
RE AD CYCL E
t
RC
Re ad Cycl e Time 12
____
15
____
20
____
ns
t
AA
Address Access Time
____
12
____
15
____
20 ns
t
ACS
Chip Select Access Time
____
12
____
15
____
20 ns
t
CLZ
(1)
Chip Sele c t to Output in Low-Z 3
____
3
____
3
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z 060708ns
t
OE
Outp ut Enab le to Outp ut Valid
____
6
____
7
____
8ns
t
OLZ
(1)
Output Enable to Output in Lo w-Z 0
____
0
____
0
____
ns
t
OHZ
(1)
Output Disable to Output in High-Z 050507ns
t
OH
Outp ut Ho ld fro m A dd re s s Change 4
____
4
____
4
____
ns
t
PU
(1)
Chi p Selec t to P o we r-Up Tim e 0
____
0
____
0
____
ns
t
PD
(1)
Chi p De s e lec t to P o we r-Do wn Tim e
____
12
____
15
____
20 ns
WRI TE CYCLE
t
WC
Write Cycle Time 12
____
15
____
20
____
ns
t
AW
Address Valid to End of Write 8
____
12
____
15
____
ns
t
CW
Chip Selec t to End of Write 8
____
12
____
15
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 8
____
12
____
15
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 6
____
8
____
9
____
ns
t
DH
Data Ho l d Ti m e 0
____
0
____
0
____
ns
t
OW
(1)
Outp u t ac tiv e fro m End -o f- Wri te 3
____
3
____
4
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z 050508ns
3514 tbl 09
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
5
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cycle No. 1(1)
Timing Waveform of Read Cycle No. 2(1,2,4)
ADDRESS
3514 drw 05
OE
CS
DATA
OUT
(5) (5) (5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
V
CC
SUPPLY
CURRENT
t
PU
t
PD
I
CC
I
SB
.
DATA
OUT
A
DDRESS
3514 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALIDPREVIOUS DATA
OUT
VALID
.
6.426
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period.
5. Transition is measured ±200mV from steady state.
A
DDRESS
CS
WE
DATA
OUT
DATA
IN
3514 drw 07
(5)
(2)
(5) (5)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AW
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
DH
t
WR
(3)(3)
.
CS
A
DDRESS
DATA
IN
3514 drw 08
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
VALID
WE
.
6.42
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
7
S
Power
XX
Speed
X
Package
X
Process/
Temperature
Range Blank
ICommercial (0°C to +70°C
)
Industrial (–40°C to +85°C)
Y400-mil SOJ (SO32-3)
12
15
20
Device
Type
IDT
Speed in nanoseconds
3514 drw 09
71124
Ordering Information
6.428
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
Datasheet Document History
8/5/99 Updated to new format
Pg. 3 Removed military entries on DC table
Pg. 4 Removed Note 1 and renumbered footnotes
Pg. 6 Revised footnotes on Write Cycle No. 1 diagram
8/13/99 Pg. 8 Added Datasheet Document History
9/30/99 Pg. 1, 3, 4, 7 Added 12ns, 15ns, and 20ns industrial temperature speed grade offerings
2/18/00 Pg. 3 Revise ISB for Industrial Temperature offerings to meet commerical specifications
3/14/00 Pg. 3 Revised ISB to accomidate speed functionality
4/01/00 Pg.4 Tightened tAW, tCW, tWP and tDW within the AC Electrical Characteristics
8/09/00 Not recommended for new designs
02/01/01 Removed "Not recommended for new designs"
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
