SLRS007B - NOVEMBER 1986 - REVISED NOVEMBER 1995 * * * * * * * * * * * * * * NE PACKAGE (TOP VIEW) 1-A Output-Current Capability Per Driver Applications Include Half-H and Full-H Solenoid Drivers and Motor Drivers Designed for Positive-Supply Applications Wide Supply-Voltage Range of 4.5 V to 36 V TTL- and CMOS-Compatible High-Impedance Diode-Clamped Inputs Separate Input-Logic Supply Thermal Shutdown Internal ESD Protection Input Hysteresis Improves Noise Immunity 3-State Outputs Minimized Power Dissipation Sink/Source Interlock Circuitry Prevents Simultaneous Conduction No Output Glitch During Power Up or Power Down Improved Functional Replacement for the SGS L293 1,2EN 1A 1Y HEAT SINK AND GROUND 1 16 2 15 3 14 4 13 5 12 2Y 2A 6 11 7 10 VCC2 8 9 VCC1 4A 4Y HEAT SINK AND GROUND 3Y 3A 3,4EN FUNCTION TABLE (each driver) INPUTS OUTPUT A EN Y H H H L H L X L Z H = high-level, L = low-level X = irrelevant Z = high-impedance (off) In the thermal shutdown mode, the output is in a highimpedance state regardless of the input levels. description The SN754410 is a quadruple high-current half-H driver designed to provide bidirectional drive currents up to 1 A at voltages from 4.5 V to 36 V. The device is designed to drive inductive loads such as relays, solenoids, dc and bipolar stepping motors, as well as other high-current/high-voltage loads in positive-supply applications. All inputs are compatible with TTL-and low-level CMOS logic. Each output (Y) is a complete totem-pole driver with a Darlington transistor sink and a pseudo-Darlington source. Drivers are enabled in pairs with drivers 1 and 2 enabled by 1,2EN and drivers 3 and 4 enabled by 3,4EN. When an enable input is high, the associated drivers are enabled and their outputs become active and in phase with their inputs. When the enable input is low, those drivers are disabled and their outputs are off and in a high-impedance state. With the proper data inputs, each pair of drivers form a full-H (or bridge) reversible drive suitable for solenoid or motor applications. A separate supply voltage (VCC1) is provided for the logic input circuits to minimize device power dissipation. Supply voltage VCC2 is used for the output circuits. The SN754410 is designed for operation from - 40C to 85C. Copyright 1995, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ * DALLAS, TEXAS 75265 * HOUSTON, TEXAS 77251-1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 SLRS007B - NOVEMBER 1986 - REVISED NOVEMBER 1995 logic symbol 1A 1,2EN 2A 3A 3, 4EN 4A logic diagram 2 3 1 EN 1, 2EN EN 7 6 10 11 9 EN 2A 2Y 3A 3Y 3, 4EN EN 15 1A 1Y 14 4A 4Y 2 3 7 6 10 11 9 15 14 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC2 VCC1 Current Source Output Input GND 2 GND * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 1Y 1 2Y 3Y 4Y SLRS007B - NOVEMBER 1986 - REVISED NOVEMBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Output supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 36 V Output supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 36 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3 V to VCC2 + 3 V Peak output current (nonrepetitive, tw 5 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 A Continuous total power dissipation at (or below) 25C free-air temperature (see Note 2) . . . . . . . . 2075 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network GND. 2. For operation above 25C free-air temperature, derate linearly at the rate of 16.6 mW/C. To avoid exceeding the design maximum virtual junction temperature, these ratings should not be exceeded. Due to variations in individual device electrical characteristics and thermal resistance, the built-in thermal overload protection can be activated at power levels slightly above or below the rated dissipation. recommended operating conditions MIN MAX Output supply voltage, VCC1 4.5 5.5 V Output supply voltage, VCC2 4.5 36 V High-level input voltage, VIH 2 -0.3 5.5 V 0.8 V -40 125 C Low-level input voltage, VIL Operating virtual junction temperature, TJ UNIT Operating free-air temperature, TA -40 85 C The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for logic voltage levels. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 3 SLRS007B - NOVEMBER 1986 - REVISED NOVEMBER 1995 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input clamp voltage II = - 12 mA IOH = - 0.5 A VOH High-level output voltage IOH = - 1 A IOH = - 1 A, MIN TJ = 25C TYP MAX UNIT -0.9 -1.5 V VCC2 -1.5 VCC2 -2 VCC2 -1.1 VCC2 -1.8 VCC2 -1.4 1 V Low-level output voltage IOL = 0.5 A IOL = 1 A IOL = 1 A, VOKH High-level output clamp voltage IOK = - 0.5 A IOK = 1 A VCC2 + 1.4 VCC2 + 1.9 -2 Low-level output clamp voltage -1.3 -2.5 IOZ(off) Off-state high-impedance-state output current IOK = 0.5 A IOK = - 1 A VO = VCC2 -1.1 VOKL VOL IIH IIL High-level input current VO = 0 VI = 5.5 V Low-level input current VI = 0 ICC1 Output supply current IO = 0 ICC2 Output supply current IO = 0 1.4 2 TJ = 25C 1.2 V 1.8 VCC2 + 2 VCC2 + 2.5 500 -500 V A A 10 A -10 A All outputs at high level 38 All outputs at low level 70 All outputs at high impedance 25 All outputs at high level 33 All outputs at low level 20 All outputs at high impedance All typical values are at VCC1 = 5 V, VCC2 = 24 V, TA = 25C. V mA mA 5 switching characteristics, VCC1 = 5 V, VCC2 = 24 V, CL = 30 pF, TA = 25C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td1 td2 Delay time, high-to-low-level output from A input 400 ns Delay time, low-to-high-level output from A input 800 ns tTLH tTHL Transition time, low-to-high-level output 300 ns 300 ns tr tf Rise time, pulse input tw ten1 Pulse duration Enable time to the high level 700 ns ten2 tdis1 Enable time to the low level 400 ns 900 ns tdis2 Disable time from the low level 600 ns 4 Transition time, high-to-low-level output See Figure 1 Fall time, pulse input See Figure 2 Disable time from the high level * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * SLRS007B - NOVEMBER 1986 - REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION Input Pulse Generator (see Note A) 5V tf 24 V VCC1 VCC2 3V 90% 90% Input 1.5 V A Circuit Under Test tr Y 1.5 V 10% 10% tw td1 Output EN 0V td2 V 90% OH 90% CL = 30 pF (see Note B) Output GND 3V 10% 10% TEST CIRCUIT VOL tTHL tTLH VOLTAGE WAVEFORMS Figure 1. Test Circuit and Switching Times From Data Inputs Input Pulse Generator (see Note A) 5V 24 V VCC1 VCC2 EN Circuit Under Y Test A 12 V tr Input RL = 22 tf 3V 90% 90% 1.5 V 1.5 V 10% 10% 0V tw Output tdis1 tdis2 CL = 30 pF (see Note B) 12 V GND Output To 3 V for tPZH and tPHZ To 0 V for tPZL and tPLZ 50% 50% VOL ten1 TEST CIRCUIT Output ten2 50% VOH 50% 12 V VOLTAGE WAVEFORMS Figure 2. Test Circuit and Switching Times From Enable Inputs NOTES: A. The pulse generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 10 s, PRR = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 5 SLRS007B - NOVEMBER 1986 - REVISED NOVEMBER 1995 APPLICATION INFORMATION 5V 16 10 k 24 V 8 VCC1 SN754410 VCC2 2 Control A 3 EN 1 EN 7 6 1 10 11 EN 9 2 EN Control B 15 14 GND 4, 5, 12, 13 Figure 3. Two-Phase Motor Driver 6 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * Motor PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN754410NE ACTIVE PDIP NE 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN754410NEE4 ACTIVE PDIP NE 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDI003 - OCTOBER 1994 NE (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 20 PIN SHOWN 0.070 (1,78) MAX 11 20 PINS ** DIM A C 1 20 0.914 (23,22) MIN MAX B 16 0.780 (19,80) 0.975 (24,77) MIN 0.930 (23,62) MAX 1.000 (25,40) 10 C MIN 0.240 (6,10) 0.260 (6,61) MAX 0.260 (6,60) 0.280 (7,11) 0.020 (0,51) MIN A 0.200 (5,08) MAX Seating Plane 0.155 (3,94) 0.125 (3,17) 0.100 (2,54) 0.021 (0,533) 0.015 (0,381) 0.010 (0,25) M 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN B 0.200 (5,08) MAX Seating Plane 0.155 (3,94) 0.125 (3,17) 0.100 (2,54) 0.021 (0,533) 0.015 (0,381) 0.010 (0,25) M 0- 15 0.010 (0,25) NOM 4040054 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (16 pin only) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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