D16750 - Digital Core Design

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

D

D1

16

67

75

50

0

Configurable UART with FIFO

ver 2.08

OVERVIEW

The D16750 is a soft Core of a Universal

Asynchronous Receiver/Transmitter (UART)

functionally identical to the TL16C750. The

D16750 allows serial transmission in two

modes: UART mode and FIFO mode. In FIFO

mode internal FIFOs are activated allowing 64

bytes (plus 3 bits of error data per byte in the

RCVR FIFO) to be stored in both receive and

transmit directions. D16750 performs serial-to-

parallel conversion on data characters

received from a peripheral device or a

MODEM, and parallel-to-serial conversion on

data characters received from the CPU. The

CPU can read the complete status of the

UART at any time during the functional

operation. Status information reported

includes the type and condition of the transfer

operations being performed by the UART, as

well as any error conditions (parity, overrun,

framing, or break interrupt). D16750 includes

a programmable baud rate generator that is

capable of dividing the timing reference clock

input by divisors of 1 to (216-1), and producing

a 16 × clock for driving the internal transmitter

logic. Provisions are also included to use this

16 × clock to drive the receiver logic. The

D16750 has complete MODEM control

capability, and a processor-interrupt system.

Interrupts can be programmed to the user's

requirements, minimizing the computing

required to handle the communications link.

In the FIFO mode, there is a selectable

autoflow control feature that can significantly

reduce software overload and increase

system efficiency by automatically controlling

serial data flow through the RTS output and

the CTS input signals

The separate BAUD CLK line allow to set an

exact transmission speed, while the UART

internal logic is clocked with the CPU

frequency.

Two DMA modes are supported: single

transfer and multi-transfer. These modes

allow UART to interface to higher performance

DMA units, which can interleave their

transfers between CPU cycles or execute

multiple byte transfers.

The configuration capability allows user to

enable or disable during Synthesis process

the Modem Control Logic and FIFO's Control

Logic, change the FIFO size. So in

applications with area limitation and where the

UART works only in 16450 mode, disabling

Modem Control and FIFO's allow to save

about 50% of logic resources.

The core is perfect for applications, where the

UART Core and microcontroller are clocked

by the same clock signal and are implemented

inside the same ASIC or FPGA chip, as well

as for standalone implementation, where

several UARTs are required to be

implemented inside a single chip, and driven

by some off-chip devices. Thanks to universal

interface D16750 core implementation and

verification are very simply, by eliminating a

number of clock trees in complete system.

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are trademarks of their respective owners.

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○

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http://www.dcd.pl

1-, 1½-, or 2-stop bit generation

KEY FEATURES

Software compatible with 16450, 16550

and 16750 UARTs

Configuration capability

Separate configurable BAUD clock line

Two modes of operation: UART mode and

FIFO mode

Majority Voting Logic

In the FIFO mode transmitter and receiver

are each buffered with 16 byte or 64 byte

FIFO to reduce the number of interrupts

presented to the CPU

Optional FIFO size extension to 128, 256

or 512 Bytes

Adds or deletes standard asynchronous

communication bits (start, stop, and parity)

to or from the serial data

In UART mode receiver and transmitter

are double buffered to eliminate a need for

precise synchronization between the CPU

and serial data

Independently controlled transmit, receive,

line status, and data set interrupts

False start bit detection

16 bit programmable baud generator

MODEM control functions (CTS, RTS,

DSR, DTR, RI, and DCD)

Programmable automatic Hardware Flow

Control logic through Auto-RTS and Auto-

CTS

Fully programmable serial-interface

characteristics:

5-, 6-, 7-, or 8-bit characters

Even, odd, or no-parity bit gene ration and

detection

Baud generation

Complete status reporting capabilities

Line break generation and detection.

Internal diagnostic capabilities:

Loop-back controls for communication s link

fault isolation

Break, parity, overrun, fra ming error

simulation

Two DMA Modes allows single and multi-

transfer

Technology independent HDL Source

Code

Full prioritized interrupt system controls

Fully synthesizable static design with no

internal tri-state buffers

APPLICATIONS

Serial Data communications applications

Modem interface

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design license allows use IP Core in

single FPGA bitstream and ASIC

implementation.

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA

bitstreams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time

restriction except One Year license where

time of use is limited to 12 months.

●

○

Single Design license for

VHDL, Verilog source code called HDL

Source

○ Encrypted, or plain text EDIF called Netlist

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○

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One Year license for

Encrypted Netlist only

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Desi gns

All trademarks mentioned in this document

are trademarks of their respective owners.

♦

◊

♦

◊

♦

◊

♦

◊

●

http://www.DigitalCoreDesign.com

http://www.dcd.pl

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench

environment

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

● Delivery the IP Core updates, minor

and major versions changes

● Delivery the documentation updates

● Phone & email support

CONFIGURATION

The following parameters of the D16750 core

can be easy adjusted to requirements of

dedicated application and technology.

Configuration of the core can be prepared by

effortless changing appropriate constants in

package file. There is no need to change any

parts of the code.

- enable

•Baud generator - disable

- enable

•External RCLK source - disable

- enable

•External BAUDCLK source - disable

- enable

•Modem Control logic - disable

- enable

•SCR Register - disable

- enable

•FIFO Control logic - disable

- standard 16/64

•FIFO size - large up to 512

DESIGN FEATURES

The functionality of the D16750 core was

based on the Texas Instruments TL16C750A.

The following characteristics differentiate the

D16750 from Texas Instruments devices:

The bi-directional data bus has been split

into two separate buses: datai(7:0),

datao(7:0)

Signals rd2 and wr2, xin, and xout have

been removed from interface

Signal ADS and address latch have been

removed

The DLL, DLM and THR registers are

reset to all zeros

TEMT and THRE bits of Line Status

Register, are reset during the second

clock rising edge following a THR write

RCLK clock is replaced by global clock

CLK, internally divided by BAUD factor.

Asynchronous microcontroller interface is

replaced by equivalent Universal interface

All latches implemented in original 16750

devices are replaced by equivalent flip-flop

registers, with the same functionality

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

SYMBOL

datai(7:0)

address(2:0)

datao(7:0)

so

rts

dtr

out1

out2

cts

dsr

dcd

ri

wr

rd

cs

si

rst

clk

rclk

baudclk

baudout

intr

ddis

txrdy

rxrdy

D16750

baudclken

rclken

PINS DESCRIPTION

PIN TYPE DESCRIPTION

rst input Global reset

clk input Global clock

datai[7:0] input Parallel data input

addr[2:0] input Address bus

cs input Chip select input

wr input Write input

rd input Read input

rclk input Receiver clock

baudclk input Baud generator clock

si input Serial data input

cts input Clear to send input

dsr input Data set ready input

dcd input Data carrier detect input

ri input Ring indicator input

baudclken input Baud generator clock enable

rclken input Receiver clock enable

baudout output Baud generator output

datao[7:0] output Parallel data output

so output Serial data output

ddis output Driver disable output

txrdy output Transmitter ready output

rxrdy output Receiver ready output

rts output Request to send output

dtr output Data terminal ready output

out1 output Output 1

out2 output Output 2

intr output Interrupt request output

Note: When enabled RCLK and BAUDCLK pins

frequency should be at least two times lower

than CLK, 2*fRCLK< fCLK

APPLICATION

D16750

addr(2:0)

addr

latch

datai(7:0)

datao(7:0)

w

r

rd

cs

intr

rxrdy

txrdy

out1

out2

EIA

Drivers

so

si

rts

dt

r

ds

r

dcd

cts

ri

baudclken

rclken

clk

rs

t

baudclk

rclk

CPU

add

r

ale

datao(7:0)

datai(7:0)

we

rd

cs

in

t

Typical D16750 and processor connection is

shown in figure above.

BLOCK DIAGRAM

Data Bus Buffer - The data Bus Buffer

accepts inputs from the system bus and

generates control signals for the other D16750

functional blocks. Address bus ADDR(2:0)

selects one of the register to be read

from/written into. Both RD and WE signals are

active low, and are qualified by CS; RD and

WE are ignored unless the D16750 has been

selected by holding CS low.

Baud Generator - The D16750 contains a

programmable 16 bit baud generator that

divides clock input by a divisor in the range

between 1 and (216–1). The output frequency

of the baud generator is 16× the baud rate.

The formula for the divisor is:

16*baudrate

frequency

divisor =

Two 8-bit registers, called divisor latches DLL

and DLM, store the divisor in a 16-bit binary

format. These divisor latches must be loaded

during initialization of the D16750 in order to

ensure desired operation of the baud

generator. When either of the divisor latches

is loaded, a 16-bit baud counter is also loaded

on the CLK rising edge following the write to

DLL or DLM to prevent long counts on initial

load.

Modem Control Logic controls the interface

with the MODEM or data set (or a peripheral

device emulating a MODEM).

Interrupt Controller - D16750 consists fully

prioritized interrupt system controller. It

controls interrupt requests to the CPU and

interrupt priority. Interrupt controller contains

Interrupt Enable (IER) and Interrupt

Identification (IIR) registers.

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

rclk

rclken

si

Receiver

Control

&

Shift Register

RCVR Buffer

&

RCVR FIFO

addr(2:0)

datai(7:0)

datao(7:0)

rd

wr

cs

ddis

txrdy

rxrdy

Data Bus

Buffer

Baud

Generator

clk

rst

Interrupt

Controller

rts

cts

dtr

dsr

dcd

ri

out1

out2

Modem

control

logic

so

Transmitter

Control

&

Shift Register

THR Buffer

&

THR FIFO

intr

baudclk

baudclken

baudout

Receiver Control - Receiving starts when the

falling edge on Serial Input (SI) during IDLE

State is detected. After starting the SI input is

sampled every 16 internal baud cycles as it is

shown in figure below. When the logic 1 state

is detected during START bit it means that the

False Start bit was detected and receiver back

to the IDLE state.

Receiver FIFO - The Rx FIFO can be 64

(128, 256, 512) levels deep, it receives data

until the number of bytes in the FIFO equals

the selected interrupt trigger level. At that time

if Rx interrupts are enabled, the UART will

issue an interrupt to the CPU. The Rx FIFO

will continue to store bytes until it is full, and

will not accept any next byte. Any more data

entering the Rx shift register will set the

Overrun Error flag.

Transmitter Control module controls

transmission of written to THR (Transmitter

Holding register) character via serial output

SO. The new transmission starts on the next

overflow signal of internal baud generator,

after writing to THR register or Transmitter

FIFO. Transmission control contains THR

register and transmitter shift register.

Transmitter FIFO - the Tx portion of the

UART transmits data through SO as soon as

the CPU loads a byte into the Tx FIFO. The

UART will prevent loads to the Tx FIFO if it

currently holds 64 (128, 256, 512) characters

(depending on FCR(5) bit value and selected

FIFO size). Loading to the Tx FIFO will again

be enabled as soon as the next character is

transferred to the Tx shift register. These

capabilities account for the largely

autonomous operation of the Tx. The UART

starts the above operations typically with a Tx

interrupt.

PERFORMANCE

The following table gives a survey about

the Core area and performance in the

ALTERA® devices after Place & Route:

Device Speed

grade Logic Cells Fmax

CYCLONE -6 4841149 MHz

CYCLONE2 -6 4991160 MHz

STRATIX -5 4841158 MHz

STRATIX2 -3 4181255 MHz

STRATIXGX -5 4841163 MHz

MERCURY -5 5401136 MHz

EXCALIBUR -1 5111112 MHz

APEX II -7 5121145 MHz

APEX20KC -7 5111135 MHz

APEX20KE -1 511196 MHz

APEX20K -1 511187 MHz

ACEX1K -1 543193 MHz

FLEX10KE -1 5431 94 MHz

1- FIFOs implemented in EAB’s – 1216 Bits

Core performance in ALTERA® devices

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

D16X50 UARTS FAMILY OVERVIEW

The family of DCD D16X50 UART IP Cores combine a high–performance, low cost, and small

compact size, offering the best price/performance ratio in the IP Market. The DCD’s Cores are

dedicated for use in cost-sensitive consumer products, computer peripherals, office automation,

automotive control systems, security and telecommunication applications.

The D16X50 IP Cores are written in pure VHDL/VERILOG HDL languages which make them

technologically independent. All of the D16X50 IP Cores can be fully customized according to

customer needs.

Design

UARTS number

UART Mode

FIFO Mode of

operation

FIFO Size (Bytes)

Majority voting

logic

Separate BAUD

Clock line

Software Flow

Control

RTS/CTS Flow

Control

MODEM Control

False START Bit

detection

Complete status

reporting

Internal diagnostic

capabilities

Prioritized interrupt

system

Break generation

and detection

IRDA Port

1284 Parallel Port

D16450 1 - - - - -* -*

D16550 1 2* 16 - - -* -*

D16750 1 2* 64 - -* -*

D16552 2 4* 16 - -

D16752 2 4* 64 -* -*

D16754 4 8* 64 -* -*

*-Optional

D16X50 family of Configurable UARTs with FIFO IP Cores

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

CONTACTS

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

e-mail: info@dcd.pl

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tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Distributors:

Please check http://www.dcd.pl/apartn.php

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