Ultralow Noise
Drivers for Low Voltage ADCs
Data Sheet ADA4930-1/ADA4930-2
Rev. C Document Feedback
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FEATURES
Low input voltage noise: 1.2 nV/√Hz
Low common-mode output: 0.9 V on single supply
Extremely low harmonic distortion
−104 dBc HD2 at 10 MHz
−79 dBc HD2 at 70 MHz
−73 dBc HD2 at 100 MHz
−101 dBc HD3 at 10 MHz
−82 dBc HD3 at 70 MHz
−75 dBc HD3 at 100 MHz
High speed
−3 dB bandwidth of 1.35 GHz, G = 1
Slew rate: 3400 V/μs, 25% to 75%
0.1 dB gain flatness to 380 MHz
Fast overdrive recovery of 1.5 ns
0.5 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V or 5 V
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
GENERAL DESCRIPTION
The ADA4930-1/ADA4930-2 are very low noise, low distortion,
high speed differential amplifiers. They are an ideal choice for
driving 1.8 V high performance ADCs with resolutions up to
14 bits from dc to 70 MHz. The adjustable output common
mode allows the ADA4930-1/ADA4930-2 to match the input of
the ADC. The internal common-mode feedback loop provides
exceptional output balance, suppression of even-order harmonic
distortion products, and dc level translation.
With the ADA4930-1/ADA4930-2, differential gain configurations
are easily realized with a simple external feedback network of
four resistors determining the closed-loop gain of the amplifier.
The ADA4930-1/ADA4930-2 are fabricated using Analog Devices,
Inc., proprietary silicon-germanium (SiGe), complementary
bipolar process, enabling them to achieve very low levels of
distortion with an input voltage noise of only 1.2 nV/√Hz.
FUNCTIONAL BLOCK DIAGRAMS
–FB
+IN
–IN
+FB
–OUT
PD
+OUT
VOCM
+
VS
+
VS
+
VS
+
VS
–VS
–VS
–VS
–VS
09209-001
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADA4930-1
Figure 1.
–IN1
+FB1
+VS1
+VS1
–FB2
+IN2
–IN2
+FB2
+VS2
VOCM2
+OUT2
+VS2 –VS1
–VS1
–FB1
+IN1
PD1
–OUT1
ADA4930-2 –VS2
–VS2
VOCM1
+OUT1
PD2
–OUT2
09209-002
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
11
7
12
20
19
21
22
23
24
Figure 2.
0
1
10
100
10 100 1k 10k 100k 1M 10M 100M
VN (nV/
√
hz)
FREQUENCY (Hz)
09209-003
Figure 3. Voltage Noise Spectral Density
The low dc offset and excellent dynamic performance of the
ADA4930-1/ADA4930-2 make them well suited for a wide
variety of data acquisition and signal processing applications.
The ADA4930-1 is available in a Pb-free, 3 mm × 3 mm 16-lead
LFCSP, and the ADA4930-2 is available in a Pb-free, 4 mm × 4 mm
24-lead LFCSP. The pinout has been optimized to facilitate printed
circuit board (PCB) layout and minimize distortion. The
ADA4930-1 is specified to operate over the −40°C to +105°C
temperature range, and the ADA4930-2 is specified to operate over
the −40°C to +105°C temperature range for 3.3 V or 5 V supply
voltages.
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 2 of 25
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
3.3 V Operation ............................................................................ 3
3.3 V VOCM to VO, cm Performance ............................................... 4
3.3 V General Performance ......................................................... 4
5 V Operation ............................................................................... 5
5 V VOCM to VO, cm Performance .................................................. 6
5 V General Performance ............................................................ 6
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 15
Operational Description ................................................................ 16
Definition of Terms .................................................................... 16
Theory of Operation ...................................................................... 17
Analyzing an Application Circuit ............................................ 17
Setting the Closed-Loop Gain .................................................. 17
Estimating the Output Noise Voltage ...................................... 17
Impact of Mismatches in the Feedback Networks ................. 18
Input Common-Mode Voltage Range ..................................... 18
Minimum RG Value .................................................................... 19
Setting the Output Common-Mode Voltage .......................... 19
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Layout, Grounding, and Bypassing .............................................. 23
High Performance ADC Driving ................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
5/2017—Rev. B to Rev. C
Changes to Figure 5 and Figure 6 ........................................................... 8
Changes to Input Common-Mode Adjustment with DC Biased
Source Section .......................................................................................... 21
Changes to High Performance ADC Driving Section
and Figure 60 .................................................................................... 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
1/2015—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
10/2010—Rev. 0 to Rev. A
Changes to General Description Section ....................................... 1
10/2010—Revision 0: Initial Version
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 3 of 25
SPECIFICATIONS
3.3 V OPERATION
VS = 3.3 V, VICM = 0.9 V, VOCM = 0.9 V, RF = 301 Ω, RG = 301 Ω, RL, dm = 1 kΩ, single-ended input, differential output, TA = 25°C, TMIN to
TMAX = −40°C to +105°C, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
V
O, dm
= 0.1 V p-p
1430
MHz
−3 dB Large Signal Bandwidth VO, dm = 2 V p-p 887 MHz
Bandwidth for 0.1 dB Flatness VO, dm = 0.1 V p-p
ADA4930-1 380 MHz
ADA4930-2 89 MHz
Slew Rate VO, dm = 2 V step, 25% to 75% 2877 V/µs
Settling Time to 0.1% VO, dm = 2 V step, RL = 200 Ω 6.3 ns
Overdrive Recovery Time G = 3, VIN, dm = 0.7 V p-p pulse 1.5 ns
NOISE/HARMONIC PERFORMANCE
HD2/HD3 VO, dm = 2 V p-p, fC = 10 MHz −98/−97 dB
VO, dm = 2 V p-p, fC = 30 MHz −91/−88 dB
VO, dm = 2 V p-p, fC = 70 MHz −79/−79 dB
VO, dm = 2 V p-p, fC = 100 MHz −73/−73 dB
Third-Order IMD VO, dm = 1 V p-p/tone, fC = 70.05 MHz ± 0.05 MHz 91 dBc
V
O, dm
= 1 V p-p/tone, f
C
= 140.05 MHz ± 0.05 MHz
86
dBc
Input Voltage Noise f = 100 kHz 1.15 nV/√Hz
Input Current Noise f = 100 kHz 3 pA/√Hz
Crosstalk f = 100 MHz, ADA4930-2, RL = 200 Ω −90 dB
DC PERFORMANCE
Input Offset Voltage VIP = VIN = VOCM = 0 V, RL = open circuit −3.1 −0.5 +3.1 mV
Input Offset Voltage Drift TMIN to TMAX 2.75 µV/°C
Input Bias Current −36 −24 −16 µA
Input Bias Current Drift TMIN to TMAX −0.05 µA/°C
Input Offset Current −1.8 +0.1 +1.8 µA
Open-Loop Gain RF = RG = 10 kΩ, ΔVO = 0.5 V, RL = open circuit 64 dB
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range 0.3 1.2 V
Input Resistance Differential 150 kΩ
Common mode 3 MΩ
Input Capacitance Common mode 1 pF
CMRR ΔVICM = 0.5 V dc; RF = RG = 10 kΩ, RL = open circuit −82 −77 dB
OUTPUT CHARACTERISTICS
Output Voltage Each single-ended output; RF = RG = 10 kΩ 0.11 1.74 V
Linear Output Current Each single-ended output; f = 1 MHz, TDH ≤ 60 dBc 30 mA
Output Balance Error f = 1 MHz 55 dB
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 4 of 25
3.3 V VOCM TO VO, CM PERFORMANCE
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
OCM
−3 dB Bandwidth VO, cm = 0.1 V p-p 745 MHz
Slew Rate VO, cm = 2 V p-p, 25% to 75% 828 V/µs
VOCM INPUT CHARACTERISTICS
Input Voltage Range 0.8 1.1 V
Input Resistance 7.0 8.3 10.3 kΩ
Input Offset Voltage VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V −25 +15.4 +31 mV
Input Voltage Noise f = 100 kHz 23.5 nV/√Hz
Gain 0.99 1 1.02 V/V
CMRR ΔVOCM = 0.5 V dc; RF = RG = 10 kΩ, RL = open circuit −83 −77 dB
3.3 V GENERAL PERFORMANCE
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 3.3 V
Quiescent Current per Amplifier Enabled 32 35 40 mA
Enabled, TMIN to TMAX variation 81 µA/°C
Disabled 0.44 1.8 2.35 mA
+PSRR ΔVICM = 0.5 V; RF = RG = 10 kΩ, RL = open circuit −74 −70 dB
−PSRR ΔVICM = 0.5 V; RF = RG = 10 kΩ, RL = open circuit −87 −76 dB
POWER-DOWN (
PD
)
PD Input Voltage Disabled <0.8 V
Enabled >1.3 V
Turn-Off Time 1 µs
Turn-On Time 12 ns
PD Pin Bias Current
Enabled PD = 3.3 V 0.09 µA
Disabled PD = 0 V 97 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 5 of 25
5 V OPERATION
VS = 5 V, V ICM = 0.9 V, VOCM = 0.9 V, RF = 301 Ω, RG = 301 Ω, RL, dm = 1 kΩ, single-ended input, differential output, TA= 25°C,
TMIN to TMAX = −40°C to +105°C, unless otherwise noted.
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VO, dm = 0.1 V p-p 1350 MHz
−3 dB Large Signal Bandwidth VO, dm = 2 V p-p 937 MHz
Bandwidth for 0.1 dB Flatness VO, dm = 0.1 V p-p
ADA4930-1 369 MHz
ADA4930-2 90 MHz
Slew Rate VO, dm = 2 V step, 25% to 75% 3400 V/µs
Settling Time to 0.1% VO, dm = 2 V step, RL = 200 Ω 6 ns
Overdrive Recovery Time G = 3, VIN, dm = 0.7 V p-p pulse 1.5 ns
NOISE/HARMONIC PERFORMANCE
HD2/HD3 VO, dm = 2 V p-p, fC = 10 MHz −104/−101 dB
VO, dm = 2 V p-p, fC = 30 MHz −91/−93 dB
VO, dm = 2 V p-p, fC = 70 MHz −79/−82 dB
VO, dm = 2 V p-p, fC = 100 MHz −73/−75 dB
Third-Order IMD VO, dm = 1 V p-p/tone, fC = 70.05 MHz ± 0.05 MHz 94 dBc
VO, dm = 1 V p-p/tone, fC = 140.05 MHz ± 0.05 MHz 90 dBc
Input Voltage Noise f = 100 kHz 1.2 nV/√Hz
Input Current Noise f = 100 kHz 2.8 pA/√Hz
Crosstalk f = 100 MHz, ADA4930-2, RL = 200 Ω −90 dB
DC PERFORMANCE
Input Offset Voltage VIP = VIN = VOCM = 0 V, RL = open circuit −3.1 −0.15 +3.1 mV
Input Offset Voltage Drift
T
MIN
to T
MAX
1.8
µV/°C
Input Bias Current −34 −23 −15 µA
Input Bias Current Drift TMIN to TMAX −0.05 µA/°C
Input Offset Current −0.82 +0.1 +0.82 µA
Open-Loop Gain RF = RG = 10 kΩ, ΔVO = 1 V, RL = open circuit 64 dB
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range 0.3 2.8 V
Input Resistance Differential 150 kΩ
Common mode
3
MΩ
Input Capacitance Common mode 1 pF
CMRR ΔVICM = 1 V dc; RF = RG = 10 kΩ, RL = open circuit −82 −77 dB
OUTPUT CHARACTERISTICS
Output Voltage Each single-ended output; RF = RG = 10 kΩ 0.18 3.38 V
Linear Output Current Each single-ended output; f = 1 MHz, TDH ≤ 60 dBc 30 mA
Output Balance Error f = 1 MHz 55 dB
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 6 of 25
5 V VOCM TO VO, CM PERFORMANCE
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
V
OCM
DYNAMIC PERFORMANCE
−3 dB Bandwidth VO, cm = 0.1 V p-p 740 MHz
Slew Rate VO, cm = 2 V p-p, 25% to 75% 1224 V/µs
VOCM INPUT CHARACTERISTICS
Input Voltage Range 0.5 2.3 V
Input Resistance 7.0 8.3 10.2 kΩ
Input Offset Voltage VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V −25 +0.35 +15 mV
Input Voltage Noise f = 100 kHz 23.5 nV/√Hz
Gain 0.99 1 1.02 V/V
CMRR ΔVOCM = 1.5 V; RF = RG = 10 kΩ, RL = open circuit −80 −77 dB
5 V GENERAL PERFORMANCE
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 5 V
Quiescent Current per Amplifier Enabled 31.1 34 38.4 mA
Enabled, TMIN to TMAX variation 74.5 µA/°C
Disabled 0.45 1.8 2.6 mA
+PSRR
ΔV
ICM
= 1 V; R
F
= R
G
= 10 kΩ, R
L
= open circuit
−74
−71
dB
−PSRR ΔVICM = 1 V; RF = RG = 10 kΩ, RL = open circuit −91 −75 dB
POWER-DOWN (PD)
PD Input Voltage Disabled <2.5 V
Enabled >3 V
Turn-Off Time 1 µs
Turn-On Time 12 ns
PD Pin Bias Current
Enabled PD = 5 V 0.09 µA
Disabled PD = 0 V 97 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 7 of 25
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Supply Voltage 5.5 V
Power Dissipation
See Figure 4
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD51-7.
Table 8. Thermal Resistance
Package Type θJA Unit
16-Lead LFCSP (Exposed Pad) 98 °C/W
24-Lead LFCSP (Exposed Pad) 67 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4930-1/
ADA4930-2 packages is limited by the associated rise in
junction temperature (TJ) on the die. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
ADA4930-1/ADA4930-2. Exceeding a junction temperature of
150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and
power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation vs. the
ambient temperature for the ADA4930-1 single 16-lead LFCSP
(98°C/W) and the ADA4930-2 dual 24-lead LFCSP (67°C/W)
on a JEDEC standard 4-layer board.
3.5
0–40 11090 100
MAXIMUM POWER DISSIPATIO N (W)
TEMPERATURE (°C)
0.5
1.0
1.5
2.0
2.5
3.0
–30 –20 –10 010 20 30 40 50 60 70 80
ADA4930-2
ADA4930-1
09209-004
Figure 4. Maximum Power Dissipation vs. Ambient Temperature,
4-Layer Board
ESD CAUTION
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 8 of 25
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
N
OTES
1
. EXPOSED PADDLE. T HE EXPOSED PAD IS NOT
ELE CTRIC AL L Y CO NNE CTED T O T H E DE VICE. IT I S
TYPICALLY SOL DERED TO GROUND OR A POWER
PL ANE ON T HE P C B THAT IS THERM ALL Y CONDUCT IVE .
–FB
+IN
–IN
+FB
+VS
+VS
+VS
+VS
–VS
–VS
–VS
–VS
–OUT
PD
+OUT
VOCM
09209-005
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADA4930-1
TOP VIEW
(No t to S cale)
Figure 5. ADA4930-1 Pin Configuration
+IN1
–IN1
+FB1
+V
S1
+V
S1
–FB2
+IN2
–IN2
+FB2
+V
S2
V
OCM2
+OUT2
+V
S2
–V
S1
–V
S1
–FB1
PD1
–OUT1
–V
S2
–V
S2
V
OCM1
+OUT1
PD2
–OUT2
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELE CTRI CALLY CO N NEC TED TO THE DE VICE . IT IS
TYP ICAL LY SOLDERE D TO GRO UND OR A POWER
PL A NE ON T HE PCB THAT IS T HE RMALLY CONDUCT IVE .
09209-006
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
11
7
12
20
19
21
22
23
24
ADA4930-2
TOP VI EW
(Not t o S cale)
Figure 6. ADA4930-2 Pin Configuration
Table 9. ADA4930-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 −FB Negative Output for Feedback
Component Connection.
2 +IN Positive Input Summing Node.
3 −IN Negative Input Summing Node.
4 +FB Positive Output for Feedback
Component Connection.
5 to 8 +VS Positive Supply Voltage.
9 VOCM Output Common-Mode Voltage.
10 +OUT Positive Output for Load Connection.
11 −OUT Negative Output for Load Connection.
12 PD Power-Down Pin.
13 to 16 −VS Negative Supply Voltage.
EPAD
Exposed Paddle. The exposed pad is not
electrically connected to the device. It is
typically soldered to ground or a power
plane on the PCB that is thermally
conductive.
Table 10. ADA4930-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Negative Input Summing Node 1.
2 +FB1 Positive Output Feedback Pin 1.
3, 4 +VS1 Positive Supply Voltage 1.
5 −FB2 Negative Output Feedback Pin 2.
6 +IN2 Positive Input Summing Node 2.
7 −IN2 Negative Input Summing Node 2.
8 +FB2 Positive Output Feedback Pin 2.
9, 10 +VS2 Positive Supply Voltage 2.
11 VOCM2 Output Common-Mode Voltage 2.
12 +OUT2 Positive Output 2.
13 −OUT2 Negative Output 2.
14 PD2 Power-Down Pin 2.
15, 16 −VS2 Negative Supply Voltage 2.
17 VOCM1 Output Common-Mode Voltage 1.
18 +OUT1 Positive Output 1.
19 −OUT1 Negative Output 1.
20 PD1 Power-Down Pin 1.
21, 22 −VS1 Negative Supply Voltage 1.
23 −FB1 Negative Output Feedback Pin 1.
24 +IN1 Positive Input Summing Node 1.
EPAD
Exposed Paddle. The exposed pad is
not electrically connected to the
device. It is typically soldered to
ground or a power plane on the PCB
that is thermally conductive.
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 9 of 25
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, VICM = 0.9 V, V OCM = 0.9 V, RL, dm = 1 kΩ, unless otherwise noted.
–27
–24
–21
–18
–15
–12
–9
–6
–3
0
3
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
NORMALIZED CLOSED LOOP GAIN (dB)
V
IN
= 100mV
G = 1, R
G
= 300Ω
G = 2, R
G
= 150Ω
G = 5, R
G
= 60Ω
09209-007
Figure 7. Small Signal Frequency Response
at Gain = 1, Gain = 2, and Gain = 5
–27
–24
–21
–18
–15
–12
–9
–6
–3
0
3
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
CLOSED LOOP GAIN (dB)
V
IN
= 100mV
V
S
= 3.3V
V
S
= 5.0V
09209-008
Figure 8. Small Signal Frequency Response
at VS = 3.3 V and VS = 5 V
–27
–24
–21
–18
–15
–12
–9
–6
–3
0
3
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
CLOSED LOOP GAIN (dB)
V
IN
= 100mV
T
A
= –40° C
T
A
= +25°C
T
A
= +105°C
09209-009
Figure 9. Small Signal Frequency Response
at TA = −40°C, TA = 25°C, and TA = 105°C
–27
–24
–21
–18
–15
–12
–9
–6
–3
0
3
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
NORMALIZED CLOSED LOOP GAIN (dB)
V
IN
= 2V p-p
G = 1, R
G
= 300Ω
G = 2, R
G
= 150Ω
G = 5, R
G
= 60Ω
09209-010
Figure 10. Large Signal Frequency Response
at Gain = 1, Gain = 2, and Gain = 5
–27
–24
–21
–18
–15
–12
–9
–6
–3
3
0
6
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
CLOSED LOOP GAIN (dB)
V
IN
= 2V p-p
V
S
= 3.3V
V
S
= 5.0V
09209-011
Figure 11. Large Signal Frequency Response
at VS = 3.3 V and VS = 5 V
–27
–24
–21
–18
–15
–12
–9
–6
–3
3
0
6
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
CLOSED LOOP GAIN (dB)
V
IN
= 2V p-p
T
A
= –40° C
T
A
= +25°C
T
A
= +105°C
09209-012
Figure 12. Large Signal Frequency Response
at TA = −40°C, TA = 25°C, and TA = 105°C
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 10 of 25
–27
–24
–21
–18
–15
–12
–9
–6
–3
0
3
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
NORMALIZED CLOSED LOOP GAIN (dB)
V
IN
= 100mV p - p
R
L
= 1kΩ
R
L
= 200Ω
09209-013
Figure 13. Small Signal Frequency Response for RL = 200 Ω and RL = 1 kΩ
–6
–5
–4
–3
–2
–1
0
1
2
3
1M 10M 100M 1G
FREQUENCY ( Hz )
GAI N ( dB)
09209-014
V
IN
= 100mV
Figure 14. VOCM Small Signal Frequency Response
–120
–110
–100
–90
–80
–70
DISTORTION (dBc)
–60
–50
–40
1M 10M
100M 200M
FREQUENCY (Hz)
HD2, G AIN = 1
HD3, G AIN = 1
HD2, G AIN = 2
HD3, G AIN = 2
HD2, G AIN = 5
HD3, G AIN = 5
09209-015
Figure 15. Harmonic Distortion vs. Frequency
for Gain = 1, Gain = 2, and Gain = 5
–27
–24
–21
–18
–15
–12
–9
–6
–3
3
0
6
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
CLOSED-LOOP GAIN (dB)
V
IN
= 2V p-p
R
L
= 1kΩ
R
L
= 200Ω
09209-016
Figure 16. Large Signal Frequency Response
for RL = 200 Ω and RL = 1 kΩ
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
1M 10M 100M 1G
GAI N ( dB)
FREQUENCY (Hz)
ADA4930-2, 200Ω, OUT 1
ADA4930-2, 200Ω, OUT 2
ADA4930-1, 200Ω
ADA4930-1, 1kΩ
ADA4930-2, 1kΩ, OUT 1
ADA4930-2, 1kΩ, OUT 2
09209-017
Figure 17. Small Signal 0.1 dB Flatness vs. Frequency for
RL = 200 Ω and RL = 1 kΩ
–110
–100
–90
–80
–70
–60
–50
1M 10M 100M 200M
DISTORTION (dBc)
FREQUENCY
(Hz)
HD2, R
L
= 200Ω
HD3, R
L
= 200Ω
HD2, R
L
= 1kΩ
HD3, R
L
= 1kΩ
09209-018
Figure 18. Harmonic Distortion vs. Frequency
for RL = 200 Ω and RL = 1 kΩ
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 11 of 25
–110
–100
–90
–80
–70
–105
–95
–85
–75
–65
–60
1M 10M 100M 200M
DISTORTION (dBc)
FREQUENCY (Hz)
HD2, V
S
= 5.0V
HD3, V
S
= 5.0V
HD2, V
S
= 3.3V
HD3, V
S
= 3.3V
09209-019
Figure 19. ADA4930-1 Harmonic Distortion vs. Frequency
at VS = 3.3 V and VS = 5 V
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.4
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
DISTORTION (dBc)
70MHz, HD2
70MHz, HD3
10MHz, HD2
10MHz, HD3
V
OCM
ABOVE – V
S
(V)
09209-020
Figure 20. Harmonic Distortion vs. VOCM at VS = 3.3 V
at 10 MHz and 70 MHz
–140
–120
–100
–80
–60
–40
–20
0
DISTOTION (dBc)
FREQUENCY (Hz)
HD2, VOUT = 1V p-p
HD3, VOUT = 1V p-p
HD2, V
OUT
= 2V p-p
HD3, V
OUT
= 2V p-p
1M 10M 100M 200M
09209-021
Figure 21. Distortion vs. VOUT at VS = 3.3 V
–140
–120
–100
–80
–60
–40
–20
1.0 1.5 2.0 2.5 3.0 3.5
DISTORTON (dBc)
VOUT (V p-p)
HD2, 3. 3V
HD3, 3. 3V
HD2, 5. 0V
HD3, 5. 0V
09209-022
Figure 22. Harmonic Distortion vs. Output @ 10 MHz
–110
–100
–90
–80
–70
–60
–50
–40
0.5 1.0 1.5 2.0 2.5 3.0
DISTORTION (dBc)
VOCM ABOVE – V S(V)
70MHz, HD2
70MHz, HD3
10MHz, HD2
10MHz, HD3
09209-023
Figure 23. Harmonic Distortion vs. VOCM
at 10 MHz and 70 MHz
–140
–120
–100
–80
–60
–40
–20
0
20
69.8 69.9 70.0 70.1 70.2 70.3
FREQUENCY (MHz)
NORM ALIZED S P ECTRUM ( dBc)
09209-024
Figure 24. 70 MHz Intermodulation Distortion
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 12 of 25
100k 1M 10M 100M 1G
FRE Q UE NCY ( Hz )
CMRR (dB)
09209-025
–70
–75
–65
–60
–55
–50
–45
–40
Figure 25. CMRR vs. Frequency, RL = 200 Ω
–1401M 10M 100M 1G
FREQUENCY (Hz)
CROSSTALK ( dB)
–120
–100
–80
–60
–130
–110
–90
–70 CHANNEL 1 TO CHANNEL 2
CHANNEL 2 TO CHANNEL 1
09209-026
Figure 26. Crosstalk vs. Frequency, RL = 200 Ω
–70
–60
–50
–40
–30
–20
–10
0
1M 10M 100M 1G 10G
FREQUENCY ( Hz )
S PARAMETERS (dB)
S11
S22
09209-027
Figure 27. S11, S22, RL = 200 Ω
–100
–90
–80
–70
–60
–50
–40
–30
–20
100k 1M 10M 100M 1G
PSRR ( dB)
FREQUENCY (Hz)
09209-028
Figure 28. PSRR vs. Frequency, RL = 200 Ω
1M 10M 100M 1G
FREQUENCY ( Hz )
CROSS TAL K ( dB)
–50
–35
–55
–40
–25
–60
–45
–30
–20
V
IN
= 1V p-p
GAI N = 2
09209-029
Figure 29. Output Balance vs. Frequency, RL = 200 Ω
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
–55
–50
1M 10M 100M 200M
DISTORTION (dBc)
FREQUENCY (Hz)
RL = 200Ω
RL = 1kΩ
09209-030
Figure 30. SFDR
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 13 of 25
–300
–240
–180
–120
–60
0
60
–270
–210
–150
–90
30
30
–40
–20
0
20
40
60
80
–30
–10
10
30
50
70
10k 100k 1M 10M 100M 1G 10G
PHASE (°)
GAIN (dB)
FREQUENCY (MHz)
09209-031
GAIN
PHASE
Figure 31. Open Loop Gain and Phase
0.10
0.05
0
–0.05
–0.10 0246 10
V
OUT
(V)
TIME (ns)
8
09209-032
Figure 32. Small Signal Pulse Response
0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0 246 10
V
OUT
(V)
TIME (ns)
8
V
O
= 2V p-p
V
O
= 1V p-p
09209-033
Figure 33. Large Signal Pulse Response
0
1
10
100
10 100 1k 10k 100k 1M 10M 100M
V
N
(nV/
√
hz)
FREQUENCY (Hz)
09209-034
Figure 34. Voltage Noise Spectral Density
0.80
0.82
0.84
0.86
0.88
0.90
0.92
0.94
0.96
0.98
1.00
02468101214161820
V
OUT
(V)
TIME (ns)
09209-035
Figure 35. Small Signal VOCM Pulse Response
0
0.5
1.0
1.5
2.0
2.5
3.0
0 2 4 6 8 10 12 14 16 18 20
V
OUT
(V)
TIME (ns)
09209-036
Figure 36. Large Signal VOCM Pulse Response
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 14 of 25
–0.25
0
0 100 200 300 400 500 600 700 800 900 1000
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
VOL
T
AGE (V)
TIME (ns)
PD
+OUT
–OUT
0
9209-037
Figure 37. PD Response vs. Time
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
0 5 10 15 20 25 30 35 40 45 50
VOLTAGE (V)
TIME (ns)
V
IN
× 3
V
O, dm
09209-038
Figure 38. Vo, dm Overdrive Recovery
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 15 of 25
TEST CIRCUITS
ADA4930
1kΩ
+V
S
301Ω
301Ω
50Ω
0.9V 0.9V
0.9V
301Ω
26.7Ω
301Ω
V
OCM
57.6Ω
V
IN
09209-046
Figure 39. Equivalent Basic Test Circuit
+VS
ADA4930
301Ω
301Ω50Ω
301Ω
50Ω
50Ω
26.7Ω
301Ω
VOCM
57.6Ω
VIN
09209-047
0.9V 0.9V
0.9V
Figure 40. Test Circuit for Output Balance
0.9V 0.9V
0.9V
0.9V
+V
S
ADA4930
301Ω
301Ω
50Ω
301Ω
412Ω
412Ω
26.7Ω
301Ω
V
OCM
261Ω
57.6Ω
V
IN
FILTER 0.1µF
0.1µF
FILTER
09209-048
Figure 41. Test Circuit for Distortion Measurements
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 16 of 25
OPERATIONAL DESCRIPTION
DEFINITION OF TERMS
+IN
–IN +OUT
–OUT
+D
IN
–FB
+FB
–D
IN
V
OCM
R
G
R
F
R
G
V
OUT, dm
R
L, dm
R
F
ADA4930
09209-049
Figure 42. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or,
equivalently, output differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Common-Mode Voltage
Common-mode voltage refers to the average of two node voltages.
The output common-mode voltage is defined as
VOUT, cm = (V+OUT + V−OUT)/2
Balance
Output balance is a measure of how close the differential signals are
to being equal in amplitude and opposite in phase. Output balance
is most easily determined by placing a well-matched resistor
divider between the differential voltage nodes and comparing the
magnitude of the signal at the divider midpoint with the magnitude
of the differential signal (see Figure 39). By this definition, output
balance is the magnitude of the output common-mode voltage
divided by the magnitude of the output differential mode voltage.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
=
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 17 of 25
THEORY OF OPERATION
The ADA4930-1/ADA4930-2 differ from conventional op amps
in that they have two outputs whose voltages move in opposite
directions and an additional input, VOCM. Like an op amp, they rely
on high open-loop gain and negative feedback to force these
outputs to the desired voltages. The ADA4930-1/ADA4930-2
behave much like standard voltage feedback op amps and facilitate
single-ended-to-differential conversions, common-mode level
shifting, and amplifications of differential signals. Like op amps,
the ADA4930-1/ADA4930-2 have high input impedance and low
output impedance.
Two feedback loops control the differential and common-mode
output voltages. The differential feedback, set with external
resistors, controls the differential output voltage. The common-
mode feedback controls the common-mode output voltage. This
architecture makes it easy to set the output common-mode level
to any arbitrary value within the specified limits. The output
common-mode voltage is forced to be equal to the voltage applied
to the VOCM input by the internal common-mode feedback loop.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results
in differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The ADA4930-1/ADA4930-2 use high open-loop gain and
negative feedback to force their differential and common-mode
output voltages to minimize the differential and common-mode
error voltages. The differential error voltage is defined as the
voltage between the differential inputs labeled +IN and −IN
(see Figure 42). For most purposes, this voltage can be assumed
to be zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 42 is
determined by
G
F
dmIN
dmOUT
R
R
V
V=
,
,
where the gain and feedback resistors, RG and RF, on each side
are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4930-1/ADA4930-2 can
be estimated using the noise model in Figure 43. The input-referred
noise voltage density, vnIN, is modeled as differential. The noise
currents, inIN− and inIN+, appear between each input and ground.
ADA4930
+
RF2
VnOD
VnCM
VOCM
VnIN
RF1
RG2
RG1 VnRF1
VnRF2
VnRG1
VnRG2
inIN+
inIN–
09209-050
Figure 43. Noise Model
Similar to the case of conventional op amps, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by an appropriate output factor.
The output voltage due to vnIN is obtained by multiplying vnIN by
the noise gain, GN.
The circuit noise gain is
( )
21
N
ββ
G+
=2
where the feedback factors are
G1
F1
G1
1
R
R
R
β+
=
and
G2
F2
G2
2RR
R
β+
=
.
When the feedback factors are matched, RF1/RG1 = RF2/RG2,
β1 = β2 = β, and the noise gain becomes
G
F
N
R
R
β
G+== 1
1
.
The noise currents are uncorrelated with the same mean-square
value, and each produces an output voltage that is equal to the
noise current multiplied by the associated feedback resistance.
The noise voltage density at the VOCM pin is vnCM. When the
feedback networks have the same feedback factor, as in most
cases, the output noise due to vnCM is common-mode and the
output noise from VOCM is zero.
Each of the four resistors contributes (4kTRxx)1/2. The noise
from the feedback resistors appears directly at the output, and
the noise from the gain resistors appears at the output multiplied
by RF/RG.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
∑
=
=8
1i
2
)( nODinOD vv
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 18 of 25
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise Contribution Input Noise Term
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Terms
Differential Input vnIN vnIN GN vnOD1 = GN(vnIN)
Inverting Input inIN+ inIN+ × (RF2) 1 vnOD2 = (inIN+)(RF2)
Noninverting Input inIN− inIN− × (RF1) 1 vnOD3 = (inIN−)(RF1)
VOCM Input vnCM vnCM 0 vnOD4 = 0
Gain Resistor RG1 vnRG1 (4kTRG1)1/2 RF1/RG1 vnOD5 = (RF1/RG1)(4kTRG1)1/2
Gain Resistor RG2 vnRG2 (4kTRG2)1/2 RF2/RG2 vnOD6 = (RF2/RG2)(4kTRG2)1/2
Feedback Resistor RF1 vnRF1 (4kTRF1)1/2 1 vnOD7 = (4kTRF1)1/2
Feedback Resistor RF2 vnRF2 (4kTRF2)1/2 1 vnOD8 = (4kTRF2)1/2
Table 12. Differential Input, DC-Coupled, VS = 5 V
Nominal Gain (dB) RF1, RF2 (Ω) RG1, RG2 (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
0 301 301 602 4.9
6 301 150 300 6.2
10 301 95.3 190.6 7.8
14 301 60.4 120.4 10.1
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω, VS = 5 V
Nominal Gain (dB) RF1, RF2 (Ω) RG1 (Ω) RT (Ω) RIN, cm (Ω) RG2 (Ω)1 Differential Output Noise Density (nV/√Hz)
0
301
142
64.2
190.67
170
5.9
6 301 63.4 84.5 95.06 95 7.8
10 301 33.2 1 k 53.54 69.3 9.3
14 301 10.2 1.15 k 17.5 57.7 10.4
1 RG2 = RG1 + (RS||RT).
Table 11 summarizes the input noise sources, the multiplication
factors, and the output-referred noise density terms.
Table 12 and Table 13 list several common gain settings, associated
resistor values, input impedance, and output noise density for both
balanced and unbalanced input configurations.
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
The gain from the VOCM pin to VO, dm is equal to
2(β1 − β2)/(β1 + β2)
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VOCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VOCM input
to VO, dm is either +2 or −2, depending on which loop is closed. The
feedback loops are nominally matched to within 1% in most
applications, and the output noise and offsets due to the VOCM
input are negligible.
If the loops are intentionally mismatched by a large amount, it is
necessary to include the gain term from VOCM to VO, dm and
account for the extra noise. For example, if β1 = 0.5 and β2 = 0.25,
the gain from VOCM to VO, dm is 0.67. If the VOCM pin is set to 0.9 V,
a differential offset voltage is present at the output of
(0.9 V)(0.67) = 0.6 V. The differential output noise contribution
is (5 nV/√Hz)(0.67) = 3.35 nV/√Hz. Both of these results are
undesirable in most applications; therefore, it is best to use
nominally matched feedback factors.
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
As a practical summarization of the previous issues, resistors of
1% tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 9 mV due
to a 0.9 V VOCM input, negligible VOCM noise contribution, and
no significant degradation in output balance error.
INPUT COMMON-MODE VOLTAGE RANGE
The input common-mode range at the summing nodes of the
ADA4930-1/ADA4930-2 is specified as 0.3 V to 1.5 V at VS = 3.3 V.
To avoid nonlinearities, the voltage swing at the +IN and −IN
terminals must be confined to these ranges.
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 19 of 25
MINIMUM RG VALUE
Due to the wide bandwidth of the ADA4930-1/ADA4930-2, the
value of RG must be greater than or equal to 301 Ω at unity gain
to provide sufficient damping in the amplifier front end. In the
terminated case, RG includes the Thevenin resistance of the
source and load terminations.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4930-1/ADA4930-2 is biased at 3/10 of
the total supply voltage above −VS with an internal voltage divider.
The input impedance of the VOCM pin is 8.4 kΩ. When relying
on the internal bias, the output common-mode voltage is within
about 100 mV of the expected value.
In cases where accurate control of the output common-mode
level is required, it is recommended that an external source or
resistor divider be used with source resistance less than 100 Ω.
The output common-mode offset listed in the Specifications
section assumes that the VOCM input is driven by a low
impedance voltage source.
It is also possible to connect the VOCM input to a common-mode
voltage (VCM) output of an ADC. However, care must be taken
to ensure that the output has sufficient drive capability. The
input impedance of the VOCM pin is approximately 10 kΩ. If
multiple ADA4930-1/ADA4930-2 devices share one reference
output, it is recommended that a buffer be used.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance depends on whether the signal
source is single-ended or differential. For a balanced differential
input signal, as shown in Figure 44, the input impedance (RIN, dm)
between the inputs (+DIN and −DIN) is RIN, dm = 2 × RG.
+V
S
ADA4930
+IN
–IN
R
F
R
F
+D
IN
–D
IN
V
OCM
R
G
R
G
V
OUT, dm
09209-051
Figure 44. ADA4930-1/ADA4930-2 Configured for Balanced (Differential) Inputs
For an unbalanced single-ended input signal, as shown in
Figure 45, the input impedance is
RIN,SE = RG1
)
1
(+
+
β2
β1
β2β1
where:
β1 =
F1
G1
G1
RR
R
+
β2 =
2
2
F
G2
G
RR
R
+
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
RG1
RG2
RF2
RF1
VOCM
RIN, SE
09209-052
Figure 45. ADA4930-1/ADA4930-2 with Unbalanced (Single-Ended) Input
For a balanced system where RG1 = RG2 = RG and RF1 = RF2 = RF,
the equations simplify to
+
−
=
+
==
)2(
1
F
G
F
G
IN,SE
F
G
G
RR
R
R
R
and
RR
R
β2β1
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG1. The common-mode
voltage at the amplifier input terminals can be easily determined
by noting that the voltage at the inverting input is equal to the
noninverting output voltage divided down by the voltage divider
formed by RF2 and RG2. This voltage is present at both input
terminals due to negative voltage feedback and is in phase with
the input signal, thus reducing the effective voltage across RG1,
partially bootstrapping it.
Terminating a Single-Ended Input
This section describes the five steps that properly terminate a
single-ended input to the ADA4930-1/ADA4930-2. Assume a
system gain of 1, RF1 = RF2 = 301 Ω, an input source with an open-
circuit output voltage of 2 V p-p, and a source resistance of 50 Ω.
Figure 46 shows this circuit.
1. Calculate the input impedance.
β1 = β2 = 301/602 = 0.5 and RIN = 401.333 Ω
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 20 of 25
R
S
50Ω
V
S
2V p-p
R
IN
401.333Ω
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
R
G1
301Ω
R
G2
301Ω
R
F2
301Ω
R
F1
301Ω
V
OCM
09209-053
Figure 46. Single-Ended Input Impedance RIN
2. Add a termination resistor, RT. To match the 50 Ω source
resistance, RT is added. Because RT||401.33 Ω = 50 Ω,
RT = 57.116 Ω.
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
R
S
50Ω
R
G1
301Ω
R
G2
301Ω
R
F2
301Ω
R
F1
301Ω
V
OCM
V
S
2V p-p
R
IN
50Ω
R
T
57.116Ω
09209-054
Figure 47. Adding Termination Resistor RT
3. Replace the source-termination resistor combination with
its Thevenin equivalent. The Thevenin equivalent of the
source resistance RS and the termination resistance RT is
RTH = RS||RT = 26.66 Ω. The Thevenin equivalent of the
source voltage is
VTH = VS
T
S
T
R
R
R
+
= 1.066 V p-p
R
S
50Ω
V
S
2V p-p
R
T
57.116Ω
R
TH
26.661Ω
V
TH
1.066V p-p
09209-055
Figure 48. Thevenin Equivalent Circuit
4. Set RF1 = RF2 = RF to maintain a balanced system.
Compensate the imbalance caused by RTH. There are two
methods available to compensate, which follow:
• Add RTH to RG2 to maintain balanced gain resistances
and increase RF1 and RF2 to RF =
TH
S
V
V
Gain(RG + RTH) to
maintain the system gain.
• Decrease RG2 to RG2 =
GainV
V
R
S
TH
F
×
×
to maintain system
gain and decrease RG1 to (RG2 − RTH) to maintain
balanced gain resistances.
The first compensation method is used in the Analog Devices
DiffAmpCalc™ tool. Using the second compensation method,
RG2 = 160.498 Ω and RG1 = 160.498 − 26.66 = 133.837 Ω. The
modified circuit is shown in Figure 49.
ADA4930
RLVOUT, dm
+VS
–VS
RTH
26.661Ω
RG1
133.837Ω
RG2
160.498Ω
RF2
301Ω
RF1
301Ω
VOCM
VTH
1.066V p-p
09209-056
Figure 49. Thevenin Equivalent with Matched Gain Resistors
Figure 49 presents an easily manageable circuit with matched
feedback loops that can be easily evaluated.
5. The modified gain resistor, RG1, changes the input impedance.
Repeat Step 1 through Step 4 several times using the modified
value of RG1 from the previous iteration until the value of
RT does not change from the previous iteration. After three
additional iterations, the change in RG1 is less than 0.1%.
The final circuit is shown in Figure 50 with the closest
0.5% resistor values.
ADA4930
RLVOUT, dm
1.990V p-p
+VS
–VS
RS
50Ω
RG
142Ω
VP
VN
RG2
169Ω
RF1
301Ω
RF2
301Ω
VOCM
VS
2V p-p
0.998V p-p
RT
64.2Ω
09209-057
Figure 50. Terminated Single-Ended-to-Differential System with G = 1
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 21 of 25
Terminating a Single-Ended Input in a Single-Supply
Applications
When the application circuit of Figure 50 is powered by a single
supply, the common-mode voltage at the amplifier inputs, VP
and VN, may have to be raised to comply with the specified input
common-mode range. Two methods are available: a dc bias on
the source, as shown in Figure 51, or by connecting resistors
RCM between each input and the supply, as shown on Figure 54.
Input Common-Mode Adjustment with DC Biased Source
To drive a 1.8 V ADC with VCM = 1 V, a 3.3 V single supply
minimizes the power dissipation of the ADA4930-1/ADA4930-2.
The application circuit of Figure 50 on a 3.3 V single supply with a
dc bias added to the source is shown in Figure 51.
ADA4930
R
L
V
OUT, dm
1.990V p-p
3.3V
R
S
50Ω
R
G1
142Ω
V
P
V
N
R
G2
142Ω
R
F2
301Ω
R
F1
301Ω
V
OCM
V
S
2V p-p
V
DC
R
T
64.2Ω
64.2Ω
50Ω
09209-151
Figure 51. Single-Supply, Terminated Single-Ended-to-Differential System
with G = 1
To determine the minimum required dc bias, the following steps
must be taken:
1. Convert the terminated inputs to their Thevenin equivalents,
as shown in the Figure 52 circuit.
ADA4930
R
L
V
OUT, dm
1.99V p-p
3.3V
VON
VOP
R
TH
28.11Ω
R
G1
142Ω
V
P
V
N
R
G2
142Ω
R
F2
301Ω
R
F1
301Ω
V
OCM
V
TH
1.124V p-p
V
DC-TH
09209-159
R
TH
28.11Ω
Figure 52. Thevenin Equivalent of Single-Supply Application Circuit
2. Write a nodal equation for VP or VN.
( )
THDCTH
ON
THDCTH
P
VVVVVV
−−
−−
++
+
++= 28.11142301
28.11 142
)(
28.11142301
28.11 142
THDC
OP
THDC
NVVVV −− −
++
+
+=
Recognize that while the ADA4930-1/ADA4930-2 is in its
linear operating region, VP and VN are equal. Therefore,
both equations in Step 2 give equal results.
3. To comply with the minimum specified input common-mode
voltage of 0.3 V at VS = 3.3 V, set the minimum value of VP
and VN to 0.3 V.
4. Recognize that VP and VN are at their minimum values when
VOP and VS are at their minimum (and therefore VON is at its
maximum).
Let
VP min = VN min = 0.3 V, VOCM = VCM = 1 V, V TH min = −VTH/2
VON max = VOCM + VOUT, dm/4 and VOP min = VOCM − VOU T, dm/4
Substitute conditions into the nodal equation for VP and solve
for VDC-TH.
0.3 = −1.124/2 + VDC-TH + 0.361 × (1 + 1.99/4 + 1.124/2 – VDC-TH)
0.3 + 0.562 − 0.361 − 0.18 − 0.203 = 0.639 VDC-TH
VDC-TH = 0.186 V
Or
Substitute conditions into the nodal equation for VN and
solve for VDC-TH.
0.3 = VDC-TH + 0.361 × (1 − 1.99/4 − VDC-TH)
0.3 – 0.361 + 0.18 = 0.639 × VDC-TH
VDC-TH = 0.186 V
5. Converting VDC-TH from its Thevenin equivalent results in
V 0.330.186 =×
+
=
TH
TH
S
DC
R
RR
V
The final application circuit is shown in Figure 53. The
additional dc bias of 0.33 V at the inputs ensures that the
minimum input common-mode requirements are met when
the source signal is bipolar with a 2 V p-p amplitude and
VOCM is at 1 V.
3.3V
ADA4930 R
L
V
OUT, dm
1.990V p-p
R
S
50Ω
R
G1
142Ω
R
G2
142Ω
R
F2
301Ω
R
F1
301Ω
V
OCM
V
S
2V p-p
R
T
64.2Ω
64.2Ω
09209-160
V
P
V
N
50Ω
V
DC
0.33V
Figure 53. Single-Supply Application Circuit with DC Source Bias
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 22 of 25
Input Common-Mode Adjustment with Resistors
The circuit shown in Figure 54 shows an alternate method to
bias the amplifier inputs, eliminating the dc source.
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
3.3V
3.3V
R
S
50Ω
R
G1
301Ω
R
G2
301Ω
R
F2
301Ω
R
F1
301Ω
R
CM
V
OCM
R
CM
V
S
V
S
V
SOURCE
2V p-p R
T
09209-152
V
IN
Figure 54. Single-Supply Biasing Scheme with Resistors
Define β1 = RP/RF1 and β2 = RN/RF2, where RP = RG1||RCM||RF1
and RN = RG2||RCM||RF2.
Set RF1 = RF2 = RF to maintain a balanced system, as shown.
Write a nodal equation at VP and solve for VP.
++
+
=
CM
F
SOCM
IN
G
F
P
R
R
VVV
R
R
β2β1
β1β2
V2
2
1
Determine VP min. This is the minimum input common-mode
voltage from the Specifications section. For a 3.3 V supply, VP min
= 0.3 V.
Determine the minimum input voltage, VIN min at the output of
the source. Recognize that once properly terminated, the source
voltage is ½ of its open circuit value. Therefore, VIN min = −0.5 V.
Rearrange the VP equation for RCM
−−
+
=
OCM
minIN
G
F
P
F
SCM
VV
R
R
V
β1β2
β2β1
RVR 2
2
11
1
min
Calculate the following:
1. β1 and β2. For the circuit shown in Figure 54, β1 = 0.5 and
β2 = 0.5.
2. RCM for VP min = 0.3 V and VIN min = −0.5 V. RCM = 9933 Ω.
3. The new values for β1 and β2. β1 = 0.4925 and β2 = 0.4925.
4. The input impedance using the following:
−+
+
=
−
=
−
β1β2
R
R
β2β1
β2β1
R
V
V
RR
G1
F1
G1
INP
P
G1SEIN 1
1
RIN-SE = 399.35 Ω.
5. RT, RTH, and VTH. RT = 57.16 Ω, RTH = 26.67 Ω, and
VTH = 1.067 V.
6. The new values for RG1 and RG2. RG2 = 160.55 Ω and
RG1 = 133.88 Ω.
7. The new values for β1 and β2. β1 = 0.284 and β2 = 0.317.
8. The new value of RCM. RCM = 4759.63 Ω.
9. Repeat Step 3 through Step 8 until the values of RG1 and RG2
remain constant between iterations. After four iterations,
the final circuit is shown in Figure 55.
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
R
S
50Ω
R
G1
142Ω
R
G2
170Ω
R
F2
301Ω
R
F1
301Ω
R
CM
1.87kΩ
R
CM
1.87kΩ
V
OCM
+V
S
+V
S
V
S
2V p-p
R
T
65.1Ω
09209-153
Figure 55. Single-Supply, Single-Ended Input System with Bias Resistors
Data Sheet ADA4930-1/ADA4930-2
Rev. C | Page 23 of 25
LAYOUT, GROUNDING, AND BYPASSING
The ADA4930-1/ADA4930-2 are high speed devices. Realizing
their superior performance requires attention to the details of
high speed PCB design.
The first requirement is to use a multilayer PCB with solid ground
and power planes that cover as much of the board area as possible.
Bypass each power supply pin directly to a nearby ground plane, as
close to the device as possible. Use 0.1 µF high frequency ceramic
chip capacitors.
Provide low frequency bulk bypassing, using 10 µF tantalum
capacitors from each supply to ground.
Stray transmission line capacitance in combination with package
parasitics can potentially form a resonant circuit at high
frequencies, resulting in excessive gain peaking or possible
oscillation.
Signal routing should be short and direct to avoid such parasitic
effects. Provide symmetrical layout for complementary signals
to maximize balanced performance.
09209-058
Figure 56. ADA4930-1 Ground and Power Plane Voiding
in the Vicinity of RF and RG
Use radio frequency transmission lines to connect the driver
and receiver to the amplifier.
Minimize stray capacitance at the input/output pins by clearing
the underlying ground and low impedance planes near these pins
(see Figure 56).
If the driver/receiver is more than one-eighth of the wavelength
from the amplifier, the signal trace widths should be minimal.
This nontransmission line configuration requires the underlying
and adjacent ground and low impedance planes to be cleared
near the signal lines.
The exposed thermal paddle is internally connected to the ground
pin of the amplifier. Solder the paddle to the low impedance
ground plane on the PCB to ensure the specified electrical
performance and to provide thermal relief. To reduce thermal
impedance further, it is recommended that the ground planes
on all layers under the paddle be connected together with vias.
1.30
0.80
0.80
1.30
09209-059
Figure 57. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
0.8 mm
1.3 mm
POWER P LANE
GRO UND P LANE
TOP METAL
BOTTOM METAL
09209-060
Figure 58. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
ADA4930-1/ADA4930-2 Data Sheet
Rev. C | Page 24 of 25
HIGH PERFORMANCE ADC DRIVING
The ADA4930-1/ADA4930-2 provide excellent performance in
3.3 V single-supply applications.
The circuit shown in Figure 59 is an example of the ADA4930-1
driving an AD9255, 14-bit, 80 MSPS ADC that is specified to
operate with a single 1.8 V supply. The performance of the ADC
is optimized when it is driven differentially, making the best use of
the signal swing available within the 1.8 V supply. The ADA4930-1
performs the single-ended-to-differential conversion, common-
mode level shifting, and buffering of the driving signal.
The ADA4930-1 is configured for a single-ended input to
differential output with a gain of 2 V/V. The 84.5 Ω termination
resistor, in parallel with the single-ended input impedance of
95.1 Ω, provides a 50 Ω termination for the source. The additional
31.6 Ω (95 Ω total) at the inverting input balances the parallel
impedance of the 50 Ω source and the termination resistor that
drives the noninverting input.
The VOCM pin is connected to the VCM output of the AD9255 and
sets the output common mode of the ADA4930-1 at 0.9 V.
Note that a dc bias must be added to the signal source and its
Thevenin equivalent to the gain resistor on the inverting side
to ensure that the inputs of the ADA4930-1 are kept at or above
the specified minimum input common-mode voltage at all times.
The 0.5 V dc bias at the signal source and the 0.314 V dc bias on
the gain resistor at the inverting input set the inputs of the
ADA4930-1 to ~0.48 V dc. With 1 V p-p maximum signal swing
at the input, the ADA4930-1 inputs swing between 0.36 V and
0.6 V.
For a common-mode voltage of 0.9 V, ea ch ADA4930-1 output
swings between 0.401 V and 1.398 V, providing a 1.994 V p-p
differential output.
A third-order, 40 MHz, low-pass filter between the ADA4930-1
and the AD9255 reduces the noise bandwidth of the amplifier
and isolates the driver outputs from the ADC inputs.
The circuit shown in Figure 60 is an example of ½ of an
ADA4930-2 driving ½ of an AD9640, a 14-bit, 80 MSPS
ADC that is specified to operate with a single 1.8 V supply.
The performance of the ADC is optimized when it is driven
differentially, making the best use of the signal swing available
within the 1.8 V supply. The ADA4930-2 performs the single-
ended-to-differential conversion, common-mode level shifting,
and buffering of the driving signal.
The ADA4930-2 is configured for a single-ended input to
differential output with a gain of 2 V/V. The 88.5 Ω termination
resistor, in parallel with the single-ended input impedance of
114.75 Ω, provides a 50 Ω termination for the source. The
increased gain resistance at the inverting input balances the 50 Ω
source resistance and the termination resistor that drives the
noninverting input.
The VOCM pin is connected to the CML output of the AD9640 and
sets the output common mode of the ADA4930-2 at 1 V.
The 739 Ω resistors between each input and the 3.3 V supply
provide the necessary dc bias to guarantee compliance with the
input common-mode range of the ADA4930-2.
For a common-mode voltage of 1 V, each ADA4930-2 output
swings between 0.501 V and 1.498 V, providing a 1.994 V p-p
differential output.
A third-order, 40 MHz, low-pass filter between the ADA4930-2
and the AD9640 reduces the noise bandwidth of the amplifier
and isolates the driver outputs from the ADC inputs.
1.8V
DRVDDAVDD
VIN–
VIN+
AD9255
AGND VCM
D11 TO
D0
90pF
30pF
168nH
168nH
33Ω
33Ω
50Ω
VIN
1V p-p
95Ω
0.314V
63.4Ω
VOCM
3.3V
ADA4930-1
+
0.5V
84.5Ω
301Ω
301Ω
09209-157
Figure 59. Driving an AD9255, 14-Bit, 80 MSPS ADC
1.8V
DRVDDAVDD
VIN–
VIN+
AD9640
AGND CML
D11 TO
D0
90pF
30pF
168nH
168nH
50Ω
VIN
1V p-p 96.2Ω
64.2Ω
33Ω
33Ω
739Ω
739Ω
VOCM
VOCM
3.3V
3.3V
3.3V
ADA4930-2
+
88.5Ω
301Ω
301Ω
Figure 60. Driving an AD9640, 14-Bit, 80 MSPS ADC
Data Sheet
ADA4930-1/ADA4930-2
Rev. C | Page 25 of 25
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.32
0.25
0.20
1.80
1.70 SQ
1.60
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
EXPOSED
PAD
PIN 1
INDICATOR
(0.30)
0.50
0.40
0.30
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
0.20 M I N
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS M O-220- WEED- 2.
10-09-2013-A
PKG-004326
Figure 61. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-35)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-220- WGGD-8.
BOTTOM VIEWTOP VIEW
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0. 05 MAX
0.02 NO M
0.203 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
01-18-2012-A
0.30
0.25
0.20
PIN 1
INDICATOR
0.20 M IN
2.40
2.30 SQ
2.20
EXPOSED
PAD
Figure 62. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity Branding
ADA4930-1YCPZ-R2 −40°C to +105°C 16-Lead LFCSP CP-16-35 250 H1G
ADA4930-1YCPZ-RL −40°C to +105°C 16-Lead LFCSP CP-16-35 5,000 H1G
ADA4930-1YCPZ-R7 −40°C to +105°C 16-Lead LFCSP CP-16-35 1,500 H1G
ADA4930-2YCPZ-R2 −40°C to +105°C 24-Lead LFCSP CP-24-14 250
ADA4930-2YCPZ-RL −40°C to +105°C 24-Lead LFCSP CP-24-14 5,000
ADA4930-2YCPZ-R7
−40°C to +105°C
24-Lead LFCSP
CP-24-14
1,500
1 Z = RoHS Compliant Part.
©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09209-0-5/17(C)