THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 HIGH-SPEED FULLY DIFFERENTIAL I/O AMPLIFIERS FEATURES KEY APPLICATIONS * * * * High Performance - 100 MHz, -3 dB Bandwidth - 50 V/s Slew Rate - 75 dB Total Harmonic Distortion at 1 MHz (VO = 2 VPP) - 5.4 nV/Hz Input-Referred Noise (10 kHz) Differential Input/Differential Output - Balanced Outputs Reject Common-Mode Noise - Differential Reduced Second Harmonic Distortion Power Supply Range - VDD = 3.3 V Simple Single-Ended To Differential Conversion Differential ADC Driver/Differential Antialiasing Differential Transmitter and Receiver Output Level Shifter * * * THS4121 D, DGN, OR DGK PACKAGE (TOP VIEW) THS4120 D, DGN, OR DGK PACKAGE (TOP VIEW) VIN- VOCM VDD VOUT+ 1 8 2 7 3 6 4 5 VIN- VOCM VDD VOUT+ VIN+ PD GND VOUT- 1 8 2 7 3 6 4 5 VIN+ NC GND VOUT- DESCRIPTION The THS412x is one in a family of fully differential-input, differential-output devices fabricated using Texas Instruments' state-of-the-art submicron CMOS process. The THS412x consists of a true, fully differential signal path from input to output. This results in excellent common-mode noise rejection and improved total harmonic distortion. Table 1. HIGH-SPEED DIFFERENTIAL I/O FAMILY (1) DEVICE NUMBER OF CHANNELS POWERDOWN THS4120 (1) 1 Yes THS4121 1 - For proper functiionality, an external 10-k pullup resistor is required between the PD pin and the positive supply. RELATED DEVICES DESCRIPTION SINGLE SUPPLY VOLTAGE RANGE SPLIT SUPPLY VOLTAGE RANGE THS413x 150 MHz, 51 V/s, 1.3 nV/Hz 5 V to 30 V 2.5 to 15 THS414x 160 MHz, 450 V/s, 6.5 nV/Hz 5 V to 30 V 2.5 to 15 THS415x 150 MHz, 650 V/s, 7.6 nV/Hz 5 V to 30 V 2.5 to 15 DEVICE (1) (1) See the TI Web site for additional high-speed amplifier devices. TYPICAL A/D APPLICATION CIRCUIT VDD 3.3 V VIN VOCM - + AIN + - AIN AVDD AVSS DVDD Vref DIGITAL OUTPUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2001-2004, Texas Instruments Incorporated THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGED DEVICES TA MSOP PowerPADTM SMALL OUTLINE(D) 0C to 70C -40C to 85C EVALUATION MODULES MSOP (DGN) SYMBOL (DGK) SYMBOL THS4120CD THS4120CDGN ARL THS4120CDGK ATZ THS4120EVM THS4121CD THS4121CDGN ASB THS4121CDGK ATO THS4121EVM THS4120ID THS4120IDGN ARM THS4120IDGK ARN - THS4121ID THS4121IDGN ASC THS4121IDGK ASN - ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage, GND to VDD 3.6 V VDD VI Input voltage IO Output current (sink) VID Differential input voltage (2) 110 mA VDD Continuous total power dissipation See Dissipation Rating Table TJ Maximum junction temperature (3) 150C TJ Maximum junction temperature, continuous operation, long-term reliability (4) TA Operating free-air temperature Tstg Storage Temperature 125C C suffix 0C to 70C I suffix -40C to 85C -65C to 150C Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds ESD ratings (1) (2) (3) (4) 300C HBM 4000 V CDM 1500 V MM 200 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The THS412x may incorporate a PowerPadTM on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the PowerPadTM thermally enhanced package. The absolute maximum temperature under any condition is limited by the constraints of the silicon process. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATING TABLE (1) (2) 2 POWER RATING (2) PACKAGE JA (1) (C/W) JC (C/W) TA = 25C TA = 85C D 97.5 38.3 1.02 W 410 mW DGN 58.4 4.7 1.71 W 685 mW DGK 260 54.2 385 mW 154 mW This data was taken using the JEDEC standard High-K test PCB. Power rating is determined with a junction temperature of 125C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125C for best performance and long-term reliability. Submit Documentation Feedback THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS Supply voltage TA Operating free-air temperature TYP MAX 1.5 1.65 1.75 Single supply 3 3.3 3.5 C suffix 0 70 -40 85 Split supply VDD MIN I suffix UNIT V C ELECTRICAL CHARACTERISTICS VDD = 3.3 V, RL = 800 , TA = 25C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE BW Small-signal bandwidth (-3 dB) VDD = 3.3 V, Gain = 1, Rf = 200 SR Slew rate (2) VDD = 3.3 V, Gain = 1 Settling time to 0.1% ts MHz 55 V/s 60 Differential step voltage = 2 VPP, Gain = 1 Settling time to 0.01% 100 ns 292 DISTORTION PERFORMANCE THD Total harmonic distortion Differential input, differential output Gain = 1, Rf = 200 , RL = 800 , VO = 2 VPP VDD = 3.3 V, f = 1 MHz -75 dB THD Total harmonic distortion Differential input, differential output Gain = 1, Rf = 200 , RL = 800 , VO = 4 VPP VDD = 3.3 V, f = 1 MHz -66 dB Spurious free dynamic range (SFDR) Differential input, differential output, VO = 4 VPP Rf = 200 , f = 1 MHz -69 dB Third intermodulation distortion VI = 0.071 VRMS Gain = 1, f = 10 MHz -75 dBc NOISE PERFORMANCE Vn Input voltage noise f = 10 kHz 5.4 nV/Hz In Input current noise f = 10 kHz 1 fA/Hz DC PERFORMANCE Open-loop gain Input offset voltage VS Input offset voltage, referred to VOCM Offset voltage drift IIB Input bias current IOS Input offset current Current offset drift (1) (2) TA = 25C TA = full range 60 66 dB 66 TA = 25C 3 8 TA = full range 4 9 TA = 25C 5 13 TA = full range TA = full range TA = full range TA = full range mV 14 25 V/C 1.2 pA 100 5 fA fA/C The full range temperature is 0C to 70C for the C suffix, and -40C to 85C for the I suffix. Slew rate is measured differentially from an output level range of 25% to 75%. Submit Documentation Feedback 3 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (Continued) VDD = 3.3 V, RL = 800 , TA = 25C (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS CMRR Common-mode rejection ratio TA = full range 64 96 dB VICR Common-mode input voltage range TA = full range 0.65 to VDD - 0.1 0.35 to VDD V ri Input resistance (dc level) Measured into each input terminal 820 M Ci Input capacitance, closed loop 3 pF ro Output resistance 1 V See Figure 16 OUTPUT CHARACTERISTICS VOH High-level output Voltage VIC = VDD/2, VDD = 3.3 V, TA = 25C 3.05 3.15 VOL Low-level output Voltage VIC = VDD/2, VDD = 3.3 V, TA = 25C 0.25 0.15 V IO Output current (sink), RL = 7 VDD = 3.3 V, TA = 25C 80 100 mA IO Output current (source), RL = 7 VDD = 3.3 V, TA = 25C 20 25 mA 3.3 V POWER SUPPLY VDD Supply voltage range Single supply IDD Quiescent current (per amplifier) VDD = 3.3 V PSRR Power-supply rejection ratio TA = 25C TA = 25C 11 13.5 TA = full range mA 16 68 85 dB POWER-DOWN CHARACTERISTICS (THS4120 ONLY) Power-down voltage level (2) Power-down quiescent current ton Turn-on time delay toff Turn-off time delay zo Output impedance (1) (2) Enable >1.4 Power down <1.2 TA = 25C 120 TA = full range 130 50% of final supply current value f = 1 MHz V A 4.8 s 3 ns 1 k The full range temperature is 0C to 70C for the C suffix, and -40C to 85C for the I suffix. For detail information on the power-down circuit, see the power-down section in the application section of this data sheet. TYPICAL CHARACTERISTICS Table of Graphs FIGURE Small-signal frequency response SR THD 1 Slew rate 2 vs Frequency Total harmonic distortion vs Output voltage vs Frequency Harmonic distortion VO 4 5, 6, 7 vs Output voltage 8, 9 Third intermodulation distortion vs Output voltage 10 Output voltage vs Load resistance 11 Settling time 4 3 12 Vn Voltage noise vs Frequency 13 VOO Output offset voltage vs Common-mode input voltage 14 CMMR Common-mode rejection ratio vs Frequency 15 zos Single-ended output impedance (closed loop) vs Frequency 16 Submit Documentation Feedback THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) FIGURE zo Single-ended (VOCM) input impedance vs Frequency 17 SMALL-SIGNAL FREQUENCY RESPONSE SLEW RATE 2 1.5 Rf = 390 Falling Edge 1 Rf = 200 0 Gain - dB VO - Output Voltage - V Rf = 270 1 Rf = 150 -1 -2 -3 1M 0 -0.5 -1 G=1 VI = 22.5 mVRMS VDD = 3.3 V -4 100 k VDD = 3.3 V, VO = 2 VPP, TA= 25C G=1 RL = 800 0.5 Rising Edge -1.5 10 M 100 M 0 1G 20 40 t - Time - ns f - Frequency - Hz Figure 2. TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGE -50 VDD = 3.3 V, VO = 4 VPP Rf = 200 , RL = 800 G=1 THD - Total Harmonic Distortion - dB THD - Total Harmonic Distortion - dB 80 Figure 1. -20 -30 60 -40 -50 Single-Ended Input / Differential Output -60 -70 Differential Input/ Differential Output -80 100 k VDD = 3.3 V, f = 1 MHz Rf = 200 , RL = 800 Single Input / Differential Output -60 Differential Input / Differential Output -70 -80 -90 1M f - Frequency - Hz 10 M 0 Figure 3. 1 2 3 VO - Output Voltage - V 4 5 Figure 4. Submit Documentation Feedback 5 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 THS4121 TOTAL HARMONIC DISTORTION vs FREQUENCY -60 -40 5th_HD 2nd_HD 3rd_HD -70 -80 -90 3rd_HD -100 -120 100 k -30 -40 3rd_HD -60 2nd_HD -70 -80 -90 5th_HD 4th_HD 1M f - Frequency - Hz -120 100 k 10 M 1M f - Frequency - Hz Figure 6. THS4121 HARMONIC DISTORTION vs FREQUENCY THS4121 HARMONIC DISTORTION vs OUTPUT VOLTAGE -60 -70 2nd_HD -50 3rd_HD -60 -70 5th_HD 4th_HD -90 VDD = 3.3 V, f = 1 MHz, RL = 800 , Rf = 200 , G=1 -80 2nd_HD 3rd_HD -90 -100 -110 Differential Input / Differential Output Single Input / Differential Output -100 100 k 1M f - Frequency - Hz 10 M -120 0 0.5 1 1.5 2 2.5 3 3.5 VO - Output Voltage - V Figure 7. 6 10 M Figure 5. VDD = 3.3 V, VO = 4 VPP, RL = 800 , Rf = 200 , G=1 -80 Differential Input / Differential Output -110 Differential Input / Differential Output 4th_HD -20 VDD = 3.3 V, VO = 4 VPP, RL = 800 , Rf = 200 , G=1 -100 -110 Harmonic Distortion - dB -50 Harmonic Distortion - dB Harmonic Distortion - dB -50 -30 VDD = 3.3 V, VO = 2 VPP, RL = 800 , Rf = 270 , G=1 Harmonic Distortion - dB -40 THS4121 HARMONIC DISTORTION vs FREQUENCY Figure 8. Submit Documentation Feedback 4 4.5 5 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 THS4121 HARMONIC DISTORTION vs OUTPUT VOLTAGE -70 Harmonic Distortion - dB -10 VDD = 3.3 V, f = 1 MHz, RL = 800 , Rf = 200 , G=1 -80 2nd_HD Third Intermodulation Distortion - dBc -60 THIRD INTERMODULALTION DISTORTION vs OUTPUT VOLTAGE 3rd_HD -90 4th_HD -100 5th_HD -110 VDD = 3.3 V, f = 1 MHz Rf = 270 , RL = 800 -20 -30 f = 10 MHz -40 -50 -60 f = 5 MHz -70 -80 Single Input / Differential Output -120 0 0.5 1 1.5 2 2.5 3 VO - Output Voltage - V 3.5 4 -90 -25 4.5 -20 Figure 9. -10 -5 10 SETTLING TIME VDD = 3.3 V, VO = 2 VPP, RF = 330 , RL = 800 , G=1 VDD = 3.3 V 1.02 VO - Output Voltage - V Sink VO - Output Voltage - V 5 1.03 2 1 0.5 0 -0.5 -1 1.01 1 0.99 0.98 Settling Time, 1% = 40 ns, 0.1% = 60 ns, 0.01% = 292 ns 0.97 Source -1.5 -2 100 0 Figure 10. THS4121 OUTPUT VOLTAGE vs LOAD RESISTANCE 1.5 -15 VO - Output Voltage - V 0.96 1k RL - Load Resistance - 10k 0.95 0 Figure 11. 100 200 300 t - Time - ns 400 500 Figure 12. Submit Documentation Feedback 7 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 VOLTAGE NOISE vs FREQUENCY OUTPUT OFFSETE VOLTAGE vs COMMON-MODE INPUT VOLTAGE 0.1 120 VOO - Output Offset Voltage - V V n - Voltage Noise - nV/ Hz 140 100 80 60 40 0 -0.1 -0.2 -0.3 20 0 -0.4 1 10 100 1k f - Frequency - Hz 10 k 100 k 0 Figure 13. Figure 14. THS4121 COMMON-MODE REJECTION RATIO vs FREQUENCY THS4121 SINGLE-ENDED OUTPUT IMPEDANCE vs FREQUENCY -70 -80 -90 -100 -110 100 k 8 3 1000 VDD = 3.3 V, Rf = 1 k, RL = 800 , G=1 z os - Single-Ended Output Impedance - CMRR - Common-Mode Rejection Ratio - dB -50 -60 0.5 1 1.5 2 2.5 V IC - Common-Mode Input Voltage - V 1M 10 M 100 M VDD = 3.3 V, VI = 5 dBm G=1 100 10 1 100 k f - Frequency - Hz 1M 10 M f - Frequency - Hz Figure 15. Figure 16. Submit Documentation Feedback 100 M THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 THS4121 SINGLE-ENDED (VOCM) INPUT IMPEDANCE vs FREQUENCY Z is - Single-Ended (VOCM ) Input Impedance - 1M VDD = 3.3 V, VI = -0.071 V(RMS) 100 k 10 k 1k 100 10 100 k 1M 100 M 10 M f - Frequency - Hz 1G Figure 17. Submit Documentation Feedback 9 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 APPLICATION INFORMATION RESISTOR MATCHING Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. VOCM sets the dc level of the output signals. If no voltage is applied to the VOCM pin, it is set to the midrail voltage internally defined as: V DD ) V SS 2 (1) In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential mode is the same as the input with the gain of 1. VOCM has a high bandwidth capability up to the typical operation range of the amplifier. For the prevention of noise going through the device, use a 0.1-F capacitor on the VOCM pin as a bypass capacitor. The following graph shows the simplified diagram of the THS412x. VDD Output Buffer VIN- x1 VOUT+ C VIN+ Vcm Error Amplifier + _ C x1 VDD 30 k VSS 30 k VSS VOCM Figure 18. THS412x Simplified Diagram Submit Documentation Feedback R VOUT- Output Buffer 10 R THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 APPLICATION INFORMATION (continued) DATA CONVERTERS Data converters are one of the most popular applications for the fully differential amplifiers. Fully differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VDD/2. The differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit. If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input terminal of the amplifier should not exceed the common-mode input voltage range. 3.3 V VDD 3.3 V VIN + - AIN1 - + AIN2 VOCM 0.1 F AVDD DVDD AVSS Vref Figure 19. Differential Amplifier Using a Single Supply Some single-supply applications may require the input voltage to exceed the common-mode input voltage range. In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within the specifications of the amplifier. VDD VCC R(g) VIN RPU VP 3.3 V VOUT + - - + VOCM 0.1 F R(g) VDD Rf AIN1 AIN2 VOUT RPU VCC AVDD DVDD AVSS Vref Rf Figure 20. Circuit With Improved Common-Mode Input Voltage The following equation is used to calculate RPU: V -V P DD R + PU 1 VIN - V P R ) V OUT - VP R1 (g) f Submit Documentation Feedback (2) 11 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 APPLICATION INFORMATION (continued) DRIVING A CAPACITIVE LOAD Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS412x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases the device's phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 21. A minimum value of 20 should work well for most applications. For example, in 50- transmission systems, setting the series resistor value to 50 both isolates any capacitance loading and provides the proper line impedance matching at the source end. Rf 20 Output R(g) THS412x 20 R(g) Output Rf Figure 21. Driving a Capacitive Load ACTIVE ANTIALIAS FILTERING For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 22 presents a method by which the noise may be filtered in the THS412x. Proper ground referencing should be considered. R2 C1 VDD R1 - VIN+ R(t) VINVOCM R3 VIC C3 R4 VSS C1 R2 Figure 22. Antialias Filtering 12 AVDD VIN+ + THS412x + C2 R1 VDD C3 R3 VINVs R4 Submit Documentation Feedback DVDD VOCM THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 APPLICATION INFORMATION (continued) The transfer function for this filter circuit is: Rt 2R4 ) Rt K H (f) + x d f 2 1 jf 1 ) j2fR4RtC3 2R4 ) Rt - FSF x fc ) Q FSF x fc ) 1 Where K + R2 R1 (3) 2 x R2R3C1C2 1 FSF x fc + and Q + R3C1 ) R2C1 ) KR3C1 2 2 x R2R3C1C2 (4) K sets the pass-band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the quality factor. FSF + Re 2 ) |Im| 2 and Q + Re 2 ) |Im| 2 2Re (5) Where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 = C, and C2 = nC results in: 2 x mn 1 FSF x fc + and Q + 1 ) m(1 ) K) 2RC 2 x mn (6) Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select C and calculate R for the desired fc. PRINCIPLES OF OPERATION THEORY OF OPERATION The THS412x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereas fully differential amplifiers are differential in/differential out. Differential Amplifier Rf R(g) THS412x Fully Differential Amplifier VDD _ _ VIN- VIN+ + VO+ + + R(g) Rf _ VO- VOCM GND Figure 23. Differential Amplifier Versus a Fully Differential Amplifier To understand the THS412x fully differential amplifiers, the definition for the pinouts of the amplifier are provided. Input voltage definition V ID Output voltage definition V Transfer function V + VI) - V I- VO) - VO- OD + OD + V Output common-mode voltage V ID x A V IC V + OC f OC VI) ) VI- 2 + (7) VO) ) VO- 2 (8) (9) (10) Submit Documentation Feedback 13 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 PRINCIPLES OF OPERATION (continued) Differential Structure Rejects Coupled Noise at the Input Differential Structure Rejects Coupled Noise at the Output VDD _ VINVIN+ + VO+ + _ VO- VOCM Differential Structure Rejects Coupled Noise at the Power Supply GND Figure 24. Definition of the Fully Differential Amplifier The following schematics depict the differences between the operation of the THS412x, fully differential amplifier, in two different modes. Fully differential amplifiers can work with differential input or can be implemented as single in/differential out. Rf VDD R(g) VINVs VIN+ R(g) Note: For proper operation, maintain symmetry by setting Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g) A = Rf/R(g) - + VO+ +- VO- VOCM GND Rf Figure 25. Amplifying Differential Signals Rf VIN- R(g) VDD RECOMMENDED RESISTOR VALUES - + +- VIN+ Vs R(g) VO+ GAIN R(g) Rf VO- 1 150 150 VOCM GND Rf Figure 26. Single In With Differential Out If each output is measured independently, each output is one-half of the input signal when gain is 1. The following equations express the transfer function for each output: V + 1 V O 2 I (11) The second output is equal and opposite in sign: V + -1 V O 2 I 14 Submit Documentation Feedback (12) THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 PRINCIPLES OF OPERATION (continued) Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting amplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice as much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input signal of 1 VPP. If the output of the amplifier is 2 VPP, then it is not practical to feed a 2-VPP signal into the targeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-VPP signals with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differential amplifier. The final result indicates twice as much dynamic range. Figure 27 illustrates the increase in dynamic range. The gain factor should be considered in this scenario. The THS412x fully differential amplifier offers an improved CMRR and PSRR due to its symmetrical input and output. Furthermore, second harmonic distortion is improved. Second harmonics tend to cancel because of the symmetrical output. a VOD= 1-0 = 1 VDD VINVIN+ +1 _ + + _ VOCM VSS VO+ 0 VO- +1 0 VOD = 0-1 = -1 b Figure 27. Fully Differential Amplifier With Two 1-VPP Signals CIRCUIT LAYOUT CONSIDERATIONS To achieve the levels of high-frequency performance of the THS412x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS412x evaluation board is available to use as a guide for layout or for evaluating the device performance. * * * * * Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling - Use a 6.8-F tantalum capacitor in parallel with a 0.1-F ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inch (2,54 mm) between the device power terminals and the ceramic capacitors. Sockets - Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements - Optimum high-frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier. Surface-mount passive components - Using surface-mount passive components is recommended for high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. POWER-DOWN MODE The THS4120 features a power-down pin (PD) which lowers the quiescent current from 11 mA down to 120 A, ideal for reducing system power. The power-down pin of the amplifier must be pulled high via a 10-k pullup resistor between the PD pin and the positive supply (see Figure 28) in the absence of an applied voltage, putting Submit Documentation Feedback 15 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 PRINCIPLES OF OPERATION (continued) the amplifier in the power-on mode of operation. To turn off (disable) the amplifier in an effort to conserve power, the power-down pin can be driven towards the negative rail or ground. The threshold voltages for power-on and power-down are relative to the supply rails and given in the specification tables. Above the Enable Threshold Voltage, the device is on. Below the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is not specified. Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a high-impedance output. The power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain-setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs. The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach 50% of the nominal quiescent current. The enable time delay is in the order of microseconds due to the amplifier moving in and out of the linear mode of operation. 3.3 V PD 10 kW + THS4120 _ VIN VOCM Figure 28. Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of the amplifier. An example of the closed-loop output impedance is shown in Figure 29. 16 Submit Documentation Feedback THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 PRINCIPLES OF OPERATION (continued) zos - Single-Ended Output Impedance (in Power Down) - THS4120 SINGLE-ENDED OUTPUT IMPEDANCE (IN POWER DOWN) vs FREQUENCY 10000 VCC = 3.3 V 1000 100 10 100 k 1M 10 M 100 M f - Frequency - Hz 1G Figure 29. Submit Documentation Feedback 17 THS4120 THS4121 www.ti.com SLOS319D - FEBRUARY 2001 - REVISED OCTOBER 2004 PRINCIPLES OF OPERATION (continued) GENERAL PowerPAD DESIGN CONSIDERATIONS (APPLICABLE TO DIFFERENTIAL AMPLIFIER FAMILY) The THS412x is available packaged in a thermally enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe on which the die is mounted [see Figure 30(a) and Figure 30(b)]. This arrangement results in the leadframe being exposed as a thermal pad on the underside of the package [see Figure 30(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking. More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002). This document can be found at the TI Web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. DIE Side View (a) Thermal Pad DIE End View (b) A. Bottom View (c) The thermal pad is electrically isolated from all terminals in the package. Figure 30. Views of Thermally Enhanced DGN Package 18 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp THS4120CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120CDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120CDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4120IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp THS4121CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121CDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121IDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121IDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4121IDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device THS4121IDGNRG4 16-Aug-2012 Status (1) ACTIVE Package Type Package Drawing MSOPPowerPAD DGN Pins 8 Package Qty 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant THS4120CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4120IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4120IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4121CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4121CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4121IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4121IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4120CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4120IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4120IDR SOIC D 8 2500 367.0 367.0 35.0 THS4121CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 THS4121CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4121IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 THS4121IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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