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FEATURES KEY APPLICATIONS
THS4121
D, DGN, OR DGK PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
VIN−
VOCM
VDD
VOUT+
VIN+
NC
GND
VOUT−
THS4120
D, DGN, OR DGK PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
VIN−
VOCM
VDD
VOUT+
VIN+
PD
GND
VOUT−
DESCRIPTION
+
DIGITAL
OUTPUT
VIN −
+ −
DVDD
VOCM
AVSS
AVDD
AIN
AIN
VDD
Vref
3.3 V
TYPICAL A/D APPLICATION CIRCUIT
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
HIGH-SPEED FULLY DIFFERENTIAL I/O AMPLIFIERS
•Simple Single-Ended To Differential•High Performance
Conversion– 100 MHz, –3 dB Bandwidth
•Differential ADC Driver/Differential– 50 V/ µs Slew Rate
Antialiasing– 75 dB Total Harmonic Distortion at 1 MHz
•Differential Transmitter and Receiver(V
O
= 2 V
PP
)
•Output Level Shifter– 5.4 nV/ √Hz Input-Referred Noise (10 kHz)•Differential Input/Differential Output– Balanced Outputs Reject Common-ModeNoise
– Differential Reduced Second HarmonicDistortion
•Power Supply Range– V
DD
= 3.3 V
Table 1. HIGH-SPEED DIFFERENTIAL I/O FAMILYThe THS412x is one in a family of fullydifferential-input, differential-output devices
NUMBER OFDEVICE POWERDOWNCHANNELSfabricated using Texas Instruments' state-of-the-artsubmicron CMOS process.
THS4120
(1)
1 YesTHS4121 1 –The THS412x consists of a true, fully differentialsignal path from input to output. This results inexcellent common-mode noise rejection and
(1) For proper functiionality, an external 10-k Ωpullup resistor isimproved total harmonic distortion.
required between the PD pin and the positive supply.
RELATED DEVICES
SINGLE SUPPLY SPLIT SUPPLYDEVICE
(1)
DESCRIPTION
VOLTAGE RANGE VOLTAGE RANGE
THS413x 150 MHz, 51 V/ µs, 1.3 nV/ √Hz 5 V to 30 V ±2.5 to ±15THS414x 160 MHz, 450 V/ µs, 6.5 nV/ √Hz 5 V to 30 V ±2.5 to ±15THS415x 150 MHz, 650 V/ µs, 7.6 nV/ √Hz 5 V to 30 V ±2.5 to ±15
(1) See the TI Web site for additional high-speed amplifier devices.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICES
EVALUATIONT
A
MSOP PowerPAD™ MSOP
MODULESSMALL OUTLINE(D)
(DGN) SYMBOL (DGK) SYMBOL
THS4120CD THS4120CDGN ARL THS4120CDGK ATZ THS4120EVM0°C to 70 °C
THS4121CD THS4121CDGN ASB THS4121CDGK ATO THS4121EVMTHS4120ID THS4120IDGN ARM THS4120IDGK ARN ––40 °C to 85 °C
THS4121ID THS4121IDGN ASC THS4121IDGK ASN –
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage, GND to V
DD
3.6 VV
I
Input voltage ±V
DD
I
O
Output current (sink)
(2)
110 mAV
ID
Differential input voltage ±V
DD
Continuous total power dissipation See Dissipation Rating TableT
J
Maximum junction temperature
(3)
150 °CT
J
Maximum junction temperature, continuous operation, long-term reliability
(4)
125 °CC suffix 0 °C to 70 °CT
A
Operating free-air temperature
I suffix –40 °C to 85 °CT
stg
Storage Temperature –65 °C to 150 °CLead temperature 1,6 mm (1/16 Inch) from case for 10 seconds 300 °CHBM 4000 VESD ratings CDM 1500 VMM 200 V
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The THS412x may incorporate a PowerPad™ on the underside of the chip. This acts as a heatsink and must be connected to athermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperaturewhich could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing thePowerPad™ thermally enhanced package.(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature mayresult in reduced reliability and/or lifetime of the device.
POWER RATING
(2)PACKAGE θ
JA
(1)
(°C/W) θ
JC
(°C/W)
T
A
= 25 °C T
A
= 85 °C
D 97.5 38.3 1.02 W 410 mWDGN 58.4 4.7 1.71 W 685 mWDGK 260 54.2 385 mW 154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.(2) Power rating is determined with a junction temperature of 125 °C. This is the point where distortionstarts to substantially increase. Thermal management of the final PCB should strive to keep thejunction temperature at or below 125 °C for best performance and long-term reliability.
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
MIN TYP MAX UNIT
Split supply ±1.5 ±1.65 ±1.75V
DD
Supply voltage VSingle supply 3 3.3 3.5C suffix 0 70T
A
Operating free-air temperature °CI suffix –40 85
V
DD
= 3.3 V, R
L
= 800 Ω, T
A
= 25 °C (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
BW Small-signal bandwidth (–3 dB) V
DD
= 3.3 V, Gain = 1, R
f
= 200 Ω100 MHzSR Slew rate
(2)
V
DD
= 3.3 V, Gain = 1 55 V/ µsSettling time to 0.1% 60t
s
Differential step voltage = 2 V
PP
, Gain = 1 nsSettling time to 0.01% 292
DISTORTION PERFORMANCE
Total harmonic distortionTHD Differential input, differential output V
DD
= 3.3 V, f = 1 MHz –75 dBGain = 1, R
f
= 200 Ω, R
L
= 800 Ω, V
O
= 2 V
PP
Total harmonic distortionTHD Differential input, differential output V
DD
= 3.3 V, f = 1 MHz –66 dBGain = 1, R
f
= 200 Ω, R
L
= 800 Ω, V
O
= 4 V
PP
Spurious free dynamic range (SFDR)
R
f
= 200 Ω, f = 1 MHz –69 dBDifferential input, differential output, V
O
= 4 V
PP
Third intermodulation distortion V
I
= 0.071 V
RMS
Gain = 1, f = 10 MHz –75 dBc
NOISE PERFORMANCE
V
n
Input voltage noise f = 10 kHz 5.4 nV/ √HzI
n
Input current noise f = 10 kHz 1 fA/ √Hz
DC PERFORMANCE
T
A
= 25 °C 60 66Open-loop gain dBT
A
= full range 66T
A
= 25 °C 3 8Input offset voltage
T
A
= full range 4 9
mVV
S
T
A
= 25 °C 5 13Input offset voltage, referred to V
OCM
T
A
= full range 14Offset voltage drift T
A
= full range 25 µV/ °CI
IB
Input bias current 1.2 pAT
A
= full rangeI
OS
Input offset current 100 fACurrent offset drift T
A
= full range 5 fA/ °C
(1) The full range temperature is 0 °C to 70 °C for the C suffix, and –40 °C to 85 °C for the I suffix.(2) Slew rate is measured differentially from an output level range of 25% to 75%.
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ELECTRICAL CHARACTERISTICS (Continued)
TYPICAL CHARACTERISTICS
Table of Graphs
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
V
DD
= 3.3 V, R
L
= 800 Ω, T
A
= 25 °C (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
CMRR Common-mode rejection ratio T
A
= full range 64 96 dB0.350.65 toV
ICR
Common-mode input voltage range T
A
= full range to VV
DD
– 0.1
V
DD
r
i
Input resistance (dc level) Measured into each input terminal 820 M ΩC
i
Input capacitance, closed loop 3 pFr
o
Output resistance See Figure 16 1Ω
OUTPUT CHARACTERISTICS
V
OH
High-level output Voltage V
IC
= V
DD
/2, V
DD
= 3.3 V, T
A
= 25 °C 3.05 3.15 VV
OL
Low-level output Voltage V
IC
= V
DD
/2, V
DD
= 3.3 V, T
A
= 25 °C 0.25 0.15 VI
O
Output current (sink), R
L
= 7 ΩV
DD
= 3.3 V, T
A
= 25 °C 80 100 mAI
O
Output current (source), R
L
= 7 ΩV
DD
= 3.3 V, T
A
= 25 °C 20 25 mA
POWER SUPPLY
V
DD
Supply voltage range Single supply 3.3 VT
A
= 25 °C 11 13.5I
DD
Quiescent current (per amplifier) V
DD
= 3.3 V mAT
A
= full range 16PSRR Power-supply rejection ratio T
A
= 25 °C 68 85 dB
POWER-DOWN CHARACTERISTICS (THS4120 ONLY)
Enable >1.4Power-down voltage level
(2)
VPower down <1.2T
A
= 25 °C 120Power-down quiescent current µAT
A
= full range 130t
on
Turn-on time delay 4.8 µs50% of final supply current valuet
off
Turn-off time delay 3 nsz
o
Output impedance f = 1 MHz 1 k Ω
(1) The full range temperature is 0 °C to 70 °C for the C suffix, and –40 °C to 85 °C for the I suffix.(2) For detail information on the power-down circuit, see the power-down section in the application section of this data sheet.
FIGURE
Small-signal frequency response 1SR Slew rate 2vs Frequency 3THD Total harmonic distortion
vs Output voltage 4vs Frequency 5, 6, 7Harmonic distortion
vs Output voltage 8, 9Third intermodulation distortion vs Output voltage 10V
O
Output voltage vs Load resistance 11Settling time 12V
n
Voltage noise vs Frequency 13V
OO
Output offset voltage vs Common-mode input voltage 14CMMR Common-mode rejection ratio vs Frequency 15z
os
Single-ended output impedance (closed loop) vs Frequency 16
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−1.5
−1
−0.5
0
0.5
1
1.5
0 20 40 60 80
t − Time − ns
VDD = 3.3 V,
VO = 2 VPP,
TA= 25°C
G = 1
RL = 800 Ω
− Output Voltage − VVO
Rising Edge
Falling Edge
−4
−2
−1
0
1
2
100 k 1M 10 M 100 M 1G
G = 1
VI = 22.5 mVRMS
VDD = 3.3 V
Rf = 270 Ω
Rf = 200 Ω
Gain − dB
f − Frequency − Hz
Rf = 390 Ω
Rf = 150 Ω
−3
VO − Output Voltage − V
−90
−80
−70
−60
−50
0 1 2 3 4 5
VDD = 3.3 V,
f = 1 MHz
Rf = 200 Ω,
RL = 800 Ω
Differential Input /
Differential Output
Single Input /
Differential Output
THD − Total Harmonic Distortion − dB
−80
−70
−60
−50
−40
−30
−20
100 k 1 M 10 M
THD − Total Harmonic Distortion − dB
f − Frequency − Hz
Differential Input/
Differential Output
Single−Ended Input /
Differential Output
VDD = 3.3 V,
VO = 4 VPP
Rf = 200 Ω,
RL = 800 Ω
G = 1
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
FIGURE
z
o
Single-ended (V
OCM
) input impedance vs Frequency 17
SMALL-SIGNAL FREQUENCY RESPONSE SLEW RATE
Figure 1. Figure 2.
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTIONvs vsFREQUENCY OUTPUT VOLTAGE
Figure 3. Figure 4.
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−120
−110
−100
−90
−80
−70
−60
−50
−40
100 k 1 M 10 M
Harmonic Distortion − dB
f − Frequency − Hz
5th_HD
4th_HD
3rd_HD
3rd_HD
VDD = 3.3 V,
VO = 2 VPP,
RL = 800 Ω,
Rf = 270 Ω,
G = 1
3rd_HD2nd_HD
Differential Input /
Differential Output
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
5th_HD 4th_HD
3rd_HD
2nd_HD
100 k 1 M 10 M
Harmonic Distortion − dB
f − Frequency − Hz
VDD = 3.3 V,
VO = 4 VPP,
RL = 800 Ω,
Rf = 200 Ω,
G = 1
Differential Input /
Differential Output
−100
−90
−80
−70
−60
−50
−40
−30
−20
100 k 1 M 10 M
Harmonic Distortion − dB
f − Frequency − Hz
5th_HD
4th_HD
3rd_HD
2nd_HD
VDD = 3.3 V,
VO = 4 VPP,
RL = 800 Ω,
Rf = 200 Ω,
G = 1
Single Input / Differential Output
Harmonic Distortion − dB
VDD = 3.3 V,
f = 1 MHz,
RL = 800 Ω,
Rf = 200 Ω,
G = 1
VO − Output Voltage − V
−120
−110
−100
−90
−80
−70
−60
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
3rd_HD
2nd_HD
Differential Input /
Differential Output
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
THS4121 THS4121TOTAL HARMONIC DISTORTION HARMONIC DISTORTIONvs vsFREQUENCY FREQUENCY
Figure 5. Figure 6.
THS4121 THS4121HARMONIC DISTORTION HARMONIC DISTORTIONvs vsFREQUENCY OUTPUT VOLTAGE
Figure 7. Figure 8.
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−120
−110
−100
−90
−80
−70
−60
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Harmonic Distortion − dB
5th_HD
4th_HD
3rd_HD
2nd_HD
VDD = 3.3 V,
f = 1 MHz,
RL = 800 Ω,
Rf = 200 Ω,
G = 1
Single Input / Differential Output
VO − Output Voltage − V
−90
−80
−70
−60
−50
−40
−30
−20
−10
−25 −20 −15 −10 −5 0 5 10
Third Intermodulation Distortion − dBc
VO − Output Voltage − V
f = 10 MHz
f = 5 MHz
VDD = 3.3 V,
f = 1 MHz
Rf = 270 Ω,
RL = 800 Ω
0.95
0.96
0.97
0.98
0.99
1
1.01
1.02
1.03
0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Settling Time,
1% = 40 ns,
0.1% = 60 ns,
0.01% = 292 ns
VDD = 3.3 V,
VO = 2 VPP,
RF = 330 Ω,
RL = 800 Ω,
G = 1
VDD = 3.3 V
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
Source
Sink
100
− Output Voltage − V
1k 10k
VO
RL − Load Resistance − Ω
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
THS4121
HARMONIC DISTORTION THIRD INTERMODULALTION DISTORTIONvs vsOUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 9. Figure 10.
THS4121
OUTPUT VOLTAGE
vsLOAD RESISTANCE SETTLING TIME
Figure 11. Figure 12.
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1 10 100
− Voltage Noise −
f − Frequency − Hz
1 k 10 k
VnnV/ Hz
0
20
40
60
80
100
120
140
100 k
−0.4
−0.3
−0.2
−0.1
0
0.1
− Output Offset Voltage − V
− Common-Mode Input Voltage − VVIC
VOO
0 0.5 1 1.5 2 2.5 3
100 k 1 M
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
10 M 100 M
VDD = 3.3 V,
Rf = 1 kΩ,
RL = 800 Ω,
G = 1
−110
−100
−90
−80
−70
−60
−50
1
10
100
1000
100 k 1 M 10 M 100 M
− Single-Ended Output Impedance −
f − Frequency − Hz
zos Ω
VDD = 3.3 V,
VI = 5 dBm
G = 1
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
VOLTAGE NOISE OUTPUT OFFSETE VOLTAGEvs vsFREQUENCY COMMON-MODE INPUT VOLTAGE
Figure 13. Figure 14.
THS4121 THS4121COMMON-MODE REJECTION RATIO SINGLE-ENDED OUTPUT IMPEDANCEvs vsFREQUENCY FREQUENCY
Figure 15. Figure 16.
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APPLICATION INFORMATION
RESISTOR MATCHING
ǒVDDǓ)ǒVSSǓ
2
(1)
_
+
x1
Output Buffer
Vcm Error
Amplifier
C R
CR
x1
Output Buffer
VOUT+
VOUT-
VDD
VSS
VIN-
VIN+
30 kΩ30 kΩVDD
VSS VOCM
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltagedepends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortiondiminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better tokeep the performance optimized.
V
OCM
sets the dc level of the output signals. If no voltage is applied to the V
OCM
pin, it is set to the midrail voltageinternally defined as:
In the differential mode, the V
OCM
on the two outputs cancel each other. Therefore, the output in the differentialmode is the same as the input with the gain of 1. V
OCM
has a high bandwidth capability up to the typicaloperation range of the amplifier. For the prevention of noise going through the device, use a 0.1- µF capacitor onthe V
OCM
pin as a bypass capacitor. The following graph shows the simplified diagram of the THS412x.
Figure 18. THS412x Simplified Diagram
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DATA CONVERTERS
VIN
-
+-
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
3.3 V
Vref
3.3 V
VDD
0.1 µF
VDD
VIN
-
+-
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
Vref
3.3 V
VDD
0.1 µF
VCC
RPU
VCC
RPU
R(g)
R(g)
VP
Rf
Rf
VOUT
VOUT
RPU +VP– VDD
ǒVIN – VPǓ1
R(g) )ǒVOUT – VPǓ1
Rf
(2)
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
APPLICATION INFORMATION (continued)
Data converters are one of the most popular applications for the fully differential amplifiers.
Fully differential amplifiers can operate with a single supply. V
OCM
defaults to the midrail voltage, V
DD
/2. Thedifferential output may be fed into a data converter. This method eliminates the use of a transformer in thecircuit. If the ADC has a reference voltage output (V
ref
), then it is recommended to connect it directly to the V
OCMof the amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage tothe input terminal of the amplifier should not exceed the common-mode input voltage range.
Figure 19. Differential Amplifier Using a Single Supply
Some single-supply applications may require the input voltage to exceed the common-mode input voltage range.In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within thespecifications of the amplifier.
Figure 20. Circuit With Improved Common-Mode Input Voltage
The following equation is used to calculate R
PU
:
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DRIVING A CAPACITIVE LOAD
THS412x
Output
Output
20 Ω
20 Ω
R(g)
R(g)
Rf
Rf
ACTIVE ANTIALIAS FILTERING
VIN-
VIN++
-+
-
VOCM
VOCM
VIN-
VIN+
VSS
THS412x
C3
C3
R4
R(t)
R2
R4
C1
VDD
C1
R2
R3
R3
C2
R1
R1
Vs
VIC
VDD
DVDD
AVDD
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
APPLICATION INFORMATION (continued)
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions aretaken. The first is to realize that the THS412x has been internally compensated to maximize its bandwidth andslew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on theoutput decreases the device's phase margin leading to high-frequency ringing or oscillations. Therefore, forcapacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output ofthe amplifier, as shown in Figure 21 . A minimum value of 20 Ωshould work well for most applications. Forexample, in 50- Ωtransmission systems, setting the series resistor value to 50 Ωboth isolates any capacitanceloading and provides the proper line impedance matching at the source end.
Figure 21. Driving a Capacitive Load
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-passfilters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 22 presents amethod by which the noise may be filtered in the THS412x. Proper ground referencing should be considered.
Figure 22. Antialias Filtering
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Hd(f) +ȧ
ȧ
ȡ
Ȣ
K
–ǒf
FSF x fcǓ2)1
Qjf
FSF x fc )1ȧ
ȧ
ȣ
Ȥ
xȧ
ȡ
Ȣ
Rt
2R4 )Rt
1)j2πfR4RtC3
2R4 )Rt ȧ
ȣ
ȤWhere K +R2
R1
(3)
FSF x fc +1
2π2 x R2R3C1C2
Ǹand Q +2 x R2R3C1C2
Ǹ
R3C1 )R2C1 )KR3C1
(4)
FSF +Re2)|Im|2
Ǹand Q +Re2)|Im|2
Ǹ2Re
(5)
FSF x fc +1
2πRC 2 x mn
Ǹand Q +2 x mn
Ǹ
1)m(1)K)
(6)
PRINCIPLES OF OPERATION
THEORY OF OPERATION
Rf
R(g)
R(g) Rf
_
+
Differential Amplifier
VOCM
_
+_
+
VDD
VIN−
VIN+
VO+
VO−
THS412x
Fully Differential Amplifier
GND
Input voltage definition VID +ǒVI)Ǔ–ǒVI–ǓVIC +ǒVI)Ǔ)ǒVI–Ǔ
2
(7)
Output voltage definition VOD +ǒVO)Ǔ–ǒVO–ǓVOC +ǒVO)Ǔ)ǒVO–Ǔ
2
(8)
Transfer function VOD +VID x AǒfǓ
(9)
Output common−mode voltage VOC
(10)
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
APPLICATION INFORMATION (continued)The transfer function for this filter circuit is:
K sets the pass-band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is thequality factor.
Where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR,C1 = C, and C2 = nC results in:
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then selectC and calculate R for the desired fc.
The THS412x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereasfully differential amplifiers are differential in/differential out.
Figure 23. Differential Amplifier Versus a Fully Differential Amplifier
To understand the THS412x fully differential amplifiers, the definition for the pinouts of the amplifier areprovided.
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VOCM
_
+_
+
VDD
VIN-
VIN+
VO+
VO-
Differential Structure Rejects
Coupled Noise at the Output
Differential Structure Rejects
Coupled Noise at the Input
Differential Structure Rejects
Coupled Noise at the Power Supply GND
-
Rf
R(g)
+
+
-
GND
VDD
R(g)
Rf
Vs
VIN-
VIN+
VO+
VO-
VOCM
Note: For proper operation, maintain
symmetry by setting
Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g)
⇒ A = Rf/R(g)
-
Rf
R(g)
+
+
-
GND
VDD
R(g)
Rf
Vs
VIN-
VIN+
VO+
VO-
VOCM
GAIN R(g) ΩRf Ω
1 150 150
RECOMMENDED RESISTOR VALUES
VO+1
2VI
(11)
VO+–1
2VI
(12)
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION (continued)
Figure 24. Definition of the Fully Differential Amplifier
The following schematics depict the differences between the operation of the THS412x, fully differentialamplifier, in two different modes. Fully differential amplifiers can work with differential input or can beimplemented as single in/differential out.
Figure 25. Amplifying Differential Signals
Figure 26. Single In With Differential Out
If each output is measured independently, each output is one-half of the input signal when gain is 1. Thefollowing equations express the transfer function for each output:
The second output is equal and opposite in sign:
14
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VOCM
_
+_
+
VDD
VIN-
VIN+
VO+
VO-
VOD= 1-0 = 1
VOD = 0-1 = -1
a
b
+1
0
+1
0
VSS
CIRCUIT LAYOUT CONSIDERATIONS
POWER-DOWN MODE
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION (continued)Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an invertingamplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice asmuch dynamic range compared to single-ended amplifiers. For example, a 1-V
PP
ADC can only support an inputsignal of 1 V
PP
. If the output of the amplifier is 2 V
PP
, then it is not practical to feed a 2-V
PP
signal into thetargeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-V
PPsignals with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designerhas been able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differentialamplifier. The final result indicates twice as much dynamic range. Figure 27 illustrates the increase in dynamicrange. The gain factor should be considered in this scenario. The THS412x fully differential amplifier offers animproved CMRR and PSRR due to its symmetrical input and output. Furthermore, second harmonic distortion isimproved. Second harmonics tend to cancel because of the symmetrical output.
Figure 27. Fully Differential Amplifier With Two 1-V
PP
Signals
To achieve the levels of high-frequency performance of the THS412x, follow proper printed-circuit board highfrequency design techniques. A general set of guidelines is given below. In addition, a THS412x evaluationboard is available to use as a guide for layout or for evaluating the device performance.•Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a lowinductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removedto minimize the stray capacitance.•Proper power supply decoupling - Use a 6.8- µF tantalum capacitor in parallel with a 0.1- µF ceramic capacitor on eachsupply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a0.1- µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1- µFcapacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in theconnecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inch (2,54mm) between the device power terminals and the ceramic capacitors.•Sockets - Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in thesocket pins often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is thebest implementation.
•Short trace runs/compact part placements - Optimum high-frequency performance is achieved when stray seriesinductance has been minimized. To realize this, the circuit layout should be made as compact as possible, therebyminimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its lengthshould be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier.•Surface-mount passive components - Using surface-mount passive components is recommended for high-frequencyamplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components,the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount componentsnaturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leadedcomponents are used, it is recommended that the lead lengths be kept as short as possible.
The THS4120 features a power-down pin ( PD) which lowers the quiescent current from 11 mA down to 120 µA,ideal for reducing system power. The power-down pin of the amplifier must be pulled high via a 10-k Ωpullupresistor between the PD pin and the positive supply (see Figure 28 ) in the absence of an applied voltage, putting
15Submit Documentation Feedback
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_
+
THS4120
10 kW
3.3 V
PD
VOCM
VIN
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION (continued)the amplifier in the power-on mode of operation. To turn off (disable) the amplifier in an effort to conserve power,the power-down pin can be driven towards the negative rail or ground. The threshold voltages for power-on andpower-down are relative to the supply rails and given in the specification tables. Above the Enable ThresholdVoltage, the device is on. Below the Disable Threshold Voltage, the device is off. Behavior in between thesethreshold voltages is not specified.
Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. Thepower-down mode is not intended to provide a high-impedance output. The power-down functionality is notintended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into theoutput of the amplifier is dominated by the feedback and gain-setting resistors, but the output impedance of thedevice itself varies depending on the voltage applied to the outputs.
The time delays associated with turning the device on and off are specified as the time it takes for the amplifierto reach 50% of the nominal quiescent current. The enable time delay is in the order of microseconds due to theamplifier moving in and out of the linear mode of operation.
Figure 28.
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be lowwhile in the power-down state. This is because the feedback resistor (R
f
) and the gain resistor (R
(g)
) are stillconnected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output ofthe amplifier. An example of the closed-loop output impedance is shown in Figure 29 .
16
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10
100
1000
10000
100 k 1 M 10 M 100 M 1 G
− Single-Ended Output Impedance (in Power Down) −
f − Frequency − Hz
zos Ω
THS4120
SINGLE-ENDED OUTPUT IMPEDANCE
(IN POWER DOWN)
vs
FREQUENCY
VCC = 3.3 V
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION (continued)
Figure 29.
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GENERAL PowerPAD DESIGN CONSIDERATIONS (APPLICABLE TO DIFFERENTIAL
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
THS4120
THS4121
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION (continued)
AMPLIFIER FAMILY)The THS412x is available packaged in a thermally enhanced DGN package, which is a member of thePowerPAD family of packages. This package is constructed using a downset leadframe on which the die ismounted [see Figure 30 (a) and Figure 30 (b)]. This arrangement results in the leadframe being exposed as athermal pad on the underside of the package [see Figure 30 (c)]. Because this thermal pad has direct thermalcontact with the die, excellent thermal performance can be achieved by providing a good thermal path awayfrom the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also besoldered to a copper area underneath the package. Through the use of thermal paths within this copper area,heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of thesurface mount with the, heretofore, awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be foundin the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002 ). This documentcan be found at the TI Web site (www.ti.com) by searching on the key word PowerPAD. The document can alsobe ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
A. The thermal pad is electrically isolated from all terminals in the package.
Figure 30. Views of Thermally Enhanced DGN Package
18
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PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4120CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4120IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4121CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4121IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4121IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4120CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4120IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4120IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4121CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4121CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4121IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4121IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4120CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4120IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4120IDR SOIC D 8 2500 367.0 367.0 35.0
THS4121CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
THS4121CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4121IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
THS4121IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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