4-154
File Number
3989.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999.
RFG60P06E
60A, 60V, 0.030 Ohm, ESD Rated,
P-Channel Power MOSFET
The RFG60P06E P-Channel power MOSFET is
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI circuits
gives optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integrated circuits.
The RFG60P06E incorporates ESD protection and is
designed to withstand 2kV (Human Body Model) of ESD.
Formerly developmental type TA09836.
Features
• 60A, 60V
•r
DS(ON) = 0.030Ω
• Temperature Compensating PSPICE® Model
• 2kV ESD Rated
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
Symbol
Packaging
JEDEC STYLE TO-247
Ordering Information
PART NUMBER PACKAGE BRAND
RFG60P06E TO-247 RFG60P06E
NOTE: When ordering use the entire part numberr RFG60P06E.
D
G
S
DRAIN
(BOTTOM
SIDE METAL)
SOURCE
DRAIN
GATE
Data Sheet July 1999
4-155
Absolute Maximum Ratings TC = 25oC
RFG60P06E UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS -60 V
Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3, Figure 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 60
Refer to Peak Current Curve A
Single Pulse Avalanche Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve
Electrostatic Discharge Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ESD
MIL-STD-883, Category B(2) 2KV
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
1.43 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ= 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V -60 - - V
Gate To Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA -2--4 V
Zero Gate Voltage Drain Current IDSS VDS = -60V,
VGS = 0V TC = 25oC---1µA
TC = 150oC - - -50 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - 100 nA
Drain to Source On Resistance rDS(ON) ID = 60A, VGS = -10V - - 0.030 W
Turn-On Time tON VDD = -30V, ID = 30A,
RL = 1.0Ω, VGS = -10V,
RGS = 2.5Ω
- - 125 ns
Turn-On Delay Time td(ON) -20- ns
Rise Time tr-60- ns
Turn-Off Delay Time td(OFF) -65- ns
Fall Time tf-20- ns
Turn-Off Time tOFF - - 125 ns
Total Gate Charge Qg(TOT) VGS = 0 to -20V VDD = -48V,
ID = 60A,
RL = 0.8Ω
- - 450 nC
Gate Charge at -10V Qg(-10) VGS = 0 to -10V - - 225 nC
Threshold Gate Charge Qg(TH) VGS = 0 to -2V - - 15 nC
Input Capacitance CISS VDS = -25V, VGS = 0V,
f = 1MHz - 7200 - pF
Output Capacitance COSS - 1700 - pF
Reverse Transfer Capacitance CRSS - 325 - pF
Thermal Resistance Junction to Case RθJC - - 0.70 oC/W
Thermal Resistance Junction to Ambient RθJA --80
oC/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 45A - - 1.5 V
Diode Reverse Recovery Time trr ISD = 45A, dISD/dt = 100A/µs - - 125 ns
NOTES:
2. Pulse test: pulse width ≤ 300µs maximum, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
RFG60P06E
4-156
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
1.2
1.0
0.8
0.6
0.4
0.2
00 25 50 75 100 125 150 175
POWER DISSIPATION MULTIPLIER
TC, CASE TEMPERATURE (oC)
-50
-40
-30
-20
-10
025 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
-60
-70
1
0.1
0.01
10-5 10-4 10-3 10-2 10-1 100101
ZθJC, NORMALIZED
THERMAL IMPEDANCE
t, RECTANGULAR PULSE DURATION (s)
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
PDM
t1
t2
0.01
0.02
0.05
0.1
0.2
0.5
SINGLE PULSE
-500
-100
-10
-1-1 -10 -60
VDS, DRAIN TO SOURCE VOLTAGE (V)
1ms
100µs
10ms
100ms
VDSS MAX = -60V
ID, DRAIN CURRENT (A)
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
TC = 25oCDC
10-5 10-4 10-3 10-2 10-1 100101
-100
-103
t, PULSE WIDTH (ms)
IDM, PEAK CURRENT (A)
-50
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
II
25 175 TC
–
150
------------------------



=
TC = 25oC
VGS = -10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
RFG60P06E
4-157
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
-200
-100
-10
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
STARTING TJ = 150oC
STARTING TJ = 25oC
If R = 0
tAV = (L) (IAS) / (1.3RATED BVDSS - VDD)
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
If R ≠ 0
VGS = -5V
VGS = -7V
VGS = -6V
VGS = -8V
VGS = -4.5V
VGS = -20V
VGS = -10V
00-2-4-6-8
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
-30
-60
-90
-120
PULSE DURATION = 80µs
TC = 25oC
DUTY CYCLE = 0.5% MAX
0-2 -4 -6 -8 -10
VGS, GATE TO SOURCE VOLTAGE (V)
ID(ON), ON STATE DRAIN CURRENT (A)
0
-30
-60
-120
-90 175oC
-55oC
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = -15V 2.0
1.5
1.0
0.5
0-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED ON RESISTANCE
PULSE DURATION = 80µs
VGS = -10V, ID = -60A
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
0-80 -40 0 40 80 160120 200
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED GATE
VGS = VDS, ID = - 250µA2.0
1.5
1.0
0.5
0-80 -40 0 40 80 120 160 200
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
ID = -250µA
RFG60P06E
4-158
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
CISS
COSS
CRSS
6000
4000
2000
00-5 -10 -15 -20 -25
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
8000
VGS = 0V, f = 1MHz
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
-60
-45
-30
-15
0
-10
-7.5
-5.0
-2.5
0
20 IG(REF)
IG(ACT) 80 IG(REF)
IG(ACT)
t, TIME (µs)
VDD = BVDSS VDD = BVDSS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
RL = 1.0Ω
IG(REF) = -4mA
VGS = -10V
tP
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RGS
DUT +
-VDD
VDS
VGS
td(ON)
tr
90%
10%
VDS 90%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
tON
10%
0
0
RFG60P06E
4-159
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms
(Continued)
RL
VGS
+
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = -2V
Qg(-10)
VGS = -10V
Qg(TOT)
VGS = -20V
VDS
-VGS
IG(REF)
0
0
RFG60P06E
4-160
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com
PSPICE Electrical Model
.SUBCKT RFG60P06E 2 1 3; REV 9/20/94
CA 12 8 1.01e-8
CB 15 14 1.05e-8
CIN 6 8 6.9e-9
DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD
DPLCAP 10 6 DPLCAPMOD
EBREAK 5 11 17 18 -76.35
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTO 20 6 8 18 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 7.9e-9
LSOURCE 3 7 4.18e-9
MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 12.83e-3
RGATE 9 20 1.5
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.25e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 -0.83
.MODEL DBDMOD D (IS=1.24e-12 RS=4.72e-3 TRS1=1.43e-3 TRS2=-4.91e-7 CJO=6.98e-9 TT=1.5e-7)
.MODEL DBKMOD D (RS=1.11e-1 TRS1=1.34e-3 TRS2=4.46e-12)
.MODEL DPLCAPMOD D (CJO=15e-10 IS=1e-30 N=10)
.MODEL MOSMOD PMOS (VTO=-3.71 KP=31.5 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=9.42e-4 TC2=0)
.MODEL RDSMOD RES (TC1=5.85e-3 TC2=7.69e-6)
.MODEL RVTOMOD RES (TC1=-3.39e-3 TC2=1.07e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.6 VOFF=2.6)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.6 VOFF=4.6)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.16 VOFF=-3.84)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.84 VOFF=1.16)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
MOS1
10
DPLCAP
RDRAIN
DBREAK
LDRAIN
DRAIN
SOURCE
LSOURCE
DBODY
RBREAK
RVTO
VBAT
+
-
19
IT
RSOURCE
EBREAK
MOS2
EDSEGS
RIN CIN
VTO
ESG
S1A S2A
S2BS1B
CBCA
EVTO
RGATE
GATE
LGATE
5
2
1817
7
11
21
8
6
16
2091
12 15
14
13
13
814
13
6
85
8
18
8
+
-
+
-
+
-
+
-
+
-
+
-
3
8
6
17
18
RFG60P06E