AmPAL18P8 20-Pin IMOX Programmable Array Logic Distinctive Characteristics @ Individually programmable output polarity on each output @ Pin compatible superset of mast combinatorial 20-pin PAL devices @ Eight logical product terms per output for increased logic power @ Increased input/output flexibility - 18 possible array inputs - Eight bidirectional |/Os with individually controilable output enable General Description The AmPAL18P8 is an ultra high-performance, functionally enhanced 20-pin Programmable Array Logic element. It utilizes the familiar sum-of-products (AND-OR) structure allowing users to program custom logic functions to pre- cisely fit their application. The AmPAL18P8 offers significantly enhanced functional capabilities when compared to ather combinatorial 20-pin PAL devices. These include two additional bidirectional I/O pins as well as additional product terms (bringing each output to eight logical and one three-state control product @ Ultra high-speed version tpp = 15 ns maximum @ Superior aqualitv - AC and DC parametric testing performed on every part - Extensive on-chip test circuitry ensures post-program- ming functional yield (PPFY) of 99.9% @ Platinum-Silicide fuses ensure high programming yield > 98%, fast programming and unsurpassed reli- ability * Replaces 13 combinatorial 20-Pin PAL devices term) for extra logic power. The device also features individually user programmable output polarity, giving the designer the capability to handle both active HIGH and active LOW outputs on the same device. A wide variety of speed/power selections is available, allowing precise matching to system requirements. The ultra high-speed version offers 15 ns maximum input to output propagation delay, opening up many new applica- tions for the use of programmabie logic. Block Diagram Io PRODUCT SELECTOR GUIDE Family Part No. AmPAL16P8 Power Quarter Half Full Grade Power Power Power Ordering 1 A PBB Part No. 18P8Q 18P8L 1BP8AL BFS, 1BP8| Speed Standard High igh Grade Speed Speed Speed Max. STO| APL|STD|APL|STO| APL|STD| APL| STD] APL Access 1 20 Time (ns) 35 | 40 | 35 | 40 | 25 | 30 | 26 | 30 Max. Operating 180 Current 55 90 (mA) STO = AMD "'Standard products APL = AMD Approved Products List' products BD005942 05799E/0 JANUARY 1988 5-202 ol Monolithio rat Memories aAmPAL18P8 Connection Diagrams Top View Tos NS 20 [2 Yeo iCje2 wf] ve ys 1a [7] vo | js w [J v0 \ Cs 18 [7] vo \ iCye 18 [] vo ; (C7 uw [7] yo 1Cya 3 [7] vo 1C]s 12 [J vo ano [_] 10 nti 0009210 Note: Pin 1 is marked for orientation. Lcc* vO vo vO vO 0 Cp009220 *Same Pinouts apply for PLCC. Ordering Information Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is. formed by a combination of: A. Device Number AMPAL 18P. B. Speed/Power Option Cc. Package Type D. Temperature Range E. Optional Processing Pp & Db. L. A, DEVICE NUMBER/DESCRIPTION . OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C= Commerciat (0 ta + 70C) E = Extended Commercial (-55 to + 125C) . PACKAGE TYPE P = 20-Pin Plastic IP {PD 020) D = 20-Pin Ceramic DIP (CD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) L = 20-Pin Ceramic Leadiess Chip Carrier (CL 020) SPEED/POWER OPTION B = Ultra High Speed/Standard Power A= High Speed/Standard Power AL = High Speed/Half Power L = Standard Speed/Half Power Q = Standard Speed/Quarter Power Valid Combinations AmPAL18P8 20-Pin [MOX Programmable Array Logic Valid Combinations AMPAL16P88 AMPAL18PBA PC, DC, DE, AMPAL18P8AL JC. LC. LE AMPAL1BP8t_ AMPAL18P8Q products. T1 mono#thic HK) memories &N Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on AMO's standard military grade 5-203AmPAL18P8 Ordering Information (Cont'd.) APL Products AND products for Aereospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-833C requirements. The order number (Valid Combination) for APL products is formed by a combination of: . Device Number . Speed/Power Option . Device Class . Package Type . Lead Finish -AMPAL18P5. AL f | E. LEAD FINISH A= Hot Solder DIP noon > O. PACKAGE TYPE A = 20-Pin Ceramic CIP (CD 020) 2 = 20-Pin Ceramic Leadiess Chip Carrier (CL 020) C. DEVICE CLASS /B = Class B B. SPEED/POWER OPTION B = Ultra High Speed/Standard Power A=High Speed/Standard Power AL = High Speed/Half Power L = Standard Speed/Half Power Q = Standard Speed/Quarter Power A. DEVICE NUMBER/DESCRIPTION AmPAL16P8 20-Pin IMOX Programmable Array Logic Valid Combinations Valid Combinations 1 ae : . : 8PeB Valid Combinations list configurations planned to be AMPAL18PBA supported in volume for this device, Consult the local AMD AMPAL18PBAL IBAA, /B2A sales office to confirm availability of specific valid AMPAL18P8L combinations or to check for newly released valid AMPAL18P8Q combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11 The AmPAL18P8 can be used as a functional and pin-for-pin replacement for each of the following 20-pin devices: PAL10H8 PAL14L4 PAL12H6 PAL16L2 PAL14H4 PAL16P8 PALi6H2 PAL10L8 PAL12L6 -204 cl Monouthio LA) Memories clPRODUCT TERMS (0-71) } a eersesess * o s ry 0 " - 62 PSsRIRET ry " 2 w o Benker AmPAL18P8 Logic Diagram INPUTS (0-36) @res 4607 FON BaXs BBW BNE NENT wus BHM Os273 @567 PWN 2K BITE NADH HHA BAS WIM Eighteen Array Inputs - 10 dedicated - 8 bidirectional 1/O Elght 8-Wide AND-OR Structures - Combinatorial outputs - Programmable output enable for each output - Programmable polarity on each output Tl mononthio Kl memories iN LDO000040 5-205AmPAL18P8 EEE el Functional Description The AmPAL18P8 is a functionally enhanced Programmable Array Logic (PAL) device. The Block Diagram on page ?? shows the basic architecture of the AmPAL18P8. There are up to eighteen inputs and eight outputs available. The inputs are connected to a programmable AND array which contains 72 logical product terms. initially the AND gates are connected, via fuses, to both the true and complement of every input. By selective programming of fuses, the AND gates may be "connected" to only the true input (by blowing the comple- ment fuse) to only the complement input (by blowing the true fuse), or to neither type of input (by blowing both fuses), establishing a logical "don't care." When both the true and complement fuses are left intact, a logical false results on the output of the AND gate. An AND gate with all fuses blown wilt assume the logical true state. The AmPAL18P8 has a possible maximum of 18 input pins, two more than previous 20-pin PAL devices. The extra inputs extend the functional capabilities of the device, which reduces design limitations, making it easier to design with and more flexible. The AmPAL18P8 can be programmed with more complex logic equations due to the eight product terms and one control term for each output. The control terms also allow for each of the eight bi-directional |/Os to be three-stated, greatly expand- ing the realm of design possibilities. The eight bi-directional |/O pins enhance the usefulness of the AmPAL18P8 by allowing for greater complexity of logic equations and hence more logic power. The AmPAL18P8 also has programmable output polarity, giving the designer the choice of either active HIGH or active LOW on each of the eight outputs. This simplifies the task of programming the AmPAL18P8 and allows more freedom in optimizing the logic functions. The high-speed version of the AmPAL18P8 boasts 15 ns maximum input-to-output propaga- tion delay, and creates new possibilities for the use of pro- grammable logic devices in a wide variety of applications. The AmPAL18P8 is manufactured using Advanced Micro Devices IMOX oxide isolation process. This advanced pro- cess permits an increase in density and a decrease in internal capacitance, resulting in the fastest possible programmable logic devices. The AMPAL18P8 is fabricated with AMD's fast- programming, highly reliable Platinum-Silicide Fuse technolo- gy. Utilizing an easily implemented programming algorithm, these products can be rapidly programmed to any customized pattern. Platinum-Silicide was selected as the fuse-link material to achieve a well-controlied melt rate, resulting in large non- conductive gaps that ensure very stable, long-term reliability. Extensive operating testing has proven that this low-field, large gap technology offers high reliability. The AmPAL18P8 has been designed with extensive internal test circuitry that allows the programming and operating circuitry in the part to be thoroughly tested at the factory before programming. This assures exceilent programming yield and functional performance to data sheet parameters after programming. The Post-Programming Functional Yield (PPFY) for this device is consistently better than 99.9%. Programmer/Development Systems Refer to Programmer Reference Guide Input/Output Diagrams Input Ax Output Nec. INPUT PROGRAMMING TO ARRAY CURRENT PATH IGoo0803 5-206 Tl monolithic Hi memories 1AmPAL18P8 Neen a Absolute Maximum Ratings Storage Temperature .......... eee -65 to + 150C Supply Voltage with Respect to Ground .............0.00- -0.5 to +70 V DC Voltage Applied to Outputs {except during programming)........... ~0.5 to +Voc Max. DC Voltage Applied to Outputs During Programming ...............-0:ccceeeee 16 V Output Current Into Outputs During Programming (Maximum duration of 1 second).................... 200 mA DC Input Voltage........... ee. . (0.5 to +55 V DC tnput Current ...... 0. cece ee eee -30 to +5.0 mA Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Operating Ranges Commercial (C) Devices Temperature (TA) ......0-:cceceecceeceeeneneneenens 0 to +75C Supply Voltage (Vcc) . veteeees +4.75 to +6.25 V Extended Commercial (E) Devices Temperature (TA) ........ccccseceeeeeecteeeereereee -55C Min. Temperature (T).......-... ee .+125C Max. Supply Voltage (VCC) ...-eceeeceeeee ees +4.50 to +5.50 V Military (M) Devices Temperature (TA)......cccceecccseeee tec eee eee eees ~55C Min. Temperature (TC)......cce cece eeeeeeeeee renee +125C Max. Supply Voltage (VOC) ......ceceeceeeeeee + 4.50 to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Characteristics over operating range unless otherwise specified; included in Group A, Subgroup 1, 2, 3 tests uniess otherwise noted roymbol Deserintion Test Conditions Min. Wee's Max. | Units 18P8A, 18P8B lon =-3.2 MA Tiepai tapeaL |COML | 24 3.5 Volts Vou Output HIGH Voltage loH =-2 MA 18P8Q loH =-2 MA (all. versions) MIL von Min.. 18PBA, 1@PB Vin or lo=24 mA Taps, 1ePBAL | COM'L VoL Output LOW Voltage vit lol = 12 mA | 18P8Q 0.50 | Volts lo.=12 mA | A,B. ALL loL=8 mA | 18P8Q MIL ote 2) Input HIGH level Guaranteed Input Logical HIGH Voltage for All inputs 2.0 Volts (not 6 2) Input LOW level Guaranteed Input Logical LOW Voltage for All inputs 0.8 | Volts hie Input LOW Current Voc = Max., Vin = 0.40 V -20 ~100 BA lw Input HIGH Current Voc = Max. Vin = 2.7 V 25 BA h Input HIGH Current Voc = Max.. Vin =5.5 V 1.0 mA Isc Output Short Circuit Current Voc = Max., Vout = 0.5 V (Note 3) -30 ~60 -90 mA 18P8A, 18P8B 180 loc Power Supply Current Voc = Max. 18P8L, 1BP8AL 90 mA 18P8Q 55 vy Input Clamp Voltage Veco =Min., fin =-18 MA -09 -1.2 | Volts oz Output Leak Current Vcc = Max., Viy = ViLor Viy 2 = ~ < pA Notes: 1. Typicat limits are at Voc = 5.0 V and Ta = 25C. 2. These are adsolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. Not more than one output should be tested at a time. Duration of the short circuit snould not be more than one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. Capacitance Parameter Parameter Test Conditions Typ. Units Symbol Description CIN input Capacitance Vin = 2.0 V @ f= 1 MHz 6 pF Cout Output Capacitance Vout = 2.0 V @ f= 1 MHz 9 Note: These parameters are not 100% tested, but are evaiuated at initial characterization and at any time the design is modified where capacitance may be affected. Tl Monotthic Hi] memories Ot 5-207AmPAL18P8 Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS MUST BE WILL BE STEADY STEADY WILL BE maycuanee aber FROMH TOL WILL BE mescnames Naan FROML TOH DON'T CARE. CHANGING, ANY CHANGE STATE PERMITTED UNKNOWN CENTER GOES NOT LINE IS HIGH APPLY IMPEDANCE OFF STATE KS000010 Switching Test Circuit Vee &; tR-43s Jl. OUTPUTS TC003050 Note: Cy and C2 are to bypass Vcc to ground during testing. TEST OUTPUT LOADS Power (RL) | Re S| Cu tpF) | C1 HF) | C2 (uF) Grade [STD] APL | STD| APL |STD/APL|STO/APL|STO/APL 16P8B AL | 200 | 390 | 390 | 750] 50 0.1 0.01 L tapea | 390 | 600 | 750 |1200/ 50 04 0.01 STD = AMD Standard' products APL = AMD "Approved Products List' products Switching Characteristics over operating range unless otherwise specified; included in Group A, Subgroup 9, 10, 11 tests unless otherwise noted Commercial Military/Extended 18P8B 18P8A/AL | 18P8L/Q 18P8B 18P8A/AL | 18P8L/Q Parameter Description Typ. | Max. | Typ. | Max. | Typ. | Max. | Typ. | Max. | Typ. | Max. | Typ. | Max. | Units ipo Input to Output Delay 12 15 16 26 25 35 12 20 15 30 25 40 ns tea Input to Output Enable 12 16 15 25 25 35 12 20 15 30 25 40 ns ter input to Output Disable 12 15 15 25 25 35 12 20 15 30 25 40 ns Notes: 1. Typical limits are at Voc = 5.0 V and Ta = 25C. 2. tpp is tested with switch S; closed and CG, = 50 pF. . For three-state output, output enable times are tested with C_ = 50 pF to the 1.5 V level; S; 1s open for high-impedance to HIGH tests and closed for high-impedance to LOW tests. Output disable times are tested with C, = 5 pF. HIGH to high-impedance tests are made to an output voltage of VoH-0.5 V with S; open; LOW to high-impedance tests are made to the Vo, + 0.5 V level with S; closed. Switching Waveform ov 15V | 0.0 v | Ys TK Vou WF021820 5-208 Tl monotithto HED memories ZA